DS90CF363BMT/NOPB

DS90CF363B www.ti.com SNLS180D – JULY 2004 – REVISED APRIL 2013 +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz Check for Samples: DS90CF363B FEATURES 1 • 2 • • • • • • • • • • • No Special Start-up Sequence Required between Clock/Data and /PD Pins. Input Signal (Clock and Data) can be Applied Either Before or After the Device is Powered. Support Spread Spectrum Clocking up to 100KHz Frequency Modulation & Deviations of ±2.5% Center Spread or −5% Down Spread. "Input Clock Detection" Feature will Pull all LVDS Pairs to Logic Low when Input Clock is Missing and when /PD Pin is Logic High. 18 to 68 MHz Shift Clock Support Best–in–Class Set & Hold Times on TxINPUTs Tx Power Consumption < 130 mW (typ) @65MHz Grayscale 40% Less Power Dissipation than BiCMOS Alternatives Tx Power-Down Mode < 37μW (typ) Supports VGA, SVGA, XGA and Dual Pixel SXGA. Narrow Bus Reduces Cable Size and Cost Up to 1.3 Gbps Throughput Up to 170 Megabytes/sec Bandwidth • • • • • 345 mV (typ) Swing LVDS Devices for Low EMI PLL Requires no External Components Compatible with TIA/EIA-644 LVDS Standard Low Profile 48-lead TSSOP Package Improved Replacement for: – SN75LVDS84, DS90CF363A DESCRIPTION The DS90CF363B transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 170 Mbytes/sec. The DS90CF363B is fixed as a Falling edge strobe transmitter and will interoperate with a Falling edge strobe Receiver (DS90CF366) without any translation logic. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. Block Diagram Figure 1. DS90CF363B See Package Number DGG0048A 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2013, Texas Instruments Incorporated DS90CF363B SNLS180D – JULY 2004 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Value Unit −0.3 to +4 V CMOS/TTL Input Voltage −0.3 to (VCC + 0.3) V LVDS Driver Output Voltage −0.3 to (VCC + 0.3) V Supply Voltage (VCC) LVDS Output Short Circuit Duration Continuous Junction Temperature +150 °C Storage Temperature −65 to +150 °C +260 °C 1.98 W Lead Temperature (Soldering, 4 sec) Maximum Package Power Dissipation Capacity @ 25°C DGG-48 (TSSOP) Package: DS90CF363B Package Derating: DS90CF363B 16 mW/°C above +25°C ESD Rating (HBM, 1.5 kΩ, 100 pF) ESD Rating (EIAJ, 0Ω, 200 pF) (1) 7 kV 500 V Absolute Maximum Ratings are those values beyond which the safety of the device cannot be verified. They are not meant to imply that the device should be operated at these limits. Electrical Characteristics specify conditions for device operation. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. (2) Recommended Operating Conditions Supply Voltage (VCC) Operating Free Air Temperature (TA) Min Nom Max Units 3.0 3.3 3.6 V −10 +25 +70 °C 200 mVPP 68 MHz Supply Noise Voltage (VCC) TxCLKIN frequency 18 Electrical Characteristics (1) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ (2) Max Units CMOS/TTL DC SPECIFICATIONS VIH High Level Input Voltage 2.0 VCC V VIL Low Level Input Voltage GND 0.8 V VCL Input Clamp Voltage ICL = −18 mA −0.79 −1.5 V IIN Input Current V IN = 0.4V, 2.5V or VCC +1.8 +10 μA V IN = GND −10 0 RL = 100Ω 250 345 μA LVDS DC SPECIFICATIONS VOD Differential Output Voltage ΔVOD Change in VOD between complimentary output states VOS Offset Voltage ΔVOS Change in VOS between complimentary output states IOS Output Short Circuit Current (1) (2) (3) 2 (3) 1.13 VOUT = 0V, RL = 100Ω 1.25 −3.5 450 mV 35 mV 1.38 V 35 mV −5 mA Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and ΔVOD ). Typical values are given for VCC = 3.3V and T A = +25°C unless specified otherwise. VOS previously referred as VCM. Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: DS90CF363B DS90CF363B www.ti.com SNLS180D – JULY 2004 – REVISED APRIL 2013 Electrical Characteristics(1) (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol IOZ Typ (2) Max Units Power Down = 0V, VOUT = 0V or V CC ±1 ±10 μA RL = 100Ω, f = 25 MHz CL = 5 pF, f = 40 MHz Worst Case Pattern f = 65 MHz (Figure 2 and Figure 5 ) " Typ " values are given for V CC = 3.6V and T A = +25°C, " Max " values are given for V CC = 3.6V and T A = −10°C 29 40 mA 34 45 mA 42 55 mA RL = 100Ω, f = 25 MHz CL = 5 pF, f = 40 MHz 16 Grayscale Pattern f = 65 MHz (Figure 3 and Figure 5 ) " Typ " values are given for V CC = 3.6V and T A = +25°C, " Max " values are given for V CC = 3.6V and T A = −10°C 28 40 mA 32 45 mA 39 50 mA Power Down = Low Driver Outputs in TRI-STATE under Power Down Mode 11 150 μA Parameter Conditions Output TRI-STATE Current Min TRANSMITTER SUPPLY CURRENT ICCTW ICCTG ICCTZ Transmitter Supply Current Worst Case Transmitter Supply Current 16 Grayscale Transmitter Supply Current Power Down Recommended Transmitter Input Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Min Typ Max Units 5 ns T 50.0 ns 0.5T 0.65T ns 0.65T ns 6.0 ns TCIT TxCLK IN Transition Time (Figure 6 ) TCIP TxCLK IN Period (Figure 7 ) 14.7 TCIH TxCLK IN High Time (Figure 7 ) 0.35T TCIL TxCLK IN Low Time (Figure 7 ) 0.35T 0.5T TXIT TxIN, and Power Down pin transition Time TXPD Minimum pulse width for Power Down pin signal 1.5 1 us Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Min Typ Max Units LLHT LVDS Low-to-High Transition Time (Figure 5 ) 0.75 1.4 ns LHLT LVDS High-to-Low Transition Time (Figure 5 ) 0.75 1.4 ns TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 12 ) (1) −0.20 0 +0.20 ns TPPos1 Transmitter Output Pulse Position for Bit 1 2.00 2.20 2.40 ns TPPos2 Transmitter Output Pulse Position for Bit 2 4.20 4.40 4.60 ns TPPos3 Transmitter Output Pulse Position for Bit 3 6.39 6.59 6.79 ns TPPos4 Transmitter Output Pulse Position for Bit 4 8.59 8.79 8.99 ns TPPos5 Transmitter Output Pulse Position for Bit 5 10.70 10.99 11.19 ns TPPos6 Transmitter Output Pulse Position for Bit 6 12.99 13.19 13.39 ns (1) f = 65 MHz The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. This parameter is functionality tested only on Automatic Test Equipment (ATE). Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: DS90CF363B 3 DS90CF363B SNLS180D – JULY 2004 – REVISED APRIL 2013 www.ti.com Transmitter Switching Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Min (1) Max Units −0.25 0 +0.25 ns 3.32 3.57 3.82 ns TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 12 ) TPPos1 Transmitter Output Pulse Position for Bit 1 TPPos2 Transmitter Output Pulse Position for Bit 2 6.89 7.14 7.39 ns TPPos3 Transmitter Output Pulse Position for Bit 3 10.46 10.71 10.96 ns TPPos4 Transmitter Output Pulse Position for Bit 4 14.04 14.29 14.54 ns TPPos5 Transmitter Output Pulse Position for Bit 5 17.61 17.86 18.11 ns TPPos6 Transmitter Output Pulse Position for Bit 6 21.18 21.43 21.68 ns −0.45 0 +0.45 ns 5.26 5.71 6.16 ns (1) f = 40 MHz Typ TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 12 ) TPPos1 Transmitter Output Pulse Position for Bit 1 f= 25MHz TPPos2 Transmitter Output Pulse Position for Bit 2 10.98 11.43 11.88 ns TPPos3 Transmitter Output Pulse Position for Bit 3 16.69 17.14 17.59 ns TPPos4 Transmitter Output Pulse Position for Bit 4 22.41 22.86 23.31 ns TPPos5 Transmitter Output Pulse Position for Bit 5 28.12 28.57 29.02 ns TPPos6 Transmitter Output Pulse Position for Bit 6 33.84 34.29 34.74 ns TSTC TxIN Setup to TxCLK IN (Figure 7 ) 2.5 THTC TxIN Hold to TxCLK IN (Figure 7 ) 0.5 TCCD TxCLK IN to TxCLK OUT Delay (Figure 8 ) 50% duty cycle input clock is assumed, T A= −10°C, and 65MHz for " Min ", T A = 70°C, and 25MHz for " Max ", VCC = 3.6V SSCG Spread Spectrum Clock support; Modulation frequency with a linear profile (2) ns ns 3.011 f = 25 MHz 100KHz ± 2.5%/−5% f = 40 MHz 100KHz ± 2.5%/−5% f = 65 MHz 100KHz ± 2.5%/−5% 6.082 ns TPLLS Transmitter Phase Lock Loop Set (Figure 9 ) 10 ms TPDD Transmitter Power Down Delay (Figure 11 ) 100 ns (2) Care must be taken to ensure TSTC and THTC are met so input data are sampling correctly. This SSCG parameter only shows the performance of tracking Spread Spectrum Clock applied to TxCLK IN pin, and reflects the result on TxCLKOUT+ and TxCLK− pins. AC Timing Diagrams Figure 2. “Worst Case” Test Pattern 4 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: DS90CF363B DS90CF363B www.ti.com SNLS180D – JULY 2004 – REVISED APRIL 2013 The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display. Figure 2 and Figure 3 show a falling edge data strobe (TxCLK IN/RxCLK OUT). Recommended pin to signal mapping. Customer may choose to define differently. Figure 3. “16 Grayscale” Test Pattern Figure 4. DS90CF363B (Transmitter) LVDS Output Load Figure 5. DS90CF363B (Transmitter) LVDS Transition Times Figure 6. DS90CF363B (Transmitter) Input Clock Transition Time Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: DS90CF363B 5 DS90CF363B SNLS180D – JULY 2004 – REVISED APRIL 2013 www.ti.com Figure 7. DS90CF363B (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe) Figure 8. DS90CF363B (Transmitter) Clock In to Clock Out Delay (Falling Edge Strobe) Figure 9. DS90CF363B (Transmitter) Phase Lock Loop Set Time Figure 10. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs 6 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: DS90CF363B DS90CF363B www.ti.com SNLS180D – JULY 2004 – REVISED APRIL 2013 Figure 11. Transmitter Power Down Delay Figure 12. Transmitter LVDS Output Pulse Position Measurement Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: DS90CF363B 7 DS90CF363B SNLS180D – JULY 2004 – REVISED APRIL 2013 www.ti.com DS90CF363B PIN DESCRIPTIONS — FPD LINK TRANSMITTER Pin Name I/O No. TxIN I 21 TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines—FPLINE, FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable). TxOUT+ O 3 Positive LVDS differential data output. TxOUT− O 3 Negative LVDS differential data output. FPSHIFT IN I 1 TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN. TxCLK OUT+ O 1 Positive LVDS differential clock output. TxCLK OUT− O 1 Negative LVDS differential clock output. PWR DOWN I 1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down. See Applications Information . VCC I 4 Power supply pins for TTL inputs. GND I 4 Ground pins for TTL inputs. PLL VCC I 1 Power supply pin for PLL. PLL GND I 2 Ground pins for PLL. LVDS VCC I 1 Power supply pin for LVDS outputs. LVDS GND I 3 Ground pins for LVDS outputs. 1 No connect NC Description APPLICATIONS INFORMATION The DS90CF363B are backward compatible with the DS90C363/DS90CF363A and are a pin-for-pin replacement. This device may also be used as a replacement for the DS90CF563 (5V, 65MHz) and DS90CF561 (5V, 40MHz) FPD-Link Transmitters with certain considerations/modifications: 1. Change 5V power supply to 3.3V. Provide this supply to the VCC, LVDS VCC and PLL VCC of the transmitter. TRANSMITTER INPUT PINS The DS90CF363B transmitter input and control inputs accept 3.3V LVTTL/LVCMOS levels. They are not 5V tolerant. TRANSMITTER INPUT CLOCK/DATA SEQUENCING The DS90CF363B does not require any special requirement for sequencing of the input clock/data and PD (PowerDown) signal. The DS90CF363B offers a more robust input sequencing feature where the input clock/data can be inserted after the release of the PD signal. In the case where the clock/data is stopped and reapplied, such as changing video mode within Graphics Controller, it is not necessary to cycle the PD signal. However, there are in certain cases where the PD may need to be asserted during these mode changes. In cases where the source (Graphics Source) may be supplying an unstable clock or spurious noisy clock output to the LVDS transmitter, the LVDS Transmitter may attempt to lock onto this unstable clock signal but is unable to do so due the instability or quality of the clock source. The PD signal in these cases should then be asserted once a stable clock is applied to the LVDS transmitter. Asserting the PWR DOWN pin will effectively place the device in reset and disable the PLL, enabling the LVDS Transmitter into a power saving standby mode. However, it is still generally a good practice to assert the PWR DOWN pin or reset the LVDS transmitter whenever the clock/data is stopped and reapplied but it is not mandatory for the DS90CF363B. SPREAD SPECTRUM CLOCK SUPPORT The DS90CF363B can support Spread Spectrum Clocking signal type inputs. The DS90CF363B outputs will accurately track Spread Spectrum Clock/Data inputs with modulation frequencies of up to 100KHz (max.)with either center spread of ±2.5% or down spread -5% deviations. POWER SOURCES SEQUENCE In typical applications, it is recommended to have VCC, LVDS VCC and PLL VCC from the same power source with three separate de-coupling bypass capacitor groups. There is no requirement on which VCC entering the device first. 8 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: DS90CF363B DS90CF363B www.ti.com SNLS180D – JULY 2004 – REVISED APRIL 2013 Pin Diagram Figure 13. Typical Application Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: DS90CF363B 9 DS90CF363B SNLS180D – JULY 2004 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision C (April 2013) to Revision D • 10 Page Changed layout of National Data Sheet to TI format ............................................................................................................ 9 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: DS90CF363B PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) DS90CF363BMT/NOPB ACTIVE TSSOP DGG 48 38 RoHS & Green SN Level-2-260C-1 YEAR -10 to 70 DS90CF363BMT DS90CF363BMTX/NOPB ACTIVE TSSOP DGG 48 1000 RoHS & Green SN Level-2-260C-1 YEAR -10 to 70 DS90CF363BMT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of