DS90CF384AQ
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SNLS345A – AUGUST 2011 – REVISED APRIL 2013
DS90CF384AQ +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65 MHz
Check for Samples: DS90CF384AQ
FEATURES
DESCRIPTION
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The DS90CF384AQ receiver converts the four LVDS
data streams at up to 1.8 Gbps throughput (227
Megabytes/sec bandwidth) back into parallel 28 bits
of LVCMOS/LVTTL data. In a Display application, the
28 bits include: 24 bits of RGB data and up to 4 bits
of video control (Hsync, Vsync, DE and CNTL).
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Automotive Grade Device, AEC-Q100 Grade 3
Qualified
Operating Temperature Range: –40°C to +85°C
20 to 65 MHz Shift Clock Support
50% Duty Cycle on Receiver Output Clock
Best–in–Class Set & Hold Times on
RxOUTPUTs
Rx Power Consumption 700V (EIAJ)
Supports VGA, SVGA, XGA and Dual Pixel
SXGA.
PLL Requires No External Components
Compatible with TIA/EIA-644 LVDS Standard
Low Profile 56-Lead TSSOP Package
The DS90CF384AQ device is enhanced over prior
generation FPD-Link receivers, provides a wider data
valid time on the receiver output and is offered as an
AEC-Q100 grade 3 device.
FPD-Link is an ideal means to solve EMI and cable
size problems associated with wide, high speed
LVCMOS/LVTTL interfaces.
Block Diagram
Figure 1. DS90CF384AQ Block Diagram
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
DS90CF384AQ
SNLS345A – AUGUST 2011 – REVISED APRIL 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Absolute Maximum Ratings (1) (2)
−0.3V to +4V
Supply Voltage (VCC)
LVCMOS/LVTTL Input Voltage
−0.3V to (VCC + 0.3V)
LVCMOS/LVTTL Output Voltage
−0.3V to (VCC + 0.3V)
LVDS Receiver Input Voltage
−0.3V to (VCC + 0.3V)
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
For soldering specifications: see http://www.ti.com/lit/SNOA549
Maximum Package Power Dissipation Capacity @ 25°C
DGG Package:
1.61 W
DGG Package Derating:
12.4 mW/°C above +25°C
ESD Rating
(HBM, 1.5 kΩ, 100 pF)
> 7 kV
(EIAJ, 0Ω, 200 pF)
(1)
(2)
> 700V
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the device should be operated at these limits. The “Electrical Characteristics” specify conditions for device operation.
Recommended OperatingConditions
Supply Voltage (VCC)
Min
Nom
Max
Units
3.0
3.3
3.6
V
−40
+25
+85
°C
2.4
V
Operating Free Air
Temperature (TA )
Receiver Input Range
0
Supply Noise Voltage (VCC)
100
mVPP
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ (1)
Max
Units
LVCMOS/LVTTL DC SPECIFICATIONS (For Power Down Pin)
VIH
High Level Input Voltage
2.0
VCC
V
VIL
Low Level Input Voltage
GND
0.8
V
VCL
Input Clamp Voltage
ICL = −18 mA
−0.79
−1.5
V
IIN
Input Current
V IN = 0.4V, 2.5V or VCC
+1.8
+10
μA
V IN = GND
−10
2.7
μA
0
LVCMOS/LVTTL DC SPECIFICATIONS
VOH
High Level Output Voltage
IOH = −0.4 mA
VOL
Low Level Output Voltage
IOL = 2 mA
0.06
0.3
V
IOS
Output Short Circuit Current
VOUT = 0V
−60
−120
mA
+100
mV
3.3
V
LVDS RECEIVER DC SPECIFICATIONS
VTH
Differential Input High Threshold
VTL
Differential Input Low Threshold
IIN
Input Current
(1)
2
V CM = +1.2V
−100
mV
V IN = +2.4V, VCC = 3.6V
±10
μA
V IN = 0V, VCC = 3.6V
±10
μA
Typical values are given for VCC = 3.3V and TA = +25C.
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SNLS345A – AUGUST 2011 – REVISED APRIL 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
RECEIVER SUPPLY CURRENT
ICCRW
ICCRG
ICCRZ
(2)
Typ (1)
Max
Units
f = 32.5 MHz
49
65
mA
f = 37.5 MHz
53
70
mA
f = 65 MHz
81
105
mA
f = 32.5 MHz
28
mA
f = 37.5 MHz
30
mA
f = 65 MHz
43
mA
Power Down = Low, Receiver Outputs
Stay Low during Power Down Mode
10
Parameter
Conditions
Min
(2)
Receiver Supply Current
Worst Case
CL = 8 pF, Worst Case
Pattern (Figure 2 and
Figure 4)
Receiver Supply Current,
16 Grayscale
CL = 8 pF, 16 Grayscale
Pattern (Figure 3 and
Figure 4)
Receiver Supply Current
Power Down
55
μA
Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
unless otherwise specified (except VOD and ΔV OD).
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
CLHT
CMOS/TTL Low-to-High Transition Time (Figure 4 )
CHLT
CMOS/TTL High-to-Low Transition Time (Figure 4)
RSPos0
Receiver Input Strobe Position for Bit 0 (Figure 10)
RSPos1
Min
Typ
Max
Units
2
5
ns
1.8
5
ns
1.20
1.96
2.82
ns
Receiver Input Strobe Position for Bit 1
6.91
7.67
8.53
ns
RSPos2
Receiver Input Strobe Position for Bit 2
12.62
13.38
14.24
ns
RSPos3
Receiver Input Strobe Position for Bit 3
18.33
19.09
19.95
ns
RSPos4
Receiver Input Strobe Position for Bit 4
24.04
24.80
25.66
ns
RSPos5
Receiver Input Strobe Position for Bit 5
29.75
30.51
31.37
ns
RSPos6
Receiver Input Strobe Position for Bit 6
35.46
36.22
37.08
ns
RSPos0
Receiver Input Strobe Position for Bit 0 (Figure 10)
0.7
1.1
1.4
ns
RSPos1
Receiver Input Strobe Position for Bit 1
2.9
3.3
3.6
ns
RSPos2
Receiver Input Strobe Position for Bit 2
5.1
5.5
5.8
ns
RSPos3
Receiver Input Strobe Position for Bit 3
7.3
7.7
8.0
ns
RSPos4
Receiver Input Strobe Position for Bit 4
9.5
9.9
10.2
ns
RSPos5
Receiver Input Strobe Position for Bit 5
11.7
12.1
12.4
ns
RSPos6
Receiver Input Strobe Position for Bit 6
13.9
14.3
14.6
ns
RSKM
RxIN Skew Margin (1)(Figure 11)
f = 25 MHz
f = 65 MHz
f = 25 MHz
750
ps
f = 65 MHz
500
ps
15
T
50
ns
f = 65 MHz
5.0
7.6
9.0
ns
9.0
ns
RCOP
RxCLK OUT Period (Figure 5)
RCOH
RxCLK OUT High Time (Figure 5)
RCOL
RxCLK OUT Low Time (Figure 5)
5.0
6.3
RSRC
RxOUT Setup to RxCLK OUT (Figure 5)
4.5
7.3
RHRC
RxOUT Hold to RxCLK OUT (Figure 5)
4.0
6.3
RCCD
RxCLK IN to RxCLK OUT Delay @ 25°C, VCC = 3.3V (Figure 6)
3.5
5.0
RPLLS
RPDD
(1)
ns
ns
7.5
ns
Receiver Phase Lock Loop Set (Figure 7)
10
ms
Receiver Power Down Delay (Figure 9)
1
μs
Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the
DS90C383B transmitter pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window RSPos). The RSKM will change when different transmitters are used. This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type/length of cable), and clock jitter (less than 250 ps).
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SNLS345A – AUGUST 2011 – REVISED APRIL 2013
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AC Timing Diagrams
Figure 2. “Worst Case” Test Pattern
The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
Figure 2 and Figure 3 show a falling edge data strobe (TxCLK IN / RxCLK OUT).
Recommended pin to signal mapping. Application may choose to define differently, check compatibility with source.
Figure 3. “16 Grayscale” Test Pattern
Figure 4. Receiver CMOS/TTL Output Load and Transition Times
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SNLS345A – AUGUST 2011 – REVISED APRIL 2013
Figure 5. Receiver Output Setup/Hold and High/Low Times
Figure 6. Receiver Clock In to Clock Out Delay
Figure 7. Receiver Phase Lock Loop Set Time
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SNLS345A – AUGUST 2011 – REVISED APRIL 2013
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Figure 8. 28 Parallel TTL Data Inputs/Outputs Mapped to LVDS Bits (TxINn / RxOUTn)
Figure 9. Receiver Power Down Delay
6
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SNLS345A – AUGUST 2011 – REVISED APRIL 2013
Figure 10. Receiver LVDS Input Strobe Position
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DS90CF384AQ
SNLS345A – AUGUST 2011 – REVISED APRIL 2013
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C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
Tppos—Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
Cable Skew—typically 10 ps–40 ps per foot, media dependent
Cycle-to-cycle jitter is less than 250 ps at 65 MHz.
ISI is dependent on interconnect length; may be zero.
Figure 11. Receiver LVDS Input Skew Margin
DS90CF384AQ Pin Descriptions — 56L TSSOP Package
Pin Name
I/O
No.
RxIN+
I
4
Positive LVDS differentiaI data inputs.
RxIN−
I
4
Negative LVDS differential data inputs.
RxOUT
O
28
TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 3 control lines—FPLINE, FPFRAME,
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
RxCLK IN+
I
1
Positive LVDS differential clock input.
RxCLK IN−
I
1
Negative LVDS differential clock input.
RxCLK OUT
O
1
TTL Ievel clock output. The falling edge acts as data strobe.
PWR DOWN
I
1
TTL level input. When asserted (low input) the receiver outputs are low.
VCC
I
4
Power supply pins for TTL outputs.
GND
I
5
Ground pins for TTL outputs.
PLL VCC
I
1
Power supply for PLL.
PLL GND
I
2
Ground pin for PLL.
LVDS VCC
I
1
Power supply pin for LVDS inputs.
LVDS GND
I
3
Ground pins for LVDS inputs.
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Description
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DS90CF384AQ
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SNLS345A – AUGUST 2011 – REVISED APRIL 2013
Pin Diagram for TSSOP Package
DS90CF384AQ
Figure 12. 56-Lead TSSOP (DGG Package)
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Product Folder Links: DS90CF384AQ
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DS90CF384AQ
SNLS345A – AUGUST 2011 – REVISED APRIL 2013
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REVISION HISTORY
Changes from Original (April 2013) to Revision A
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10
Page
Changed layout of National Data Sheet to TI format ............................................................................................................ 9
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
DS90CF384AQMT/NOPB
ACTIVE
TSSOP
DGG
56
34
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 85
DS90CF384AQ
MT
DS90CF384AQMTX/NOPB
ACTIVE
TSSOP
DGG
56
1000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 85
DS90CF384AQ
MT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
