DS90CF384AQMTX/NOPB

DS90CF384AQ www.ti.com SNLS345A – AUGUST 2011 – REVISED APRIL 2013 DS90CF384AQ +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65 MHz Check for Samples: DS90CF384AQ FEATURES DESCRIPTION • The DS90CF384AQ receiver converts the four LVDS data streams at up to 1.8 Gbps throughput (227 Megabytes/sec bandwidth) back into parallel 28 bits of LVCMOS/LVTTL data. In a Display application, the 28 bits include: 24 bits of RGB data and up to 4 bits of video control (Hsync, Vsync, DE and CNTL). 1 2 • • • • • • • • • • • Automotive Grade Device, AEC-Q100 Grade 3 Qualified Operating Temperature Range: –40°C to +85°C 20 to 65 MHz Shift Clock Support 50% Duty Cycle on Receiver Output Clock Best–in–Class Set & Hold Times on RxOUTPUTs Rx Power Consumption 700V (EIAJ) Supports VGA, SVGA, XGA and Dual Pixel SXGA. PLL Requires No External Components Compatible with TIA/EIA-644 LVDS Standard Low Profile 56-Lead TSSOP Package The DS90CF384AQ device is enhanced over prior generation FPD-Link receivers, provides a wider data valid time on the receiver output and is offered as an AEC-Q100 grade 3 device. FPD-Link is an ideal means to solve EMI and cable size problems associated with wide, high speed LVCMOS/LVTTL interfaces. Block Diagram Figure 1. DS90CF384AQ Block Diagram 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011–2013, Texas Instruments Incorporated DS90CF384AQ SNLS345A – AUGUST 2011 – REVISED APRIL 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Absolute Maximum Ratings (1) (2) −0.3V to +4V Supply Voltage (VCC) LVCMOS/LVTTL Input Voltage −0.3V to (VCC + 0.3V) LVCMOS/LVTTL Output Voltage −0.3V to (VCC + 0.3V) LVDS Receiver Input Voltage −0.3V to (VCC + 0.3V) Junction Temperature +150°C Storage Temperature −65°C to +150°C For soldering specifications: see http://www.ti.com/lit/SNOA549 Maximum Package Power Dissipation Capacity @ 25°C DGG Package: 1.61 W DGG Package Derating: 12.4 mW/°C above +25°C ESD Rating (HBM, 1.5 kΩ, 100 pF) > 7 kV (EIAJ, 0Ω, 200 pF) (1) (2) > 700V If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that the device should be operated at these limits. The “Electrical Characteristics” specify conditions for device operation. Recommended OperatingConditions Supply Voltage (VCC) Min Nom Max Units 3.0 3.3 3.6 V −40 +25 +85 °C 2.4 V Operating Free Air Temperature (TA ) Receiver Input Range 0 Supply Noise Voltage (VCC) 100 mVPP Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ (1) Max Units LVCMOS/LVTTL DC SPECIFICATIONS (For Power Down Pin) VIH High Level Input Voltage 2.0 VCC V VIL Low Level Input Voltage GND 0.8 V VCL Input Clamp Voltage ICL = −18 mA −0.79 −1.5 V IIN Input Current V IN = 0.4V, 2.5V or VCC +1.8 +10 μA V IN = GND −10 2.7 μA 0 LVCMOS/LVTTL DC SPECIFICATIONS VOH High Level Output Voltage IOH = −0.4 mA VOL Low Level Output Voltage IOL = 2 mA 0.06 0.3 V IOS Output Short Circuit Current VOUT = 0V −60 −120 mA +100 mV 3.3 V LVDS RECEIVER DC SPECIFICATIONS VTH Differential Input High Threshold VTL Differential Input Low Threshold IIN Input Current (1) 2 V CM = +1.2V −100 mV V IN = +2.4V, VCC = 3.6V ±10 μA V IN = 0V, VCC = 3.6V ±10 μA Typical values are given for VCC = 3.3V and TA = +25C. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DS90CF384AQ DS90CF384AQ www.ti.com SNLS345A – AUGUST 2011 – REVISED APRIL 2013 Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol RECEIVER SUPPLY CURRENT ICCRW ICCRG ICCRZ (2) Typ (1) Max Units f = 32.5 MHz 49 65 mA f = 37.5 MHz 53 70 mA f = 65 MHz 81 105 mA f = 32.5 MHz 28 mA f = 37.5 MHz 30 mA f = 65 MHz 43 mA Power Down = Low, Receiver Outputs Stay Low during Power Down Mode 10 Parameter Conditions Min (2) Receiver Supply Current Worst Case CL = 8 pF, Worst Case Pattern (Figure 2 and Figure 4) Receiver Supply Current, 16 Grayscale CL = 8 pF, 16 Grayscale Pattern (Figure 3 and Figure 4) Receiver Supply Current Power Down 55 μA Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and ΔV OD). Receiver Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter CLHT CMOS/TTL Low-to-High Transition Time (Figure 4 ) CHLT CMOS/TTL High-to-Low Transition Time (Figure 4) RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 10) RSPos1 Min Typ Max Units 2 5 ns 1.8 5 ns 1.20 1.96 2.82 ns Receiver Input Strobe Position for Bit 1 6.91 7.67 8.53 ns RSPos2 Receiver Input Strobe Position for Bit 2 12.62 13.38 14.24 ns RSPos3 Receiver Input Strobe Position for Bit 3 18.33 19.09 19.95 ns RSPos4 Receiver Input Strobe Position for Bit 4 24.04 24.80 25.66 ns RSPos5 Receiver Input Strobe Position for Bit 5 29.75 30.51 31.37 ns RSPos6 Receiver Input Strobe Position for Bit 6 35.46 36.22 37.08 ns RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 10) 0.7 1.1 1.4 ns RSPos1 Receiver Input Strobe Position for Bit 1 2.9 3.3 3.6 ns RSPos2 Receiver Input Strobe Position for Bit 2 5.1 5.5 5.8 ns RSPos3 Receiver Input Strobe Position for Bit 3 7.3 7.7 8.0 ns RSPos4 Receiver Input Strobe Position for Bit 4 9.5 9.9 10.2 ns RSPos5 Receiver Input Strobe Position for Bit 5 11.7 12.1 12.4 ns RSPos6 Receiver Input Strobe Position for Bit 6 13.9 14.3 14.6 ns RSKM RxIN Skew Margin (1)(Figure 11) f = 25 MHz f = 65 MHz f = 25 MHz 750 ps f = 65 MHz 500 ps 15 T 50 ns f = 65 MHz 5.0 7.6 9.0 ns 9.0 ns RCOP RxCLK OUT Period (Figure 5) RCOH RxCLK OUT High Time (Figure 5) RCOL RxCLK OUT Low Time (Figure 5) 5.0 6.3 RSRC RxOUT Setup to RxCLK OUT (Figure 5) 4.5 7.3 RHRC RxOUT Hold to RxCLK OUT (Figure 5) 4.0 6.3 RCCD RxCLK IN to RxCLK OUT Delay @ 25°C, VCC = 3.3V (Figure 6) 3.5 5.0 RPLLS RPDD (1) ns ns 7.5 ns Receiver Phase Lock Loop Set (Figure 7) 10 ms Receiver Power Down Delay (Figure 9) 1 μs Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the DS90C383B transmitter pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window RSPos). The RSKM will change when different transmitters are used. This margin allows for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less than 250 ps). Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DS90CF384AQ 3 DS90CF384AQ SNLS345A – AUGUST 2011 – REVISED APRIL 2013 www.ti.com AC Timing Diagrams Figure 2. “Worst Case” Test Pattern The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display. Figure 2 and Figure 3 show a falling edge data strobe (TxCLK IN / RxCLK OUT). Recommended pin to signal mapping. Application may choose to define differently, check compatibility with source. Figure 3. “16 Grayscale” Test Pattern Figure 4. Receiver CMOS/TTL Output Load and Transition Times 4 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DS90CF384AQ DS90CF384AQ www.ti.com SNLS345A – AUGUST 2011 – REVISED APRIL 2013 Figure 5. Receiver Output Setup/Hold and High/Low Times Figure 6. Receiver Clock In to Clock Out Delay Figure 7. Receiver Phase Lock Loop Set Time Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DS90CF384AQ 5 DS90CF384AQ SNLS345A – AUGUST 2011 – REVISED APRIL 2013 www.ti.com Figure 8. 28 Parallel TTL Data Inputs/Outputs Mapped to LVDS Bits (TxINn / RxOUTn) Figure 9. Receiver Power Down Delay 6 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DS90CF384AQ DS90CF384AQ www.ti.com SNLS345A – AUGUST 2011 – REVISED APRIL 2013 Figure 10. Receiver LVDS Input Strobe Position Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DS90CF384AQ 7 DS90CF384AQ SNLS345A – AUGUST 2011 – REVISED APRIL 2013 www.ti.com C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos—Transmitter output pulse position (min and max) RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference) Cable Skew—typically 10 ps–40 ps per foot, media dependent Cycle-to-cycle jitter is less than 250 ps at 65 MHz. ISI is dependent on interconnect length; may be zero. Figure 11. Receiver LVDS Input Skew Margin DS90CF384AQ Pin Descriptions — 56L TSSOP Package Pin Name I/O No. RxIN+ I 4 Positive LVDS differentiaI data inputs. RxIN− I 4 Negative LVDS differential data inputs. RxOUT O 28 TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 3 control lines—FPLINE, FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable). RxCLK IN+ I 1 Positive LVDS differential clock input. RxCLK IN− I 1 Negative LVDS differential clock input. RxCLK OUT O 1 TTL Ievel clock output. The falling edge acts as data strobe. PWR DOWN I 1 TTL level input. When asserted (low input) the receiver outputs are low. VCC I 4 Power supply pins for TTL outputs. GND I 5 Ground pins for TTL outputs. PLL VCC I 1 Power supply for PLL. PLL GND I 2 Ground pin for PLL. LVDS VCC I 1 Power supply pin for LVDS inputs. LVDS GND I 3 Ground pins for LVDS inputs. 8 Description Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DS90CF384AQ DS90CF384AQ www.ti.com SNLS345A – AUGUST 2011 – REVISED APRIL 2013 Pin Diagram for TSSOP Package DS90CF384AQ Figure 12. 56-Lead TSSOP (DGG Package) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DS90CF384AQ 9 DS90CF384AQ SNLS345A – AUGUST 2011 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Original (April 2013) to Revision A • 10 Page Changed layout of National Data Sheet to TI format ............................................................................................................ 9 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DS90CF384AQ PACKAGE OPTION ADDENDUM www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status Material type (1) (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material MSL rating/ Peak reflow (4) (5) Op temp (°C) Part marking (6) DS90CF384AQMT/NOPB Active Production TSSOP (DGG) | 56 34 | TUBE Yes SN Level-2-260C-1 YEAR -40 to 85 DS90CF384AQ MT DS90CF384AQMT/NOPB.B Active Production TSSOP (DGG) | 56 34 | TUBE Yes SN Level-2-260C-1 YEAR -40 to 85 DS90CF384AQ MT DS90CF384AQMTX/NOPB Active Production TSSOP (DGG) | 56 1000 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 85 DS90CF384AQ MT (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Aug-2025 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS K0 P1 B0 W Reel Diameter Cavity A0 B0 K0 W P1 A0 Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes Q1 Q2 Q1 Q2 Q3 Q4 Q3 Q4 User Direction of Feed Pocket Quadrants *All dimensions are nominal Device DS90CF384AQMTX/ NOPB Package Package Pins Type Drawing TSSOP DGG 56 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 14.5 1.8 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Aug-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W L H *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90CF384AQMTX/NOPB TSSOP DGG 56 1000 356.0 356.0 45.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Aug-2025 TUBE T - Tube height L - Tube length W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) DS90CF384AQMT/NOPB DGG TSSOP 56 34 495 10 2540 5.79 DS90CF384AQMT/ NOPB.B DGG TSSOP 56 34 495 10 2540 5.79 Pack Materials-Page 3 PACKAGE OUTLINE DGG0056A TSSOP - 1.2 mm max height SCALE 1.200 SMALL OUTLINE PACKAGE C 8.3 TYP 7.9 SEATING PLANE PIN 1 ID AREA A 0.1 C 54X 0.5 56 1 14.1 13.9 NOTE 3 2X 13.5 28 B 6.2 6.0 29 56X 0.27 0.17 0.08 1.2 MAX C A B (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0 -8 0.15 0.05 0.75 0.50 DETAIL A TYPICAL 4222167/A 07/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-153. www.ti.com EXAMPLE BOARD LAYOUT DGG0056A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 56X (1.5) SYMM 1 56 56X (0.3) 54X (0.5) (R0.05) TYP SYMM 28 29 (7.5) LAND PATTERN EXAMPLE SCALE:6X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4222167/A 07/2015 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DGG0056A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 56X (1.5) SYMM 1 56 56X (0.3) 54X (0.5) (R0.05) TYP SYMM 29 28 (7.5) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4222167/A 07/2015 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. 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