DS90CF563, DS90CF564
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SNLS107E – JULY 1997 – REVISED APRIL 2013
DS90CF563/DS90CF564 LVDS 18-Bit Color Flat Panel Display (FPD) Link - 65 MHz
Check for Samples: DS90CF563, DS90CF564
FEATURES
DESCRIPTION
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The DS90CF563 transmitter converts 21 bits of
CMOS/TTL data into three LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked
transmit clock is transmitted in parallel with the data
streams over a fourth LVDS link. Every cycle of the
transmit clock 21 bits of input data are sampled and
transmitted. The DS90CF564 receiver converts the
LVDS data streams back into 21 bits of CMOS/TTL
data. At a transmit clock frequency of 65 MHz, 18 bits
of RGB data and 3 bits of LCD timing and control
data (FPLINE, FPFRAME, DRDY) are transmitted at
a rate of 455 Mbps per LVDS data channel. Using a
65 MHz clock, the data throughput is 171 Mbytes per
second. These devices are offered with falling edge
data strobes for convenient interface with a variety of
graphics and LCD panel controllers.
1
2
20 to 65 MHz Shift Clk Support
Up to 171 Mbytes/s Bandwidth
Cable Size is Reduced to Save Cost
290 mV Swing LVDS Devices for Low EMI
Low Power CMOS Design (< 550 mW typ)
Power-down Mode Saves Power (< 0.25 mW)
PLL Requires No External Components
Low Profile 48-Lead TSSOP Package
Falling Edge Data Strobe
Compatible with TIA/EIA-644 LVDS Standard
Single Pixel Per Clock XGA (1024 x 768)
Supports VGA, SVGA, XGA and Higher
1.3 Gbps Throughput
This chipset is an ideal means to solve EMI and
cable size problems associated with wide, high speed
TTL interfaces.
Block Diagram
Figure 1. DS90CF563
DS90CF563MTD is no longer available.
Figure 2. DS90CF564
See Package Number DGG0048A
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1997–2013, Texas Instruments Incorporated
DS90CF563, DS90CF564
SNLS107E – JULY 1997 – REVISED APRIL 2013
www.ti.com
Application
Absolute Maximum Ratings (1) (2)
−0.3V to +6V
Supply Voltage (VCC)
CMOS/TTL Input Voltage
−0.3V to (VCC + 0.3V)
CMOS/TTL Output Voltage
−0.3V to (VCC + 0.3V)
LVDS Receiver Input Voltage
−0.3V to (VCC + 0.3V)
LVDS Driver Output Voltage
−0.3V to (VCC + 0.3V)
LVDS Output Short Circuit Duration
Continuous
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
Lead Temperature (Soldering, 4 sec)
+260°C
Maximum Package Power Dissipation @ +25°C
This device does not meet 2000V ESD rating
(1)
(2)
(3)
(3)
DGG0048A (TSSOP)
Package:
DS90CF563
1.98W
DS90CF564
1.89W
Package Derating:
DS90CF563
16 mW/°C above +25°C
DS90CF564
15 mW/°C above +25°C
.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be verified. They are not meant to imply
that the device should be operated at these limits. The “Electrical Characteristics” specify conditions for device operation.
ESD Rating: HBM (1.5 kΩ, 100 pF) PLL V CC ≥ 1000V All other pins ≥ 2000V EIAJ (0Ω, 200 pF) ≥ 150V
Recommended Operating Conditions
Min
Nom
Max
Units
Supply Voltage (VCC)
4.75
5.0
5.25
V
Operating Free Air Temperature (TA)
−10
+25
+70
°C
2.4
V
100
mVP-P
Receiver Input Range
0
Supply Noise Voltage (VCC)
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS/TTL DC SPECIFICATIONS
VIH
High Level Input Voltage
2.0
VCC
V
VIL
Low Level Input Voltage
GND
0.8
V
VOH
High Level Output Voltage
IOH = −0.4 mA
VOL
Low Level Output Voltage
IOL = 2 mA
2
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3.8
4.9
0.1
V
0.3
V
Copyright © 1997–2013, Texas Instruments Incorporated
Product Folder Links: DS90CF563 DS90CF564
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SNLS107E – JULY 1997 – REVISED APRIL 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
−1.5
V
VCL
Input Clamp Voltage
ICL = −18 mA
−0.7
9
IIN
Input Current
VIN = VCC, GND, 2.5V or 0.4V
±5.1
IOS
Output Short Circuit Current
VOUT = 0V
±10
μA
−120
mA
450
mV
35
mV
1.37
5
V
35
mV
1.6
V
LVDS DRIVER DC SPECIFICATIONS
VOD
Differential Output Voltage
ΔVOD
Change in VOD between
Complementary Output States
R L = 100Ω
VCM
Common Mode Voltage
ΔVCM
Change in VCM between
Complementary Output States
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
IOS
Output Short Circuit Current
VOUT = 0V, RL = 100Ω
IOZ
Output TRI-STATE Current
Power Down = 0V, VOUT = 0V or VCC
250
1.1
290
1.25
1.3
0.9
1.01
V
−2.9
−5
mA
±1
±10
μA
+100
mV
LVDS RECEIVER DC SPECIFICATIONS
VTH
Differential Input High Threshold
VTL
Differential Input Low Threshold
IIN
Input Current
V CM = +1.2V
−100
VIN = +2.4V
mV
VCC = 5.5V
VIN = 0V
±10
μA
±10
μA
TRANSMITTER SUPPLY CURRENT
ICCTW
ICCTG
ICCTZ
Transmitter Supply Current,
Worst Case
RL = 100Ω, CL = 5 pF,
Worst Case Pattern
(Figure 3, Figure 5)
Transmitter Supply Current,
16 Grayscale
RL = 100Ω, CL = 5 pF,
16 Grayscale Pattern
(Figure 4, Figure 5)
Transmitter Supply Current,
Power Down
f = 32.5 MHz
49
63
mA
f = 37.5 MHz
51
64
mA
f = 65 MHz
70
84
mA
f = 32.5 MHz
40
55
mA
f = 37.5 MHz
41
55
mA
f = 65 MHz
55
67
mA
1
25
μA
Power Down = Low
RECEIVER SUPPLY CURRENT
ICCRW
ICCRG
ICCRZ
Receiver Supply Current,
CL = 8 pF,
f = 32.5 MHz
64
77
mA
Worst Case
Worst Case Pattern
f = 37.5 MHz
70
85
mA
(Figure 3, Figure 6)
f = 65 MHz
110
140
mA
Receiver Supply Current,
CL = 8 pF,
f = 32.5 MHz
35
55
mA
16 Grayscale
16 Grayscale Pattern
f = 37.5 MHz
37
55
mA
(Figure 4, Figure 6)
f = 65 MHz
55
67
mA
1
10
μA
Receiver Supply Current,
Power Down = Low
Power Down
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min
Typ
Max
Units
LLHT
LVDS Low-to-High Transition Time (Figure 5)
0.75
1.5
ns
LHLT
LVDS High-to-Low Transition Time (Figure 5)
0.75
1.5
ns
TCIT
TxCLK IN Transition Time (Figure 7)
8
ns
TCCS
TxOUT Channel-to-Channel Skew
350
ps
(1)
(1)
(Figure 8)
This limit based on bench characterization.
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SNLS107E – JULY 1997 – REVISED APRIL 2013
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Transmitter Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
TCCD
Parameter
Min
TxCLK IN to TxCLK OUT Delay @ 25°C, VCC = 5.0V
Typ
3.5
Max
Units
8.5
ns
(Figure 11)
TCIP
TxCLK IN Period (Figure 9)
TCIH
TxCLK IN High Time (Figure 9)
15
T
50
ns
0.35T
0.5T
0.65T
ns
TCIL
TxCLK IN Low Time (Figure 9)
TSTC
TxIN Setup to TxCLK IN (Figure 9 )
0.35T
0.5T
0.65T
ns
5
3.5
THTC
TxIN Hold to TxCLK IN (Figure 9)
ns
2.5
1.5
ns
TPDD
Transmitter Powerdown Delay (Figure 20)
100
ns
TPLLS
Transmitter Phase Lock Loop Set (Figure 13)
10
ms
TPPos0
Transmitter Output Pulse Position 0 (Figure 15)
−0.30
0
0.30
ns
TPPos1
Transmitter Output Pulse Position 1
1.70
1/7 Tclk
2.50
ns
TPPos2
Transmitter Output Pulse Position 2
3.60
2/7 Tclk
4.50
ns
TPPos3
Transmitter Output Pulse Position 3
5.90
3/7 Tclk
6.75
ns
TPPos4
Transmitter Output Pulse Position 4
8.30
4/7 Tclk
9.00
ns
TPPos5
Transmitter Output Pulse Position 5
10.40
5/7 Tclk
11.10
ns
TPPos6
Transmitter Output Pulse Position 6
12.70
6/7 Tclk
13.40
ns
f = 65 MHz
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Typ
Max
Units
CLHT
Symbol
CMOS/TTL Low-to-High Transition Time (Figure 6)
Parameter
Min
2.5
4.0
ns
CHLT
CMOS/TTL High-to-Low Transition Time (Figure 6)
2.0
3.5
ns
RCOP
RxCLK OUT Period
15
T
50
ns
RCOH
RxCLK OUT High Time
f = 65 MHz
7.8
9
ns
RCOL
RxCLK OUT Low Time
f = 65 MHz
3.8
5
ns
RSRC
RxOUT Setup to RxCLK OUT
f = 65 MHz
2.5
4.2
ns
RHRC
RxOUT Hold to RxCLK OUT
f = 65 MHz
4.0
5.2
RCCD
RxCLK IN to RxCLK OUT Delay @ 25°C, VCC = 5.0V
6.4
ns
10.7
ns
10
ms
1
μs
(Figure 12)
RPLLS
Receiver Phase Lock Loop Set (Figure 14)
RSKM
RxIN Skew Margin
RPDD
Receiver Powerdown (Figure 19)
(1)
4
(1)
(Figure 16)
VCC = 5V, TA =25°C
600
ps
Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter
output skew (TCCS) and the setup and hold time (internal data sampling window), allowing for LVDS cable skew dependent on
type/length and source clock (TxCLK IN) jitter.
RSKM ≥ cable skew (the, length) + source clock jitter (cycle to cycle)
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Product Folder Links: DS90CF563 DS90CF564
DS90CF563, DS90CF564
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SNLS107E – JULY 1997 – REVISED APRIL 2013
AC Timing Diagrams
Figure 3. “Worst Case” Test Pattern
Device Pin Name
Signal
TxCLK IN / RxCLK OUT
Dot Clk
Signal Pattern
Signal Frequency
f
TxIN0 / RxOUT0
R0
f / 16
TxIN1 / RxOUT1
R1
f/8
TxIN2 / RxOUT2
R2
f/4
TxIN3 / RxOUT3
R3
f/2
TxIN4 / RxOUT4
R4
Steady State, Low
TxIN5 / RxOUT5
R5
Steady State, Low
TxIN6 / RxOUT6
G0
f / 16
TxIN7 / RxOUT7
G1
f/8
TxIN8 / RxOUT8
G2
f/4
TxIN9 / RxOUT9
G3
f/2
TxIN10 / RxOUT10
G4
Steady State, Low
TxIN11 / RxOUT11
G5
Steady State, Low
TxIN12 / RxOUT12
B0
f / 16
TxIN13 / RxOUT13
B1
f/8
TxIN14 / RxOUT14
B2
f/4
TxIN15 / RxOUT15
B3
f/2
TxIN16 / RxOUT16
B4
Steady State, Low
TxIN17 / RxOUT17
B5
Steady State, Low
TxIN18 / RxOUT18
HSYNC
Steady State, High
TxIN19 / RxOUT19
VSYNC
Steady State, High
TxIN20 / RxOUT20
ENA
Steady State, High
(1)
The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
(2)
The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
(3)
Figure 3 and Figure 4 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
(4)
Recommended pin to signal mapping. Customer may choose to define differently.
Figure 4. “16 Grayscale” Test Pattern
Copyright © 1997–2013, Texas Instruments Incorporated
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DS90CF563, DS90CF564
SNLS107E – JULY 1997 – REVISED APRIL 2013
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Figure 5. DS90CF563 (Transmitter) LVDS Output Load and Transition Times
Figure 6. DS90CF564 (Receiver) CMOS/TTL Output Load and Transition Times
Figure 7. DS90CF563 (Transmitter) Input Clock Transition Time
Note: Measurements at Vdiff = 0V
Note: TCSS measured between earliest and latest LVDS edges.
Note: TxCLK Differential High→Low Edge
Figure 8. DS90CF563 (Transmitter) Channel-to-Channel Skew and Pulse Width
Figure 9. DS90CF563 (Transmitter) Setup/Hold and High/Low Times
6
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DS90CF563, DS90CF564
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SNLS107E – JULY 1997 – REVISED APRIL 2013
Figure 10. DS90CF564 (Receiver) Clock In to Clock Out Delay
Figure 11. DS90CF563 (Transmitter) Clock In to Clock Out Delay
Figure 12. DS90CF564 (Receiver) Clock In to Clock Out Delay
Figure 13. DS90CF563 (Transmitter) Phase Lock Loop Set Time
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Figure 14. DS90CF564 (Receiver) Phase Lock Loop Set Time
Figure 15. Transmitter LVDS Output Pulse Position Measurement
8
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DS90CF563, DS90CF564
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SNLS107E – JULY 1997 – REVISED APRIL 2013
SW—Setup and Hold Time (Internal Data Sampling Window)
TCCS—Transmitter Output Skew
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)
Cable Skew—typically 10 ps–40 ps per foot
Figure 16. Receiver LVDS Input Skew Margin
Figure 17. Seven Bits of LVDS in One Clock Cycle
Figure 18. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CF563)
Figure 19. Receiver Powerdown Delay
Copyright © 1997–2013, Texas Instruments Incorporated
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Figure 20. Transmitter Powerdown Delay
DS90CF563 Pin Descriptions—FPD Link Transmitter
Pin Name
I/O
No.
TxIN
I
21
TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines—FPLINE, FPFRAME, DRDY (also
referred to as HSYNC, VSYNC, Data Enable)
Description
TxOUT+
O
3
Positive LVDS differential data output
TxOUT−
O
3
Negative LVDS differential data output
FPSHIFT IN
I
1
TTL level clock input. The falling edge acts as data strobe
TxCLK OUT+
O
1
Positive LVDS differential clock output
TxCLK OUT−
O
1
Negative LVDS differential clock output
PWR DOWN
I
1
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down
VCC
I
4
Power supply pins for TTL inputs
GND
I
5
Ground pins for TTL inputs
PLL VCC
I
1
Power supply pin for PLL
PLL GND
I
2
Ground pins for PLL
LVDS VCC
I
1
Power supply pin for LVDS outputs
LVDS GND
I
3
Ground pins for LVDS outputs
I/O
No.
RxIN+
I
3
Positive LVDS differential data inputs
RxIN−
I
3
Negative LVDS differential data inputs
RxOUT
O
21
TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines—FPLINE, FPFRAME,
DRDY(also referred to as HSYNC, VSYNC, Data Enable)
RxCLK IN+
I
1
Positive LVDS differential clock input
RxCLK IN−
I
1
Negative LVDS differential clock input
FPSHIFT OUT
O
1
TTL level clock output. The falling edge acts as data strobe
PWR DOWN
I
1
TTL level input. Assertion (low input) maintains the receiver outputs in the previous state
VCC
I
4
Power supply pins for TTL outputs
GND
I
5
Ground pins for TTL outputs
PLL VCC
I
1
Power supply for PLL
PLL GND
I
2
Ground pin for PLL
LVDS VCC
I
1
Power supply pin for LVDS inputs
LVDS GND
I
3
Ground pins for LVDS inputs
DS90CF564 Pin Descriptions—FPD Link Receiver
Pin Name
10
Description
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SNLS107E – JULY 1997 – REVISED APRIL 2013
Connection Diagram
DS90CF563
DS90CF564
Copyright © 1997–2013, Texas Instruments Incorporated
Product Folder Links: DS90CF563 DS90CF564
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DS90CF563, DS90CF564
SNLS107E – JULY 1997 – REVISED APRIL 2013
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REVISION HISTORY
Changes from Revision D (April 2013) to Revision E
•
12
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 11
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
DS90CF564MTD/NOPB
ACTIVE
TSSOP
DGG
48
38
RoHS & Green
SN
Level-2-260C-1 YEAR
-10 to 70
DS90CF564MTD
>B
DS90CF564MTDX/NOPB
ACTIVE
TSSOP
DGG
48
1000
RoHS & Green
SN
Level-2-260C-1 YEAR
-10 to 70
DS90CF564MTD
>B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
