DS90CP22MTX/NOPB

DS90CP22 www.ti.com SNLS053E – MARCH 2000 – REVISED APRIL 2013 DS90CP22 800 Mbps 2x2 LVDS Crosspoint Switch Check for Samples: DS90CP22 FEATURES DESCRIPTION • • DS90CP22 is a 2x2 crosspoint switch utilizing LVDS (Low Voltage Differential Signaling) technology for low power, high speed operation. Data paths are fully differential from input to output for low noise generation and low pulse width distortion. The nonblocking design allows connection of any input to any output or outputs. LVDS I/O enable high speed data transmission for point-to-point interconnects. This device can be used as a high speed differential crosspoint, 2:1 mux, 1:2 demux, repeater or 1:2 signal splitter. The mux and demux functions are useful for switching between primary and backup circuits in fault tolerant systems. The 1:2 signal splitter and 2:1 mux functions are useful for distribution of serial bus across several rack-mounted backplanes. 1 2 • • • • • • • • • • • • • DC - 800 Mbps Low Jitter, Low Skew Operation 65 ps (typ) of Pk-Pk Jitter with PRBS = 223−1 Data Pattern at 800 Mbps Single +3.3 V Supply Less than 330 mW (typ) Total Power Dissipation Non-Blocking "'Switch Architecture"' Balanced Output Impedance Output Channel-to-Channel Skew is 35 ps (typ) Configurable as 2:1 mux, 1:2 demux, Repeater or 1:2 Signal Splitter LVDS Receiver Inputs Accept LVPECL Signals Fast Switch Time of 1.2ns (typ) Fast Propagation Delay of 1.3ns (typ) Receiver Input Threshold < ±100 mV Available in 16 Lead TSSOP and SOIC Packages Conforms to ANSI/TIA/EIA-644-1995 LVDS Standard Operating Temperature: −40°C to +85°C The DS90CP22 accepts LVDS signal levels, LVPECL levels directly or PECL with attenuation networks. The individual LVDS outputs can be put into TRISTATE by use of the enable pins. For more details, please refer to the Application Information section of this datasheet. Connection Diagram Figure 1. SOIC-16 Package or TSSOP-16 Package 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2013, Texas Instruments Incorporated DS90CP22 SNLS053E – MARCH 2000 – REVISED APRIL 2013 www.ti.com Figure 2. Diff. Output Eye-Pattern in 1:2 split mode @ 800 Mbps Conditions: 3.3 V, PRBS = 223−1 data pattern, VID = 300mV, VCM = +1.2 V, 200 ps/div, 100 mV/div These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) −0.3V to +4V Supply Voltage (VCC) −0.3V to (VCC + 0.3V) CMOS/TTL Input Voltage (EN0, EN1, SEL0, SEL1) LVDS Receiver Input Voltage (IN+, IN−) −0.3V to +4V LVDS Driver Output Voltage (OUT+, OUT−) −0.3V to +4V LVDS Output Short Circuit Current Continuous Junction Temperature +150°C −65°C to +150°C Storage Temperature Range Lead Temperature (Soldering, 4 sec.) Maximum Package Power Dissipation at 25°C +260°C 16L SOIC 1.435 W 16L SOIC Package Derating 11.48 mW/°C above +25°C 16L TSSOP 0.866 W 16L TSSOP Package Derating ESD Rating 9.6 mW/°C above +25°C (HBM, 1.5kΩ, 100pF) > 5 kV (EIAJ, 0Ω, 200pF) (1) (2) > 250 V If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. “Absolute Maximum Ratings” are these beyond which the safety of the device cannot be verified. They are not meant to imply that the device should be operated at these limits. “Electrical Characteristics” provides conditions for actual device operation. Recommended Operating Conditions Supply Voltage (VCC) Receiver Input Voltage Typ Max Units 3.0 3.3 3.6 V 0 Operating Free Air Temperature 2 Min -40 Submit Documentation Feedback +25 VCC V +85 °C Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90CP22 DS90CP22 www.ti.com SNLS053E – MARCH 2000 – REVISED APRIL 2013 Electrical Characteristics (1) Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Conditions Min Typ Max Units V CMOS/TTL DC SPECIFICATIONS (EN0,EN1,SEL0,SEL1) VIH High Level Input Voltage 2.0 VCC VIL Low Level Input Voltage GND 0.8 V IIH High Level Input Current VIN = 3.6V or 2.0V; VCC = 3.6V +20 μA IIL Low Level Input Current VIN = 0V or 0.8V; VCC = 3.6V VCL Input Clamp Voltage ICL = −18 mA +7 ±1 ±10 μA −0.8 −1.5 V LVDS OUTPUT DC SPECIFICATIONS (OUT0,OUT1) VOD Differential Output Voltage ΔVOD RL = 75Ω 270 365 475 mV RL = 75Ω, VCC = 3.3V, TA = 25°C 285 365 440 mV 35 mV Change in VOD between Complimentary Output States (2) VOS Offset Voltage ΔVOS Change in VOS between Complimentary Output States 1.0 IOZ Output TRI-STATE Current TRI-STATE Output, 1.2 ±1 1.45 V 35 mV ±10 μA VOUT = VCC or GND IOFF Power-Off Leakage Current VCC = 0V; VOUT = 3.6V or GND ±1 ±10 μA IOS Output Short Circuit Current VOUT+ OR VOUT− = 0V −15 −25 mA IOSB Both Outputs Short Circuit Current VOUT+ AND VOUT− = 0V −30 −50 mA 0 +100 mV LVDS RECEIVER DC SPECIFICATIONS (IN0,IN1) VTH Differential Input High Threshold VCM = +0.05V or +1.2V or +3.25V, VTL Differential Input Low Threshold Vcc = 3.3V −100 VCMR Common Mode Voltage Range VID = 100mV, Vcc = 3.3V 0.05 IIN Input Current 0 mV 3.25 V VIN = +3.0V, VCC = 3.6V or 0V ±1 ±10 μA VIN = 0V, VCC = 3.6V or 0V ±1 ±10 μA SUPPLY CURRENT ICCD Total Supply Current RL = 75Ω, CL = 5 pF, EN0 = EN1 = High 98 125 mA ICCZ TRI-STATE Supply Current EN0 = EN1 = Low 43 55 mA Max Units (1) (2) All typical are given for VCC = +3.3V and TA = +25°C, unless otherwise stated. VOS is defined and measured on the ATE as (VOH + VOL) / 2. AC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified (1) Symbol TSET Min Typ Input to SEL Setup Time (2), (Figure 3 and Figure 4) Parameter Conditions 0.7 0.5 (2) ns THOLD Input to SEL Setup Time , (Figure 3 and Figure 4) 1.0 0.5 TSWITCH SEL to Switched Output, (Figure 3 and Figure 4) 0.9 1.2 1.7 ns TPHZ Disable Time (Active to TRI-STATE) High to Z, Figure 5 2.1 4.0 ns TPLZ Disable Time (Active to TRI-STATE) Low to Z, Figure 5 3.0 4.5 ns TPZH Enable Time (TRI-STATE to Active) Z to High, Figure 5 25.5 55.0 ns TPZL Enable Time (TRI-STATE to Active) Z to Low, Figure 5 25.5 55.0 ns TLHT Output Low-to-High Transition Time, 20% to 80%, Figure 7 290 400 580 ps THLT Output High-to-Low Transition Time, 80% to 20%, Figure 7 290 400 580 ps (1) (2) ns The parameters are specified by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage and temperature) range. TSET and THOLD time specify that data must be in a stable state before and after the SEL transition. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90CP22 3 DS90CP22 SNLS053E – MARCH 2000 – REVISED APRIL 2013 www.ti.com AC Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified(1) Symbol Parameter Conditions TJIT Max Units 40 90 ps 65 120 ps 0.9 1.3 1.6 ns 1.0 1.3 1.5 ns 0.9 1.3 1.6 ns 1.0 23 VID = 300mV; PRBS=2 -1 data pattern; VCM = 1.2V at 800Mbps Propagation Low to High Delay, Figure 8 Propagation Low to High Delay, Figure 8 TPHLD Typ VID = 300mV; 50% Duty Cycle; VCM = 1.2V at 800Mbps LVDS Data Path Peak to Peak Jitter (3) TPLHD Min VCC = 3.3V, TA = 25°C Propagation High to Low Delay, Figure 8 1.3 1.5 ns TSKEW Propagation High to Low Delay, Figure 8 Pulse Skew |TPLHD - TPHLD| 0 225 ps TCCS Output Channel-to-Channel Skew, Figure 9 35 80 ps (3) VCC = 3.3V, TA = 25°C The parameters are specified by design. The limits are based on statistical analysis of the device performance over PVT range with the following equipment test setup: HP70004A (display mainframe) with HP70841B (pattern generator), 5 feet of RG-142 cable with DUT test board and HP83480A (digital scope mainframe) with HP83483A (20GHz scope module). AC Timing Diagrams Figure 3. Input-to-Select rising edge setup and hold times and mux switch time Figure 4. Input-to-Select falling edge setup and hold times and mux switch time 4 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90CP22 DS90CP22 www.ti.com SNLS053E – MARCH 2000 – REVISED APRIL 2013 Figure 5. Output active to TRI-STATE and TRI-STATE to active output time Figure 6. LVDS Output Load Figure 7. LVDS Output Transition Time Figure 8. Propagation Delay Low-to-High and High-to-Low Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90CP22 5 DS90CP22 SNLS053E – MARCH 2000 – REVISED APRIL 2013 www.ti.com Figure 9. Output Channel-to-Channel Skew in 1:2 splitter mode PIN DESCRIPTIONS 6 Pin Name # of Pin Input/Output IN+ 2 I Non-inverting LVDS input Description IN - 2 I Inverting LVDS input OUT+ 2 O Non-inverting LVDS Output OUT - 2 O Inverting LVDS Output EN 2 I A logic low on the Enable puts the LVDS output into TRI-STATE and reduces the supply current SEL 2 I 2:1 mux input select GND 1 P Ground VCC 1 P Power Supply NC 2 No Connect Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90CP22 DS90CP22 www.ti.com SNLS053E – MARCH 2000 – REVISED APRIL 2013 APPLICATION INFORMATION MODES OF OPERATION The DS90CP22 provides three modes of operation. In the 1:2 splitter mode, the two outputs are copies of the same single input. This is useful for distribution / fan-out applications. In the repeater mode, the device operates as a 2 channel LVDS buffer. Repeating the signal restores the LVDS amplitude, allowing it to drive another media segment. This allows for isolation of segments or long distance applications. The switch mode provides a crosspoint function. This can be used in a system when primary and redundant paths are supported in fault tolerant applications. INPUT FAIL-SAFE The receiver inputs of the DS90CP22 do not have internal fail-safe biasing. For point-to-point and multidrop applications with a single source, fail-safe biasing may not be required. When the driver is off, the link is inactive. If fail-safe biasing is required, this can be accomplished with external high value resistors. The IN+ should be pull to Vcc with 10kΩ and the IN− should be pull to Gnd with 10kΩ. This provides a slight positive differential bias, and sets a known HIGH state on the link with a minimum amount of distortion. UNUSED LVDS INPUTS Unused LVDS Receiver inputs should be tied off to prevent the high-speed sensitive input stage from picking up noise signals. The open input to IN+ should be pull to Vcc with 10kΩ and the open input to IN− should be pull to Gnd with 10kΩ. UNUSED CONTROL INPUTS The SEL and EN control input pins have internal pull down devices. Unused pins may be tied off or left as noconnect (if a LOW state is desired). EXPANDING THE NUMBER OF OUTPUT PORTS To expand the number of output ports, more than one DS90CP22 can be used. Total propagation delay through the devices should be considered to determine the maximum expansion. For example, if 2 X 4 is desired, than three of the DS90CP22 are required. A minimum of two device propagation delays (2 x 1.3ns = 2.6ns (typ)) can be achieved. For a 2 X 8, a total of 7 devices must be used with propagation delay of 3 x 1.3ns = 3.9ns (typ). The power consumption will increase proportional to the number of devices used. PCB LAYOUT AND POWER SYSTEM BYPASS Circuit board layout and stack-up for the DS90CP22 should be designed to provide noise-free power to the device. Good layout practice also will separate high frequency or high level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (4 to 10 mils) for power/ground sandwiches. This increases the intrinsic capacitance of the PCB power system which improves power supply filtering, especially at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range 0.01 µF to 0.1 µF. It is recommended practice to use two vias at each power pin of the DS90CP22 as well as all RF bypass capacitor terminals. Dual vias reduce the interconnect inductance by up to half, thereby reducing interconnect inductance and extending the effective frequency range of the bypass components. The outer layers of the PCB may be flooded with additional ground plane. These planes will improve shielding and isolation as well as increase the intrinsic capacitance of the power supply plane system. Naturally, to be effective, these planes must be tied to the ground supply plane at frequent intervals with vias. Frequent via placement also improves signal integrity on signal transmission lines by providing short paths for image currents which reduces signal distortion. There are more common practices which should be followed when designing PCBs for LVDS signaling. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90CP22 7 DS90CP22 SNLS053E – MARCH 2000 – REVISED APRIL 2013 www.ti.com COMPATIBILITY WITH LVDS STANDARD The DS90CP22 is compatible with LVDS and Bus LVDS Interface devices. It is enhanced over standard LVDS drivers in that it is able to driver lower impedance loads with standard LVDS levels. Standard LVDS drivers provide 330mV differential output with a 100Ω load. The DS90CP22 provides 365mV with a 75Ω load or 400mV with 100Ω loads. This extra drive capability is useful in certain multidrop applications. In backplane multidrop configurations, with closely spaced loads, the effective differential impedance of the line is reduced. If the mainline has been designed for 100Ω differential impedance, the loading effects may reduce this to the 70Ω range depending upon spacing and capacitance load. Terminating the line with a 75Ω load is a better match than with 100Ω and reflections are reduced. BLOCK DIAGRAM Table 1. Function Table 8 SEL0 SEL1 OUT0 OUT1 Mode 0 0 IN0 IN0 1:2 splitter 0 1 IN0 IN1 repeater 1 0 IN1 IN0 switch 1 1 IN1 IN1 1:2 splitter Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90CP22 DS90CP22 www.ti.com SNLS053E – MARCH 2000 – REVISED APRIL 2013 Typical Performance Characteristics Diff. Output Voltage (VOD) vs. Resistive Load (RT) Peak-to-Peak Output Jitter at VCM = +0.4V vs. VID Figure 10. Figure 11. Peak-to-Peak Output Jitter at VCM = +1.2V vs. VID Peak-to-Peak Output Jitter at VCM = +1.6V vs. VID Figure 12. Figure 13. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90CP22 9 DS90CP22 SNLS053E – MARCH 2000 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision D (April 2013) to Revision E • 10 Page Changed layout of National Data Sheet to TI format ............................................................................................................ 9 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90CP22 PACKAGE OPTION ADDENDUM www.ti.com 30-Sep-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) DS90CP22M-8 NRND SOIC D 16 48 Non-RoHS & Green Call TI Level-1-235C-UNLIM -40 to 85 DS90CP22M -8 DS90CP22M-8/NOPB ACTIVE SOIC D 16 48 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 DS90CP22M -8 DS90CP22MT NRND TSSOP PW 16 92 Non-RoHS & Green Call TI Level-1-260C-UNLIM -40 to 85 DS90CP 22MT DS90CP22MT/NOPB ACTIVE TSSOP PW 16 92 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 DS90CP 22MT DS90CP22MTX/NOPB ACTIVE TSSOP PW 16 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 DS90CP 22MT DS90CP22MX-8/NOPB ACTIVE SOIC D 16 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 DS90CP22M -8 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of