DS90CR561/DS90CR562
LVDS 18-Bit Color Flat Panel Display (FPD) Link
General Description
The DS90CR561 transmitter converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fourth LVDS link. Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. The DS90CR562 receiver converts the
LVDS data streams back into 21 bits of CMOS/TTL data. At
a transmit clock frequency of 40 MHz, 18 bits of RGB data
and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 280 Mbps per
LVDS data channel. Using a 40 MHz clock, the data throughput is 105 Megabytes per second. These devices are offered
with rising edge data strobes for convenient interface with a
variety of graphics and LCD panel controllers.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
n
n
n
n
n
n
n
n
n
Up to 105 Megabyte/sec bandwidth
Narrow bus reduces cable size and cost
290 mV swing LVDS devices for low EMI
Low power CMOS design
Power-down mode
PLL requires no external components
Low profile 48-lead TSSOP package
Rising edge data strobe
Compatible with TIA/EIA-644 LVDS standard
Block Diagrams
DS90CR561
DS90CR562
DS012470-27
Order Number DS90CR561MTD
See NS Package Number MTD48
DS012470-1
Order Number DS90CR562MTD
See NS Package Number MTD48
APPLICATION
DS012470-2
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation
DS012470
www.national.com
DS90CR561/DS90CR562 LVDS 18-Bit Color Flat Panel Display (FPD) Link
July 1997
DS90CR561/DS90CR562
Connection Diagrams
DS90CR561
DS90CR562
DS012470-3
www.national.com
DS012470-4
2
Maximum Power Dissipation @ +25˚C
MTD48 (TSSOP) Package:
DS90CR561
1.98W
DS90CR562
1.89W
Package Derating:
DS90CR561
16 mW/˚C above +25˚C
DS90CR562
15 mW/˚C above +25˚C
This device does not meet 2000V ESD rating (Note 4)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
CMOS/TTL Input Voltage
CMOS/TTL Ouput Voltage
LVDS Receiver Input
Voltage
LVDS Receiver Input
Voltage
LVDS Output Short Circuit
Duration
Junction Temperature
Storage Temperature
Range
Lead Temperature
(Soldering, 4 sec.)
−0.3V to +6V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
Recommended Operating
Conditions
−0.3V to (VCC + 0.3V)
continuous
+150˚C
Supply Voltage (VCC)
Operating Free Air Temperature
(TA)
Receiver Input Range
Supply Noise Voltage (VCC)
−65˚C to +150˚C
+260˚C
Min Nom Max Units
4.5 5.0 5.5
V
−10 +25 +70
˚C
0
2.4
V
100 mVP-P
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VCC
V
0.8
V
0.1
0.3
V
−0.79
−1.5
V
± 5.1
± 10
µA
−120
mA
CMOS/TTL DC SPECIFICATIONS
VIH
High Level Input Voltage
2.0
VIL
Low Level Input Voltage
VOH
High Level Output Voltage
IOH = −0.4 mA
VOL
Low Level Output Voltage
IOL = 2 mA
GND
3.8
VCL
Input Clamp Voltage
ICL = −18 mA
IIN
Input Current
VIN = VCC, GND, 2.5V or 0.4V
IOS
Output Short Circuit Current
VOUT = 0V
4.9
V
LVDS DRIVER DC SPEClFlCATIONS
VOD
Differential Output Voltage
∆VOD
Change in VOD between
R
L
= 100Ω
250
290
450
mV
35
mV
Complimentary Output States
VCM
Common Mode Voltage
∆VCM
Change in VCM between
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
IOS
Output Short Circuit Current
VOUT = OV, RL = 100Ω
IOZ
Output TRI-STATE ® Current
Power Down = 0V, VOUT = 0V or VCC
1.1
1.25 1.375
V
35
mV
1.6
V
−2.9
−5
mA
±1
± 10
µA
+100
mV
Complimentary Output States
1.3
0.9
1.01
V
LVDS RECEIVER DC SPECIFlCATIONS
VTH
Differential Input High
Threshold
VTL
Differential Input Low Threshold
IIN
Input Current
V
CM
= +1.2V
−100
VIN = +2.4V
mV
VCC = 5.5V
VIN = 0V
± 10
± 10
µA
µA
TRANSMITTER SUPPLY CURRENT
ICCTW
ICCTG
Transmitter Supply Current,
RL = 100Ω, CL = 5 pF,
f = 32.5 MHz
34
51
mA
Worst Case
Worst Case Pattern (Figures 1, 3)
f = 37.5 MHz
36
53
mA
Transmitter Supply Current,
RL = 100Ω, CL = 5 pF,
f = 32.5 MHz
27
47
mA
16 Grayscale
Grayscale Pattern (Figures 2, 3)
f = 37.5 MHz
28
48
mA
3
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DS90CR561/DS90CR562
Absolute Maximum Ratings (Note 1)
DS90CR561/DS90CR562
Electrical Characteristics
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
1
25
µA
55
75
mA
TRANSMITTER SUPPLY CURRENT
I CCTZ
Transmitter Supply Current,
Power Down = Low
Power Down
RECEIVER SUPPLY CURRENT
ICCRW
Receiver Supply Current,
Worst Case
Worst Case Pattern (Figures 1, 4)
f = 37.5 MHz
60
80
mA
ICCRG
Receiver Supply Current,
CL = 8 pF,
f = 32.5 MHz
35
55
mA
16 Grayscale
16 Grayscale Pattern (Figures 2, 4)
f = 37.5 MHz
37
58
mA
ICCRZ
Receiver Supply Current,
Power Down = Low
1
10
µA
CL = 8 pF,
f = 32.5 MHz
Power Down
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for VCC = 5.0V and TA = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and ∆VOD).
Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF)
PLL V CC ≥ 1000V
All other pins ≥ 2000V
EIAJ (0Ω, 200 pF) ≥ 150V
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Typ
Max
Units
LLHT
Symbol
LVDS Low-to-High Transition Time (Figure 3 )
Parameter
Min
0.75
1.5
ns
LHLT
LVDS High-to-Low Transition Time (Figure 3 )
0.75
1.5
ns
TCIT
TxCLK IN Transition Time (Figure 5)
8
ns
TCCS
TxOUT Channel-to-Channel Skew (Note 5) (Figure 6)
350
ps
TPPos0
Transmitter Output Pulse Position for Bit 0 (Figure 17)
−200
150
350
ps
TPPos1
Transmitter Output Pulse Position for Bit 1
6.3
7.2
7.5
ns
TPPos2
Transmitter Output Pulse Position for Bit 2
12.8
13.6
14.6
ns
TPPos3
Transmitter Output Pulse Position for Bit 3
20
20.8
21.5
ns
TPPos4
Transmitter Output Pulse Position for Bit 4
27.2
28
28.5
ns
TPPos5
Transmitter Output Pulse Position for Bit 5
34.5
35.2
35.6
ns
TPPos6
Transmitter Output Pulse Position for Bit 6
42.2
42.6
42.9
ns
TPPos0
Transmitter Output Pulse Position for Bit 0 (Figure 17)
−100
100
300
ps
TPPos1
Transmitter Output Pulse Position for Bit 1
2.9
3.3
3.9
ns
TPPos2
Transmitter Output Pulse Position for Bit 2
6.1
6.6
7.1
ns
TPPos3
Transmitter Output Pulse Position for Bit 3
9.7
10.2
10.7
ns
TPPos4
Transmitter Output Pulse Position for Bit 4
13
13.5
14.1
ns
TPPos5
Transmitter Output Pulse Position for Bit 5
17
17.4
17.8
ns
TPPos6
Transmitter Output Pulse Position for Bit 6
20.3
20.8
21.4
ns
f = 20 MHz
f = 40 MHz
TCIP
TxCLK IN Period (Figure 7)
25
T
50
ns
TCIH
TxCLK IN High Time (Figure 7)
0.35T
0.5T
0.65T
ns
TCIL
TxCLK IN Low Time (Figure 7)
0.35T
0.5T
0.65T
ns
TSTC
TxIN Setup to TxCLK IN (Figure 7)
THTC
TxIN Hold to TxCLK IN (Figure 7)
TCCD
TxCLK IN to TxCLK OUT Delay @ 25˚C,
f = 20 MHz
14
f = 40 MHz
8
2.5
5
ns
ns
2
ns
9.7
ns
10
ms
VCC = 5.0V (Figure 9)
TPLLS
Transmitter Phase Lock Loop Set (Figure 11)
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4
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
TPDD
Parameter
Min
Typ
Transmitter Powerdown Delay (Figure 15)
Max
Units
100
ns
Note 5: This limit based on bench characterization.
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min
Typ
Max
Units
3.5
6.5
ns
2.7
6.5
ns
T
50
ns
CLHT
CMOS/TTL Low-to-High Transition Time (Figure 4)
CHLT
CMOS/TTL High-to-Low Transition Time (Figure 4)
RCOP
RxCLK OUT Period (Figure 8)
RSKM
Receiver Skew Margin (Note 6)
f = 20 MHz
1.1
ns
VCC = 5V, TA = 25˚C (Figure 18)
f = 40 MHz
700
ps
RxCLK OUT High Time (Figure 8)
f = 20 MHz
19
ns
f = 40 MHz
6
ns
ns
RCOH
25
RCOL
RxCLK OUT Low Time (Figure 8)
f = 20 MHz
21.5
f = 40 MHz
10.5
ns
RSRC
RxCLK Setup to RxCLK OUT (Figure 8)
f = 20 MHz
14
ns
f = 40 MHz
4.5
ns
f = 20 MHz
16
ns
f = 40 MHz
6
ns
RHRC
RCCD
RxCLK Hold to RxCLK OUT (Figure 8)
RxCLK IN to RxCLK OUT Delay @ 25˚C,
7.6
11.9
ns
VCC = 5.0V (Figure 10)
RPLLS
Receiver Phase Lock Loop Set (Figure 12)
10
ms
RPDD
Receiver Powerdown Delay (Figure 16)
1
µs
Note 6: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account for transmitter output skew (TCCS)
and the setup and hold time (internal data sampling window), allowing LVDS cable skew dependant on the type/length and source clock (TxCLK IN) jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle).
AC Timing Diagrams
DS012470-5
FIGURE 1. “Worst Case” Test Pattern
5
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DS90CR561/DS90CR562
Transmitter Switching Characteristics
DS90CR561/DS90CR562
AC Timing Diagrams
(Continued)
DS012470-6
Note 7: The worst case test pattern produces a maximum toggling of device digital circuitry, LVDS I/O and TTL I/O.
Note 8: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 9: Figure 1 and Figure 2 show a rising edge data strobe (TxCLK IN/RxCLK OUT).
Note 10: Recommended pin to signal mapping. Customer may choose to define differently.
FIGURE 2. “16 Grayscale” Test Pattern (Notes 7, 8, 9, 10)
DS012470-8
DS012470-9
FIGURE 3. DS90CR561 (Transmitter) LVDS Output Load and Transition Timing
DS012470-10
DS012470-11
FIGURE 4. DS90CR562 (Receiver) CMOS/TTL Output Load and Transition Timing
DS012470-15
FIGURE 5. DS90CR561 (Transmitter) Input Clock Transition Time
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6
DS90CR561/DS90CR562
AC Timing Diagrams
(Continued)
DS012470-16
Measurements at Vdiff = 0V
TCCS measured between earliest and latest initial LVDS edges.
TxCLK OUT Differential High → Low Edge for DS90CF561
TxCLK OUT Differential Low → High Edge for DS90CR561
FIGURE 6. DS90CR561 (Transmitter) Channel-to-Channel Skew and Pulse Width
DS012470-12
FIGURE 7. DS90CR561 Setup/Hold and High/Low Times
DS012470-13
FIGURE 8. DS90CR562 Setup/Hold and High/Low Times
DS012470-17
FIGURE 9. DS90CR561 (Transmitter) Clock In to Clock Out Delay
7
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DS90CR561/DS90CR562
AC Timing Diagrams
(Continued)
DS012470-18
FIGURE 10. DS90CR562 (Receiver) Clock In to Clock Out Delay
DS012470-14
FIGURE 11. DS90CR561 (Transmitter) Phase Lock Loop Set Time
DS012470-19
FIGURE 12. DS90CR562 (Receiver) Phase Lock Loop Set Time
DS012470-21
FIGURE 13. Seven Bits of LVDS in One Clock Cycle
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8
DS90CR561/DS90CR562
AC Timing Diagrams
(Continued)
DS012470-22
FIGURE 14. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CR561)
DS012470-23
FIGURE 15. Transmitter Powerdown Delay
DS012470-24
FIGURE 16. Receiver Powerdown Delay
9
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DS90CR561/DS90CR562
AC Timing Diagrams
(Continued)
DS012470-25
FIGURE 17. Transmitter LVDS Output Pulse Position Measurement
DS012470-26
SW — Setup and Hold Time (Internal data sampling window)
TCCS — Transmitter Output Skew
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)
Cable Skew — Typically 10 ps–40 ps per foot
FIGURE 18. Receiver LVDS Input Skew Margin
DS90CR561 Pin Description—FPD Link Transmitter
I/O
No.
TxIN
Pin Name
I
21
TxOUT+
O
3
Positive LVDS differential data output
TxOUT−
O
3
Negative LVDS differential data output
FPSHIFT IN
I
1
TTL level clock input. The rising edge acts as data strobe.
TxCLK OUT+
O
1
Positive LVDS differential clock output
TxCLK OUT−
O
1
Negative LVDS differential clock output
PWR DOWN
I
1
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power
down.
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Description
TTL Level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines (FPLINE,
FPFRAME, DRDY). (Also referred to as HSYNC, VSYNC and DATA ENABLE.)
10
I/O
No.
VCC
Pin Name
I
4
Power supply pins for TTL inputs
GND
I
5
Ground pins for TTL inputs
PLL VCC
I
1
Power supply pin for PLL
PLL GND
I
2
Ground pins for PLL
LVDS VCC
I
1
Power supply pin for LVDS outputs
LVDS GND
I
3
Ground pins for LVDS outputs
DS90CR561/DS90CR562
DS90CR561 Pin Description—FPD Link Transmitter
(Continued)
Description
DS90CR562 Pin Description—FPD Link Receiver
Pin Name
RxIN+
I/O
No.
I
3
Positive LVDS differential data inputs
Description
Negative LVDS differential data inputs
RxIN−
I
3
RxOUT
O
21
RxCLK IN+
I
1
Positive LVDS differential clock input
RxCLK IN−
I
1
Negative LVDS differential clock input
FPSHIFT OUT
O
1
TTL level clock output. The rising edge acts as data strobe.
PWR DOWN
I
1
TTL level input. Assertion (low input) maintains the receiver outputs in the previous state.
VCC
I
4
Power supply pins for TTL outputs
GND
I
5
Ground pins for TTL outputs
PLL VCC
I
1
Power supply for PLL
PLL GND
I
2
Ground pin for PLL
LVDS VCC
I
1
Power supply pin for LVDS inputs
LVDS GND
I
3
Ground pins for LVDS inputs
TTL level outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines (FPLINE,
FPFRAME, DRDY). (Also referred to as HSYNC, VSYNC and DATA ENABLE.)
11
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DS90CR561/DS90CR562 LVDS 18-Bit Color Flat Panel Display (FPD) Link
Physical Dimensions
inches (millimeters) unless otherwise noted
48-Lead Molded Thin Shrink Small Outline Package, JEDEC
NS Package Number MTD48
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
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Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
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2. A critical component is any component of a life
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can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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Response Group
Tel: 65-2544466
Fax: 65-2504466
Email: ap.support@nsc.com
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Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
National P/N DS90CR561 - LVDS 18-Bit Color Flat Panel Display (FPD) Link
See Displays Products
Products > Analog - Flat Panel Display > Flat Panel Display Link > DS90CR561
DS90CR561 Product Folder
LVDS 18-Bit Color Flat Panel Display (FPD) Link
See Also: DS90C363A - 3V supply
Generic P/N 90CR561
General
Description
Features
Package
& Models
Datasheet
Parametric Table
Samples
& Pricing
Application
Notes
Parametric Table
Supply Voltage
5V
Graphic Bits (bit)
6
Pixel Clock
20 - 40 MHz
Strobe Edge
Rising
Function
Transmitter
Datasheet
Size in
Date
Kbytes
Title
DS90CR561 DS90CR562 LVDS 18-Bit Color Flat Panel
Display (FPD) Link
DS90CR561 DS90CR562 LVDS 18-Bit Color Flat Panel
Display (FPD) Link (JAPANESE)
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Samples &
Pricing
Electronic
Orders
SPICE IBIS
Qty $US each
Models
TSSOP
48
MSL
Full
production
N/A
N/A
DS90CR561MTDX TSSOP
48
MSL
Full
production
N/A
N/A
DS90CR561MTD
24 Hour
Samples
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Size
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Marking
1K+
$5.9500
rail
of
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National P/N DS90CR561 - LVDS 18-Bit Color Flat Panel Display (FPD) Link
Die
Full
production
Wafer
Full
production
DS90CR561 MDC
DS90CR561 MWC
N/A
N/A
N/A
tray
of
N/A
-
wafer
jar
of
N/A
-
Samples
N/A
General Description
The DS90CR561 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential
Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over
a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The
DS90CR562 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit
clock frequency of 40 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME,
DRDY) are transmitted at a rate of 280 Mbps per LVDS data channel. Using a 40 MHz clock, the data
throughput is 105 Megabytes per second. These devices are offered with rising edge data strobes for
convenient interface with a variety of graphics and LCD panel controllers.
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL
interfaces.
Features
●
●
●
●
●
●
●
●
●
Up to 105 Megabyte/sec bandwidth
Narrow bus reduces cable size and cost
290 mV swing LVDS devices for low EMI
Low power CMOS design
Power-down mode
PLL requires no external components
Low profile 48-lead TSSOP package
Rising edge data strobe
Compatible with TIA/EIA-644 LVDS standard
Application Notes
Size in
Date
Kbytes
Title
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5AN-1032: Application Note 1032 An Introduction to FPD 80
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98
Application Note 1032 An Introduction to FPD Link
(JAPANESE)
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National P/N DS90CR562 - LVDS 18-Bit Color Flat Panal Display (FPD) Link
See Flat Panel Display
Products
Products > Analog - Flat Panel Display > Flat Panel Display Link > DS90CR562
DS90CR562 Product Folder
LVDS 18-Bit Color Flat Panal Display (FPD) Link
See Also: DS90CF364A - 3V supply
Generic P/N 90CR562
General
Description
Features
Package
& Models
Datasheet
Parametric Table
Samples
& Pricing
Parametric Table
Supply Voltage
5V
Graphic Bits (bit)
6
Pixel Clock
20 - 40 MHz
Strobe Edge
Rising
Function
Receiver
Datasheet
Size in
Date
Kbytes
Title
DS90CR561 DS90CR562 LVDS 18-Bit Color Flat Panel
Display (FPD) Link
DS90CR561 DS90CR562 LVDS 18-Bit Color Flat Panel
Display (FPD) Link (JAPANESE)
View Online Download
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Package Availability, Models, Samples & Pricing
Part Number
Package
Status
Type Pins MSL
Budgetary
Samples &
Pricing
Electronic
Orders
SPICE IBIS
Qty $US each
Models
TSSOP
48
MSL
Full
production
N/A
N/A
DS90CR562MTDX TSSOP
48
MSL
Full
production
N/A
N/A
DS90CR562MTD
24 Hour
Samples
Buy Now
Std
Pack
Size
Package
Marking
1K+
$5.9500
rail
of
38
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DS90CR562MTD
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1K+
$5.9500
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1000
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DS90CR562MTD
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file:///H|/imaging/BITTING/cpl/20020808_1/08062002_10/NATL/08062002_HTML/DS90CR562.html (1 of 2) [Aug-09-2002 10:07:25 AM]
National P/N DS90CR562 - LVDS 18-Bit Color Flat Panal Display (FPD) Link
Die
Full
production
Wafer
Full
production
DS90CR562 MDC
DS90CR562 MWC
N/A
N/A
N/A
Samples
N/A
tray
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N/A
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wafer
jar
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General Description
The DS90CR561 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential
Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over
a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The
DS90CR562 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit
clock frequency of 40 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME,
DRDY) are transmitted at a rate of 280 Mbps per LVDS data channel. Using a 40 MHz clock, the data
throughput is 105 Megabytes per second. These devices are offered with rising edge data strobes for
convenient interface with a variety of graphics and LCD panel controllers.
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL
interfaces.
Features
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Up to 105 Megabyte/sec bandwidth
Narrow bus reduces cable size and cost
290 mV swing LVDS devices for low EMI
Low power CMOS design
Power-down mode
PLL requires no external components
Low profile 48-lead TSSOP package
Rising edge data strobe
Compatible with TIA/EIA-644 LVDS standard
[Information as of 5-Aug-2002]
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