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DS90LT012AH
SNLS199B – SEPTEMBER 2005 – REVISED JANUARY 2019
DS90LT012AH high temperature 3-V LVDS differential line receiver
1 Features
3 Description
•
•
•
•
•
•
The DS90LT012AH is a single CMOS differential line
receiver designed for applications requiring ultra-low
power dissipation, low noise, and high data rates.
The devices are designed to support data rates in
excess of 400 Mbps (200 MHz) using Low Voltage
Differential Swing (LVDS) technology
1
•
•
•
•
•
•
–40°C to +125°C Temperature Range Operation
Compatible With ANSI TIA/EIA-644-A Standard
>400-Mbps (200-MHz) Switching Rates
100-ps Differential Skew (Typical)
3.5-ns Maximum Propagation Delay
Integrated Line Termination Resistor (100 Ω
Typical)
Single 3.3-V Power Supply Design (2.7-V to 3.6-V
Range)
Power-Down High Impedance on LVDS Inputs
LVDS Inputs Accept LVDS/CML/LVPECL Signals
Pinout Simplifies PCB Layout
Low Power Dissipation (10 mW Typical at 3.3-V
Static)
5-Pin SOT-23 Package
2 Applications
•
•
•
•
•
•
•
•
•
•
Board-to-Board Communication
Test and Measurement
LED Video Walls
Motor Drives
Wireless Infrastructure
Telecom Infrastructure
Multi-Function Printers
NIC Cards
Rack Servers
Ultrasound Scanners
Connection Diagram
The DS90LT012AH accepts low voltage (350 mV
typical) differential input signals and translates them
to 3-V CMOS output levels. The DS90LT012AH
includes an input line termination resistor for point-topoint applications.
The DS90LT012AH and companion LVDS line driver
DS90LV011AH provide a new alternative to high
power PECL/ECL devices for high-speed interface
applications.
Device Information(1)
PART NUMBER
DS90LT012AH
PACKAGE
SOT-23 (5)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90LT012AH
SNLS199B – SEPTEMBER 2005 – REVISED JANUARY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
4
5
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
8.4 Device Functional Modes........................................ 10
9
Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application .................................................. 10
10 Power Supply Recommendations ..................... 14
10.1 Power Supply Considerations............................... 14
11 Layout................................................................... 14
11.1 Layout Guidelines ................................................. 14
11.2 Layout Example ................................................... 18
12 Device and Documentation Support ................. 19
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
13 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2013) to Revision B
Page
•
Removed NRND disclaimer from the data sheet ................................................................................................................... 1
•
Changed data sheet text and format to TI's latest documentation standards ........................................................................ 1
•
Moved the ESD Ratings to the ESD Ratings table ............................................................................................................... 4
•
Changed and moved thermal resistance (θJA) parameter in the Absolute Maximum Ratings table to the Thermal
Information table .................................................................................................................................................................... 4
•
Removed the duplicate Truth Table that shared the same information found in the DS90LT012AH Receiver
Function table ......................................................................................................................................................................... 8
Changes from Original (April 2013) to Revision A
•
2
Page
Changed layout of National Data Sheet to TI format ............................................................................................................. 1
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5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
VDD
1
I
Power supply pin, +3.3 V ± 0.3 V
GND
2
I
Ground pin
IN+
3
I
Non-inverting reciever input pin
IN-
4
I
Inverting reciever input pin
TTL OUT
5
O
LVTTL/LVCMOS reciever output pin
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6 Specifications
6.1 Absolute Maximum Ratings
(1)
MIN
MAX
UNIT
Supply Voltage (VDD)
−0.3
4
V
Input Voltage (IN+, IN−)
−0.3
3.9
V
Output Voltage (TTL OUT)
−0.3
VDD + 0.3
V
Output Short Circuit Current
−100
mA
902
mW
DBV Package
Maximum Package Power Dissipation at
+25°C
Derate DBV Package (above +25°C)
7.22
mW/°C
Lead Temperature Range Soldering
(4 sec.)
260
°C
150
°C
150
°C
Maximum Junction Temperature
−65
Storage Temperature, Tstg
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) (1.5 kΩ, 100 pF)
2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
2000
EIAJ (0 Ω, 200 pF)
700
IEC direct (330 Ω, 150 pF)
7000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±XXX
V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000
V may actually have higher performance.
6.3 Recommended Operating Conditions
MIN
TYP
MAX
UNIT
Supply Voltage (VDD)
+2.7
+3.3
+3.6
V
Ambient Temperature (TA)
−40
25
+125
°C
+130
°C
Junction Temperature (T(J)
6.4 Thermal Information
DS90LT012AH
THERMAL METRIC (1)
DBV (SOT-23)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
179
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
105.5
°C/W
RθJB
Junction-to-board thermal resistance
44.7
°C/W
ψJT
Junction-to-top characterization parameter
20.4
°C/W
ψJB
Junction-to-board characterization parameter
44.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.
(1)
(2)
4
(1) (2)
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
unless otherwise specified (such as VID).
All typicals are given for: VDD = +3.3 V and TA = +25°C.
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Electrical Characteristics (continued)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.
PARAMETER
TEST CONDITIONS
VTH
Differential Input High Threshold
VTL
Differential Input Low Threshold
VCM
Input Current (DS90LV012A)
−30
0
−30
UNIT
mV
mV
V
VDD = 3 V to 3.6 V, VID = 100 mV
V
0.05
VDD – 0.3
TA = 125°C
0.1
2.35
V
VIN = +2.8 V
−10
±1
+10
μA
−10
±1
+10
μA
+20
μA
VIN = 0 V
VIN = +3.6 V
VDD = 3.6 V or 0 V
VDD = 0 V
−20
IN+, IN−
VDD = 3.6 V or 0 V
VDD = 0 V
VIN+ = +0.4 V, VIN− = +0 V
IIND
Differential Input Current
RT
Integrated Termination Resistor
CIN
Input Capacitance
VOH
Output High Voltage
VOL
Output Low Voltage
IOL = 2 mA, VID = −200 mV
IOS
Output Short-Circuit Current
VOUT = 0V
VCL
Input Clamp Voltage
ICL = −18 mA
IDD
No Load Supply Current
Inputs Open
3
VIN+ = +2.4 V, VIN− = +2.0 V
4
μA
4
μA
4
μA
3.9
4.4
mA
100
Ω
3
pF
IN+ = IN− = GND
IOH = −0.4 mA, VID = +200 mV
2.4
3.1
V
IOH = −0.4 mA, Inputs terminated
2.4
3.1
V
2.4
3.1
IOH = −0.4 mA, Inputs shorted
(4)
MAX
2.35
VIN = 0 V
Change in Magnitude of IIN
−100
TYP
0.05
VIN = +2.8 V
(3)
MIN
VDD = 2.7 V, VID = 100 mV
VIN = +3.6 V
ΔIIN
PIN
VCM dependant on VDD (3)
Common-Mode Voltage
IIN
(1) (2)
TTL OUT
(4)
VDD
V
0.3
0.5
−15
−50
−100
mA
V
−1.5
−0.7
9
mA
V
5.4
VDD is always higher than IN+ and IN− voltage. IN+ and IN− are allowed to have voltage range −0.05 V to +2.35 V when VDD = 2.7 V
and |VID| / 2 to VDD − 0.3 V when VDD = 3.0 V to 3.6 V. VID is not allowed to be greater than 100 mV when VCM = 0.05 V to 2.35 V when
VDD = 2.7 V or when VCM = |VID| / 2 to VDD − 0.3 V when VDD = 3.0 V to 3.6 V.
Output short-circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted
at a time, do not exceed maximum junction temperature specification.
6.6 Switching Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.
(1) (2)
MIN
TYP
tPHLD
Differential Propagation Delay High to Low
PARAMETER
1
1.8
3.5
ns
tPLHD
Differential Propagation Delay Low to High
1
1.7
3.5
ns
0
100
400
ps
0
0.3
1.0
ns
0
0.4
1.5
ns
ps
(3)
MAX
tSKD1
Differential Pulse Skew |tPHLD − tPLHD|
tSKD3
Differential Part to Part Skew
(4)
tSKD4
Differential Part to Part Skew
(5)
tTLH
Rise Time
350
800
tTHL
Fall Time
175
800
fMAX
Maximum Operating Frequency
(1)
(2)
(3)
(4)
(5)
(6)
CL = 15 pF
VID = 200 mV
(Figure 9 and Figure 10)
(6)
200
250
UNIT
ps
MHz
CL includes probe and jig capacitance.
Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50 Ω, tr and tf (0% to 100%) ≤ 3 ns for IN±.
tSKD1 is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of
the same channel.
tSKD3, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
at the same VDD and within 5°C of each other within the operating temperature range.
tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
over the recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min|
differential propagation delay.
fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, differential (1.05 V to 1.35 peak to peak). Output criteria:
60%/40% duty cycle, VOL (max 0.4 V), VOH (min 2.4 V), load = 15 pF (stray plus probes). The parameter is specified by design. The limit
is based on the statistical analysis of the device over the PVT range by the transition times (tTLH and tTHL).
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6.7 Typical Characteristics
6
Figure 1. Power Supply Current vs Power Supply Voltage
Figure 2. Output Short-Circuit Current vs Power Supply
Voltage
Figure 3. Output High Voltage vs Power Supply Voltage
Figure 4. Output Low Voltage vs Power Supply Voltage
Figure 5. Differential Propagation Delay High to Low vs
Power Supply Voltage at 1 MHz
Figure 6. Differential Propagation Delay High to Low vs
Power Supply Voltage at 250 MHz
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Typical Characteristics (continued)
Figure 7. Differential Propagation Delay Low to High vs
Power Supply Voltage at 1 MHz
Figure 8. Differential Propagation Delay Low to High vs
Power Supply Voltage at 250 MHz
7 Parameter Measurement Information
Figure 9. Receiver Propagation Delay and Transition Time Test Circuit
Figure 10. Receiver Propagation Delay and Transition Time Waveforms
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8 Detailed Description
8.1 Overview
The DS90LT012AH is a single-channel, low-voltage differential signaling (LVDS) line receiver. It operates from a
single power supply that is nominally 3.3 V, but the supply can be as low as 3 V and as high as 3.6 V. The input
to the DS90LT012AH is a differential signal complying with the LVDS Standard (TIA/EIA-644), and the output is a
3.3-V LVCMOS/LVTTL signal. The differential input signal operates with a signal level of 340 mV, nominally, at a
common-mode voltage of 1.2 V. The differential nature of the inputs provides immunity to common-mode
coupled signals that the driven signal may experience. A termination resistor of 100 Ω is intergrated into
DS90LT012AH.
LVDS receivers are intended to be primarily used in an point-to-point configuration. This configuration provides a
clean signaling environment for the fast edge rates of the drivers. The receiver is connected to the driver through
a balanced media which may be a standard twisted-pair cable, a parallel pair cable, or simply PCB traces.
Typically the characteristic impedance of the media is in the range of 100 Ω. The intergrated termination resistor
converts the driver output (current mode) into a voltage without the need for external termination and is detected
by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a midstream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin
limits, and total termination loading must be taken into account.
8.2 Functional Block Diagram
IN +
LVCMOS/
LVTTL OUT
IN -
8.3 Feature Description
The DS90LT012AH is capable of detecting signals as low as 100 mV, over a ±1-V common-mode range
centered around 1.2 V. The AC parameters of the input pins are optimized for a recommended operating input
voltage range of 0 V to 2.4 V (measured from each pin to ground). The device will operate for receiver input
voltages up to VDD, but exceeding VDD will turn on the ESD protection circuitry which will clamp the bus voltages.
Table 1. DS90LT012AH Receiver Function
INPUTS
OUTPUT
VID = [IN+] − [IN−]
TTL OUT
VID ≥ 0 V
H
VID ≤ −0.1 V
L
Full Fail-safe OPEN/SHORT or Terminated
H
8.3.1 Termination
DS90LT012AH integrates the terminating resistor for point-to-point applications. The resistor value will be
between 90 Ω and 133 Ω.
8.3.2 Threshold
The LVDS Standard (ANSI/TIA/EIA-644-A) specifies a maximum threshold of ±100 mV for the LVDS receiver.
The DS90LT012AH supports an enhanced threshold region of −100 mV to 0 V. This is useful for fail-safe biasing.
The threshold region is shown in the Voltage Transfer Curve (VTC) in Figure 11. The typical DS90LT012AH
LVDS receiver switches at about −30 mV. Note that with VID = 0 V, the output will be in a HIGH state. With an
external fail-safe bias of +25 mV applied, the typical differential noise margin is now the difference from the
switch point to the bias point. In the example shown in Figure 11, this would be 55 mV of Differential Noise
8
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Margin (DNM) (+25 mV − (−30 mV)). With the enhanced threshold region of −100 mV to 0 V, this small external
fail-safe biasing of +25 mV (with respect to 0 V) gives a DNM of a comfortable 55 mV. With the standard
threshold region of ±100 mV, the external fail-safe biasing must be +25 mV with respect to +100 mV or +125 mV,
giving a DNM of 155 mV that is a stronger fail-safe biasing than necessary for the DS90LT012AH. If more DNM
is required, then a stronger fail-safe bias point can be set by changing resistor values.
Figure 11. VTC of the DS90LT012AH LVDS Receiver
8.3.3 Fail-Safe Feature
The LVDS receiver is a high-gain, high-speed device that amplifies a small differential signal (20 mV) to
LVCMOS/LVTTL logic levels. Due to the high gain and tight threshold of the receiver, take care to prevent noise
from appearing as a valid signal.
The receiver's internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe
protection (a stable known state of HIGH output voltage) for floating, terminated, or shorted receiver inputs.
1. Open Input Pins: It is not required to tie the receiver inputs to ground or any supply voltage. Internal failsafe
circuitry will ensure a HIGH, stable output state for open inputs.
2. Terminated Input: If the driver is disconnected (cable unplugged), or if the driver is in a power-off condition,
the receiver output will again be in a HIGH state, even with the end cable 100-Ω termination resistor across
the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable
picks up more than 10 mV of differential noise, the receiver may see the noise as a valid signal and switch.
To insure that any noise is seen as common-mode and not differential, a balanced interconnect should be
used. A twisted-pair cable will offer better balance than flat ribbon cable.
3. Shorted Inputs: If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0-V
differential input voltage, the receiver output will remain in a HIGH state. Shorted input fail-safe is not
supported across the common-mode range of the device (GND to 2.4 V). It is only supported with inputs
shorted and no external common-mode voltage applied.
External lower value pullup and pulldown resistors (for a stronger bias) may be used to boost fail-safe in the
presence of higher noise levels. The pullup and pulldown resistors should be in the 5-kΩ to 15-kΩ range to
minimize loading and waveform distortion to the driver. The common-mode bias point should be set to
approximately 1.2 V (less than 1.75 V) to be compatible with the internal circuitry.
The DS90LT012AH is compliant to the original ANSI EIA/TIA-644 specification and is also compliant to the new
ANSI EIA/TIA-644-A specification with the exception of the newly added ΔIIN specification. Due to the internal
fail-safe circuitry, ΔIIN cannot meet the 6-µA maximum specified. This exception will not be relevant unless more
than 10 receivers are used.
Additional information on the fail-safe biasing of LVDS devices may be found in AN-1194 Failsafe Biasing of
LVDS Interfaces (SNLA051).
8.3.4 Probing LVDS Transmission Lines
Always use high impedance (> 100 kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz)
scope. Improper probing will give deceiving results.
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8.3.5 Cables and Connectors, General Comments
When choosing cable and connectors for LVDS, it is important to remember:
• Use controlled impedance media. The cables and connectors used should have a matched differential
impedance of about 100 Ω. They should not introduce major impedance discontinuities.
• Balanced cables (that is, twisted-pair) are usually better than unbalanced cables (ribbon cable, simple coax)
for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling
effects and also tend to pick up electromagnetic radiation and common-mode (not differential mode) noise
rejected by the receiver.
• For cable distances < 0.5 M, most cables can be made to work effectively. For distances 0.5 M ≤ d ≤ 10 M,
CAT 3 (category 3) twisted-pair cable works well, and this cable is readily available and relatively
inexpensive.
8.4 Device Functional Modes
The device has one mode of operation that applies when operated within the Recommended Operating
Conditions.
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DS90LT012AH device is a single-channel LVDS receiver. The functionality of this device is simple, yet
extremely flexible, leading to its use in designs ranging from wireless base stations to desktop computers. The
varied class of potential applications share features and applications are discussed in the Typical Application
section.
9.2 Typical Application
9.2.1 Point-to-Point Communications
The most basic application for LVDS buffers, as found in this data sheet, is for point-to-point communications of
digital data shown in Figure 12.
Figure 12. Typical Application
10
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Typical Application (continued)
A point-to-point communications channel has a single transmitter (driver) and a single receiver. This
communications topology is often referred to as simplex. In Figure 12, the driver receives a single-ended input
signal and the receiver outputs a single-ended recovered signal. The LVDS driver converts the single-ended
input to a differential signal for transmission over a balanced interconnecting media of 100-Ω characteristic
impedance. The conversion from a single-ended signal to an LVDS signal retains the digital data payload while
translating to a signal whose features are more appropriate for communication over extended distances or in a
noisy environment.
9.2.1.1 Design Requirements
Table 2 lists the design parameters for this example.
Table 2. Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUE
Receiver Supply Voltage (VCC)
3 to 3.6 V
Receiver Output Voltage
0 to 3.6 V
Signaling Rate
0 to 400 Mbps
Interconnect Characteristic Impedance
100 Ω
Termination Resistance
100 Ω
Number of Receiver Nodes
1
Ground shift between driver and receiver
±1 V
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Receiver Bypass Capacitance
Bypass capacitors play a key role in power distribution circuitry. Specifically, they create low-impedance paths
between power and ground. At low frequencies, a good digital power supply offers very low-impedance paths
between its terminals. However, as higher frequency currents propagate through power traces, the source is
quite often incapable of maintaining a low-impedance path to ground. Bypass capacitors are used to address this
shortcoming. Usually, large bypass capacitors (10 μF to 1000 μF) at the board-level do a good job up into the
kHz range. Due to their size and length of their leads, they tend to have large inductance values at the switching
frequencies of modern digital circuitry. To solve this problem, one must resort to the use of smaller capacitors
(nF to μF range) installed locally next to the integrated circuit.
Multilayer ceramic chip or surface-mount capacitors (size 0603 or 0805) minimize lead inductances of bypass
capacitors in high-speed environments, because their lead inductance is about 1 nH. For comparison purposes,
a typical capacitor with leads has a lead inductance around 5 nH.
The value of the bypass capacitors used locally with LVDS chips can be determined by Equation 1 and
Equation 2 according to Johnson (1) equations 8.18 to 8.21. A conservative rise time of 200 ps and a worst-case
change in supply current of 1 A covers the whole range of LVDS devices offered by Texas Instruments. In this
example, the maximum power supply noise tolerated is 200 mV. However, this figure varies depending on the
noise budget available in the design. (1)
æ DIMaximum Step Change Supply Current ö
Cchip = ç
÷ ´ TRise Time
è DVMaximum Power Supply Noise ø
(1)
æ 1A ö
CLVDS = ç
÷ ´ 200 ps = 0.001 mF
è 0.2V ø
(2)
Figure 13 lowers lead inductance and covers intermediate frequencies between the board-level capacitor (>10
µF) and the value of capacitance found above (0.001 µF). TI recommends that the user place the smallest value
of capacitance as close to the chip as possible.
(1)
Howard Johnson & Martin Graham.1993. High Speed Digital Design – A Handbook of Black Magic. Prentice Hall PRT. ISBN number
013395724.
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3.3 V
0.1 µF
0.001 µF
Figure 13. Recommended LVDS Bypass Capacitor Layout
9.2.1.2.2 Interconnecting Media
The physical communication channel between the driver and the receiver may be any balanced and paired metal
conductors meeting the requirements of the LVDS standard, the key points of which are included here. This
media may be a twisted-pair, twinax, flat ribbon cable, or PCB traces.
The nominal characteristic impedance of the interconnect should be between 100 Ω and 120 Ω with a variation of
no more than 10% (90 Ω to 132 Ω).
9.2.1.2.3 PCB Transmission Lines
As per the LVDS Owner's Manual Design Guide, 4th Edition (SNLA187), Figure 14 depicts several transmission
line structures commonly used in printed-circuit boards (PCBs). Each structure consists of a signal line and
return path with a uniform cross section along its length. A microstrip is a signal trace on the top (or bottom)
layer, separated by a dielectric layer from its return path in a ground or power plane. A stripline is a signal trace
in the inner layer, with a dielectric layer in between a ground plane above and below the signal trace. The
dimensions of the structure along with the dielectric material properties determine the characteristic impedance of
the transmission line (also called controlled-impedance transmission line).
When two signal lines are placed close by, they form a pair of coupled transmission lines. Figure 14 shows
examples of edge-coupled microstrip lines, and edge-coupled or broad-side-coupled striplines. When excited by
differential signals, the coupled transmission line is referred to as a differential pair. The characteristic impedance
of each line is called odd-mode impedance. The sum of the odd-mode impedances of each line is the differential
impedance of the differential pair. In addition to the trace dimensions and dielectric material properties, the
spacing between the two traces determines the mutual coupling and impacts the differential impedance. When
the two lines are immediately adjacent; for example, S is less than 2 W, the differential pair is called a tightlycoupled differential pair. To maintain constant differential impedance along the length, it is important to keep the
trace width and spacing uniform along the length, as well as maintain good symmetry between the two lines.
Single-Ended Microstrip
Single-Ended Stripline
W
W
T
H
T
H
§ 5.98 H ·
ln ¨
¸
1.41 © 0.8 W T ¹
87
Z0
Hr
H
Z0
Edge-Coupled
60
Hr
§ 1.9 > 2 H T @ ·
ln ¨
¨ >0.8 W T @ ¸¸
©
¹
Edge-Coupled
S
S
H
H
Differential Microstrip
Zdiff
§
2 u Z0 u ¨ 1 0.48 u e
¨
©
Differential Stripline
0.96 u
s
H
·
¸
¸
¹
Zdiff
Co-Planar Coupled
Microstrips
W
G
2.9 u
s
H
·
¸
¸
¹
Broad-Side Coupled
Striplines
W
S
§
2 u Z0 u ¨ 1 0.347e
¨
©
W
G
S
H
H
Figure 14. Controlled-Impedance Transmission Lines
12
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9.2.1.3 Application Curve
Figure 15. DS90LT012AH Performance: Cable Length vs Data Rate
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10 Power Supply Recommendations
10.1 Power Supply Considerations
The DS90LT012AH driver is designed to operate from a single power supply with the supply voltage range of 3 V
to 3.6 V. In a typical application, a driver and a receiver may be on separate boards, or even separate
equipment. In these cases, separate supplies would be used at each location. The expected ground potential
difference between the driver power supply and the receiver power supply would be less than |±1 V|. Board level
and local device level bypass capacitance should be used.
11 Layout
11.1 Layout Guidelines
11.1.1 Microstrip vs. Stripline Topologies
As per the LVDS Application and Data Handbook (SLLD009), printed-circuit boards usually offer designers two
transmission line options: Microstrip and stripline. Microstrips are traces on the outer layer of a PCB, as shown in
Figure 16.
Figure 16. Microstrip Topology
On the other hand, striplines are traces between two ground planes. Striplines are less prone to emissions and
susceptibility problems because the reference planes effectively shield the embedded traces. However, from the
standpoint of high-speed transmission, juxtaposing two planes creates additional capacitance. TI recommends
routing LVDS signals on microstrip transmission lines when possible. The PCB traces allow designers to specify
the necessary tolerances for ZO based on the overall noise budget and reflection allowances. Footnotes 1 (2), 2 (3),
and 3 (4) provide formulas for ZO and tPD for differential and single-ended traces. (2) (3) (4)
Figure 17. Stripline Topology
(2)
(3)
(4)
14
Howard Johnson & Martin Graham.1993. High Speed Digital Design – A Handbook of Black Magic. Prentice Hall PRT. ISBN number
013395724.
Mark I. Montrose. 1996. Printed Circuit Board Design Techniques for EMC Compliance. IEEE Press. ISBN number 0780311310.
Clyde F. Coombs, Jr. Ed, Printed Circuits Handbook, McGraw Hill, ISBN number 0070127549.
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Layout Guidelines (continued)
11.1.2 Dielectric Type and Board Construction
The speeds at which signals travel across the board dictates the choice of dielectric. FR-4, or equivalent, usually
provides adequate performance for use with LVDS signals. If rise or fall times of LVCMOS/LVTTL signals are
less than 500 ps, empirical results indicate that a material with a dielectric constant near 3.4, such as Rogers™
4350 or Nelco N4000-13 is better suited. Once the designer chooses the dielectric, there are several parameters
pertaining to the board construction that can affect performance. The following set of guidelines were developed
experimentally through several designs involving LVDS devices:
• Copper weight: 15 g or 1/2 oz start, plated to 30 g or 1 oz
• All exposed circuitry should be solder-plated (60/40) to 7.62 μm or 0.0003 in (minimum).
• Copper plating should be 25.4 μm or 0.001 in (minimum) in plated-through-holes.
• Solder mask over bare copper with solder hot-air leveling
11.1.3 Recommended Stack Layout
Following the choice of dielectrics and design specifications, the designer must decide how many levels to use in
the stack. To reduce the LVCMOS/LVTTL to LVDS crosstalk, it is good practice to have at least two separate
signal planes as shown in Figure 18.
Layer 1: Routed Plane (LVDS Signals)
Layer 2: Ground Plane
Layer 3: Power Plane
Layer 4: Routed Plane (TTL/CMOS Signals)
Figure 18. Four-Layer PCB Board
NOTE
The separation between layers 2 and 3 should be 127 μm (0.005 in). By keeping the
power and ground planes tightly coupled, the increased capacitance acts as a bypass for
transients.
One of the most common stack configurations is the six-layer board, as shown in Figure 19.
Layer 1: Routed Plane (LVDS Signals)
Layer 2: Ground Plane
Layer 3: Power Plane
Layer 4: Ground Plane
Layer 5: Ground Plane
Layer 4: Routed Plane (TTL Signals)
Figure 19. Six-Layer PCB Board
In this particular configuration, it is possible to isolate each signal layer from the power plane by at least one
ground plane. The result is improved signal integrity, but fabrication is more expensive. Using the 6-layer board is
preferable, because it offers the layout designer more flexibility in varying the distance between signal layers and
referenced planes in addition to ensuring reference to a ground plane for signal layers 1 and 6.
11.1.4 Separation Between Traces
The separation between traces depends on several factors, but the amount of coupling that can be tolerated
usually dictates the actual separation. Low-noise coupling requires close coupling between the differential pair of
an LVDS link to benefit from the electromagnetic field cancellation. The traces should be 100-Ω differential and
thus coupled in the manner that best fits this requirement. In addition, differential pairs should have the same
electrical length to ensure that they are balanced, thus minimizing problems with skew and signal reflection.
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Layout Guidelines (continued)
In the case of two adjacent single-ended traces, one should use the 3-W rule: the distance between two traces
must be greater than two times the width of a single trace, or three times its width measured from trace center to
trace center. This increased separation effectively reduces the potential for crosstalk. The same rule should be
applied to the separation between adjacent LVDS differential pairs, whether the traces are edge-coupled or
broad-side-coupled.
W
Differential Traces
LVDS
Pair
S=
Minimum spacing as
defined by PCB vendor
W
t2W
Single-Ended Traces
TTL/CMOS
Trace
W
Figure 20. 3-W Rule for Single-Ended and Differential Traces (Top View)
Exercise caution when using autorouters, because they do not always account for all factors affecting crosstalk
and signal reflection. For instance, it is best to avoid sharp 90° turns to prevent discontinuities in the signal path.
Using successive 45° turns tends to minimize reflections.
11.1.5 Crosstalk and Ground Bounce Minimization
To reduce crosstalk, it is important to provide a return path to high-frequency currents that is as close to its
originating trace as possible. A ground plane usually achieves this. Because the returning currents always
choose the path of lowest inductance, they are most likely to return directly under the original trace, thus
minimizing crosstalk. Lowering the area of the current loop lowers the potential for crosstalk. Traces kept as short
as possible with an uninterrupted ground plane running beneath them emit the minimum amount of
electromagnetic field strength. Discontinuities in the ground plane increase the return path inductance and should
be avoided.
11.1.6 Decoupling
Each power or ground lead of a high-speed device should be connected to the PCB through a low inductance
path. For best results, one or more vias are used to connect a power or ground pin to the nearby plane. TI
recommends placing a via immediately adjacent to the pin to avoid adding trace inductance. Placing a power
plane closer to the top of the board reduces the effective via length and its associated inductance.
VCC
Via
GND
Via
4 mil
6 mil
TOP signal layer + GND fill
VDD 1 plane
Buried capacitor
GND plane
Signal layer
>
Board thickness
approximately 100 mil
2 mil
GND plane
Signal layers
VCC plane
4 mil
6 mil
Signal layer
GND plane
Buried capacitor
VDD 2 plane
BOTTOM signal layer + GND fill
>
Typical 12-Layer PCB
Figure 21. Low Inductance, High-Capacitance Power Connection
16
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Layout Guidelines (continued)
Bypass capacitors should be placed close to VDD pins. They can be placed conveniently near the
underneath the package to minimize the loop area. This extends the useful frequency range of
capacitance. Small-physical-size capacitors, such as 0402 or even 0201, or X7R surface-mount
should be used to minimize body inductance of capacitors. Each bypass capacitor is connected to the
ground plane through vias tangent to the pads of the capacitor as shown in Figure 22(a).
corners or
the added
capacitors
power and
An X7R surface-mount capacitor of size 0402 has about 0.5 nH of body inductance. At frequencies above 30
MHz or so, X7R capacitors behave as low-impedance inductors. To extend the operating frequency range to a
few hundred MHz, an array of different capacitor values like 100 pF, 1 nF, 0.03 μF, and 0.1 μF are commonly
used in parallel. The most effective bypass capacitor can be built using sandwiched layers of power and ground
at a separation of 2 to 3 mils. With a 2-mil FR4 dielectric, there is approximately 500 pF per square inch of PCB.
Refer back to Figure 14 for some examples. Many high-speed devices provide a low-inductance GND connection
on the backside of the package. This center dap must be connected to a ground plane through an array of vias.
The via array reduces the effective inductance to ground and enhances the thermal performance of the small
Surface Mount Technology (SMT) package. Placing vias around the perimeter of the dap connection ensures
proper heat spreading and the lowest possible die temperature. Placing high-performance devices on opposing
sides of the PCB using two GND planes (as shown in Figure 14) creates multiple paths for heat transfer. Often
thermal PCB issues are the result of one device adding heat to another, resulting in a very high local
temperature. Multiple paths for heat transfer minimize this possibility. In many cases the GND dap that is so
important for heat dissipation makes the optimal decoupling layout impossible to achieve due to insufficient padto-dap spacing as shown in Figure 22(b). When this occurs, placing the decoupling capacitor on the backside of
the board keeps the extra inductance to a minimum. It is important to place the VDD via as close to the device pin
as possible while still allowing for sufficient solder mask coverage. If the via is left open, solder may flow from the
pad and into the via barrel. This will result in a poor solder connection.
VDD
IN±
0402
IN+
0402
(a)
(b)
Figure 22. Typical Decoupling Capacitor Layouts
At least two or three times the width of an individual trace should separate single-ended traces and differential
pairs to minimize the potential for crosstalk. Single-ended traces that run in parallel for less than the wavelength
of the rise or fall times usually have negligible crosstalk. Increase the spacing between signal paths for long
parallel runs to reduce crosstalk. Boards with limited real estate can benefit from the staggered trace layout, as
shown in Figure 23.
Layer 1
Layer 6
Figure 23. Staggered Trace Layout
This configuration lays out alternating signal traces on different layers. Thus, the horizontal separation between
traces can be less than 2 or 3 times the width of individual traces. To ensure continuity in the ground signal path,
TI recommends having an adjacent ground via for every signal via, as shown in Figure 24. Note that vias create
additional capacitance. For example, a typical via has a lumped capacitance effect of 1/2 pF to 1 pF in FR4.
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Layout Guidelines (continued)
Signal Via
Signal Trace
Uninterrupted Ground Plane
Signal Trace
Uninterrupted Ground Plane
Ground Via
Figure 24. Ground Via Location (Side View)
Short and low-impedance connection of the device ground pins to the PCB ground plane reduces ground
bounce. Holes and cutouts in the ground planes can adversely affect current return paths if they create
discontinuities that increase returning current loop areas.
To minimize EMI problems, TI recommends avoiding discontinuities below a trace (for example, holes, slits, and
so on) and keeping traces as short as possible. Zoning the board wisely by placing all similar functions in the
same area, as opposed to mixing them together, helps reduce susceptibility issues.
11.2 Layout Example
Figure 25. Example DS90LT012AH Layout
18
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
Rogers is a trademark of Rogers Corporation.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DS90LT012AHMF
NRND
SOT-23
DBV
5
1000
Non-RoHS
& Green
Call TI
Level-1-260C-UNLIM
-40 to 125
N05
DS90LT012AHMF/NOPB
ACTIVE
SOT-23
DBV
5
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
N05
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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