DS90LT012AQMF/NOPB

DS90LT012AQ www.ti.com SNLS297E – MAY 2008 – REVISED APRIL 2013 DS90LT012AQ Automotive LVDS Differential Line Receiver Check for Samples: DS90LT012AQ FEATURES DESCRIPTION • • • • • • • The DS90LT012AQ is a single CMOS differential line receiver designed for applications requiring ultra low power dissipation, low noise, and high data rates. The devices are designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Swing (LVDS) technology 1 2 • • • • • • AECQ-100 Grade 1 -40 to +125°C Temperature Range Operation Compatible with ANSI TIA/EIA-644-A Standard >400 Mbps (200 MHz) Switching Rates 100 ps Differential Skew (Typical) 3.5 ns Maximum Propagation Delay Integrated Line Termination Resistor (100Ω Typical) Single 3.3V power supply design Power Down High Impedance on LVDS Inputs LVDS Inputs Accept LVDS/CML/LVPECL Signals Pinout Simplifies PCB Layout Low Power Dissipation (10mW Typical@ 3.3V Static) SOT-23 5-Lead Package The DS90LT012AQ accepts low voltage (350 mV typical) differential input signals and translates them to 3V CMOS output levels. The DS90LT012AQ includes an input line termination resistor for point-topoint applications. The DS90LT012AQ and companion LVDS line driver DS90LV011AQ provide a new alternative to high power PECL/ECL devices for high speed interface applications. Connection Diagram Figure 1. Top View See Package Number DBV Functional Diagram Figure 2. DS90LT012AQ Truth Table INPUTS OUTPUT [IN+] − [IN−] TTL OUT VID ≥ 0V H VID ≤ −0.1V L Full Fail-safe OPEN/SHORT or Terminated H 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2013, Texas Instruments Incorporated DS90LT012AQ SNLS297E – MAY 2008 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) −0.3V to +4V Supply Voltage (VDD) −0.3V to +3.9V Input Voltage (IN+, IN−) −0.3V to (VDD + 0.3V) Output Voltage (TTL OUT) −100mA Output Short Circuit Current Maximum Package Power Dissipation @ +25°C DBV Package 794mW Derate DBV Package 7.22 mW/°C above +25°C Package Thermal Resistance (4-Layer, 2 oz. Cu, JEDEC) θJA 138.5°C/W θJC 107.0°C/W Lead Temperature Soldering (4 sec.) +260°C Storage Temperature Range –65°C to +150°C Maximum Junction Temperature +135°C ESD Rating HBM MM (3) >250V (5) CDM (1) >8 kV (4) >1250V Absolute Maximum Ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that the devices should be operated at these limits. Electrical Characteristics specifies conditions of device operation. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Human Body Model, applicable std. JESD22-A114C Machine Model, applicable std. JESD22-A115-A Field Induced Charge Device Model, applicable std. JESD22-C101-C (2) (3) (4) (5) Recommended Operating Conditions Supply Voltage (VDD) Min Typ Max Units +3.0 +3.3 +3.6 V −40 25 +125 °C Operating Free Air Temperature (TA) Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. Symbol Parameter Conditions VCM dependant on VDD (1) (2) Pin Min VTH Differential Input High Threshold VTL Differential Input Low Threshold VCM Common-Mode Voltage VDD = 3.0V to 3.6V, VID = 100mV 0.10 IIN Input Current VIN = +2.8V −10 −10 −100 VDD = 3.6V or 0V VIN = 0V VIN = +3.6V IIND Differential Input Current VDD = 0V VIN+ = +0.4V, VIN− = +0V VIN+ = +2.4V, VIN− = +2.0V RT Integrated Termination Resistor CIN Input Capacitance (1) (2) 2 IN+, IN− IN+ = IN− = GND Typ Max Units −30 0 mV −30 V ±1 +10 μA ±1 +10 μA +20 μA 4.4 mA −20 3 mV 2.35 3.9 100 Ω 3 pF Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise specified (such as VID). All typicals are given for: VDD = +3.3V and TA = +25°C. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS90LT012AQ DS90LT012AQ www.ti.com SNLS297E – MAY 2008 – REVISED APRIL 2013 Electrical Characteristics (continued) Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (1)(2) Symbol VOH Parameter Conditions IOH = −0.4 mA, VID = +200 mV Output High Voltage VOL Min Typ TTL OUT Units 2.4 3.1 V 2.4 3.1 V IOH = −0.4 mA, Inputs shorted 2.4 3.1 IOL = 2 mA, VID = −200 mV Output Low Voltage Max IOH = −0.4 mA, Inputs terminated 0.5 V −100 mA 9 mA −15 −50 −1.5 −0.7 Output Short Circuit Current VOUT = 0V VCL Input Clamp Voltage ICL = −18 mA IDD No Load Supply Current Inputs Open VDD V 0.3 (3) IOS (3) Pin V 5.4 Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed maximum junction temperature specification. Switching Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. Symbol Parameter (1) (2) (3) (4) Conditions Min Typ Max Units tPHLD Differential Propagation Delay High to Low CL = 15 pF 1.0 1.8 3.5 ns tPLHD Differential Propagation Delay Low to High VID = 200 mV 1.0 1.7 3.5 ns tSKD1 Differential Pulse Skew |tPHLD − tPLHD| 0 100 400 ps 0 0.3 1.0 ns 0 0.4 2.5 ns 350 800 ps 175 800 tSKD3 Differential Part to Part Skew (6) tSKD4 Differential Part to Part Skew (7) tTLH Rise Time tTHL Fall Time fMAX Maximum Operating Frequency (1) (2) (3) (4) (5) (6) (7) (8) (5) (Figure 3 and Figure 4) (8) 250 ps MHz All typicals are given for: VDD = +3.3V and TA = +25°C. These parameters are ensured by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage, temperature) ranges. CL includes probe and jig capacitance. Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr and tf (0% to 100%) ≤ 3 ns for IN±. tSKD1 is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of the same channel. tSKD3, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VDD and within 5°C of each other within the operating temperature range. tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay. fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35 peak to peak). Output criteria: 60%/40% duty cycle, VOL (max 0.4V), VOH (min 2.4V), load = 15 pF (stray plus probes). Parameter Measurement Information Figure 3. Receiver Propagation Delay and Transition Time Test Circuit Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS90LT012AQ 3 DS90LT012AQ SNLS297E – MAY 2008 – REVISED APRIL 2013 www.ti.com Parameter Measurement Information (continued) Figure 4. Receiver Propagation Delay and Transition Time Waveforms Typical Applications Figure 5. Balanced System — Point-to-Point Application (DS90LT012AQ) APPLICATION INFORMATION General application guidelines and hints for LVDS drivers and receivers may be found in the following application notes: LVDS Owner's Manual (lit #550062-003), AN-808 (SNLA028), AN-977 (SNLA166), AN-971 (SNLA165), AN-916 (SNLA219), AN-805 (SNOA233), AN-903 (SNLA034). LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 5. This configuration provides a clean signaling environment for the fast edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the range of 100Ω. The internal termination resistor converts the driver output (current mode) into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. The DS90LT012AQ differential line receiver is capable of detecting signals as low as 100 mV, over a ±1V common-mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V. The driven signal is centered around this voltage and may shift ±1V around this center point. The ±1V shifting may be the result of a ground potential difference between the driver's ground reference and the receiver's ground reference, the common-mode effects of coupled noise, or a combination of the two. The AC parameters of both receiver input pins are optimized for a recommended operating input voltage range of 0V to +2.4V (measured from each pin to ground). The device will operate for receiver input voltages up to VDD, but exceeding VDD will turn on the ESD protection circuitry which will clamp the bus voltages. 4 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS90LT012AQ DS90LT012AQ www.ti.com SNLS297E – MAY 2008 – REVISED APRIL 2013 POWER DECOUPLING RECOMMENDATIONS Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended) 0.1μF and 0.001μF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the device supply pin. Additional scattered capacitors over the printed circuit board will improve decoupling. Multiple vias should be used to connect the decoupling capacitors to the power planes. A 10μF (35V) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit board between the supply and ground. PC BOARD CONSIDERATIONS Use at least 4 PCB board layers (top to bottom): LVDS signals, ground, power, TTL signals. Isolate TTL signals from LVDS signals, otherwise the TTL signals may couple onto the LVDS lines. It is best to put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s). Keep drivers and receivers as close to the (LVDS port side) connectors as possible. DIFFERENTIAL TRACES Use controlled impedance traces which match the differential impedance of your transmission medium (ie. cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave the IC (stubs should be < 10mm long). This will help eliminate reflections and ensure noise is coupled as common-mode. In fact, we have seen that differential signals which are 1mm apart radiate far less noise than traces 3mm apart since magnetic field cancellation is much better with the closer traces. In addition, noise induced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver. Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI will result! (Note that the velocity of propagation, v = c/E r where c (the speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match differential impedance and provide isolation for the differential lines. Minimize the number of vias and other discontinuities on the line. Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels. Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid discontinuities in differential impedance. Minor violations at connection points are allowable. TERMINATION The DS90LT012AQ integrates the terminating resistor for point-to-point applications. The resistor value will be between 90Ω and 133Ω. THRESHOLD The LVDS Standard (ANSI/TIA/EIA-644-A) specifies a maximum threshold of ±100mV for the LVDS receiver. The DS90LT012AQ supports an enhanced threshold region of −100mV to 0V. This is useful for fail-safe biasing. The threshold region is shown in the Voltage Transfer Curve (VTC) in Figure 6. The typical DS90LT012AQ LVDS receiver switches at about −30mV. Note that with VID = 0V, the output will be in a HIGH state. With an external fail-safe bias of +25mV applied, the typical differential noise margin is now the difference from the switch point to the bias point. In the example below, this would be 55mV of Differential Noise Margin (+25mV − (−30mV)). With the enhanced threshold region of −100mV to 0V, this small external fail-safe biasing of +25mV (with respect to 0V) gives a DNM of a comfortable 55mV. With the standard threshold region of ±100mV, the external fail-safe biasing would need to be +25mV with respect to +100mV or +125mV, giving a DNM of 155mV which is stronger fail-safe biasing than is necessary for the DS90LT012AQ. If more DNM is required, then a stronger fail-safe bias point can be set by changing resistor values. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS90LT012AQ 5 DS90LT012AQ SNLS297E – MAY 2008 – REVISED APRIL 2013 www.ti.com Figure 6. VTC of the DS90LT012AQ LVDS Receiver FAIL SAFE BIASING External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors should be in the 5kΩ to 15kΩ range to minimize loading and waveform distortion to the driver. The commonmode bias point ideally should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal circuitry. Please refer to application note AN-1194 (SNLA051), “Failsafe Biasing of LVDS Interfaces” for more information. PROBING LVDS TRANSMISSION LINES Always use high impedance (> 100kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz) scope. Improper probing will give deceiving results. CABLES AND CONNECTORS, GENERAL COMMENTS When choosing cable and connectors for LVDS it is important to remember: Use controlled impedance media. The cables and connectors you use should have a matched differential impedance of about 100Ω. They should not introduce major impedance discontinuities. Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by the receiver. For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.5M ≤ d ≤ 10M, CAT 3 (category 3) twisted pair cable works well, is readily available and relatively inexpensive. PIN DESCRIPTIONS Package Pin Number SOT-23 4 6 Pin Name Description IN− Inverting receiver input pin 3 IN+ Non-inverting receiver input pin 5 TTL OUT 1 VDD Power supply pin, +3.3V ± 0.3V 2 GND Ground pin Receiver output pin Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS90LT012AQ DS90LT012AQ www.ti.com SNLS297E – MAY 2008 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision D (April 2013) to Revision E • Page Changed layout of National Data Sheet to TI format ............................................................................................................ 6 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS90LT012AQ 7 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) DS90LT012AQMF/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 N03Q DS90LT012AQMFE/NOPB ACTIVE SOT-23 DBV 5 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 N03Q DS90LT012AQMFX/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 N03Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of