DS90LV028AQDQFTQ1

DS90LV028A-Q1 DS90LV028A-Q1 SNLS672 – AUGUST 2020 SNLS672 – AUGUST 2020 www.ti.com DS90LV028A-Q1 Automotive LVDS Dual Differential Line Receiver 1 Features 3 Description • The DS90LV028A-Q1 is a dual CMOS differential line receiver designed for applications requiring ultra low power dissipation, low noise and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology. • • • • • • • • • • AEC-Q100 qualified for automotive applications – Temperature grade 2: -40°C to +105°C >400 Mbps (200 MHz) switching rates 50 ps differential skew (typical) 0.1 ns channel-to-channel skew (typical) 2.5 ns maximum propagation delay 3.3 V power supply design Flow-through pinout Power down high impedance on LVDS inputs Low power design (18 mW at 3.3 V static) LVDS inputs accept LVDS/CML/LVPECL signals Conforms to ANSI/TIA/EIA-644 standard The DS90LV028A-Q1 accepts low voltage (350 mV typical) differential input signals and translates them to 3 V CMOS output levels. The DS90LV028A-Q1 has a flow-through design for easy PCB layout. The DS90LV028A-Q1 and companion LVDS line driver DS90LV027AQ provide a new alternative to high power PECL/ECL devices for high speed pointto-point interface applications. 2 Applications • • • Device Information (1) Electronic point of sale (EPOS) applications Automotive infotainment and cluster Automotive head unit PART NUMBER DS90LV028A-Q1 (1) PACKAGE BODY SIZE (NOM) WSON (DQF 8) 2.00 mm x 2.00 mm For all available packages, see the orderable addendum at the end of the data sheet. RIN1- R ROUT1 R ROUT2 RIN1+ RIN2- RIN2+ Functional Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: DS90LV028A-Q1 1 DS90LV028A-Q1 www.ti.com SNLS672 – AUGUST 2020 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD and Latch-Up Ratings.........................................4 6.3 Recommended Operating Conditions.........................4 6.4 Thermal Information....................................................4 6.5 Electrical Characteristics.............................................5 6.6 Switching Characteristics............................................5 6.7 Typical Performance Curves.......................................6 7 Parameter Measurement Information............................ 9 8 Detailed Description......................................................10 8.1 Overview................................................................... 10 8.2 Functional Block Diagram......................................... 10 8.3 Feature Description...................................................10 8.4 Device Functional Modes..........................................10 9 Application and Implementation.................................. 11 9.1 Application Information..............................................11 9.2 Typical Application.................................................... 11 10 Power Supply Recommendations..............................13 11 Layout........................................................................... 14 11.1 Layout Guidelines................................................... 14 11.2 Layout Examples.....................................................14 12 Device and Documentation Support..........................15 12.1 Support Resources................................................. 15 12.2 Trademarks............................................................. 15 12.3 Electrostatic Discharge Caution..............................15 12.4 Glossary..................................................................15 13 Mechanical, Packaging, and Orderable Information.................................................................... 16 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE August 2020 2 REVISION * NOTES Initial Release Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: DS90LV028A-Q1 DS90LV028A-Q1 www.ti.com SNLS672 – AUGUST 2020 5 Pin Configuration and Functions RIN1- 1 8 VCC RIN1+ 2 7 ROUT1 RIN2+ 3 6 ROUT2 RIN2- 4 5 GND Figure 5-1. DQF Package WSON 8 Pin Top View Pin Functions Pin Number Name 1 RIN1- 4 RIN2- 2 RIN1+ 3 RIN2+ 6 ROUT2 7 ROUT1 Description Inverting receiver input pin Non-inverting receiver input pin Receiver output pin 8 VCC Power supply pin, +3.3V +/- 0.3V 5 GND Ground pin Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: DS90LV028A-Q1 3 DS90LV028A-Q1 www.ti.com SNLS672 – AUGUST 2020 6 Specifications 6.1 Absolute Maximum Ratings MIN MAX UNIT Supply Voltage (VCC) −0.3 4 V Input Voltage (RIN+, RIN−) −0.3 3.9 V Output Voltage (ROUT) −0.3 VCC+0.3 V 260 °C 125 °C 150 °C Lead Temperature Range Soldering (4 sec.) Maximum Junction Temperature Storage temperature, Tstg −65 6.2 ESD and Latch-Up Ratings VALUE V(ESD) Electrostatic discharge I-Test+ Positive I-Test Latch-Up I-Test- (1) (2) Negative I-Test Latch-Up UNIT Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1250 Positive I-Test Latchup , per AEC Q100-004 at maximum ambient temperature (all signal pins) +100 mA Negative I-Test Latchup, per AEC Q100-004 at maximum ambient temperature (all signal pins except pin 3) -100 mA Negative I-Test Latchup, per AEC Q100-004 at maximum ambient temperature (pin 3) -70 mA V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. . JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions Typ Min Supply Voltage (VCC) +3.0 Receiver Input Voltage +0.5 Operating Free Air Temperature (TA) −40 +3.3 25 Max Units +3.6 V +2.1 V 105 °C 6.4 Thermal Information DS90LV028A-Q1 THERMAL METRIC(1) DQF (WSON) UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 104.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 33.3 °C/W RθJB Junction-to-board thermal resistance 27.6 °C/W ψJT Junction-to-top characterization parameter 0.3 °C/W ψJB Junction-to-board characterization parameter 27.4 °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: DS90LV028A-Q1 DS90LV028A-Q1 www.ti.com SNLS672 – AUGUST 2020 6.5 Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (1) (2) Symbol Parameter Conditions VTH Differential Input High Threshold VTL Differential Input Low Threshold Input Current VIN = 0V VIN = +3.6V VCC = 0V Output High Voltage IOH = −0.4 mA, VID (2) = +200 mV VOL Output Low Voltage IOL = 2 mA, VID (2) = −200 mV IOS Output Short Circuit Current VOUT = 0V (3) Input Clamp Voltage ICL = −18 mA ICC No Load Supply Current VID (2) = +200 mV or -200mV (1) (2) Max mV ±1 +10 uA −10 ±1 +10 uA 2.7 ROUT Units mV −10 -20 VOH VCL Typ −100 RIN+, RIN− VCC = 3.6V or 0V Min +100 VCM(1) = +1.2 V, 0.5 + (|VID|/2) V, 2.1 - (|VID|/2(2) VIN = +2.8V IIN Pin −100 −1.5 VCC +20 3.1 uA V 0.3 0.5 V −50 −15 mA 9 mA −0.8 5.4 V VCM is input common mode voltage |(VRIN+ + VRIN-)/2| VID is input differential voltage (VRIN+ - VRIN-) 6.6 Switching Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.(2) (4) (5) Symbol Parameter Conditions Min Typ Max Units tPHLD Differential Propagation Delay High to Low CL = 15 pF 1.0 1.6 2.5 ns tPLHD Differential Propagation Delay Low to High VID = 200 mV 1.0 1.7 2.5 ns tSKD1 Differential Pulse Skew |tPHLD − tPLHD| (6) (Figure 7-1 and Figure 7-2) 0 50 650 ps tSKD2 Differential Channel-to-Channel Skew-same device (7) 0 0.1 0.5 ns tSKD3 Differential Part to Part Skew (8) 0 1.0 ns tSKD4 Differential Part to Part Skew (9) 0 1.5 ns tTLH Rise Time 325 800 ps tTHL Fall Time 225 800 ps fMAX Maximum Operating Frequency (10) 250 MHz (1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise specified (such as VID). (2) All typicals are given for: VCC = +3.3V and TA = +25°C. (3) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed maximum junction temperature specification. (4) CL includes probe and jig capacitance. (5) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr and tf (0% to 100%) ≤ 3 ns for RIN. (6) tSKD1 is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of the same channel. (7) tSKD2 is the differential channel-to-channel skew of any event on the same device. This specification applies to devices having multiple receivers within the integrated circuit. (8) tSKD3, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range. (9) tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay. (10) fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35 peak to peak). Output criteria: 60%/40% duty cycle, VOL (max 0.4V), VOH (min 2.7V), load = 15 pF (stray plus probes). Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: DS90LV028A-Q1 5 DS90LV028A-Q1 www.ti.com SNLS672 – AUGUST 2020 6.7 Typical Performance Curves 6 Figure 6-1. Output High Voltage vs Power Supply Voltage Figure 6-2. Output Low Voltage vs Power Supply Voltage Figure 6-3. Output Short Circuit Current vs Power Supply Voltage Figure 6-4. Differential Transition Voltage vs Power Supply Voltage Figure 6-5. Differential Propagation Delay vs Power Supply Voltage Figure 6-6. Differential Propagation Delay vs Differential Input Voltage Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: DS90LV028A-Q1 DS90LV028A-Q1 www.ti.com SNLS672 – AUGUST 2020 Figure 6-7. Differential Propagation Delay vs Common-Mode Voltage Figure 6-9. Differential Skew vs Power Supply Voltage Figure 6-8. Transition Time vs Power Supply Voltage Figure 6-10. Differential Propagation Delay vs Load Figure 6-12. Transition Time vs Load Figure 6-11. Differential Propagation Delay vs Load Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: DS90LV028A-Q1 7 DS90LV028A-Q1 www.ti.com SNLS672 – AUGUST 2020 Figure 6-13. Transition Time vs Load 8 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: DS90LV028A-Q1 DS90LV028A-Q1 www.ti.com SNLS672 – AUGUST 2020 7 Parameter Measurement Information Figure 7-1. Receiver Propagation Delay and Transition Time Test Circuit Figure 7-2. Receiver Propagation Delay and Transition Time Waveforms Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: DS90LV028A-Q1 9 DS90LV028A-Q1 www.ti.com SNLS672 – AUGUST 2020 8 Detailed Description 8.1 Overview LVDS drivers and receivers are intended to be primarily used in a simple point-to-point configuration as is shown in Figure 9-1. This configuration provides a clean signaling environment for the fast edge rates of the drivers. The receiver is connected to the source through a impedance controlled 100 Ω differential PCB traces. A termination resistor of 100 Ω should be used, and is located as close to the receiver input pins as possible. The termination resistor converts the driver output (current mode) into a voltage that is detected by the receiver. 8.2 Functional Block Diagram RIN1- R ROUT1 R ROUT2 RIN1+ RIN2- RIN2+ 8.3 Feature Description The DS90LV028A-Q1 differential line receiver is capable of detecting signals as low as 100 mV, over a commonmode range of 0.5 + (VID/2) V to 2.1 - (VID/2) V. This is related to the driver offset voltage which is typically +1.2V. The driven signal is centered around this voltage and may shift ±0.5V around this center point. The ±0.5V shifting may be the result of a ground potential difference between the driver's ground reference and the receiver's ground reference, the common-mode effects of coupled noise, or a combination of the two. The AC parameters of both receiver input pins are optimized for a recommended operating input voltage range of +0.5V to +2.1V (measured from each pin to ground). The device will operate for receiver input voltages up to VCC, but exceeding VCC will turn on the ESD protection circuitry which will clamp the bus voltages. 8.4 Device Functional Modes Table 8-1. Truth Table (1) 10 INPUTS OUTPUT [RIN+] − [RIN−] ROUT VID ≥ 0.1V H VID ≤ −0.1V L −0.1V ≤ VID ≤ 0.1V ?(1) ? indicates state is indeterminate Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: DS90LV028A-Q1 DS90LV028A-Q1 www.ti.com SNLS672 – AUGUST 2020 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information General application guidelines and hints for LVDS drivers and receivers may be found in the LVDS application notes and design guides. 9.2 Typical Application Figure 9-1. Balanced System Point-to-Point Application 9.2.1 Design Requirements When using LVDS devices, it is important to remember to specify controlled impedance PCB traces. All components of the transmission media must have a matched differential impedance of 100 Ω. They must not introduce major impedance discontinuities. 9.2.2 Detailed Design Procedure 9.2.2.1 Power Decoupling Recommendations Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended) 0.1 μF and 0.01 μF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the device supply pin. Additional scattered capacitors over the printed circuit board will improve decoupling. Multiple vias should be used to connect the decoupling capacitors to the power planes. A 10 μF (35 V) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit board between the supply and ground. 9.2.2.2 Termination Use a termination resistor which best matches the differential impedance or your transmission line. The resistor should be between 90 Ω and 110 Ω. Remember that the current mode outputs need the termination resistor to generate the differential voltage. LVDS will not work correctly without resistor termination. Typically, connecting a single resistor across the pair at the receiver end will suffice. Surface mount 1% resistors are the best. PCB stubs, component lead, and the distance from the termination to the receiver inputs should be minimized. The distance between the termination resistor and the receiver should be < 10 mm (12 mm MAX). 9.2.2.3 Input Failsafe Biasing External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors should be in the 5 kΩ to 15 kΩ range to minimize loading and waveform distortion to the driver. The commonmode bias point ideally should be set to approximately 1.2 V to be compatible with the internal circuitry. Please refer to application note AN-1194, “Failsafe Biasing of LVDS Interfaces” (SNLA051)for more information. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: DS90LV028A-Q1 11 DS90LV028A-Q1 www.ti.com SNLS672 – AUGUST 2020 9.2.2.4 Probing LVDS Transmission Lines Always use high impedance (> 100 kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz) scope. Improper probing will give deceiving results. 9.2.3 Application Curves Figure 9-2. Power Supply Current vs Frequency 12 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: DS90LV028A-Q1 DS90LV028A-Q1 www.ti.com SNLS672 – AUGUST 2020 10 Power Supply Recommendations Bypass capacitors must be used on power pins. TI recommends using high-frequency, ceramic, 0.1-µF and 0.01-µF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the device supply pin. Additional scattered capacitors over the printed-circuit board improves decoupling. Multiple vias must be used to connect the decoupling capacitors to the power planes. A 10-µF bulk capacitor, 35-V (or greater) solid tantalum capacitor must be connected at the power entry point on the printed-circuit board between the supply and ground. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: DS90LV028A-Q1 13 DS90LV028A-Q1 www.ti.com SNLS672 – AUGUST 2020 11 Layout 11.1 Layout Guidelines 11.1.1 Differential Traces Use controlled impedance traces which match the differential impedance of your transmission trace and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave the IC (stubs should be < 10mm long). This will help eliminate reflections and ensure noise is coupled as commonmode. In fact, we have seen that differential signals which are 1mm apart radiate far less noise than traces 3mm apart since magnetic field cancellation is much better with the closer traces. In addition, noise induced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver. Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI will result! (Note that the velocity of propagation, v = c/E r where c (the speed of light) = 0.2997 mm/ps or 0.0118 in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match differential impedance and provide isolation for the differential lines. Minimize the number of vias and other discontinuities on the line. Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels. Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid discontinuities in differential impedance. Minor violations at connection points are allowable. 11.1.2 PC Board Considerations Use at least 4 PCB board layers (top to bottom): LVDS signals, ground, power, TTL signals. Isolate TTL signals from LVDS signals, otherwise the TTL signals may couple onto the LVDS lines. It is best to put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s). 11.2 Layout Examples Figure 11-1. WSON Thermal Land Pad and Pin Pads DS90LV028A DS90LV027A LVCMOS Inputs DO- 1 8 1 RIN1- VCC 16 DI 1 DO+ 1 7 2 RIN1+ ROUT1 15 3 DI 2 DO+ 2 6 3 RIN2+ ROUT2 14 4 GND DO- 2 5 4 RIN2- GND 13 1 VCC 2 Decoupling Cap (Bottom Layer) Series Termination (optional) LVCMOS Outputs Decoupling Cap (Bottom Layer) Input Termination (Required) Figure 11-2. Simplified DS90LV027A and DS90LV028A Layout 14 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: DS90LV028A-Q1 DS90LV028A-Q1 www.ti.com SNLS672 – AUGUST 2020 12 Device and Documentation Support 12.1 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.2 Trademarks TI E2E™ is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.3 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.4 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: DS90LV028A-Q1 15 DS90LV028A-Q1 www.ti.com SNLS672 – AUGUST 2020 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 16 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: DS90LV028A-Q1 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) DS90LV028AQDQFRQ1 ACTIVE WSON DQF 8 3000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 D28Q DS90LV028AQDQFTQ1 ACTIVE WSON DQF 8 250 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 D28Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of