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DS90LV031A
SNLS020D – JULY 1999 – REVISED AUGUST 2016
DS90LV031A 3-V LVDS Quad CMOS Differential Line Driver
1 Features
3 Description
•
•
•
•
•
•
•
•
•
The DS90LV031A is a quad CMOS differential line
driver designed for applications requiring ultra low
power dissipation and high data rates. The device is
designed to support data rates in excess of 400 Mbps
(200 MHz) using Low Voltage Differential Signaling
(LVDS) technology.
1
•
•
•
>400-Mbps (200-MHz) Switching Rates
0.1-ns Typical Differential Skew
0.4-ns Maximum Differential Skew
2-ns Maximum Propagation Delay
3.3-V Power Supply Design
±350-mV Differential Signaling
Low Power Dissipation (13-mW at 3.3-V Static)
Interoperable With Existing 5-V LVDS Devices
Compatible With IEEE 1596.3 SCI LVDS
Standard
Compatible With TIA/EIA-644 LVDS Standard
Industrial Operating Temperature Range
Available in SOIC and TSSOP Surface-Mount
Packaging
The DS90LV031A accepts low voltage LVTTL or
LVCMOS input levels and translates them to low
voltage (350 mV) differential output signals. In
addition the driver supports a TRI-STATE® function
that may be used to disable the output stage,
disabling the load current, and thus dropping the
device to an ultra low idle power state of 13 mW
typical.
The EN and EN* inputs allow active Low or active
High control of the TRI-STATE outputs. The enables
are common to all four drivers. The DS90LV031A and
companion line receiver (DS90LV032A) provide a
new alternative to high power psuedo-ECL devices
for high speed point-to-point interface applications.
2 Applications
•
•
Building And Factory Automation
Grid Infrastructure
Device Information(1)
PART NUMBER
DS90LV031A
PACKAGE
BODY SIZE (NOM)
SOIC (16)
9.90 mm × 3.91 mm
TSSOP (16)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram
+
RIN1
DOUT1+
R1
DOUT1-
±
+
DOUT2+
R2
RIN2
DOUT2-
±
+
DOUT3+
R3
RIN3
DOUT3-
±
+
RIN4
DOUT4+
R4
±
DOUT4-
EN
EN*
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90LV031A
SNLS020D – JULY 1999 – REVISED AUGUST 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
3
4
4
4
5
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics – Industrial .......................
Dissipation Ratings ...................................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 11
9
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 14
11.1 Layout Guidelines ................................................. 14
11.2 Layout Example .................................................... 15
12 Device and Documentation Support ................. 16
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
16
13 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2013) to Revision D
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Changes from Revision B (April 2013) to Revision C
•
2
Page
Page
Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 1
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SNLS020D – JULY 1999 – REVISED AUGUST 2016
5 Pin Configuration and Functions
D or PW Package
16-Pin SOIC or TSSOP
Top View
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
DIN
1, 7, 9, 15
I
Driver input pin, TTL/CMOS compatible
DOUT+
2, 6, 10, 14
O
Noninverting driver output pin, LVDS levels
DOUT–
3, 5, 11, 13
O
Inverting driver output pin, LVDS levels
EN
4
I
Active high enable pin, OR-ed with EN
EN
12
I
Active low enable pin, OR-ed with EN
GND
8
—
Ground pin
VCC
16
—
Power supply pin, 3.3 V ± 0.3 V
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply voltage, VCC
–0.3
4
V
Input voltage, DIN
–0.3
VCC + 0.3
V
Enable input voltage, EN, EN*
–0.3
VCC + 0.3
V
Output voltage, DOUT+, DOUT−
–0.3
3.9
V
260
°C
150
°C
150
°C
Short circuit duration, DOUT+, DOUT−
Continuous
Lead temperature, soldering (4 s)
Maximum junction temperature
Storage temperature, Tstg
(1)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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DS90LV031A
SNLS020D – JULY 1999 – REVISED AUGUST 2016
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6.2 ESD Ratings
V(ESD)
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
Electrostatic discharge
VALUE
UNIT
±6000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
VCC
Supply voltage
TA
Operating free-air temperature, industrial
MIN
NOM
MAX
UNIT
3
3.3
3.6
V
–40
25
85
°C
6.4 Thermal Information
DS90LV031A
THERMAL METRIC (1)
PW (TSSOP)
D (SOIC)
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
114
75
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
51
36
°C/W
RθJB
Junction-to-board thermal resistance
59
32
°C/W
ψJT
Junction-to-top characterization parameter
8
6
°C/W
ψJB
Junction-to-board characterization parameter
58
31.7
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SNLS020D – JULY 1999 – REVISED AUGUST 2016
6.5 Electrical Characteristics
over supply voltage and operating temperature ranges (unless otherwise noted) (1) (2) (3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
250
350
450
mV
4
35
|mV|
1.25
1.375
VOD1
Differential output voltage
RL = 100 Ω, DOUT−, DOUT+ pins (see Figure 3)
ΔVOD1
Change in magnitude of VOD1
for complementary output states
RL = 100 Ω, DOUT−, DOUT+ pins (see Figure 3)
VOS
Offset voltage
RL = 100 Ω, DOUT−, DOUT+ pins (see Figure 3)
ΔVOS
Change in magnitude of VOS
for complementary output states
RL = 100 Ω, DOUT−, DOUT+ pins (see Figure 3)
5
25
|mV|
VOH
Output voltage high
RL = 100 Ω, DOUT−, DOUT+ pins (see Figure 3)
1.38
1.6
V
VOL
Output voltage low
RL = 100 Ω, DOUT−, DOUT+ pins (see Figure 3)
VIH
Input voltage high
DIN, EN, EN* pins
2
VCC
VIL
Input voltage low
DIN, EN, EN* pins
GND
0.8
V
IIH
Input current high
VIN = VCC or 2.5 V, DIN, EN, EN* pins
±1
10
µA
IIL
Input current low
VIN = GND or 0.4 V, DIN, EN, EN* pins
−10
±1
10
µA
VCL
Input clamp voltage
ICL = –18 mA, DIN, EN, EN* pins
−1.5
−0.8
IOS
Output short circuit current
Enabled, DOUT−, DOUT+ pins (4), DIN = VCC, DOUT+
= 0 V, or DIN = GND, DOUT− = 0 V
−6
−9
mA
IOSD
Differential output short circuit
current
Enabled, VOD = 0 V, DOUT−, DOUT+ pins (4)
−6
−9
mA
IOFF
Power-off leakage
VOUT = 0 V or 3.6 V, VCC = 0 V or open, DOUT−,
DOUT+ pins
−20
±1
20
µA
IOZ
Output TRI-STATE current
EN = 0.8 V and EN* = 2 V, VOUT = 0 V or VCC,
DOUT−, DOUT+ pins
−10
±1
10
µA
ICC
No load supply current drivers
enabled
DIN = VCC or GND, VCC pin
5
8
mA
ICCL
Loaded supply current drivers
enabled
RL = 100 Ω (all channels), DIN = VCC or GND
(all inputs), VCC pin
23
30
mA
ICCZ
No load supply current drivers
disabled
DIN = VCC or GND, EN = GND, EN* = VCC, VCC
pin
2.6
6
mA
(1)
(2)
(3)
(4)
1.125
0.90
−10
V
1.03
V
V
V
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except: VOD1 and ΔVOD1.
All typicals are given for: VCC = 3.3 V, TA = 25°C.
The DS90LV031A is a current mode device and only functions within datasheet specifications when a resistive load is applied to the
driver outputs typical range is (90 Ω to 110 Ω)
Output short-circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
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6.6 Switching Characteristics – Industrial
VCC = 3.3 V ±10% and TA = –40°C to 85°C (unless otherwise noted) (1) (2) (3)
MIN
NOM
MAX
UNIT
tPHLD
Differential propagation delay
high to low
RL = 100 Ω and CL = 10 pF (see Figure 4
and Figure 5)
0.8
1.18
2
ns
tPLHD
Differential propagation delay
low to high
RL = 100 Ω and CL = 10 pF (see Figure 4
and Figure 5)
0.8
1.25
2
ns
tSKD1
Differential pulse skew (4)
|tPHLD − tPLHD|
RL = 100 Ω and CL = 10 pF (see Figure 4
and Figure 5)
0
0.07
0.4
ns
tSKD2
Channel-to-channel skew (5)
RL = 100 Ω and CL = 10 pF (see Figure 4
and Figure 5)
0
0.1
0.5
ns
tSKD3
Differential part-to-part skew (6)
RL = 100 Ω and CL = 10 pF (see Figure 4
and Figure 5)
0
1
ns
tSKD4
Differential part-to-part skew (7)
RL = 100 Ω and CL = 10 pF (see Figure 4
and Figure 5)
0
1.2
ns
tTLH
Rise time
RL = 100 Ω and CL = 10 pF (see Figure 4
and Figure 5)
0.38
1.5
ns
tTHL
Fall time
RL = 100 Ω and CL = 10 pF (see Figure 4
and Figure 5)
0.4
1.5
ns
tPHZ
Disable time high to Z
RL = 100 Ω and CL = 10 pF (see Figure 6
and Figure 7)
5
ns
tPLZ
Disable time low to Z
RL = 100 Ω and CL = 10 pF (see Figure 6
and Figure 7)
5
ns
tPZH
Enable time Z to high
RL = 100 Ω and CL = 10 pF (see Figure 6
and Figure 7)
7
ns
tPZL
Enable time Z to low
RL = 100 Ω and CL = 10 pF (see Figure 6
and Figure 7)
7
ns
fMAX
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Maximum operating frequency
(8)
200
250
MHz
All typicals are given for: VCC = 3.3 V, TA = 25°C.
Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50 Ω, tr ≤ 1 ns, and tf ≤ 1 ns.
CL includes probe and jig capacitance.
tSKD1, |tPHLD − tPLHD| is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
tSKD2 is the differential channel-to-channel skew of any event on the same device.
tSKD3, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation
delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
tSKD4, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min|
differential propagation delay.
fMAX generator input conditions: tr = tf < 1 ns, (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% / 55%, VOD >
250 mV, all channels switching.
6.7 Dissipation Ratings
MAXIMUM PACKAGE POWER DISSIPATION AT 25°C
6
D package
1088 mW
PW package
866 mW
Derate D package
8.5 mW/°C above 25°C
Derate PW package
6.9 mW/°C above 25°C
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6.8 Typical Characteristics
Figure 1. Typical DS90LV031A, DOUT (Single-Ended)
vs RL, TA = 25°C
Figure 2. Typical DS90LV031A, DOUT
vs RL, VCC = 3.3 V, TA = 25°C
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7 Parameter Measurement Information
Figure 3. Driver VOD and VOS Test Circuit
Figure 4. Driver Propagation Delay and Transition Time Test Circuit
Figure 5. Driver Propagation Delay and Transition Time Waveforms
8
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Parameter Measurement Information (continued)
Figure 6. Driver TRI-STATE Delay Test Circuit
Figure 7. Driver TRI-STATE Delay Waveforms
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8 Detailed Description
8.1 Overview
LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as
is shown in Figure 9. This configuration provides a clean signaling environment for the quick edge rates of the
drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic differential impedance of the media
is in the range of 100 Ω. A termination resistor of 100 Ω must be selected to match the media, and is located as
close to the receiver input pins as possible. The termination resistor converts the current sourced by the driver
into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver
configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as
well as ground shifting, noise margin limits, and total termination loading must be considered.
The DS90LV031A differential line driver is a balanced current source design. A current mode driver, generally
speaking has a high output impedance and supplies a constant current for a range of loads (a voltage mode
driver on the other hand supplies a constant voltage for a range of loads). Current is switched through the load in
one direction to produce a logic state and in the other direction to produce the other logic state. The output
current is typically 3.5 mA, a minimum of 2.5 mA, and a maximum of 4.5 mA. The current mode requires (as
discussed above) that a resistive termination be employed to terminate the signal and to complete the loop as
shown in Figure 9. AC or unterminated configurations are not allowed. The 3.5-mA loop current develops a
differential voltage of 350 mV across the 100-Ω termination resistor which the receiver detects with a 250-mV
minimum differential noise margin neglecting resistive line losses (driven signal minus receiver threshold
(350 mV – 100 mV = 250 mV)). The signal is centered around 1.2 V (Driver Offset, VOS) with respect to ground
as shown in Figure 8. Note that the steady-state voltage (VSS) peak-to-peak swing is twice the differential voltage
(VOD) and is typically 700 mV.
The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its
quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver
increases exponentially in most case between 20 MHz to 50 MHz. This is due to the overlap current that flows
between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed
current between its output without any substantial overlap current. This is similar to some ECL and PECL
devices, but without the heavy static ICC requirements of the ECL or PECL designs. LVDS requires >80% less
current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing
RS-422 drivers.
The TRI-STATE function allows the driver outputs to be disabled, thus obtaining an even lower power state when
the transmission of data is not required.
The footprint of the DS90LV031A is the same as the industry standard 26LS31 Quad Differential (RS-422) Driver
and is a step-down replacement for the 5-V DS90C031 Quad Driver.
10
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8.2 Functional Block Diagram
+
RIN1
DOUT1+
R1
DOUT1-
±
+
DOUT2+
R2
RIN2
DOUT2-
±
+
DOUT3+
R3
RIN3
DOUT3-
±
+
RIN4
DOUT4+
R4
±
DOUT4-
EN
EN*
Copyright © 2016, Texas Instruments Incorporated
8.3 Feature Description
8.3.1 Fail-Safe LVDS Interface
If the LVDS link as shown in Figure 9 needs to support the case where the Line Driver is disabled, powered off,
or removed (unplugged) and the Receiver device is powered on and enabled, the state of the LVDS bus is
unknown and therefore the output state of the Receiver is also unknown. If this is of concern, consult the
respective LVDS Receiver data sheet for guidance on Fail-safe Biasing options for the LVDS interface to set a
known state on the inputs for these conditions.
Figure 8. Driver Output Levels
8.4 Device Functional Modes
Table 1 lists the functional modes of DS90LV031A.
Table 1. Truth Table
ENABLES
INPUT
OUTPUTS
EN
EN*
DIN
DOUT+
L
H
X
Z
Z
L
L
H
H
H
L
All other combinations of ENABLE inputs
DOUT−
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DS90LV031A has a flow-through pinout that allows for easy PCB layout. The LVDS signals on one side of
the device easily allows for matching electrical lengths of the differential pair trace lines between the driver and
the receiver as well as allowing the trace lines to be close together to couple noise as common-mode. Noise
isolation is achieved with the LVDS signals on one side of the device and the TTL signals on the other side.
See Related Documentation for general application guidelines and hints for LVDS drivers and receivers.
9.2 Typical Application
ENABLE
Any LVDS Receiver
DATA
INPUT
RT
100Ÿ
+
DATA
OUTPUT
±
¼ DS9OLVO31A
Copyright © 2016, Texas Instruments Incorporated
Figure 9. Point-to-Point Application
9.2.1 Design Requirements
When using LVDS devices, it is important to remember to specify controlled impedance PCB traces, cable
assemblies, and connectors. All components of the transmission media must have a matched differential
impedance of about 100 Ω. They must not introduce major impedance discontinuities.
Balanced cables (for example, twisted pair) are usually better than unbalanced cables (ribbon cable) for noise
reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also
tend to pick up electromagnetic radiation as common-mode (not differential mode) noise which is rejected by the
LVDS receiver.
9.2.2 Detailed Design Procedure
9.2.2.1 Probing LVDS Transmission Lines
Always use high impedance (>100 kΩ), low capacitance (