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DS90LV032A
SNLS011D – JULY 1999 – REVISED AUGUST 2016
DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
The DS90LV032A is a quad CMOS differential line
receiver designed for applications requiring ultra-low
power dissipation and high data rates. The device is
designed to support data rates in excess of 400 Mbps
(200 MHz) using Low Voltage Differential Signaling
(LVDS) technology.
1
•
•
•
>400 Mbps (200 MHz) Switching Rates
0.1-ns Channel-to-Channel Skew (Typical)
0.1-ns Differential Skew (Typical)
3.3-ns Maximum Propagation Delay
3.3-V Power Supply Design
Power Down High Impedance on LVDS Inputs
Low Power Design (40 mW at 3.3 V Static)
Interoperable With Existing 5-V LVDS Networks
Accepts Small Swing (350 mV Typical) VID
Supports Open, Short, and Terminated Input FailSafe
Compatible With ANSI/TIA/EIA-644
Industrial Temperature Operating Range (–40°C
to 85°C)
Available in SOIC and TSSOP Packaging
The DS90LV032A accepts low voltage (350 mV
typical) differential input signals and translates them
to 3-V CMOS output levels. The receiver supports a
TRI-STATE function that may be used to multiplex
outputs. The receiver also supports open, shorted,
and terminated (100 Ω) input Fail-safe. The receiver
output is HIGH for all fail-safe conditions.
The DS90LV032A and companion LVDS line driver
(for example, DS90LV031A) provide a new
alternative to high power PECL or ECL devices for
high speed point-to-point interface applications.
Device Information(1)
2 Applications
•
•
PART NUMBER
Building And Factory Automation
Grid Infrastructure
DS90LV032A
PACKAGE
BODY SIZE (NOM)
SOIC (16)
9.90 mm × 3.91 mm
TSSOP (16)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram
RIN1+
+
RIN1-
±
RIN2+
+
RIN2-
±
RIN3+
+
RIN3-
±
RIN4+
+
RIN4-
±
R1
ROUT1
R2
ROUT2
R3
ROUT3
R4
ROUT4
EN
EN*
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90LV032A
SNLS011D – JULY 1999 – REVISED AUGUST 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
3
4
4
4
5
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Switching Characteristics ..........................................
Dissipation Ratings ...................................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 11
9
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application .................................................. 12
10 Power Supply Recommendations ..................... 14
11 Layout................................................................... 14
11.1 Layout Guidelines ................................................. 14
11.2 Layout Example .................................................... 15
12 Device and Documentation Support ................. 16
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
16
13 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2013) to Revision D
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
•
Added Thermal Information table. .......................................................................................................................................... 4
Changes from Revision B (April 2013) to Revision C
•
2
Page
Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 7
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SNLS011D – JULY 1999 – REVISED AUGUST 2016
5 Pin Configuration and Functions
D or PW Package
16-Pin SOIC or TSSOP
Top View
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
EN
4
I
Active high enable pin, OR-ed with EN
EN
12
I
Active low enable pin, OR-ed with EN
GND
8
—
RIN–
1, 7, 9, 15
I
Inverting receiver input pin
RIN+
2, 6, 10, 14
I
Noninverting receiver input pin
ROUT
3, 5, 11, 13
O
Receiver output pin
VCC
16
—
Power supply pin, 3.3 V ± 0.3 V
Ground pin
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply voltage
VCC
–0.3
4
V
Input voltage
RIN+, RIN–
–0.3
3.9
V
Enable input voltage
EN, EN*
–0.3
VCC + 0.3
V
Output voltage
ROUT
–0.3
VCC + 0.3
V
Lead temperature, soldering (4 s)
260
°C
Maximum junction temperature, TJ
150
°C
150
°C
Storage temperature, Tstg
(1)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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6.2 ESD Ratings
VALUE
Electrostatic discharge (1)
V(ESD)
(1)
Human-body model (HBM) (1)
±4500
Machine model (MM), EIAJ
±250
UNIT
V
ESD Ratings: HBM (1.5 kΩ, 100 pF) ≥ 4.5 kV and EIAJ (0 Ω, 200 pF) ≥ 250 V
6.3 Recommended Operating Conditions
VCC
MIN
NOM
MAX
3
3.3
3.6
Supply voltage
Receiver input voltage
TA
GND
Operating free-air temperature
–40
25
UNIT
V
3
V
85
°C
6.4 Thermal Information
DS90LV032A
THERMAL METRIC (1)
PW (TSSOP)
D (SOIC)
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
110
75
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
47
36
°C/W
RθJB
Junction-to-board thermal resistance
55
32
°C/W
ψJT
Junction-to-top characterization parameter
6
6
°C/W
ψJB
Junction-to-board characterization parameter
54
31.7
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over supply voltage and operating temperature ranges (unless otherwise noted) (1)
PARAMETER
VTH
Differential input high threshold
VTL
Differential input low threshold
VCMR
Common mode voltage range
IIN
VOH
VOL
Input current
Output high voltage
Output low voltage
TEST CONDITIONS
VCM = 1.2 V, RIN+, RIN– pin (2)
VID = 200 mV peak to peak, RIN+, RIN– pin (3)
VCC = 3.6 V or 0 V,
RIN+, RIN– pin
MIN
TYP
MAX
UNIT
20
100
mV
–100
–20
0.1
mV
2.3
V
VIN = 2.8 V
–10
±1
10
µA
±1
10
µA
20
µA
VIN = 0 V
–10
VCC = 0 V, VIN = 3.6 V, RIN+, RIN– pin
–20
IOH = –0.4 mA, VID = 200 mV, ROUT pin
2.7
3
V
IOH = –0.4 mA, input terminated, ROUT pin
2.7
3
V
IOH = –0.4 mA, input shorted, ROUT pin
2.7
3
IOL = 2 mA, VID = –200 mV, ROUT pin
(4)
V
0.1
0.25
V
–15
–48
–120
mA
–10
±1
10
µA
IOS
Output short-circuit current
Enabled, VOUT = 0 V, ROUT pin
IOZ
Output TRI-STATE current
Disabled, VOUT = 0 V or VCC
VIH
Input high voltage
EN, EN* pins
2
VCC
V
VIL
Input low voltage
EN, EN* pins
GND
0.8
V
II
Input current
VIN = 0 V or VCC, other input = VCC or GND,
EN, EN* pins
–10
±1
10
µA
VCL
Input clamp voltage
ICL = –18 mA, EN, EN* pins
–1.5
–0.8
No load supply current
EN, EN* = VCC or GND, inputs open, VCC pin
10
15
mA
Receivers enabled
EN, EN* = 2.4 V or 0.5 V, inputs open, VCC pin
10
15
mA
No load supply current
Receivers disabled, EN = GND, EN* = VCC,
inputs open, VCC pin
3
5
mA
ICC
ICCZ
(1)
(2)
(3)
(4)
V
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
unless otherwise specified.
VCC is always higher than RIN+ and RIN– voltage. RIN– and RIN+ are allowed to have a voltage range –0.2 V to VCC – VID / 2. However,
to be compliant with AC specifications, the common voltage range is 0.1 V to 2.3 V
The VCMR range is reduced for larger VID. Example: if VID = 400 mV, the VCMR is 0.2 V to 2.2 V. The fail-safe condition with inputs
shorted is valid over a common mode range of 0 V to 2.3 V. A VID up to VCC – 0 V may be applied to the RIN+/ RIN– inputs with the
common mode voltage set to VCC / 2. Propagation delay and differential pulse skew decrease when VID is increased from 200 mV to
400 mV. Skew specifications apply for 200 mV ≤ VID ≤ 800 mV over the common mode range.
Output short-circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output must be shorted at
a time, do not exceed maximum junction temperature specification.
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6.6 Switching Characteristics
over supply voltage and operating temperature ranges (unless otherwise noted) (1) (2)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
tPHLD
Differential propagation delay,
high to low
CL = 10 pF
1.8
3.3
ns
tPLHD
Differential propagation delay,
low to high
VID = 200 mV
1.8
3.3
ns
tSKD1
Differential pulse skew (3)
|tPHLD – tPLHD|
(4)
See Figure 4 and Figure 5
0
0.1
0.35
ns
Same device
0
0.1
0.5
ns
1
ns
tSKD2
Differential channel-to-channel skew
tSKD3
Differential part-to-part skew (5)
tSKD4
Differential part-to-part skew
(6)
1.5
ns
tTLH
Rise time
0.35
1.2
ns
tTHL
Fall time
0.35
1.2
ns
tPHZ
Disable time high to Z
RL = 2 kΩ
8
12
ns
tPLZ
Disable time low to Z
CL = 10 pF
6
12
ns
tPZH
Enable time Z to high
See Figure 6 and Figure 7
11
17
ns
tPZL
Enable time Z to low
11
17
fMAX
Maximum operating frequency (7)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
All channels switching
200
250
ns
MHz
All typicals are given for: VCC = 3.3 V, TA = 25°C.
Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50 Ω, tr and tf (0% to 100%) ≤ 3 ns for RIN.
tSKD1 is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of
the same channel
tSKD2, channel-to-channel skew, is defined as the difference between the propagation delay of one channel and that of the others on the
same chip with any event on the inputs.
tSKD3, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
at the same VCC, and within 5°C of each other within the operating temperature range.
tSKD4, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Maximum –
Minimum| differential propagation delay.
fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, differential (1.05-V to 1.35-V peak-to-peak). Output criteria:
60% / 40% duty cycle, VOL (maximum: 0.4 V), VOH (minimum: 2.7 V), load = 10 pF (stray plus probes).
6.7 Dissipation Ratings
MAXIMUM PACKAGE POWER DISSIPATION AT 25°C
D package
1025 mW
PW package
866 mW
Derate D package
8.2 mW/°C above 25°C
Derate PW package
6.9 mW/°C above 25°C
6
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6.8 Typical Characteristics
Figure 1. Typical Pulse Skew Variation
vs Common Mode Voltage
Figure 2. Variation in High-to-Low Propagation Delay
vs VCM
Figure 3. Variation in Low-to-High Propagation Delay vs VCM
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7 Parameter Measurement Information
Figure 4. Receiver Propagation Delay and Transition Time Test Circuit
Figure 5. Receiver Propagation Delay and Transition Time Waveforms
CL includes load and test jig capacitance.
S1 = VCC for tPZL, and tPLZ measurements.
S1 = GND for tPZH and tPHZ measurements.
Figure 6. Receiver TRI-STATE Delay Test Circuit
8
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Parameter Measurement Information (continued)
Figure 7. Receiver TRI-STATE Delay Waveforms
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8 Detailed Description
8.1 Overview
LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as
is shown in Figure 8. This configuration provides a clean signaling environment for the fast edge rates of the
drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic impedance of the media is in the
range of 100 Ω. A termination resistor of 100 Ω (selected to match the media) is located as close to the receiver
input pins as possible. Other configurations are possible such as a multi-receiver configuration, but the effects of
a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise
margin limits, and total termination loading must be considered.
The DS90LV032A differential line receiver is capable of detecting signals as low as 100 mV, over a ±1-V
common-mode range centered around 1.2 V. This is related to the driver offset voltage which is typically 1.2 V.
The driven signal is centered around this voltage and may shift ±1 V around this center point. The ±1-V shifting
may be the result of a ground potential difference between the ground reference of the driver and the ground
reference of the receiver, the common-mode effects of coupled noise, or a combination of the two. The AC
parameters of both receiver input pins are optimized for a recommended operating input voltage range of 0 V to
2.4 V (measured from each pin to ground). The device operates for receiver input voltages up to VCC, but
exceeding VCC turns on the ESD protection circuitry which clamps the bus voltages.
8.2 Functional Block Diagram
RIN1+
+
RIN1-
±
RIN2+
+
RIN2-
±
RIN3+
+
RIN3-
±
RIN4+
+
RIN4-
±
R1
ROUT1
R2
ROUT2
R3
ROUT3
R4
ROUT4
EN
EN*
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8.3 Feature Description
8.3.1 Fail-Safe Feature
The LVDS receiver is a high-gain, high-speed device that amplifies a small differential signal (20 mV) to CMOS
logic levels. Due to the high gain and tight threshold of the receiver, take care to prevent noise from appearing as
a valid signal.
The internal fail-safe circuitry of the receiver is designed to source or sink a small amount of current, providing
fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated, or shorted receiver
inputs.
10
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Feature Description (continued)
1. Open input pins: The DS90LV032A is a quad receiver device, and if an application requires only 1, 2, or 3
receivers, the unused channel(s) inputs must be left OPEN. Do not tie unused receiver inputs to ground or
any other voltages. The input is biased by internal high value pullup and pulldown resistors to set the output
to a HIGH state. This internal circuitry ensures a HIGH, stable output state for open inputs.
2. Terminated input: If the driver is disconnected (cable unplugged), or if the driver is in a TRI-STATE or poweroff condition, the receiver output is in a HIGH state, even with the end of cable 100-Ω termination resistor
across the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the
cable picks up more than 10 mV of differential noise, the receiver may see the noise as a valid signal and
switch. To insure that any noise is seen as common-mode and not differential, a balanced interconnect must
be used. Twisted pair cable offers better balance than flat ribbon cable.
3. Shorted inputs: If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0-V
differential input voltage, the receiver output remains in a HIGH state. Shorted input fail-safe is not supported
across the common-mode range of the device (GND to 2.4 V). It is only supported with inputs shorted and no
external common-mode voltage applied.
External lower value pullup and pulldown resistors (for a stronger bias) may be used to boost fail-safe in the
presence of higher noise levels. The pullup and pulldown resistors must be in the 5-kΩ to 15-kΩ range to
minimize loading and waveform distortion to the driver. The common-mode bias point must be set to
approximately 1.2 V (less than 1.75 V) to be compatible with the internal circuitry.
The footprint of the DS90LV032A is the same as the industry standard 26LS32 Quad Differential (RS-422)
Receiver.
8.4 Device Functional Modes
Table 1 lists the functional modes of the DS90LV032A.
Table 1. Truth Table
ENABLES
EN
EN*
L
H
All other combinations of ENABLE inputs
INPUTS
OUTPUT
RIN+ – RIN–
ROUT
X
Z
VID ≥ 0.1 V
H
VID ≤ –0.1 V
L
Full Fail-safe
OPEN/SHORT or
Terminated
H
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DS90LV032A LVDS receiver and DS90LV031A driver are intended to be primarily used in an uncomplicated
point-to-point configuration as shown in Figure 8. This configuration provides a clean signaling environment for
the fast edge rates of the drivers. The receiver is connected to the driver through a balanced media which may
be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically the characteristic
impedance of the media is in the range of 100 Ω.
9.1.1 Probing LVDS Transmission Lines
Always use high impedance (>100 kΩ), low capacitance (
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