DS90UB901Q, DS90UB902Q
www.ti.com
SNLS322E – JUNE 2010 – REVISED APRIL 2013
DS90UB901Q/DS90UB902Q 10 - 43MHz 14 Bit Color FPD-Link III Serializer and
Deserializer with Bidirectional Control Channel
Check for Samples: DS90UB901Q, DS90UB902Q
FEATURES
DESCRIPTION
•
•
•
•
The DS90UB901Q/DS90UB902Q chipset offers a
FPD-Link III interface with a high-speed forward
channel and a bidirectional control channel for data
transmission over a single differential pair. The
Serializer/Deserializer pair is targeted for direct
connections between automotive camera systems
and Host Controller/Electronic Control Unit (ECU).
The primary transport sends 16 bits of image data
over a single high-speed serial stream together with a
low latency bidirectional control channel transport that
supports I2C. Included with the 16-bit payload is a
selectable data integrity option for CRC (Cyclic
Redundancy Check) to monitor transmission link
errors. Using TI’s embedded clock technology allows
transparent full-duplex communication over a single
differential pair, carrying asymmetrical bidirectional
control information without the dependency of video
blanking intervals. This single serial stream simplifies
transferring a wide data bus over PCB traces and
cable by eliminating the skew problems between
parallel data and clock paths. This significantly saves
system cost by narrowing data paths that in turn
reduce PCB layers, cable width, and connector size
and pins.
1
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
10 MHz to 43 MHz Input PCLK Support
160 Mbps to 688 Mbps Data Throughput
Single Differential Pair Interconnect
Bidirectional Control Interface Channel with
I2C Support
Embedded Clock with DC Balanced Coding to
Support AC-Coupled Interconnects
Capable to Drive up to 10 Meters Shielded
Twisted-Pair
I2C Compatible Serial Interface
Single Hardware Device Addressing Pin
16-bit Data Payload with CRC (Cyclic
Redundancy Check) for Checking Data
Integrity
Up to 6 Programmable GPIO's
LOCK Output Reporting Pin and AT-SPEED
BIST Diagnosis Feature to Validate Link
Integrity
Integrated Termination Resistors
1.8V- or 3.3V-Compatible Parallel Bus Interface
Single Power Supply at 1.8V
ISO 10605 ESD and IEC 61000-4-2 ESD
Compliant
Automotive Grade Product: AEC-Q100 Grade 2
Qualified
Temperature Range −40°C to +105°C
No Reference Clock Required on Deserializer
Programmable Receive Equalization
EMI/EMC Mitigation
– DES Programmable Spread Spectrum
(SSCG) Outputs
– DES Receiver Staggered Outputs
In addition, the Deserializer inputs provide
equalization control to compensate for loss from the
media over longer distances. Internal DC balanced
encoding/decoding is used to support AC-Coupled
interconnects.
A Serializer standby function provides a low powersavings mode with a remote wake up capability for
signaling of a remote device.
The Serializer is offered in a 32-pin WQFN (5mm x
5mm) package, and Deserializer is offered in a 40-pin
WQFN (6mm x 6mm) package.
APPLICATIONS
•
•
•
•
•
Automotive Vision Systems
Rear View, Side View Camera
Lane Departure Warning
Parking Assistance
Blind Spot View
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2013, Texas Instruments Incorporated
DS90UB901Q, DS90UB902Q
SNLS322E – JUNE 2010 – REVISED APRIL 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Typical Application Diagram
Parallel
Data In
16
Image
Sensor
Parallel
Data Out
16
FPD-Link III
2
2
DS90UB902Q
DS90UB901Q
Bidirectional
Control Bus
Bidirectional
Control Channel
Bidirectional
Control Bus
Serializer
Microcontroller/
ECU
Deserializer
Figure 1. Typical Application Circuit
RIN+ RT
RT
GPIO [1:0]
DOUT-
GPIO [1:0]
LOCK
PASS
Timing
and
Control
PDB
MODE
BISTEN
Encoder Decoder
ID[x]
Clock
Gen
CDR
Decoder Encoder
SCL
FIFO
I2C Controller
SDA
ROUT[13:0] HS, VS
PCLK
Clock
Gen
Timing
and
Control
PDB
MODE
2
I2C Controller
PLL
16
RIN-
FIFO
PCLK
Output Latch
DOUT+
Decoder
RT
RT
Deserializer
2
Serializer
16
Encoder
DIN[13:0] HS, VS
Input Latch
Block Diagrams
SDA
SCL
ID[x]
DS90UB902Q - DESERIALIZER
DS90UB901Q - SERIALIZER
Figure 2. Block Diagram
DS90UB901Q
Serializer
DS90UB902Q
Deserializer
FPD-Link III
Camera Data
Camera Data
DOUT+
14
Image
Sensor
YUV/RGB
HSYNC
DIN[13:0]
HS, VS
VSYNC
2
14
YUV/RGB
DOUTPixel Clock
RIN+
RIN-
ROUT[13:0]
HS, VS
Bidirectional
Control Channel
PCLK
PCLK
GPIO[1:0]
GPIO[1:0]
GPI/O
SDA
Camera Unit
SCL
HSYNC
VSYNC
Pixel Clock
2
GPI/O
SDA
SDA
SCL
SCL
ECU Module
Microcontroller
SDA
SCL
Figure 3. Application Block Diagram
2
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SNLS322E – JUNE 2010 – REVISED APRIL 2013
VDDIO
DIN[7]
DIN[6]
DIN[5]
DIN[4]
DIN[3]/GPIO[5]
DIN[2]/GPIO[4]
DIN[1]/GPIO[3]
DIN[0]/GPIO[2]
DS90UB901Q Pin Diagram
24
23
22
21
20
19
18
17
25
16
GPIO[1]
15
GPIO[0]
14
VDDCML
13
DOUT+
12
DOUT-
DAP = GND
DIN[8]
26
DIN[9]
27
DS90B901Q
Serializer
32-Pin WQFN
(Top View)
DIN[12]
31
10
VDDPLL
DIN[13]
32
9
PDB
1
2
3
4
5
6
7
8
MODE
VDDT
RES
11
ID[x]
30
SDA
DIN[11]
SCL
29
PCLK
DIN[10]
VSYNC
28
HSYNC
VDDD
Serializer - DS90UB901Q
32 Pin WQFN (Top View)
See Package Number RTV0032A
DS90UB901Q SERIALIZER PIN DESCRIPTIONS
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
DIN[13:0]
32, 31, 30, 29,
27, 26, 24, 23,
22, 21, 20, 19,
18, 17
Inputs,
LVCMOS
w/ pull down
Parallel data inputs.
HSYNC
1
Inputs,
LVCMOS
w/ pull down
Horizontal SYNC Input
VSYNC
2
Inputs,
LVCMOS
w/ pull down
Vertical SYNC Input
PCLK
3
Input, LVCMOS Pixel Clock Input Pin. Strobe edge set by TRFB control register.
w/ pull down
GENERAL PURPOSE INPUT OUTPUT (GPIO)
DIN[3:0]/
GPIO[5:2]
20, 19, 18, 17
Input/Output,
LVCMOS
DIN[3:0] general-purpose pins can be individually configured as either inputs or
outputs; used to control and respond to various commands.
GPIO[1:0]
16, 15
Input/Output,
LVCMOS
General-purpose pins can be individually configured as either inputs or outputs; used
to control and respond to various commands.
BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE
SCL
4
Input/Output,
Open Drain
Clock line for the bidirectional control bus communication
SCL requires an external pull-up resistor to VDDIO.
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS90UB901Q DS90UB902Q
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DS90UB901Q, DS90UB902Q
SNLS322E – JUNE 2010 – REVISED APRIL 2013
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DS90UB901Q SERIALIZER PIN DESCRIPTIONS (continued)
Pin Name
Pin No.
I/O, Type
5
Input/Output,
Open Drain
SDA
MODE
8
ID[x]
6
Description
Data line for the bidirectional control bus communication
SDA requires an external pull-up resistor to VDDIO.
I2C Mode select
MODE = L, Master mode (default); Device generates and drives the SCL clock line.
Device is connected to slave peripheral on the bus. (Serializer initially starts up in
Input, LVCMOS
Standby mode and is enabled through remote wakeup by Deserializer)
w/ pull down
MODE = H, Slave mode; Device accepts SCL clock input and attached to an I2C
controller master on the bus. Slave mode does not generate the SCL clock, but uses
the clock generated by the Master for the data transfers.
Input, analog
Device ID Address Select
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 3
CONTROL AND CONFIGURATION
PDB
9
Power down Mode Input Pin.
PDB = H, Serializer is enabled and is ON.
Input, LVCMOS
PDB = L, Serailizer is in Power Down mode. When the Serializer is in Power Down,
w/ pull down
the PLL is shutdown, and IDD is minimized. Programmed control register data are
NOT retained and reset to default values
RES
7
Input, LVCMOS Reserved.
w/ pull down
This pin MUST be tied LOW.
FPD-LINK III INTERFACE
Input/Output,
CML
Non-inverting differential output, bidirectional control channel input. The interconnect
must be AC Coupled with a 100 nF capacitor.
12
Input/Output,
CML
Inverting differential output, bidirectional control channel input. The interconnect must
be AC Coupled with a 100 nF capacitor.
VDDPLL
10
Power, Analog
PLL Power, 1.8V ±5%
VDDT
11
Power, Analog
Tx Analog Power, 1.8V ±5%
VDDCML
14
Power, Analog
CML & Bidirectional Channel Driver Power, 1.8V ±5%
VDDD
28
Power, Digital
Digital Power, 1.8V ±5%
Power, Digital
Power for I/O stage. The single-ended inputs and SDA, SCL are powered from VDDIO.
VDDIO can be connected to a 1.8V ±5% or 3.3V ±10%
Ground, DAP
DAP must be grounded. DAP is the large metal contact at the bottom side, located at
the center of the WQFN package. Connected to the ground plane (GND) with at least
9 vias.
DOUT+
13
DOUTPOWER AND GROUND
VDDIO
VSS
4
25
DAP
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Product Folder Links: DS90UB901Q DS90UB902Q
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SNLS322E – JUNE 2010 – REVISED APRIL 2013
PASS
31
RES/CMLOUTP
32
RES/CMLOUTN
33
VDDCML
34
RIN+
RIN-
VDDR
PDB
LOCK
GPIO[0]
GPIO[1]
VDDIO1
ROUT[0]/GPIO[2]
ROUT[1]/GPIO[3]
ROUT[2]/GPIO[4]
ROUT[3]/GPIO[5]
DS90UB902Q Pin Diagram
30
29
28
27
26
25
24
23
22
21
DAP = GND
DS90B902Q
Deserializer
40-Pin WQFN
(Top View)
35
36
20
ROUT[4]
19
ROUT[5]
18
ROUT[6]
17
ROUT[7]
16
VDDIO2
15
ROUT[8]
12
ROUT[10]
MODE
40
11
ROUT[11]
1
2
3
4
5
6
7
8
9
10
ROUT[12]
39
ROUT[13]
RES
VDDIO3
VDDD
HSYNC
13
VSYNC
38
PCLK
VDDPLL
VDDSSCG
ROUT[9]
SCL
14
SDA
37
ID[x]
BISTEN
Deserializer - DS90UB902Q
40 Pin WQFN (Top View)
See Package Number RTA0040A
DS90UB902Q DESERIALIZER PIN DESCRIPTIONS
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
ROUT[13:0]
9, 10, 11, 12,
14, 15, 17, 18,
19, 20, 21, 22,
23, 24
Outputs,
LVCMOS
Parallel data outputs.
HSYNC
7
Output,
LVCMOS
Horizontal SYNC Output
VSYNC
6
Output,
LVCMOS
Vertical SYNC Output
PCLK
5
Output,
LVCMOS
Pixel Clock Output Pin.
Strobe edge set by RRFB control register.
GENERAL PURPOSE INPUT OUTPUT (GPIO)
ROUT[3:0] /
GPIO[5:2]
GPIO[1:0]
21, 22, 23, 24
Input/Output,
LVCMOS
ROUT[3:0] general-purpose pins can be individually configured as either inputs or
outputs; used to control and respond to various commands.
26, 27
Input/Output,
LVCMOS
General-purpose pins can be individually configured as either inputs or outputs; used
to control and respond to various commands.
BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE
SCL
3
Input/Output,
Open Drain
Clock line for the bidirectional control bus communication
SCL requires an external pull-up resistor to VDDIO.
SDA
2
Input/Output,
Open Drain
Data line for bidirectional control bus communication
SDA requires an external pull-up resistor to VDDIO.
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Product Folder Links: DS90UB901Q DS90UB902Q
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DS90UB901Q, DS90UB902Q
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DS90UB902Q DESERIALIZER PIN DESCRIPTIONS (continued)
Pin Name
Pin No.
MODE
40
ID[x]
1
I/O, Type
Description
I2C Mode select
MODE = L, Master mode; Device generates and drives the SCL clock line, where
Input, LVCMOS required such as Read. Device is connected to slave peripheral on the bus.
w/ pull up
MODE = H, Slave mode (default); Device accepts SCL clock input and attached to an
I2C controller master on the bus. Slave mode does not generate the SCL clock, but
uses the clock generated by the Master for the data transfers.
Input, analog
Device ID Address Select
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 4
CONTROL AND CONFIGURATION
PDB
29
Power down Mode Input Pin.
PDB = H, Deserializer is enabled and is ON.
Input, LVCMOS
PDB = L, Deserializer is in Power Down mode. When the Deserializer is in Power
w/ pull down
Down. Programmed control register data are NOT retained and reset to default
values.
LOCK
28
Output,
LVCMOS
LOCK Status Output Pin.
LOCK = H, CDR/PLL is Locked, outputs are active
LOCK = L, CDR/PLL is unlocked, the LVCMOS Outputs depend on OSS_SEL control
register, the CDR/PLL is shutdown and IDD is minimized. May be used as Link
Status.
PASS
31
Output,
LVCOMS
When BISTEN = L; Normal operation
PASS is high to indicate no errors are detected. The PASS pin asserts low to indicate
a CRC error was detected on the Link.
RES
32, 33, 39
-
Reserved
Pin 39: This pin MUST be tied LOW.
Pins 32,33: Route to test point or leave open if unused. See also FPD-LINK III
INTERFACE pin description section.
BIST MODE
BISTEN
37
PASS
31
BIST Enable Pin.
Input, LVCMOS
BISTEN = H, BIST Mode is enabled.
w/ pull down
BISTEN = L, BIST Mode is disabled.
Output,
LVCOMS
PASS Output Pin for BIST mode.
PASS = H, ERROR FREE Transmission
PASS = L, one or more errors were detected in the received payload.
Leave Open if unused. Route to test point (pad) recommended.
FPD-LINK III INTERFACE
RIN+
35
Input/Output,
CML
Non-inverting differential input, bidirectional control channel output. The interconnect
must be AC Coupled with a 100 nF capacitor.
RIN-
36
Input/Output,
CML
Inverting differential input, bidirectional control channel output. The interconnect must
be AC Coupled with a 100 nF capacitor.
CMLOUTP
32
Output, CML
Non-inverting CML Output
Monitor point for equalized differential signal. Test port is enabled via control
registers.
CMLOUTN
33
Output, CML
Inverting CML Output
Monitor point for equalized differential signal. Test port is enabled via control
registers.
VDDSSCG
4
Power, Digital
SSCG Power, 1.8V ±5%
Power supply must be connected regardless if SSCG function is in operation.
VDDIO1/2/3
25, 16, 8
Power, Digital
LVTTL I/O Buffer Power, The single-ended outputs and control input are powered
from VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10%
POWER AND GROUND
VDDD
13
Power, Digital
Digital Core Power, 1.8V ±5%
VDDR
30
Power, Analog
Rx Analog Power, 1.8V ±5%
VDDCML
34
Power, Analog
Bidirectional Channel Driver Power, 1.8V ±5%
VDDPLL
38
Power, Analog
PLL Power, 1.8V ±5%
DAP
Ground, DAP
DAP must be grounded. DAP is the large metal contact at the bottom side, located at
the center of the WQFN package. Connected to the ground plane (GND) with at least
16 vias.
VSS
6
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SNLS322E – JUNE 2010 – REVISED APRIL 2013
Absolute Maximum Ratings (1) (2) (3)
−0.3V to +2.5V
Supply Voltage – VDDn (1.8V)
−0.3V to +4.0V
Supply Voltage – VDDIO
−0.3V to + (VDDIO + 0.3V)
LVCMOS Input Voltage I/O Voltage
−0.3V to +(VDD + 0.3V)
CML Driver I/O Voltage (VDD)
−0.3V to (VDD + 0.3V)
CML Receiver I/O Voltage (VDD)
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
Maximum Package Power Dissipation Capacity Package
1/θJA °C/W above +25°
Package Derating:
θJA(based on 9 thermal vias)
DS90UB901Q 32 Lead WQFN
DS90UB902Q 40 Lead WQFN
34.3 °C/W
θJC(based on 9 thermal vias)
6.9 °C/W
θJA(based on 16 thermal vias)
28.0 °C/W
θJC(based on 16 thermal vias)
4.4 °C/W
ESD Rating (IEC 61000-4-2)
RD = 330Ω, CS = 150pF
≥±25 kV
Air Discharge (DOUT+, DOUT-, RIN+, RIN-)
≥±10 kV
Contact Discharge (DOUT+, DOUT-, RIN+, RIN-)
ESD Rating (ISO10605)
RD = 330Ω, CS = 150/330pF
ESD Rating (ISO10605)
RD = 2KΩ, CS = 150/330pF
Air Discharge (DOUT+, DOUT-, RIN+, RIN-)
≥±15 kV
Contact Discharge (DOUT+, DOUT-, RIN+, RIN-)
≥±10 kV
≥±8 kV
ESD Rating (HBM)
≥±1 kV
ESD Rating (CDM)
≥±250 V
ESD Rating (MM)
(1)
(2)
(3)
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional; the device should not be operated beyond such conditions.
For soldering specifications see product folder at www.ti.com
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Recommended Operating Conditions (1)
Min
Nom
Max
Units
Supply Voltage (VDDn)
1.71
1.8
1.89
V
LVCMOS Supply Voltage (VDDIO)
OR
1.71
1.8
1.89
V
3.0
3.3
LVCMOS Supply Voltage (VDDIO)
Supply Noise
3.6
V
VDDn (1.8V)
25
mVp-p
VDDIO (1.8V)
25
mVp-p
VDDIO (3.3V)
50
mVp-p
+105
°C
43
MHz
Operating Free Air Temperature (TA)
-40
PCLK Clock Frequency
10
(1)
+25
Supply noise testing was done with minimum capacitors (as shown on Figure 39 and Figure 40) on the PCB. A sinusoidal signal is AC
coupled to the VDDn (1.8V) supply with amplitude = 25 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the
Ser and output of the Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 1 MHz. The Des on the
other hand shows no error when the noise frequency is less than 750 kHz.
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Electrical Characteristics (1) (2) (3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
LVCMOS DC SPECIFICATIONS 3.3V I/O (SER INPUTS, DES OUTPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input Voltage
VIN = 3.0V to 3.6V
2.0
VIN
VIL
Low Level Input Voltage
VIN = 3.0V to 3.6V
GND
0.8
V
IIN
Input Current
VIN = 0V or 3.6V, VIN = 3.0V to 3.6V
+20
µA
VOH
High Level Output Voltage VDDIO = 3.0V to 3.6V, IOH = -4 mA
2.4
VDDIO
V
VOL
Low Level Output Voltage
GND
0.4
V
VDDIO = 3.0V to 3.6V, IOL = +4 mA
IOS
IOZ
Output Short Circuit
Current
VOUT = 0V
TRI-STATE Output
Current
PDB = 0V, VOUT = 0V or
VDD
-20
±1
Serializer GPIO
Outputs
-24
Deserializer LVCMOS
Outputs
-39
LVCMOS Outputs
mA
-20
±1
+20
µA
LVCMOS DC SPECIFICATIONS 1.8V I/O (SER INPUTS, DES OUTPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input Voltage
VIN = 1.71V to 1.89V
0.65 VIN
VIN +0.3
VIL
Low Level Input Voltage
VIN = 1.71V to 1.89V
GND
0.35 VIN
IIN
Input Current
VIN = 0V or 1.89V, VIN = 1.71V to 1.89V
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
VDDIO = 1.71V to 1.89V,
IOH = −2 mA
Serializer GPIO
Outputs
VDDIO = 1.71V to 1.89V,
IOH = −4 mA
Deserializer LVCMOS
Outputs
VDDIO = 1.71V to 1.89V,
IOL = +2 mA
Serializer GPIO
Outputs
VDDIO = 1.71V to 1.89V,
IOL = +4 mA
Deserializer LVCMOS
Outputs
IOS
IOZ
Output Short Circuit
Current
VOUT = 0V
TRI-STATE Output
Current
PDB = 0V, VOUT = 0V or
VDD
-20
±1
+20
µA
VDDIO 0.45
VDDIO
V
GND
0.45
V
Serializer GPIO
Outputs
-11
Deserializer LVCMOS
Outputs
-20
LVCMOS Outputs
V
mA
-20
±1
+20
µA
268
340
412
mV
1
50
mV
VDD - VOD
VDD (MAX) VOD (MIN)
V
1
50
mV
CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-)
|VOD|
Output Differential Voltage RT = 100Ω (Figure 8)
ΔVOD
Output Differential Voltage
RL = 100Ω
Unbalance
VOS
Output Differential Offset
Voltage
RL = 100Ω (Figure 8)
ΔVOS
Offset Voltage Unbalance
RL = 100Ω
IOS
Output Short Circuit
Current
DOUT+/- = 0V,
RT
Differential Internal
Termination Resistance
Differential across DOUT+ and DOUT-
VDD (MIN) VOD (MAX)
-27
80
100
mA
120
Ω
CML RECEIVER DC SPECIFICATIONS (RIN+, RIN-)
VTH
VTL
(1)
(2)
(3)
8
Differential Threshold High
Voltage
Differential Threshold Low
Voltage
+90
(Figure 10)
mV
-90
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
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Product Folder Links: DS90UB901Q DS90UB902Q
DS90UB901Q, DS90UB902Q
www.ti.com
SNLS322E – JUNE 2010 – REVISED APRIL 2013
Electrical Characteristics(1)(2)(3)
(continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VIN
Differential Input Voltage
Range
RIN+ - RIN-
180
IIN
Input Current
VIN = VDD or 0V, VDD = 1.89V
-20
±1
+20
µA
RT
Differential Internal
Termination Resistance
Differential across RIN+ and RIN-
80
100
120
Ω
62
90
mV
SER/DES SUPPLY CURRENT *DIGITAL, PLL, AND ANALOG VDD
IDDT
Serializer (Tx)
VDDn Supply Current
(includes load current)
RT = 100Ω
WORST CASE pattern
(Figure 5)
RT = 100Ω
RANDOM PRBS-7
pattern
IDDIOT
Serializer (Tx)
VDDIO Supply Current
(includes load current)
RT = 100Ω
WORST CASE pattern
(Figure 5)
Serializer (Tx) Supply
Current Power-down
PDB = 0V; All other
LVCMOS Inputs = 0V
IDDTZ
IDDIOTZ
IDDR
Deserializer (Rx) VDDn
Supply Current (includes
load current)
IDDIOR
Deserializer (Rx) VDDIO
Supply Current (includes
load current)
Deserializer (Rx) Supply
Current Power-down
mA
55
VDDIO = 1.89V
PCLK = 43 MHz
Default Registers
2
VDDIO = 3.6V
PCLK = 43 MHz
Default Registers
7
15
VDDn = 1.89V
370
775
VDDIO = 1.89V
55
125
5
mA
VDDIO = 3.6V
65
135
VDDn = 1.89V, CL = 8 pF
WORST CASE Pattern,
(Figure 5)
PCLK = 43 MHz
SSCG[3:0] = ON
Default Registers
60
96
VDDn = 1.89V, CL = 8 pF
RANDOM PRBS-7
Pattern
PCLK = 43 MHz
Default Registers
53
VDDIO = 1.89V, CL = 8 pF
PCLK = 43 MHz
WORST CASE Pattern,
Default Registers
(Figure 5)
16
25
VDDIO = 3.6V, CL = 8 pF
WORST CASE Pattern
PCLK = 43 MHz
Default Registers
38
64
VDDn = 1.89V
42
400
VDDIO = 1.89V
8
40
VDDIO = 3.6V
350
800
IDDRZ
IDDIORZ
VDDn = 1.89V
PCLK = 43 MHz
Default Registers
PDB = 0V; All other
LVCMOS Inputs = 0V
Copyright © 2010–2013, Texas Instruments Incorporated
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µA
mA
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µA
9
DS90UB901Q, DS90UB902Q
SNLS322E – JUNE 2010 – REVISED APRIL 2013
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Recommended Serializer Timing for PCLK (1)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tTCP
Transmit Clock Period
23.3
T
100
ns
tTCIH
Transmit Clock Input High
Time
0.4T
0.5T
0.6T
ns
tTCIL
Transmit Clock Input Low
Time
0.4T
0.5T
0.6T
ns
tCLKT
PCLK Input Transition Time
(Figure 11)
3
ns
fOSC
Internal oscillator clock
source
(1)
10 MHz – 43 MHz
0.5
25
MHz
Recommended Input Timing Requirements are input specifications and not tested in production.
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
tLHT
CML Low-to-High Transition
Time
tHLT
CML High-to-Low Transition
Time
tDIS
Data Input Setup to PCLK
tDIH
Data Input Hold from PCLK
tPLD
Max
Units
RL = 100Ω (Figure 6)
150
330
ps
RL = 100Ω (Figure 6)
150
330
ps
2.0
ns
2.0
ns
(1) (2)
Serializer PLL Lock Time
RL = 100Ω
Serializer Delay
RT = 100Ω, PCLK = 10–43 MHz
Register 0x03h b[0] (TRFB = 1)
(Figure 14)
tSD
tJIND
Typ
Serializer Data Inputs (Figure 12)
Min
6.386T + 5
Serializer output
intrinsic deterministic jitter .
Serializer Output Deterministic
Measured (cycle-cycle) with
Jitter
PRBS-7 test pattern
PCLK = 43 MHz (3) (4)
1
2
ms
6.386T + 12
6.386T +
19.7
ns
0.13
UI
0.04
UI
Serializer output peak-to-peak jitter
includes deterministic jitter,
random jitter, and jitter transfer
Peak-to-peak Serializer Output
from serializer input. Measured
Jitter
(cycle-cycle) with PRBS-7 test
pattern.
PCLK = 43 MHz (3) (4)
0.396
UI
λSTXBW
Serializer Jitter Transfer
Function -3 dB Bandwidth
PCLK = 43 MHz, Default Registers
(Figure 20) (3)
1.90
MHz
δSTX
Serializer Jitter Transfer
Function (Peaking)
PCLK = 43 MHz, Default Registers
(Figure 20) (3)
0.944
dB
δSTXf
Serializer Jitter Transfer
Function (Peaking Frequency)
PCLK = 43 MHz, Default Registers
(Figure 20) (3)
500
kHz
tJINR
Serializer Output Random
Jitter
tJINT
(1)
(2)
(3)
(4)
10
Serializer output intrinsic random
jitter (cycle-cycle). Alternating-1,0
pattern.
PCLK = 43 MHz (3) (4)
tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK
Specification is by design.
Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
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Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS90UB901Q DS90UB902Q
DS90UB901Q, DS90UB902Q
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SNLS322E – JUNE 2010 – REVISED APRIL 2013
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tRCP
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
Receiver Output Clock Period
tRCP = tTCP
PCLK
23.3
T
100
ns
tPDC
PCLK Duty Cycle
Default Registers
SSCG[3:0] = OFF
PCLK
45
50
55
%
tCLH
LVCMOS Low-to-High Transition
Time
1.3
2.0
2.8
1.3
2.0
2.8
1.6
2.4
3.3
1.6
2.4
3.3
0.38T
0.5T
0.38T
0.5T
4.571T
+8
4.571T
+ 12
tCHL
LVCMOS High-to-Low Transition
Time
LVCMOS Low-to-High Transition
Time
tCLH
tCHL
LVCMOS High-to-Low Transition
Time
tROS
ROUT Setup Data to PCLK
tROH
ROUT Hold Data to PCLK
VDDIO: 1.71V to 1.89V or
3.0V to 3.6V,
CL = 8 pF (lumped load)
Default Registers
(Figure 16) (1)
PCLK
VDDIO: 1.71V to 1.89V or
3.0V to 3.6V,
CL = 8 pF (lumped load)
Default Registers
(Figure 16) (1)
ROUT[13:0],
HSYNC, VSYNC
VDDIO: 1.71V to 1.89V or
3.0V to 3.6V,
CL = 8 pF (lumped load)
Default Registers
(Figure 18)
ROUT[13:0],
HSYNC, VSYNC
ns
ns
ns
tDD
Deserializer Delay
Default Registers
Register 0x03h b[0]
(RRFB = 1) (Figure 17)
10 MHz–43 MHz
tDDLT
Deserializer Data Lock Time
(Figure 15) (2)
10 MHz–43 MHz
Receiver Input Jitter Tolerance
(Figure 19,
Figure 21) (3) (4)
43 MHz
0.53
Receiver Clock Jitter
PCLK
SSCG[3:0] = OFF (1) (5)
10 MHz
300
550
43 MHz
120
250
Deserializer Period Jitter
PCLK
SSCG[3:0] = OFF (1) (6)
10 MHz
425
600
43 MHz
320
480
Deserializer Cycle-to-Cycle Clock
Jitter
PCLK
SSCG[3:0] = OFF (7) (1)
10 MHz
320
500
43 MHz
300
500
LVCMOS Output Bus
SSC[3:0] = ON
(Figure 22)
20 MHz–43 MHz
±0.5% to
±2.0%
%
20 MHz–43 MHz
9 kHz to
66 kHz
kHz
tRJIT
tRCJ
tDPJ
tDCCJ
fdev
Spread Spectrum Clocking
Deviation Frequency
fmod
Spread Spectrum Clocking
Modulation Frequency
(1)
(2)
(3)
(4)
(5)
(6)
(7)
4.571T
+ 16
ns
10
ms
UI
ps
ps
ps
Specification is by characterization and is not tested in production.
tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK
UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
tRJIT max (0.61UI) is limited by instrumentation and actual tRJIT of in-band jitter at low frequency (0
tLOW
SCL Low Period
4.7
µs
tHIGH
SCL High Period
4.0
µs
tHD:STA
Hold time for a start or a repeated start
condition
4.0
µs
tSU:STA
Set Up time for a start or a repeated
start condition
4.7
µs
tHD:DAT
Data Hold Time
tSU:DAT
Data Set Up Time
250
ns
tSU:STO
Set Up Time for STOP Condition
4.0
µs
tr
SCL & SDA Rise Time
1000
tf
SCL & SDA Fall Time
300
ns
Cb
Capacitive load for bus
400
pF
fSCL = 100 kHz
0
3.45
µs
ns
SWITCHING CHARACTERISTICS (2)
fSCL
SCL Clock Frequency
tLOW
Serializer MODE = 0 – R/W
Register 0x05 = 0x40'h
100
Deserializer MODE = 0 – READ
Register 0x06 b[6:4] = 0x00'h
100
kHz
Serializer MODE = 0 – R/W
Register 0x05 = 0x40'h
SCL Low Period
Deserializer MODE = 0 – READ
Register 0x06 b[6:4] = 0x00'h
Serializer MODE = 0 – R/W
Register 0x05 = 0x40'h
4.7
µs
4.0
µs
tHIGH
SCL High Period
tHD:STA
Hold time for a start or a repeated start
condition
Serializer MODE = 0
Register 0x05 = 0x40'h
4.0
µs
tSU:STA
Set Up time for a start or a repeated
start condition
Serializer MODE = 0
Register 0x05 = 0x40'h
4.7
µs
tHD:DAT
Data Hold Time
tSU:DAT
Data Set Up Time
tSU:STO
Set Up Time for STOP Condition
tf
SCL & SDA Fall Time
tBUF
Bus free time between a stop and start
condition
tTIMEOUT
NACK Time out
(1)
(2)
12
Deserializer MODE = 0 – READ
Register 0x06 b[6:4] = 0x00'h
0
Serializer MODE = 0
3.45
250
ns
4.0
µs
300
Serializer MODE = 0
µs
4.7
ns
µs
Serializer MODE = 1
1
Deserializer MODE = 1
Register 0x06 b[2:0]=111'b
25
ms
Recommended Input Timing Requirements are input specifications and not tested in production.
Specification is by design.
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS90UB901Q DS90UB902Q
DS90UB901Q, DS90UB902Q
www.ti.com
SNLS322E – JUNE 2010 – REVISED APRIL 2013
SDA
tLOW
tf
tHD;STA
tBUF
tr
tf
tr
SCL
tSU;STA
tHD;STA
tHIGH
tSU;STO
tSU;DAT
tHD;DAT
START
STOP
REPEATED
START
START
Figure 4. Bidirectional Control Bus Timing
Bidirectional Control Bus DC Characteristics (SCL, SDA) - I2C Compliant
Over recommended supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Max
Units
SDA and SCL
0.7 x
VDDIO
VDDIO
V
Input Low Level Voltage
SDA and SCL
GND
0.3 x
VDDIO
V
VHY
Input Hysteresis
SDA and SCL
IOZ
VIH
Input High Level
VIL
Conditions
Min
Typ
>50
mV
TRI-STATE Output Current
PDB = 0V, VOUT = 0V or VDD
-20
±1
+20
µA
IIN
Input Current
SDA or SCL,
Vin = VDDIO or GND
-20
±1
+20
µA
CIN
Input Pin Capacitance
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