DS90UB903QSQE/NOPB

DS90UB903Q, DS90UB904Q www.ti.com SNLS332E – JUNE 2010 – REVISED APRIL 2013 DS90UB903Q/DS90UB904Q 10 - 43MHz 18 Bit Color FPD-Link III Serializer and Deserializer with Bidirectional Control Channel Check for Samples: DS90UB903Q, DS90UB904Q FEATURES DESCRIPTION • • • • The DS90UB903Q/DS90UB904Q chipset offers a FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single differential pair. The DS90UB903Q/904Q incorporates differential signaling on both the high-speed forward channel and bidirectional control channel data paths. The Serializer/ Deserializer pair is targeted for direct connections between graphics host controller and displays modules. This chipset is ideally suited for driving video data to displays requiring 18-bit color depth (RGB666 + HS, VS, and DE) along with bidirectional control channel bus. The primary transport converts 21 bit data over a single highspeed serial stream, along with a separate low latency bidirectional control channel transport that accepts control information from an I2C port. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bidirectional control channel information in both directions. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. 1 2 • • • • • • • • • • • • • • • 10 MHz to 43 MHz Input PCLK Support 210 Mbps to 903 Mbps Data Throughput Single Differential Pair Interconnect Bidirectional Control Interface Channel with I2C Support Embedded Clock with DC Balanced Coding to Support AC-Coupled Interconnects Capable to Drive up to 10 Meters Shielded Twisted-Pair I2C Compatible Serial Interface Single Hardware Device Addressing Pin Up to 4 General Purpose Input (GPI)/ Output (GPO) LOCK Output Reporting Pin and AT-SPEED BIST Diagnosis Feature to Validate Link Integrity Integrated Termination Resistors 1.8V- or 3.3V-Compatible Parallel Bus Interface Single Power Supply at 1.8V ISO 10605 ESD and IEC 61000-4-2 ESD Compliant Automotive Grade Product: AEC-Q100 Grade 2 Qualified Temperature Range −40°C to +105°C No Reference Clock Required on Deserializer Programmable Receive Equalization EMI/EMC Mitigation – DES Programmable Spread Spectrum (SSCG) Outputs – DES Receiver Staggered Outputs In addition, the Deserializer inputs provide equalization control to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects. The Serializer is offered in a 40-pin lead in WQFN and Deserializer is offered in a 48-pin WQFN packages. APPLICATIONS • Automotive Display Systems – Central Information Displays – Navigation Displays – Rear Seat Entertainment – Touch Screen Displays 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2013, Texas Instruments Incorporated DS90UB903Q, DS90UB904Q SNLS332E – JUNE 2010 – REVISED APRIL 2013 www.ti.com Typical Application Diagram FPD-Link III Parallel Data In 18+3 Graphics Controller -Video Processor Parallel Data Out 18+3 4 Display Module, Touch Panel 4 DS90UB903Q DS90UB904Q GPO GPI Bidirectional Control Channel 2 Bidirectional Control Bus 2 Bidirectional Control Bus Deserializer Serializer Figure 1. Typical Application Circuit DOUT+ DOUT- RIN+ RT RT Output Latch RT Decoder Serializer 4 RT Deserializer GPO[3:0] Encoder R/G/B[5:0], 21 HS,VS,DE Input Latch Block Diagrams 21 R/G/B[5:0], HS,VS,DE 4 GPI[3:0] RINPCLK PDB BISTEN MODE LOCK PASS I2C Controller Decoder Encoder FIFO Encoder Timing and Control Decoder ID[x] I2C Controller SCL Clock Gen CDR Timing and Control PDB MODE SDA Clock Gen PLL FIFO PCLK SDA SCL ID[x] DS90UB904Q - DESERIALIZER DS90UB903Q - SERIALIZER Figure 2. Block Diagram DS90UB903Q Serializer Graphics Controller --Video Processor DS90UB904Q Deserializer FPD-Link III R[5:0] G[5:0] B[5:0] VS HS DE PCLK PLL PDB MODE Config. R[5:0] G[5:0] B[5:0] VS HS DE PCLK Config. PDB MODE BISTEN GPI[3:0] Timing Controller LCD Display --Touch Panel GPO[3:0] PC SDA SCL 2 I C 2 I C SDA SCL PC Figure 3. Application Block Diagram 2 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS90UB903Q DS90UB904Q DS90UB903Q, DS90UB904Q www.ti.com SNLS332E – JUNE 2010 – REVISED APRIL 2013 VDDIO 31 DIN[8] 32 DIN[9] 33 VDDD 34 DIN[7] DIN[6] DIN[5] DIN[4] DIN[3] DIN[2] DIN[1] DIN[0] GPO[3] GPO[2] 30 29 28 27 26 25 24 23 22 21 DS90UB903Q Pin Diagram DAP = GND DS9UB903Q Serializer 40-Pin WQFN (Top View) 20 GPO[1] 19 GPO[0] 18 VDDCML 17 DOUT+ 16 DOUT- 15 VDDT 11 RES RES DIN[16] 10 40 9 DIN[15] ID[x] MODE 8 12 SDA 39 7 DIN[14] SCL PDB 6 13 PCLK 38 5 DIN[13] DIN[20] VDDPLL 4 14 DIN[19] 37 3 DIN[12] DIN[18] 36 2 DIN[11] DIN[17] 35 1 DIN[10] Serializer - DS90UB903Q 40 Pin WQFN (Top View) See Package Number RTA0040A DS90UB903Q SERIALIZER PIN DESCRIPTIONS Pin Name Pin No. I/O, Type Description LVCMOS PARALLEL INTERFACE DIN[20:0] PCLK 5, 4, 3, 2, 1, 40, 39, 38, 37, 36, 35, 33, 32, 30, 29, 28, 27, 26, 25, 24, 23 6 Inputs, LVCMOS w/ pull down Parallel data inputs. Input, LVCMOS Pixel Clock Input Pin. Strobe edge set by TRFB control register. w/ pull down GENERAL PURPOSE OUTPUT (GPO) GPO[3:0] 22, 21, 20, 19 Output, LVCMOS General-purpose output pins can be used to control and respond to various commands. BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE SCL 7 Input/Output, Open Drain Clock line for the bidirectional control bus communication SCL requires an external pull-up resistor to VDDIO. SDA 8 Input/Output, Open Drain Data line for the bidirectional control bus communication SDA requires an external pull-up resistor to VDDIO. MODE 12 ID[x] 9 I2C Mode select MODE = L, Master mode (default); Device generates and drives the SCL clock line. Device is connected to slave peripheral on the bus. (Serializer initially starts up in Input, LVCMOS Standby mode and is enabled through remote wakeup by Deserializer) w/ pull down MODE = H, Slave mode; Device accepts SCL clock input and attached to an I2C controller master on the bus. Slave mode does not generate the SCL clock, but uses the clock generated by the Master for the data transfers. Input, analog Device ID Address Select Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 3 CONTROL AND CONFIGURATION Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS90UB903Q DS90UB904Q Submit Documentation Feedback 3 DS90UB903Q, DS90UB904Q SNLS332E – JUNE 2010 – REVISED APRIL 2013 www.ti.com DS90UB903Q SERIALIZER PIN DESCRIPTIONS (continued) Pin Name Pin No. PDB 13 RES 10, 11 I/O, Type Description Power down Mode Input Pin. PDB = H, Serializer is enabled and is ON. Input, LVCMOS PDB = L, Serailizer is in Power Down mode. When the Serializer is in Power Down, w/ pull down the PLL is shutdown, and IDD is minimized. Programmed control register data are NOT retained and reset to default values Input, LVCMOS Reserved. w/ pull down This pin MUST be tied LOW. FPD-LINK III INTERFACE Input/Output, CML Non-inverting differential output, bidirectional control channel input. The interconnect must be AC Coupled with a 100 nF capacitor. 16 Input/Output, CML Inverting differential output, bidirectional control channel input. The interconnect must be AC Coupled with a 100 nF capacitor. VDDPLL 14 Power, Analog PLL Power, 1.8V ±5% VDDT 15 Power, Analog Tx Analog Power, 1.8V ±5% VDDCML 18 Power, Analog CML & Bidirectional Channel Driver Power, 1.8V ±5% VDDD 34 Power, Digital Digital Power, 1.8V ±5% Power, Digital Power for I/O stage. The single-ended inputs and SDA, SCL are powered from VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10% Ground, DAP DAP must be grounded. DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connected to the ground plane (GND) with at least 16 vias. DOUT+ 17 DOUTPOWER AND GROUND VDDIO VSS 4 31 DAP Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS90UB903Q DS90UB904Q DS90UB903Q, DS90UB904Q www.ti.com SNLS332E – JUNE 2010 – REVISED APRIL 2013 PASS 37 GPI[3] VDDIO1 ROUT[0] ROUT[1] ROUT[2] ROUT[3] 31 30 29 28 27 26 25 33 GPI[1] GPI[0] 34 GPI[2] LOCK 35 32 VDDR PDB 36 DS90UB904Q Pin Diagram DAP = GND 24 ROUT[4] RES/CMLOUTP 38 23 ROUT[5] RES/CMLOUTN 39 22 ROUT[6] VDDCML 40 21 ROUT[7] RIN+ 41 20 VDDIO2 RIN- 42 19 ROUT[8] DS90UB904Q Deserializer 48-Pin WQFN (Top View) 8 9 10 11 12 ROUT[16] ROUT[15] ROUT[14] ROUT[13] ROUT[17] 13 ROUT[18] 48 7 ROUT[12] 6 14 VDDIO3 47 ID[x] 5 MODE ROUT[19] ROUT[11] ROUT[20] ROUT[10] 15 4 16 46 3 45 RES PCLK VDDPLL VDDSSCG VDDD 2 ROUT[9] 17 1 18 44 SCL 43 SDA RES BISTEN Deserializer - DS90UB904Q 48 Pin WQFN (Top View) See Package Number RHS0048A DS90UB904Q DESERIALIZER PIN DESCRIPTIONS Pin Name Pin No. I/O, Type Description LVCMOS PARALLEL INTERFACE ROUT[20:0] PCLK 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, 19, 21, 22, 23, 24, 25, 26, 27, 28 4 Outputs, LVCMOS Parallel data outputs. Output, LVCMOS Pixel Clock Output Pin. Strobe edge set by RRFB control register. GENERAL PURPOSE INPUT (GPI) GPI[3:0] 30, 31, 32, 33 Input, LVCMOS General-purpose input pins can be used to control and respond to various commands. BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE SCL 2 Input/Output, Open Drain Clock line for the bidirectional control bus communication SCL requires an external pull-up resistor to VDDIO. SDA 1 Input/Output, Open Drain Data line for bidirectional control bus communication SDA requires an external pull-up resistor to VDDIO. MODE 47 ID[x] 48 I2C Mode select MODE = L, Master mode; Device generates and drives the SCL clock line, where Input, LVCMOS required such as Read. Device is connected to slave peripheral on the bus. w/ pull up MODE = H, Slave mode (default); Device accepts SCL clock input and attached to an I2C controller master on the bus. Slave mode does not generate the SCL clock, but uses the clock generated by the Master for the data transfers. Input, analog Device ID Address Select Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 4. CONTROL AND CONFIGURATION Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS90UB903Q DS90UB904Q Submit Documentation Feedback 5 DS90UB903Q, DS90UB904Q SNLS332E – JUNE 2010 – REVISED APRIL 2013 www.ti.com DS90UB904Q DESERIALIZER PIN DESCRIPTIONS (continued) Pin Name Pin No. PDB 35 LOCK 34 RES I/O, Type Description Power down Mode Input Pin. PDB = H, Deserializer is enabled and is ON. Input, LVCMOS PDB = L, Deserializer is in Power Down mode. When the Deserializer is in Power w/ pull down Down. Programmed control register data are NOT retained and reset to default values. Output, LVCMOS 38, 39, 43, 46 - LOCK Status Output Pin. LOCK = H, PLL is Locked, outputs are active LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by OSS_SEL control register. May be used as Link Status. Reserved. Pins 38, 39: Route to test point or leave open if unused. See also FPD-LINK III INTERFACE pin description section. Pin 46: This pin MUST be tied LOW. Pin 43: Leave pin open. BIST MODE BISTEN 44 PASS 37 BIST Enable Pin. Input, LVCMOS BISTEN = H, BIST Mode is enabled. w/ pull down BISTEN = L, BIST Mode is disabled. Output, LVCOMS PASS Output Pin for BIST mode. PASS = H, ERROR FREE Transmission PASS = L, one or more errors were detected in the received payload. Leave Open if unused. Route to test point (pad) recommended. FPD-LINK III INTERFACE RIN+ 41 Input/Output, CML Non-inverting differential input, bidirectional control channel output. The interconnect must be AC Coupled with a 100 nF capacitor. RIN- 42 Input/Output, CML Inverting differential input, bidirectional control channel output. The interconnect must be AC Coupled with a 100 nF capacitor. CMLOUTP 38 Output, CML Non-inverting CML Output Monitor point for equalized differential signal. Test port is enabled via control registers. CMLOUTN 39 Output, CML Inverting CML Output Monitor point for equalized differential signal. Test port is enabled via control registers. VDDSSCG 3 Power, Digital SSCG Power, 1.8V ±5% Power supply must be connected regardless if SSCG function is in operation. VDDIO1/2/3 29, 20, 7 Power, Digital LVCMOS I/O Buffer Power, The single-ended outputs and control input are powered from VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10% POWER AND GROUND VDDD 17 Power, Digital Digital Core Power, 1.8V ±5% VDDR 36 Power, Analog Rx Analog Power, 1.8V ±5% VDDCML 40 Power, Analog Bidirectional Channel Driver Power, 1.8V ±5% VDDPLL 45 Power, Analog PLL Power, 1.8V ±5% DAP Ground, DAP DAP must be grounded. DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connected to the ground plane (GND) with at least 16 vias. VSS These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS90UB903Q DS90UB904Q DS90UB903Q, DS90UB904Q www.ti.com SNLS332E – JUNE 2010 – REVISED APRIL 2013 Absolute Maximum Ratings (1) (2) (3) −0.3V to +2.5V Supply Voltage – VDDn (1.8V) −0.3V to +4.0V Supply Voltage – VDDIO −0.3V to + (VDDIO + 0.3V) LVCMOS Input Voltage I/O Voltage −0.3V to +(VDD + 0.3V) CML Driver I/O Voltage (VDD) −0.3V to (VDD + 0.3V) CML Receiver I/O Voltage (VDD) Junction Temperature +150°C Storage Temperature −65°C to +150°C Maximum Package Power Dissipation Capacity 1/θJA °C/W above +25° Package Derating θJA(based on 16 thermal vias) 40 Lead WQFN 48 Lead WQFN 30.7 °C/W θJC(based on 16 thermal vias) 6.8 °C/W θJA(based on 16 thermal vias) 26.9 °C/W θJC(based on 16 thermal vias) 4.4 °C/W ESD Rating (IEC 61000-4-2) RD = 330Ω, CS = 150pF ≥±25 kV Air Discharge (DOUT+, DOUT-, RIN+, RIN-) ≥±10 kV Contact Discharge (DOUT+, DOUT-, RIN+, RIN-) ESD Rating (ISO10605) RD = 330Ω, CS = 150/330pF ESD Rating (ISO10605) RD = 2KΩ, CS = 150/330pF Air Discharge (DOUT+, DOUT-, RIN+, RIN-) ≥±15 kV Contact Discharge (DOUT+, DOUT-, RIN+, RIN-) ≥±10 kV ≥±8 kV ESD Rating (HBM) ≥±1 kV ESD Rating (CDM) ≥±250 V ESD Rating (MM) (1) (2) (3) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional; the device should not be operated beyond such conditions. For soldering specifications: see product folder at www.ti.com If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. Recommended Operating Conditions (1) Min Nom Max Units Supply Voltage (VDDn) 1.71 1.8 1.89 V LVCMOS Supply Voltage (VDDIO) OR 1.71 1.8 1.89 V 3.0 3.3 LVCMOS Supply Voltage (VDDIO) Supply Noise 3.6 V VDDn (1.8V) 25 mVp-p VDDIO (1.8V) 25 mVp-p VDDIO (3.3V) 50 mVp-p +105 °C 43 MHz Operating Free Air Temperature (TA) -40 PCLK Clock Frequency 10 (1) +25 Supply noise testing was done with minimum capacitors (as shown on Figure 37 and Figure 38) on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8V) supply with amplitude = 25 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 1 MHz. The Des on the other hand shows no error when the noise frequency is less than 750 kHz. Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS90UB903Q DS90UB904Q Submit Documentation Feedback 7 DS90UB903Q, DS90UB904Q SNLS332E – JUNE 2010 – REVISED APRIL 2013 www.ti.com Electrical Characteristics (1) (2) (3) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units LVCMOS DC SPECIFICATIONS 3.3V I/O (SER INPUTS, DES OUTPUTS, GPI, GPO, CONTROL INPUTS AND OUTPUTS) VIH High Level Input Voltage VIN = 3.0V to 3.6V 2.0 VIN V VIL Low Level Input Voltage VIN = 3.0V to 3.6V GND 0.8 V IIN Input Current VIN = 0V or 3.6V, VIN = 3.0V to 3.6V -20 +20 µA VOH High Level Output Voltage VDDIO = 3.0V to 3.6V, IOH = −4 mA 2.4 VDDIO V VOL Low Level Output Voltage VDDIO = 3.0V to 3.6V, IOL = +4 mA GND 0.4 V IOS IOZ Output Short Circuit Current VOUT = 0V TRI-STATE Output Current PDB = 0V, VOUT = 0V or VDD ±1 Serializer GPO Outputs -24 Deserializer LVCMOS Outputs -39 LVCMOS Outputs mA -20 ±1 +20 µA LVCMOS DC SPECIFICATIONS 1.8V I/O (SER INPUTS, DES OUTPUTS, GPI, GPO, CONTROL INPUTS AND OUTPUTS) VIH High Level Input Voltage VIN = 1.71V to 1.89V 0.65 VIN VIN +0.3 VIL Low Level Input Voltage VIN = 1.71V to 1.89V GND 0.35 VIN IIN Input Current VIN = 0V or 1.89V, VIN = 1.71V to 1.89V VOH High Level Output Voltage VDDIO = 1.71V to 1.89V, IOH = −4 mA VOL Low Level Output Voltage VDDIO = 1.71V to 1.89V IOL = +4 mA V IOS IOZ Output Short Circuit Current VOUT = 0V TRI-STATE Output Current PDB = 0V, VOUT = 0V or VDD Deserializer LVCMOS Outputs -20 ±1 +20 µA VDDIO 0.45 VDDIO V GND 0.45 V Serializer GPO Outputs -11 Deserializer LVCMOS Outputs -20 LVCMOS Outputs mA -20 ±1 +20 µA 268 340 412 mV 1 50 mV VDD - VOD VDD (MAX) VOD (MIN) V 1 50 mV CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-) |VOD| Output Differential Voltage RT = 100Ω (Figure 8) ΔVOD Output Differential Voltage Unbalance RL = 100Ω VOS Output Differential Offset Voltage RL = 100Ω (Figure 8) ΔVOS Offset Voltage Unbalance RL = 100Ω IOS Output Short Circuit Current DOUT+/- = 0V RT Differential Internal Termination Resistance Differential across DOUT+ and DOUT- VDD (MIN) VOD (MAX) -27 80 100 mA 120 Ω CML RECEIVER DC SPECIFICATIONS (RIN+, RIN-) (1) (2) (3) 8 The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD, VTH and VTL which are differential voltages. Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS90UB903Q DS90UB904Q DS90UB903Q, DS90UB904Q www.ti.com SNLS332E – JUNE 2010 – REVISED APRIL 2013 Electrical Characteristics(1)(2)(3) (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Differential Threshold High Voltage VTH Conditions Min Typ Max Units +90 (Figure 10) mV VTL Differential Threshold Low Voltage VIN Differential Input Voltage Range RIN+ - RIN- 180 IIN Input Current VIN = VDD or 0V, VDD = 1.89V -20 ±1 +20 µA RT Differential Internal Termination Resistance Differential across RIN+ and RIN- 80 100 120 Ω 62 90 -90 mV SER/DES SUPPLY CURRENT *DIGITAL, PLL, AND ANALOG VDD IDDT RT = 100Ω Serializer (Tx) WORST CASE pattern VDDn Supply Current (Figure 5) (includes load RT = 100Ω current) RANDOM PRBS-7 pattern VDDn = 1.89V PCLK = 43 MHz Default Registers IDDIOT Serializer (Tx) RT = 100Ω VDDIO Supply WORST CASE pattern Current (includes load (Figure 5) current) IDDTZ IDDIOTZ IDDR Serializer (Tx) Supply PDB = 0V; All other Current Power-down LVCMOS Inputs = 0V VDDn = 1.89V, CL = 8 pF Deserializer (Rx) WORST CASE Pattern VDDn Supply Current (Figure 5) (includes load VDDn = 1.89V, CL = 8 pF current) RANDOM PRBS-7 Pattern IDDIOR IDDRZ IDDIORZ VDDIO = 1.89V, CL = 8 pF Deserializer (Rx) WORST CASE Pattern VDDIO Supply (Figure 5) Current (includes load VDDIO = 3.6V, CL = 8 pF current) WORST CASE Pattern Deserializer (Rx) Supply Current Power-down PDB = 0V; All other LVCMOS Inputs = 0V mA 55 VDDIO = 1.89V PCLK = 43 MHz Default Registers 2 VDDIO = 3.6V PCLK = 43 MHz Default Registers 7 15 VDDn = 1.89V 370 775 VDDIO = 1.89V 55 125 VDDIO = 3.6V 65 135 PCLK = 43 MHz SSCG[3:0] = ON Default Registers 60 96 PCLK = 43 MHz Default Registers 53 PCLK = 43 MHz Default Registers 21 32 PCLK = 43 MHz Default Registers 49 83 VDDn = 1.89V 42 400 VDDIO = 1.89V 8 40 VDDIO = 3.6V 350 800 5 mA µA mA µA Recommended Serializer Timing for PCLK (1) Over recommended operating supply and temperature ranges unless otherwise specified. Min Typ Max Units tTCP Symbol Transmit Clock Period 23.3 T 100 ns tTCIH Transmit Clock Input High Time 0.4T 0.5T 0.6T ns tTCIL Transmit Clock Input Low Time 0.4T 0.5T 0.6T ns tCLKT PCLK Input Transition Time (Figure 11) 3 ns fOSC Internal oscillator clock source (1) Parameter Conditions 10 MHz – 43 MHz 0.5 25 MHz Recommended Input Timing Requirements are input specifications and not tested in production. Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS90UB903Q DS90UB904Q Submit Documentation Feedback 9 DS90UB903Q, DS90UB904Q SNLS332E – JUNE 2010 – REVISED APRIL 2013 www.ti.com Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units tLHT CML Low-to-High Transition Time RL = 100Ω (Figure 6) 150 330 ps tHLT CML High-to-Low Transition Time RL = 100Ω (Figure 6) 150 330 ps tDIS Data Input Setup to PCLK tDIH Data Input Hold from PCLK tPLD Serializer PLL Lock Time RL = 100Ω (1) (2) Serializer Delay RT = 100Ω, PCLK = 10–43 MHz Register 0x03h b[0] (TRFB = 1) (Figure 14) Serializer Output Deterministic Jitter Serializer output intrinsic deterministic jitter . Measured (cycle-cycle) with PRBS-7 test pattern PCLK = 43 MHz (3) (4) 0.13 UI Serializer Output Random Jitter Serializer output intrinsic random jitter (cycle-cycle). Alternating-1,0 pattern. PCLK = 43 MHz (3) (4) 0.04 UI Peak-to-peak Serializer Output Jitter Serializer output peak-to-peak jitter includes deterministic jitter, random jitter, and jitter transfer from serializer input. Measured (cycle-cycle) with PRBS-7 test pattern. PCLK = 43 MHz (3) (4) 0.396 UI λSTXBW Serializer Jitter Transfer Function -3 dB Bandwidth PCLK = 43 MHz, Default Registers (Figure 20) (3) 1.90 MHz δSTX Serializer Jitter Transfer Function (Peaking) PCLK = 43 MHz, Default Registers (Figure 20) (3) 0.944 dB δSTXf Serializer Jitter Transfer Function (Peaking Frequency) PCLK = 43 MHz, Default Registers (Figure 20) (3) 500 kHz tSD tJIND tJINR tJINT (1) (2) (3) (4) Serializer Data Inputs (Figure 12) 2.0 ns 2.0 ns 6.386T +5 1 2 ms 6.386T + 12 6.386T + 19.7 ns tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK Specification is ensured by design. Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency. Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Min Typ Max Units tRCP Symbol Receiver Output Clock Period tRCP = tTCP PCLK 23.3 T 100 ns tPDC PCLK Duty Cycle Default Registers SSCG[3:0] = OFF PCLK 45 50 55 % tCLH LVCMOS Low-to-High Transition Time 1.3 2.0 2.8 1.3 2.0 2.8 1.6 2.4 3.3 1.6 2.4 3.3 0.38T 0.5T 0.38T 0.5T tCHL Parameter Conditions LVCMOS High-to-Low Transition Time LVCMOS Low-to-High Transition Time tCLH tCHL LVCMOS High-to-Low Transition Time tROS ROUT Setup Data to PCLK tROH (1) 10 ROUT Hold Data to PCLK Pin/Freq. VDDIO: 1.71V to 1.89V or 3.0 to 3.6V, CL = 8 pF (lumped load) Default Registers (Figure 16) (1) PCLK VDDIO: 1.71V to 1.89V or 3.0 to 3.6V, CL = 8 pF (lumped load) Default Registers (Figure 16) (1) Deserializer ROUTn Data Outputs VDDIO: 1.71V to 1.89V or 3.0V to 3.6V, CL = 8 pF (lumped load) Default Registers Deserializer ROUTn Data Outputs ns ns ns Specification is ensured by characterization and is not tested in production. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS90UB903Q DS90UB904Q DS90UB903Q, DS90UB904Q www.ti.com SNLS332E – JUNE 2010 – REVISED APRIL 2013 Deserializer Switching Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units 4.571T +8 4.571T + 12 4.571T + 16 ns 10 ms tDD Deserializer Delay Default Registers Register 0x03h b[0] (RRFB = 1) (Figure 17) 10 MHz–43 MHz tDDLT Deserializer Data Lock Time (Figure 15) (2) 10 MHz–43 MHz tRJIT Receiver Input Jitter Tolerance (Figure 19, Figure 21) (3) (4) 43 MHz 0.53 Receiver Clock Jitter PCLK SSCG[3:0] = OFF (1) (5) 10 MHz 300 550 43 MHz 120 250 Deserializer Period Jitter PCLK SSCG[3:0] = OFF (1) (6) 10 MHz 425 600 43 MHz 320 480 Deserializer Cycle-to-Cycle Clock Jitter PCLK SSCG[3:0] = OFF (1) (7) 10 MHz 320 500 43 MHz 300 500 LVCMOS Output Bus SSC[3:0] = ON (Figure 22) 20 MHz–43 MHz ±0.5% to ±2.0% % 20 MHz–43 MHz 9 kHz to 66 kHz kHz tRCJ tDPJ tDCCJ fdev Spread Spectrum Clocking Deviation Frequency fmod Spread Spectrum Clocking Modulation Frequency (2) (3) (4) (5) (6) (7) UI ps ps ps tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency. tRJIT max (0.61UI) is limited by instrumentation and actual tRJIT of in-band jitter at low frequency (0 tLOW SCL Low Period 4.7 µs tHIGH SCL High Period 4.0 µs tHD:STA Hold time for a start or a repeated start condition 4.0 µs tSU:STA Set Up time for a start or a repeated start condition 4.7 µs tHD:DAT Data Hold Time tSU:DAT Data Set Up Time 250 ns tSU:STO Set Up Time for STOP Condition 4.0 µs tr SCL & SDA Rise Time 1000 tf SCL & SDA Fall Time 300 ns Cb Capacitive load for bus 400 pF fSCL = 100 kHz 0 3.45 µs ns SWITCHING CHARACTERISTICS (2) fSCL SCL Clock Frequency tLOW Serializer MODE = 0 – R/W Register 0x05 = 0x40'h 100 Deserializer MODE = 0 – READ Register 0x06 b[6:4] = 0x00'h 100 kHz Serializer MODE = 0 – R/W Register 0x05 = 0x40'h SCL Low Period Deserializer MODE = 0 – READ Register 0x06 b[6:4] = 0x00'h Serializer MODE = 0 – R/W Register 0x05 = 0x40'h 4.7 µs 4.0 µs tHIGH SCL High Period tHD:STA Hold time for a start or a repeated start condition Serializer MODE = 0 Register 0x05 = 0x40'h 4.0 µs tSU:STA Set Up time for a start or a repeated start condition Serializer MODE = 0 Register 0x05 = 0x40'h 4.7 µs tHD:DAT Data Hold Time tSU:DAT Data Set Up Time tSU:STO Set Up Time for STOP Condition tf SCL & SDA Fall Time tBUF Bus free time between a stop and start condition tTIMEOUT NACK Time out (1) (2) 12 Deserializer MODE = 0 – READ Register 0x06 b[6:4] = 0x00'h 0 Serializer MODE = 0 3.45 250 ns 4.0 µs 300 Serializer MODE = 0 µs 4.7 ns µs Serializer MODE = 1 1 Deserializer MODE = 1 Register 0x06 b[2:0]=111'b 25 ms Recommended Input Timing Requirements are input specifications and not tested in production. Specification is ensured by design. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS90UB903Q DS90UB904Q DS90UB903Q, DS90UB904Q www.ti.com SNLS332E – JUNE 2010 – REVISED APRIL 2013 SDA tf tHD;STA tLOW tBUF tr tf tr SCL tSU;STA tHD;STA tHIGH tSU;STO tSU;DAT tHD;DAT START STOP REPEATED START START Figure 4. Bidirectional Control Bus Timing Bidirectional Control Bus DC Characteristics (SCL, SDA) - I2C Compliant Over recommended supply and temperature ranges unless otherwise specified. Symbol Parameter Max Units SDA and SCL 0.7 x VDDIO VDDIO V Input Low Level Voltage SDA and SCL GND 0.3 x VDDIO V VHY Input Hysteresis SDA and SCL IOZ TRI-STATE Output Current PDB = 0V, VOUT = 0V or VDD -20 ±1 +20 µA IIN Input Current SDA or SCL, Vin = VDDIO or GND -20 ±1 +20 µA CIN Input Pin Capacitance VIH Input High Level VIL Conditions Min Typ >50 mV