DS90UB913A-Q1
DS90UB913A-Q1
SNLS443G – MAY 2013 – REVISED
NOVEMBER 2020
SNLS443G – MAY 2013 – REVISED NOVEMBER 2020
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DS90UB913A-Q1 25-MHz to 100-MHz 10- and 12-Bit FPD-Link III Serializer
1 Features
3 Description
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The DS90UB913A-Q1 device offers an FPD-Link III
interface with a high-speed forward channel and a
bidirectional control channel for data transmission
over a single coaxial cable or differential pair. The
DS90UB913A-Q1 device incorporates differential
signaling on both the high-speed forward channel and
bidirectional control channel data paths. The
serializer/deserializer pair is targeted for connections
between imagers and video processors in an ECU
(Electronic Control Unit). This device is ideally suited
for driving video data requiring up to 12-bit pixel depth
plus two synchronization signals along with
bidirectional control channel bus.
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AEC-Q100 qualified for automotive applications
– Device temperature grade 2: –40℃ to +105℃
ambient operating temperature
25-MHz to 100-MHz input pixel clock support
Programmable data payload:
– 10-Bit payload up to 100 MHz
– 12-Bit payload up to 75 MHz
Continuous low latency bidirectional control
interface channel with I2C support at 400 kHz
Embedded clock with DC-balanced coding to
support AC-coupled interconnects
Capable of driving up to 15m coaxial or 20m
shielded twisted-pair cables
Robust Power-Over-Coaxial (PoC) operation
4 Dedicated general purpose input/output
1.8-V, 2.8-V, or 3.3-V-compatible parallel inputs on
serializer
Single power supply at 1.8 V
ISO 10605 and IEC 61000-4-2 ESD compliant
Small serializer footprint (5 mm × 5 mm)
2 Applications
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Automotive
– Surround View Systems (SVS)
– Front Cameras (FC)
– Rear View Cameras (RVC)
– Sensor fusion
– Driver Monitor Cameras (DMS)
– Remote satellite RADAR, ToF, and LIDAR
sensors
Security and surveillance
Machine vision applications
Parallel
Data In
10 or 12
Using TI’s embedded clock technology allows
transparent full-duplex communication over a single
differential pair, carrying asymmetrical-bidirectional
control channel information. This single serial stream
simplifies transferring a wide data bus over PCB
traces and cable by eliminating the skew problems
between parallel data and clock paths. This
significantly saves system cost by narrowing data
paths that in turn reduce PCB layers, cable width, and
connector size and pins. Internal DC-balanced
encoding/decoding is used to support AC-coupled
interconnects.
Device Information
PART NUMBER(1)
DS90UB913A-Q1
(1)
HSYNC,
VSYNC
2
DS90UB913AQ1
4
Serializer
Bidirectional
Control Channel
5.00 mm × 5.00 mm
Parallel
Data Out
10 or 12
FPD-Link III
GPO
2
Bidirectional
Control Bus
WQFN (32)
BODY SIZE (NOM)
For all available packages, see the orderable addendum at
the end of the data sheet.
2
Megapixel
Imager/Sensor
PACKAGE
DS90UB914AQ1
HSYNC,
VSYNC
4
DSP, FPGA/
µ-Processor/
ECU
GPIO
2
Deserializer
Bidirectional
Control Bus
Copyright © 2016, Texas Instruments Incorporated
Simplified Schematic
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2020 Texas Instruments
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intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................5
Pin Functions: DS90UB913A-Q1 Serializer......................5
6 Specifications.................................................................. 8
6.1 Absolute Maximum Ratings........................................ 8
6.2 ESD Ratings............................................................... 8
6.3 Recommended Operating Conditions.........................8
6.4 Thermal Information....................................................9
6.5 Electrical Characteristics (1) (2) (3) ...............................9
6.6 Recommended Serializer Timing For PCLK (5) (6) ....12
6.7 AC Timing Specifications (SCL, SDA) - I2CCompatible.................................................................. 13
6.8 Bidirectional Control Bus DC Timing
Specifications (SCL, SDA) - I2C-Compatible (4) ......... 13
6.9 Timing Diagrams....................................................... 14
6.10 Serializer Switching Characteristics........................16
6.11 Typical Characteristics............................................ 17
7 Detailed Description......................................................18
7.1 Overview................................................................... 18
7.2 Functional Block Diagram......................................... 18
7.3 Feature Description...................................................18
7.4 Device Functional Modes..........................................22
7.5 Programming............................................................ 27
7.6 Register Maps...........................................................31
8 Layout.............................................................................46
8.1 Layout Guidelines..................................................... 46
8.2 Layout Example........................................................ 47
9 Device and Documentation Support............................49
9.1 Documentation Support............................................ 49
9.2 Receiving Notification of Documentation Updates....49
9.3 Support Resources................................................... 49
9.4 Trademarks............................................................... 49
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (January 2020) to Revision G (November 2020)
Page
• Added register 0x27[3] to register map.............................................................................................................31
• Clarified PDB voltage level for t3 and t4 in Power-Up Sequencing from 90% VPDB to PDB VIH ...................... 38
• Changed Power-Up Sequencing alternative programming steps (t3*) to add NCLK reset............................... 38
• Clarified Power-Up Sequencing alternative programming steps (t3*) to remove delay between I2C commands
..........................................................................................................................................................................38
Changes from Revision E (September 2018) to Revision F (January 2020)
Page
• Clarified GPO2 description by removing statement about leaving pin open if unused ...................................... 5
• Added register 0x27[5] to register map ............................................................................................................31
• Fixed missing register 0x29 typo ..................................................................................................................... 31
• Added maximum power up timing constraint between VDD_n and PDB ........................................................ 38
• Added recommended software programming steps if VDD_n to PDB maximum power up timing constraint
can not be met ................................................................................................................................................. 38
Changes from Revision D (October 2016) to Revision E (September 2018)
Page
• Added recommendation to ensure GPO2 is low when PDB goes high ............................................................. 5
• Added Power Over Coax supply noise to the recommended operating conditions table................................... 8
• Clarified PCLK clock frequency range and added external clock input frequency range................................... 8
• Added strap pin input current specification for MODE and IDX pins ................................................................. 9
• Updated TJIT1 PCLK input jitter in the external oscillator mode ....................................................................... 12
• Added clarification on MODE pin description in PCLK from imager mode ...................................................... 23
• Updated pullup and pulldown resistor to R1 and R2 in MODE pin configuration diagram ............................... 23
• Updated the MODE setting values to ratio....................................................................................................... 23
• Updated pullup and pulldown resistor for IDX to R3 and R4 in the diagram..................................................... 29
• Updated IDX setting values to ratio ................................................................................................................. 29
• Updated register "TYPE" column per legend ...................................................................................................31
• Added type and default value to the reserved register bits that were missing this information ....................... 31
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DS90UB913A-Q1
SNLS443G – MAY 2013 – REVISED NOVEMBER 2020
Added that register 0x00[7:1] does not auto update IDX strapped address .................................................... 31
Added description for 0x05 bits 1 and 0 (TX_MODE_12b and TX_MODE_10b) ............................................ 31
Clarified description on PDB pin usage during power up ................................................................................ 38
Added paragraph to explain setting registers if GPO2 state is not determined when PDB goes high ............ 38
Added GPO2 to suggested power-up sequencing diagram ............................................................................ 38
Added timing constraint for PDB to GPO2 delay ............................................................................................. 38
Revised coax connection diagram to include pulldown resistor for GPO2 ...................................................... 42
Revised STP connection diagram to include pulldown resistor for GPO2 .......................................................44
Changes from Revision C (April 2016) to Revision D (August 2016)
Page
• Added back channel line rate = 5.5 MHz as test condition; also added footnote for clarification between MHz
and Mbps distinction........................................................................................................................................... 9
• Removed 'ns' unit from specifications referencing period in units of T............................................................. 12
• Updated test condition specs for jitter bandwidth regarding tJIT0, tJIT1, and tJIT2.............................................. 12
• Added input external oscillator frequency range for pin/freq. .......................................................................... 12
• Added parameter for typical external oscillator frequency stability................................................................... 12
• Added test conditions to tJIND, tJINR, and tJINT...................................................................................................16
• Added DOUT± as measured output pins for jitter parameters..........................................................................16
• Added note (6) for "Serializer output peak-to-peak total jitter includes deterministic jitter, random jitter, and
jitter transfer from serializer input". .................................................................................................................. 16
• Added jitter tolerance curve for typical system IJT configuration with DS90UB913A linked to DS90UB914A. ...
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• Added device functional mode table for external oscillator operation with example XCLKIN = 48MHz. ......... 22
Changes from Revision B (December 2014) to Revision C (March 2016)
Page
• Split document into two separate documents for parts DS90UB913A-Q1 and DS90UB914A-Q1. ................... 1
• Modified Automotive Features ........................................................................................................................... 1
• Updated pin description for DIN to include active/inactive outputs corresponding to MODE setting..................5
• Added pin description to GPO pins to leave open if unused. ............................................................................ 5
• Changed Air Discharge ESD Rating (IEC61000-4-2: RD = 330 Ω, CS = 150 pF) to minimum ±25000 V. ........ 8
• Added RTV text to Thermal Information table.....................................................................................................9
• Added GPO[3:0] typical pin capacitances. ........................................................................................................ 9
• Changed Differential Output Voltage minimum specification. ............................................................................9
• Changed Single-Ended Output Voltage minimum specification......................................................................... 9
• Added Back Channel Differential Input Voltage minimum specification............................................................. 9
• Added Back Channel Single-Ended Input Voltage minimum specification......................................................... 9
• Updated IDDT for VDD_n=1.89V, VDDIO=3.6V, RL=100Ω, Random Pattern with f=100 MHz, 10-bit mode to
typical value of 65 mA; value is currently 54 mA................................................................................................ 9
• Updated IDDT for VDD_n=1.89V, VDDIO=3.6V, RL=100Ω, Random Pattern with f=75 MHz, 12-bit high freq
mode to typical value of 64 mA; value is currently 54 mA.................................................................................. 9
• Updated IDDT for VDD_n=1.89V, VDDIO=3.6V, RL=100Ω, Random Pattern with f=50 MHz, 12-bit low freq mode
to typical value of 63 mA; value is currently 54 mA. .......................................................................................... 9
• Updated frequency ranges for MODE settings and also revised with correct maximum clock periods. Added
footnote and nominal clock period to be in terms of 'T'.(6) ............................................................................... 12
• Deleted Revised jitter freq. test conditions to be > f/20 and also updated typical values for tjit0and tjit2........... 12
• Updated VOL Output Low Level row with revised IOL currents and max VOL voltages, dependent upon VDD IO
voltage. ............................................................................................................................................................ 13
• Updated Figure 2 title to state ‘“Worst-Case” Test Pattern for Power Consumption’. ...................................... 14
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Added footnote that states the following: “UI – Unit Interval is equivalent to one serialized data bit width. The
UI scales with PCLK frequency.” Add below calculations to footnote. 12-bit LF mode 1 UI = 1 / ( PCLK_Freq.
x 28 ) 12-bit HF mode 1 UI = 1 / ( PCLK_Freq. x 2/3 x 28 ) 10-bit mode 1 UI = 1 / ( PCLK_Freq. /2 x 28 ) ....16
Updated frequency requirements for 10-bit and 12-bit HF modes. 10-bit mode – 50 MHz to 100 MHz; 12-bit
HF mode – 37.5 MHz to 75 MHz; 12-bit LF mode (no change) – 25 MHz to 50 MHz. .................................... 18
Updated register 0x01[1] default value to be “0”...............................................................................................31
Changed GPO0 Enable for 0x0D[4] to GPO1 Enable...................................................................................... 31
Added Inject Forward Channel Error Register 0x2D........................................................................................ 31
Updated power up sequencing information and timing diagram. .....................................................................38
Added description specifying that the voltage applied on VDDIO (1.8 V, 3.3 V) or VDD_n (1.8 V) should be at the
input pin – any board level DC drop should be compensated. ...................................................................... 0
Added 913A EVM layout example image. ....................................................................................................... 47
Changes from Revision A (June 2013) to Revision B (December 2014)
Page
• Added datasheet flow and layout to conform with new TI standards. Added the following sections: Device
Comparison Table; Handling Ratings; Application and Implementation; Power Supply Recommendations;
Layout; Device and Documentation Support; Mechanical, Packaging, and Ordering Information .................... 1
• Added additional thermal characteristics............................................................................................................ 9
• Changed typo in Vout test condition from RL=500Ω to RL=50Ω. ....................................................................... 9
• Changed Figure 6-6 to use VODp-p and to clarify difference between STP and Coax.......................................14
• Added Internal Oscillator section to Device Functional Modes.........................................................................24
• Added reference to Power over Coax Application report..................................................................................38
• Added power up sequencing information and timing diagram..........................................................................38
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Device Comparison Table
PART NUMBER
FPD-III FUNCTION
PACKAGE
TRANSMISSION MEDIA
PCLK FREQUENCY
DS90UB913Q-Q1
Serializer
WQFN RTV (32)
STP
10 to 100 MHz
DS90UB913A-Q1
Serializer
WQFN RTV (32)
Coax or STP
25 to 100 MHz
DIN[1]
16
15
14
13
12
11
10
VDDPLL
PDB
DIN[8]
DAP = GND
DS90UB913A-Q1
Serializer
2
3
4
5
6
7
VSYNC
PCLK
SCL
SDA
ID[x]
RES
8
MODE
1
HSYNC
32
26
VDDT
27
DOUT-
28
DOUT+
9
GPO[2]/
CLKOUT
DIN[2]
17
29
18
30
19
GPO[3]/
CLKIN
DIN[3]
DIN[0]
DIN[4]
20
25
21
VDDCML
VDDD
DIN[11]
22
GPO[0]
DIN[7]
DIN[10]
23
GPO[1]
DIN[6]
DIN[9]
24
31
VDDIO
DIN[5]
5 Pin Configuration and Functions
Figure 5-1. 32-Pin WQFN Package RTV Top View
Pin Functions: DS90UB913A-Q1 Serializer
PIN
NAME
I/O
NO.
DESCRIPTION
LVCMOS PARALLEL INTERFACE
19,20,21,22,
23,24,26,27,
29,30,31,32
Inputs,
LVCMOS
w/ pulldown
Parallel Data Inputs. For 10-bit MODE, parallel inputs DIN[0:9] are active. DIN[10:11] are
inactive and should not be used. Any unused inputs (including DIN[10:11]) should be No
Connect. For 12-bit MODE (HF or LF), parallel inputs DIN[0:11] are active. Any unused
inputs should be No Connect.
1
Input,
LVCMOS
w/ pulldown
Horizontal SYNC Input. Note: HS transition restrictions: 1. 12-bit Low-Frequency mode: No
HS restrictions (raw) 2. 12-bit High-Frequency mode: No HS restrictions (raw) 3. 10-bit
mode: HS restricted to no more than one transition per 10 PCLK cycles. Leave open if
unused.
VSYNC
2
Input,
LVCMOS
w/ pulldown
Vertical SYNC Input. Note: VS transition restrictions: 1. 12-bit Low-Frequency mode: No VS
restrictions (raw) 2. 12-bit High-Frequency mode: No VS restrictions (raw) 3. 10-bit HighFrequency mode: VS restricted to no more than one transition per 10 PCLK cycles. Leave
open if unused.
PCLK
3
Input,
LVCMOS
w/ pulldown
Pixel Clock Input Pin. Strobe edge set by TRFB control register 0x03[0].
DIN[0:11]
HSYNC
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PIN
NAME
I/O
NO.
DESCRIPTION
GENERAL PURPOSE OUTPUT (GPO)
GPO[1:0]
GPO[2]/
CLKOUT
GPO[3]/
CLKIN
16,15
17
18
Output,
LVCMOS
General-purpose output pins can be configured as outputs; used to control and respond to
various commands. GPO[1:0] can be configured to be the outputs for input signals coming
from GPIO[1:0] pins on the Deserializer or can be configured to be outputs of the local
register on the Serializer. Leave open if unused.
Output,
LVCMOS
GPO[2] pin can be configured to be the output for input signal coming from the GPIO[2] pin
on the Deserializer or can be configured to be the output of the local register on the
Serializer. It can also be configured to be the output clock pin when the DS90UB913A-Q1
device is used in the External Oscillator mode. See Section 7.4 section for a detailed
description of External Oscillator Mode. It is recommended to pull GPO2 to GND with a
minimum 40-kΩ resistor to ensure GPO2=LOW when PDB transitions from LOW to HIGH.
GPO[3] can be configured to be the output for input signals coming from the GPIO[3] pin on
the Deserializer or can be configured to be the output of the local register setting on the
Input/Output,
Serializer. It can also be configured to be the input clock pin when the DS90UB913A-Q1
LVCMOS
Serializer is working with an external oscillator. See Section 7.4 section for a detailed
description of External Oscillator Mode. Leave open if unused.
BIDIRECTIONAL CONTROL BUS - I2C-COMPATIBLE
SCL
4
Input/Output, Clock line for the bidirectional control bus communication
Open Drain SCL requires an external pullup resistor to VDDIO.
SDA
5
Input/Output, Data line for the bidirectional control bus communication
Open Drain SDA requires an external pullup resistor to VDDIO.
MODE
8
Input, analog
ID[x]
6
Device ID Address Select
Input, analog The ID[x] pin on the Serializer is used to assign the I2C device address. Resistor (RID) to
Ground and 10-kΩ pullup to 1.8 V rail. See Table 7-6.
Device Mode Select
Resistor (Rmode) to Ground and 10-kΩ pullup to 1.8 V rail. MODE pin on the Serializer can
be used to select whether the system is running off the PCLK from the imager or an external
oscillator. See details in Table 7-2.
CONTROL AND CONFIGURATION
PDB
9
Input,
LVCMOS
w/ pulldown
RES
7
Input,
LVCMOS
w/ pulldown
Power Down Mode Input Pin
PDB = H, Serializer is enabled and is ON.
PDB = L, Serializer is in Power Down mode. When the Serializer is in Power Down, the PLL
is shutdown, and IDD is minimized. Programmed control register data is NOT retained and
reset to default values.
Reserved
This pin MUST be tied LOW.
FPD–Link III INTERFACE
DOUT+
DOUT-
13
Input/Output, Non-inverting differential output, bidirectional control channel input. The interconnect must
CML
be AC Coupled with a 0.1-µF capacitor.
12
Inverting differential output, bidirectional control channel input. The interconnect must be AC
Input/Output, Coupled with a 0.1-µF capacitor. For applications using single-ended coaxial interconnect, a
CML
0.047-µF AC coupling capacitor should be placed in series with a 50Ω resistor before
terminating to GND.
POWER AND GROUND(1)
6
VDDPLL
10
Power,
Analog
PLL Power, 1.8 V ±5%.
VDDT
11
Power,
Analog
Tx Analog Power, 1.8 V ±5%.
VDDCML
14
Power,
Analog
CML & Bidirectional Channel Driver Power, 1.8 V ±5%.
VDDD
28
Power, Digital Digital Power, 1.8 V ±5%.
VDDIO
25
Power, Digital
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Power for I/O stage. The single-ended inputs and SDA, SCL are powered from VDDIO.
VDDIO can be connected to a 1.8 V ±5% or 2.8 V ±10% or 3.3 V ±10%.
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PIN
NAME
NO.
VSS
DAP
(1)
I/O
Ground, DAP
DESCRIPTION
DAP must be grounded. DAP is the large metal contact at the bottom side, located at the
center of the WQFN package. Connected to the ground plane (GND) with at least 9 vias.
See Section 8.1.2.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Supply Voltage – VDD_n (VDDPLL, VDDT, VDDCML, VDDD)
−0.3
2.5
V
Supply Voltage – VDDIO
−0.3
4.0
V
LVCMOS Input Voltage
−0.3
VDDIO + 0.3
V
CML Driver I/O Voltage – (VDD_n)
-0.3
VDD_n + 0.3
V
150
°C
150
°C
Junction Temperature
Storage temperature range, Tstg
(1)
−65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 3B
Charged device model (CDM), per AEC
Q100-011
CDM ESD Classification Level C6
V(ESD)
Electrostatic discharge (IEC 61000-4-2)
RD = 330 Ω, Cs = 150pF
(ISO10605)
RD = 330 Ω, Cs = 150/330 pF
RD = 2 KΩ, Cs = 150/330 pF
(1)
UNIT
±8000
Corner pins (1, 8, 9, 16, 17, 24,
25, 32)
±1000
Other pins
Air Discharge
(DOUT+, DOUT-, RIN+, RIN-)
±25000
Contact Discharge
(DOUT+, DOUT-, RIN+, RIN-)
±7000
Air Discharge
(DOUT+, DOUT-, RIN+, RIN-)
±15000
Contact Discharge
(DOUT+, DOUT-, RIN+, RIN-)
±8000
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
1.71
1.8
1.89
V
VDDIO= 1.8 V
1.71
1.8
1.89
V
VDDIO= 3.3 V
3
3.3
3.6
VDDIO= 2.8 V
2.52
2.8
3.08
Supply Voltage (VDD_n)
LVCMOS Supply Voltage
Supply Noise(1)
Power-Over-Coax Supply
Noise
VDD_n = 1.8 V
25
VDDIO = 1.8 V
25
VDDIO = 3.3 V
50
ƒ = 30 Hz - 1 KHz, trise > 100 µs
Measured differentially between DOUT+ and DOUT–
(coax mode only)
10
mVp-p
ƒ = 1 KHz - 50 MHz
Measured differentially between DOUT+ and DOUT(coax mode only)
10
mVp-p
Operating Free Air Temperature (TA)
8
mVp-p
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–40
25
105
°C
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over operating free-air temperature range (unless otherwise noted)
MIN
PCLK Clock Frequency
External Clock Input
Frequency to GPO3
(1)
MAX
UNIT
50
100
MHz
12-bit HF mode
37.5
75
MHz
12-bit LF mode
25
50
MHz
10-bit mode
25
50
MHz
12-bit HF mode
25
50
MHz
12-bit LF mode
25
50
MHz
10-bit mode
NOM
Supply noise testing was done with minimum capacitors (as shown on Figure 8-9, Figure 8-5 on the PCB. A sinusoidal signal is AC
coupled to the VDD_n (1.8 V) supply with amplitude = 25 mVp-p measured at the device VDD_n pins. Bit error rate testing of input to the
Ser and output of the Des with 10-meter cable shows no error when the noise frequency on the Ser is less than 1 MHz. The Des on
the other hand shows no error when the noise frequency is less than 750 kHz.
6.4 Thermal Information
DS90UB913A-Q1
THERMAL METRIC(1)
RTV (WQFN)
UNIT
32 PINS
RθJA
Junction-to-ambient thermal resistance
34.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
8.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.4
°C/W
RθJB
Junction-to-board thermal resistance
23.4
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
8.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
6.5 Electrical Characteristics (1) (2) (3)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVCMOS DC SPECIFICATIONS 3.3 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input
Voltage
VIN = 3 V to 3.6 V
2
VIN
V
VIL
Low Level Input
Voltage
VIN = 3 V to 3.6 V
GND
0.8
V
IIN
Input Current
VIN = 0 V or 3.6 V, VIN = 3 V to 3.6 V
–20
20
µA
VOH
High Level Output
Voltage
VDDIO = 3 V to 3.6 V, IOH = −4 mA
2.4
VDDIO
V
VOL
Low Level Output
Voltage
VDDIO = 3 V to 3.6 V, IOL = 4 mA
GND
0.4
V
IOS
Output Short Circuit
Current
VOUT = 0 V
Serializer
GPO Outputs
IOZ
TRI-STATE Output
Current
PDB = 0 V,
VOUT = 0 V or VDDIO
Serializer
GPO Outputs
CGPO
Pin Capacitance
GPO [3:0]
±1
–15
–20
mA
20
1.5
µA
pF
LVCMOS DC SPECIFICATIONS 1.8 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input
Voltage
VIN = 1.71 V to 1.89 V
0.65 VIN
VIN
VIL
Low Level Input
Voltage
VIN = 1.71 V to 1.89 V
GND
0.35 VIN
IIN
Input Current
VIN = 0 V or 1.89 V, VIN = 1.71 V to 1.89 V
V
Copyright © 2020 Texas Instruments Incorporated
–20
±1
20
µA
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SNLS443G – MAY 2013 – REVISED NOVEMBER 2020
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
VOH
High Level Output
Voltage
VDDIO = 1.71 V to 1.89 V, IOH = −4 mA
VOL
Low Level Output
Voltage
VDDIO = 1.71 V to 1.89 V IOL = 4 mA
IOS
Output Short Circuit
Current
VOUT = 0 V
Serializer
GPO Outputs
IOZ
TRI-STATE Output
Current
PDB = 0 V,
VOUT = 0 V or VDDIO
Serializer
GPO Outputs
CGPO
Pin Capacitance
GPO [3:0]
IIN-STRAP
Strap pin input current VIN = 0 V to VDD_n
MIN
TYP
MAX
UNIT
VDDIO - 0.45
VDDIO
V
GND
0.45
V
–11
-20
mA
20
µA
1
µA
1.5
-1
pF
LVCMOS DC SPECIFICATIONS 2.8 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input
Voltage
VIN = 2.52 V to 3.08 V
0.7 VIN
VIN
VIL
Low Level Input
Voltage
VIN = 2.52 V to 3.08 V
GND
0.3 VIN
IIN
Input Current
VIN = 0 V or 3.08 V, VIN = 2.52 V to 3.08 V
VOH
High Level Output
Voltage
VDDIO = 2.52 V to 3.08 V, IOH = −4 mA
VOL
Low Level Output
Voltage
VDDIO =2.52 V to 3.08V IOL = 4 mA
IOS
Output Short Circuit
Current
VOUT = 0 V
Serializer
GPO Outputs
IOZ
TRI-STATE Output
Current
PDB = 0 V,
VOUT = 0 V or VDDIO
Serializer
GPO Outputs
CGPO
Pin Capacitance
GPO [3:0]
V
–20
±1
20
µA
VDDIO - 0.4
VDDIO
V
GND
0.4
V
–11
–20
mA
20
1.5
µA
pF
CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-)
VOD
Differential Output
Voltage
RL = 100 Ω (Figure 6-6), Back Channel Disabled
640
824
VOUT
Single-Ended Output
Voltage
RL = 50 Ω (Figure 6-6), Back Channel Disabled
320
412
ΔVOD
Differential Output
Voltage Unbalance
RL = 100 Ω
VOS
Output Offset Voltage
RL = 100 Ω (Figure 6-6)
ΔVOS
Offset Voltage
Unbalance
RL = 100 Ω
IOS
Output Short Circuit
Current
DOUT+ = 0 V or DOUT– = 0 V
Differential Internal
Termination
Resistance
Differential across DOUT+ and DOUT–
Single-ended
Termination
Resistance
DOUT+ or DOUT–
RT
VID-BC
VIN-BC
Back Channel
Differential Input
Voltage
Back Channel SingleEnded Input Voltage
mV
1
50
VDD_n - VOD/2
1
V
50
–26
80
100
mV
mV
mA
120
Ω
40
50
60
260
mV
130
mV
Back Channel Frequency = 5.5 MHz(10)
SERIALIZER SUPPLY CURRENT
10
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Copyright © 2020 Texas Instruments Incorporated
DS90UB913A-Q1
www.ti.com
SNLS443G – MAY 2013 – REVISED NOVEMBER 2020
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
IDDT
IDDT
IDDIOT
IDDTZ
IDDIOTZ
TEST CONDITIONS
Serializer (Tx)
RL = 100 Ω
VDD_n Supply Current WORST CASE pattern
(includes load current) (Figure 6-2)
Serializer (Tx)
RL = 100 Ω
VDD_n Supply Current RANDOM PRBS-7
(includes load current) pattern
Serializer (Tx)
RL = 100 Ω
VDDIO Supply Current WORST CASE pattern
(includes load current) (Figure 6-2)
Serializer (Tx) Supply
Current Power Down
PDB = 0V; All other
LVCMOS Inputs = 0 V
Serializer (Tx) VDDIO
PDB = 0V; All other
Supply Current Power
LVCMOS Inputs = 0 V
Down
Copyright © 2020 Texas Instruments Incorporated
TYP
MAX
VDD_n = 1.89 V VDDIO
= 3.6 V
f = 100 MHz, 10-bit
mode
Default Registers
MIN
61
80
VDD_n = 1.89 V VDDIO
= 3.6 V
f = 75 MHz, 12-bit
high frequency mode
Default Registers
61
80
VDD_n = 1.89 V VDDIO
= 3.6 V
f = 50 MHz, 12-bit
low frequency mode
Default Registers
61
VDD_n = 1.89 V VDDIO
= 3.6 V
f = 100 MHz, 10-bit
mode
Default Registers
65
VDD_n = 1.89 V VDDIO
= 3.6 V
f = 75 MHz, 12-bit
high frequency mode
Default Registers
64
VDD_n = 1.89 V VDDIO
= 3.6 V
f = 50 MHz, 12-bit
low frequency mode
Default Registers
63
VDDIO = 1.89 V
f = 75 MHz, 12-bit
high frequency mode
Default Registers
1.5
UNIT
mA
mA
80
mA
3
mA
VDDIO = 3.6 V
f = 75 MHz, 12-bit
high frequency
mode Default
Registers
5
8
VDDIO=1.89 V
Default Registers
300
1000
µA
VDDIO = 3.6 V
Default Registers
300
1000
µA
VDDIO = 1.89 V
Default Registers
15
100
µA
VDDIO = 3.6 V
Default Registers
15
100
µA
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6.6 Recommended Serializer Timing For PCLK (5) (6)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN / FREQ
10-bit mode
50 MHz – 100 MHz
tTCP
Transmit Clock Period
12-bit high frequency mode
37.5 MHz - 75MHz
12-bit low frequency mode
25 MHz - 50MHz
MIN
NOM
MAX
10
T
20
ns
13.33
T
26.67
ns
20
T
40
ns
tTCIH
Transmit Clock
Input High Time
0.4T
0.5T
0.6T
tTCIL
Transmit Clock
Input Low Time
0.4T
0.5T
0.6T
0.05T
0.25T
0.3T
0.05T
0.25T
0.3T
0.05T
0.25T
0.3T
10-bit mode
50 MHz – 100 MHz
tCLKT
PCLK Input Transition Time 12-bit high frequency mode
(Figure 6-7)
37.5 MHz - 75MHz
12-bit low frequency mode
25 MHz - 50MHz
tJIT0
PCLK Input Jitter
(PCLK from imager mode)
tJIT1
PCLK Input Jitter
LPF = ƒ/20, CDR PLL Loop BW = ƒPCLK = 25 –
(External Oscillator mode)(3) ƒ/15, BER = 1E-10
100 MHz(8)
tJIT2
External Oscillator Jitter(3)
ΔOSC
External Oscillator
Frequency Stability
12
(3)
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ƒ
= 25 –
LPF = ƒ/20, CDR PLL Loop BW = PCLK (8)
100 MHz
ƒ/15, BER = 1E-10
0.3
UI
0.3
UI
1T
LPF = ƒ/20, CDR PLL Loop BW = ƒOSC = 25 –
ƒ/15, BER = 1E-10
50 MHz(9)
ƒOSC = 25 –
50 MHz(9)
UNIT
±50
ppm
Copyright © 2020 Texas Instruments Incorporated
DS90UB913A-Q1
www.ti.com
SNLS443G – MAY 2013 – REVISED NOVEMBER 2020
6.7 AC Timing Specifications (SCL, SDA) - I2C-Compatible
Over recommended supply and temperature ranges unless otherwise specified. (Figure 6-1)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
100
kHz
400
kHz
RECOMMENDED INPUT TIMING REQUIREMENTS
fSCL
SCL Clock Frequency
Standard Mode
Fast Mode
Standard Mode
4.7
µs
Fast Mode
1.3
µs
Standard Mode
4.0
µs
Fast Mode
0.6
µs
Hold time for a start or a repeated start
condition
Standard Mode
4.0
µs
Fast Mode
0.6
µs
tSU:STA
Set Up time for a start or a repeated
start condition
Standard Mode
4.7
µs
Fast Mode
0.6
µs
tHD:DAT
Data Hold Time
tSU:DAT
Data Set Up Time
tSU:STO
Set Up Time for STOP Condition
tBUF
Bus Free time between Stop and Start
tr
SCL & SDA Rise Time
tf
SCL & SDA Fall Time
tLOW
SCL Low Period
tHIGH
SCL High Period
tHD:STA
Standard Mode
0
3.45
µs
Fast Mode
0
900
ns
Standard Mode
250
ns
Fast Mode
100
ns
Standard Mode
4.0
µs
Fast Mode
0.6
µs
Standard Mode
4.7
µs
Fast Mode
1.3
µs
Standard Mode
1000
ns
Fast Mode
300
ns
Standard Mode
300
ns
Fast Mode
300
ns
6.8 Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible (4)
Over recommended supply and temperature ranges unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
VDDIO
V
RECOMMENDED INPUT TIMING REQUIREMENTS
VIH
Input High Level
SDA and SCL
0.7*VDDIO
VIL
Input Low Level
SDA and SCL
GND
VHY
Input Hysteresis
VOL
Output Low Level(7)
IIN
Input Current
tR
SDA Rise Time-READ
tF
SDA Fall Time-READ
CIN
(1)
(2)
(3)
(4)
(5)
0.3*VDDIO
>50
SDA, VDDIO = 1.8 V, IOL= 0.9 mA
0
0.36
SDA, VDDIO = 3.3 V, IOL= 1.6 mA
0
0.4
SDA or SCL, VIN= VDDIO OR GND
SDA, RPU = 10 kΩ, Cb ≤ 400 pF
(Figure 6-1)
SDA or SCL
−10
10
430
V
mV
V
µA
ns
20
ns
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