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DS90UB914A-Q1
SNLS499D – APRIL 2016 – REVISED OCTOBER 2019
DS90UB914A-Q1 25-MHz to 100-MHz 10- and 12-Bit FPD-Link III Deserializer
1 Features
3 Description
•
The DS90UB914A-Q1 device offers an FPD-Link III
interface with a high-speed forward channel and a
bidirectional control channel for data transmission
over a single coaxial cable or differential pair. The
DS90UB914A-Q1 device incorporates differential
signaling on both the high-speed forward channel and
bidirectional control channel data paths. The
deserializer is targeted for connections between
imagers and video processors in an ECU (Electronic
Control Unit). This device is ideally suited for driving
video data requiring up to 12-bit pixel depth plus two
synchronization signals along with bidirectional
control channel bus.
1
•
•
•
•
•
•
•
•
•
•
•
Qualified for automotive applications AEC-Q100
– Device temperature grade 2: –40℃ to +105℃
ambient operating temperature range
– Device HBM ESD classification level ±8kV
– Device CDM ESD classification level C6
25-MHz to 100-MHz Input Pixel Clock Support
Programmable data payload:
– 10-bit Payload up to 100-MHz
– 12-bit Payload up to 75-MHz
Continuous low latency bidirectional control
interface channel with I2C support at 400-kHz
2:1 Multiplexer to choose between two input
images
Capable of receiving over 15-m coaxial or 20-m
shielded twisted-pair cables
Robust Power-Over-Coaxial (PoC) operation
Receive equalizer automatically adapts for
changes in cable loss
LOCK output reporting pin and @SPEED BIST
diagnosis feature to validate link integrity
Single power supply at 1.8-V
ISO 10605 and IEC 61000-4-2 ESD compliant
EMI/EMC mitigation with programmable spread
spectrum (SSCG) and receiver staggered outputs
2 Applications
•
•
•
Automotive
– Surround view systems (SVS)
– Rear and front view cameras
– Driver monitor cameras (DMS)
– Remote satellite RADAR sensors
Security and surveillance
Industrial machine vision
The deserializer features a multiplexer to allow
selection between two input imagers, one active at a
time. The primary video transport converts 10-bit or
12-bit data to a single high-speed serial stream, along
with a separate low latency bidirectional control
channel transport that accepts control information
from an I2C port and is independent of video blanking
period.
Using TI’s embedded clock technology allows
transparent full-duplex communication over a single
differential pair, carrying asymmetrical-bidirectional
control channel information. This single serial stream
simplifies transferring a wide data bus over PCB
traces and cable by eliminating the skew problems
between parallel data and clock paths. This
significantly saves system cost by narrowing data
paths that in turn reduce PCB layers, cable width,
and connector size and pins. In addition, the
Deserializer inputs provide adaptive equalization to
compensate for loss from the media over longer
distances. Internal DC-balanced encoding/decoding is
used to support AC-coupled interconnects.
Device Information(1)
PART NUMBER
DS90UB914A-Q1
PACKAGE
WQFN (48)
BODY SIZE (NOM)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
Parallel
Data In
10 or 12
Parallel
Data Out
10 or 12
FPD-Link III
2
Megapixel
Imager/Sensor
HSYNC,
VSYNC
2
DS90UB913AQ1
4
GPO
2
Bidirectional
Control Bus
Serializer
Bidirectional
Control Channel
DS90UB914AQ1
HSYNC,
VSYNC
4
DSP, FPGA/
µ-Processor/
ECU
GPIO
2
Deserializer
Bidirectional
Control Bus
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90UB914A-Q1
SNLS499D – APRIL 2016 – REVISED OCTOBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
9
7.1
7.2
7.3
7.4
7.5
7.6
Absolute Maximum Ratings ...................................... 9
ESD Ratings.............................................................. 9
Recommended Operating Conditions....................... 9
Thermal Information ................................................ 10
Electrical Characteristics ........................................ 10
AC Timing Specifications (SCL, SDA) - I2CCompatible ............................................................... 14
7.7 Bidirectional Control Bus DC Timing Specifications
(SCL, SDA) - I2C-Compatible ................................. 15
7.8 Deserializer Switching Characteristics.................... 15
7.9 Typical Characteristics ............................................ 17
8
Parameter Measurement Information ................ 17
9
Detailed Description ............................................ 21
8.1 Timing Diagrams and Test Circuits......................... 17
9.2
9.3
9.4
9.5
9.6
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming ..........................................................
Register Maps .........................................................
22
22
27
33
38
10 Application and Implementation........................ 49
10.1 Application Information.......................................... 49
10.2 Typical Applications .............................................. 53
11 Power Supply Recommendations ..................... 57
12 Layout................................................................... 58
12.1 Layout Guidelines ................................................. 58
12.2 Layout Example .................................................... 59
13 Device and Documentation Support ................. 61
13.1
13.2
13.3
13.4
13.5
13.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
61
61
61
61
61
61
14 Mechanical, Packaging, and Orderable
Information ........................................................... 61
9.1 Overview ................................................................. 21
4 Revision History
Changes from Revision C (November 2018) to Revision D
Page
•
Added tDLH and tDHL to Output Load and Transition Times diagram ................................................................................ 18
•
Added 953A in the list of compatible serializers................................................................................................................... 21
•
Changed text in MODE Pin Configuration figure from "Serializer" to "Deserializer" ............................................................ 29
•
Clarified bit descriptions for registers 0x1D-0x1E bits 4 and 0............................................................................................. 44
•
Added timing diagram and data table for PDB to I2C ready delay ...................................................................................... 51
Changes from Revision B (October 2016) to Revision C
Page
•
Clarified when PCLK becomes active with respect to LOCK ................................................................................................ 6
•
Added Power Over Coax supply noise to the recommended operating conditions table ..................................................... 9
•
Corrected to tDLH and tDHL for data low-to-high and high-to-low transition time ................................................................... 15
•
Moved the timing diagrams to the Parameter Measurement Information section................................................................ 17
•
Added reference to compatibility with DS90UB953-Q1/935-Q1 serializers ........................................................................ 21
•
Updated pullup and pulldown resistor to R1 and R2 in MODE pin configuration diagram ................................................... 29
•
Updated register "TYPE" column per legend ...................................................................................................................... 38
•
Added type and default value to the reserved register bits that were missing this information .......................................... 38
Changes from Revision A (June 2016) to Revision B
Page
•
Added Back Channel Line Rate specification; also added footnote for clarification between MHz and Mbps distinction. .. 11
•
Revised back channel VOD specification from 175mV to 182 mV. .................................................................................... 11
•
Removed 'ns' unit from specifications referencing period in units of T. ............................................................................... 15
•
Revise Deserializer Delay specification due to the swapped information. .......................................................................... 16
2
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SNLS499D – APRIL 2016 – REVISED OCTOBER 2019
•
Revised jitter tolerance curve to be for typical system IJT configuration with DS90UB913A linked to DS90UB914A. ...... 17
•
Added device functional mode table for external oscillator operation with example XCLKIN = 48MHz. ............................ 27
•
Fixed typo and changed "deserializer" to "serializer". .......................................................................................................... 39
•
Added register 0x05 for Forward Channel Low Frequency Gain. ....................................................................................... 40
•
Added registers 0x27, 0x47 for Forward Channel Tuning/Impedance Control. ................................................................... 47
•
Revised rise time and delay conditions to include 10% to 90% parameters instead of VIH and VIL. ................................. 50
•
Changed max rise time for VDDIO and VDD_N to be 5ms instead of 1.5ms during power-up. ............................................... 50
•
Revised power-up timing paragraph for clarity and correctness. ......................................................................................... 50
•
Changed VIL and VIH specs to 10% and 90% respectively for rising/falling edges. ........................................................... 50
Changes from Original (April 2016) to Revision A
Page
•
Split document into two separate documents for parts DS90UB913A-Q1 SNLS443 and DS90UB914A-Q1 SNLS499. ..... 1
•
Combined revision history showing changes when this document was part of the DS90UB913A-Q1 SNLS443 datasheet 1
•
Added Automotive Features ................................................................................................................................................... 1
•
Updated pin description for ROUT to include active/inactive outputs corresponding to MODE setting................................. 5
•
Added pin description to GPIO pins to leave open if unused. ............................................................................................... 6
•
Updated frequency requirements for 10-bit and 12-bit HF modes. 10-bit mode – 50 MHz to 100 MHz; 12-bit HF
mode – 37.5 MHz to 75 MHz; 12-bit LF mode (no change) – 25 MHz to 50 MHz. .............................................................. 6
•
Added pin description to RIN pins to leave open if unused. ................................................................................................. 8
•
Changed Air Discharge ESD Rating (IEC61000-4-2: RD = 330 Ω, CS = 150 pF) to minimum ±25000 V. .......................... 9
•
Added additional thermal characteristics.............................................................................................................................. 10
•
Added GPIO[3:0] typical pin capacitance ............................................................................................................................ 10
•
Changed Differential Input Voltage minimum specification. ................................................................................................. 11
•
Changed Single-Ended Input Voltage minimum specification.............................................................................................. 11
•
Added Back Channel Differential Output Voltage minimum specification. ........................................................................... 11
•
Added Back Channel Single-Ended Output Voltage minimum specification........................................................................ 11
•
Added footnote that states the following: “UI – Unit Interval is equivalent to one serialized data bit width. The UI
scales with PCLK frequency.” Also added below calculations to footnote. 12-bit LF mode 1 UI = 1 / ( PCLK_Freq. x
28 ) 12-bit HF mode 1 UI = 1 / ( PCLK_Freq. x 2/3 x 28 ) 10-bit mode 1 UI = 1 / ( PCLK_Freq. /2 x 28 ) ........................ 11
•
Updated IDDIOR for VDDIO=1.89V, CL=8pF, Worst-Case Pattern with f=50 MHz, 12-bit low freq mode to typical value of
16 mA; value is currently 21 mA. ........................................................................................................................................ 12
•
Updated IDDIOR for VDDIO=1.89V, CL=8pF, Random Pattern with f=50 MHz, 12-bit low freq mode to typical value of 10
mA; value is currently 14 mA................................................................................................................................................ 12
•
Updated IDDR for VDD_n=1.89V, CL=4pF, Random Pattern with f=100 MHz, 10-bit mode to typical value of 69 mA;
value is currently 57 mA. ..................................................................................................................................................... 12
•
Updated IDDR for VDD_n=1.89V, CL=4pF, Random Pattern with f=75 MHz, 12-bit high freq mode to typical value of 71
mA; value is currently 60 mA................................................................................................................................................ 12
•
Updated IDDR for VDD_n=1.89V, CL=4pF, Random Pattern with f=50 MHz, 12-bit low freq mode to typical value of 67
mA; value is currently 56 mA................................................................................................................................................ 12
•
Updated VOL Output Low Level row with revised IOL currents and max VOL voltages, dependent upon VDDIO voltage........ 15
•
Updated frequency ranges for MODE settings and also revised with correct maximum clock periods. Added footnote
and nominal clock period to be in terms of 'T'. ..................................................................................................................... 15
•
Changed typo on footnote to reflect 'tDPJ'. ............................................................................................................................ 16
•
Updated Figure 2 title to state ‘“Worst-Case” Test Pattern for Power Consumption’ .......................................................... 17
•
Updated Figure 3 “Deserializer Vswing Diagram” with correct notation. ............................................................................. 18
•
Changed Figure 3 to clarify difference between STP and Coax .......................................................................................... 18
•
Table 2, row 5 with “static” input LOCK output status changed to “L”. ............................................................................... 30
•
Table 5 heading updated to state “DS90UB914A-Q1 DESERIALIZER. ............................................................................. 36
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3
DS90UB914A-Q1
SNLS499D – APRIL 2016 – REVISED OCTOBER 2019
www.ti.com
•
Changed description of deserializer reg 0x00 bit[0]=0 from "set using address coming from CAD" to "set from ID[x]" ..... 38
•
Added row to register 0x01[2] for Back Channel Enable – 0: Disable 1: Enable................................................................. 38
•
Changed SSCG Units for fmod (register 0x02[3:0]) to Reflect Hz instead of KHz............................................................... 39
•
Changed parity error reset bit to be NOT self-clearing. ...................................................................................................... 39
•
Changed EQ gain values (dB) @ maximum line rate (1.4Gbps). ........................................................................................ 40
•
Changed description of deserializer reg 0x04 to have correct register setting for each equalization gain level. ................ 40
•
Added registers 0x26, 0x46 for Bidirectional Control Channel (BCC)Tuning. ..................................................................... 47
•
Added deserializer 0x4C SEL register.................................................................................................................................. 48
•
Updated EQ Register Bits 0x4E[3:0] to be Reserved. Also changed EQ gain values (dB) @ maximum line rate
(1.4Gbps).............................................................................................................................................................................. 48
•
Added reference to Power over Coax Application report ..................................................................................................... 49
•
Updated power up sequencing information and timing diagram. ........................................................................................ 49
•
Added power up sequencing information and timing diagram. ............................................................................................ 49
•
Added 914A PDB Reset timing constraints and diagram. ................................................................................................... 50
•
Removed Figure 21 and Figure 43 regarding adaptive equalizer graphs for loss compensation (Coax/STP). .................. 52
•
Renamed C1 and C2 to C22 and C23 for RIN0+ and RIN0- respectively on Typical Application Diagrams (Coax &
STP). .................................................................................................................................................................................... 54
•
Added description specifying that the voltage applied on VDDIO (1.8 V, 3.3 V) or VDD_n (1.8 V) should be at the input
pin – any board level DC drop should be compensated. .................................................................................................... 57
•
Added 914A EVM layout example image. ........................................................................................................................... 60
5 Device Comparison Table
4
PART NUMBER
FPD-III FUNCTION
PACKAGE
TRANSMISSION MEDIA
PCLK FREQUENCY
DS90UB914Q-Q1
Deserializer
WQFN RHS (48)
STP
10 to 100 MHz
DS90UB914A-Q1
Deserializer
WQFN RHS (48)
Coax or STP
25 to 100 MHz
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SNLS499D – APRIL 2016 – REVISED OCTOBER 2019
6 Pin Configuration and Functions
PDB
VDDIO1
GPIO[0]
30
29
28
GPIO[3]
VDDCML1
31
25
RIN1+
32
GPIO[1]
RIN133
GPIO[2]
IDx[1]
34
26
IDx[0]
35
27
VDDR
36
RHS Package
48-Pin WQFN
Top View
24
ROUT[0]
23
ROUT[1]
MODE
37
CMLOUTP
38
CMLOUTN
39
22
ROUT[2]
VDDCML0
40
21
ROUT[3]
RIN0+
41
20
VDDIO2
RIN0-
42
19
ROUT[4]
RES
43
18
ROUT[5]
DAP = GND
DS90UB914A-Q1
Deserializer
7
8
9
10
11
12
PCLK
VSYNC
HSYNC
ROUT[11]
ROUT[10]
ROUT[9]
VDDIO3
13
6
48
5
LOCK
OEN
PASS
ROUT[8]
BISTEN
ROUT[7]
14
4
15
47
OSS_SEL
46
3
SEL
VDDSSCG
ROUT[6]
2
VDDD
16
SCL
17
45
1
44
SDA
RES
VDDPLL
Pin Functions: DS90UB914A-Q1 Deserializer
PIN
NAME
I/O
NO.
DESCRIPTION
LVCMOS PARALLEL INTERFACE
11,12,13,14,
15,16,18,19,
21,22,23,24
Outputs,
LVCMOS
Parallel Data Outputs
For 10-bit MODE, parallel outputs ROUT[9:0] are active. ROUT[11:10] are inactive and
should not be used. Any unused outputs (including ROUT[11:10]) should be No Connect.
For 12-bit MODE (HF or LF), parallel outputs ROUT[11:0] are active. Any unused outputs
should be No Connect.
HSYNC
10
Output,
LVCMOS
Horizontal SYNC Output. Note: HS transition restrictions: 1. 12-bit Low-Frequency mode: No
HS restrictions (raw) 2. 12-bit High-Frequency mode: No HS restrictions (raw) 3. 10-bit
mode: HS restricted to no more than one transition per 10 PCLK cycles. Leave open if
unused.
VSYNC
9
Output,
LVCMOS
Vertical SYNC Output. Note: VS transition restrictions: 1. 12-bit Low-Frequency mode: No
VS restrictions (raw) 2. 12-bit High-Frequency mode: No VS restrictions (raw) 3. 10-bit mode:
VS restricted to no more than one transition per 10 PCLK cycles. Leave open if unused.
8
Output,
LVCMOS
Pixel Clock Output Pin
Strobe edge set by RRFB control register.
In the 12-bit low frequency mode and 10-bit mode, the PCLK will become active before
LOCK goes high.
In the 12-bit high frequency mode, the PCLK and LOCK become active at the same time.
ROUT[11:0]
PCLK
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Pin Functions: DS90UB914A-Q1 Deserializer (continued)
PIN
NAME
I/O
NO.
DESCRIPTION
GENERAL PURPOSE INPUT/OUTPUT (GPIO)
GPI0[1:0]
GPIO[3:2]
27,28
General-purpose input/output pins can be used to control and respond to various commands.
Digital
They may be configured to be the input signals for the corresponding GPOs on the serializer
Input/Output,
or they may be configured to be outputs to follow local register settings. Leave open if
LVCMOS
unused.
25,26
Digital
Input/Output
LVCMOS
General purpose input/output pins GPO[3:2] can be configured to be input signals for GPOs
on the Serializer. In addition they can also be configured to be outputs to follow the local
register settings. When the SerDes chipsets are working with an external oscillator, these
pins can be configured only to be outputs to follow the local register settings. Leave open if
unused.
BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE
SCL
2
Input/Output, Clock line for the bidirectional control bus communication
Open Drain SCL requires an external pullup resistor to VDDIO.
SDA
1
Input/Output, Data line for bidirectional control bus communication
Open Drain SDA requires an external pullup resistor to VDDIO.
MODE
37
Device Mode Select
Resistor to Ground and 10-kΩ pullup to 1.8 V rail. The MODE pin on the Deserializer can be
used to configure the Serializer and Deserializer to work in different input PCLK range. See
details in Table 2.
12– bit low frequency mode – (25 – 50 MHz operation):
In this mode, the Serializer and Deserializer can accept up to 12-bits DATA+2 SYNC. Input
PCLK range is from 25 MHz to 50 MHz. Note: No HS/VS restrictions.
Input, analog 12– bit high frequency mode – (37.5 – 75 MHz operation): In this mode, the Serializer and
Deserializer can accept up to 12-bits DATA + 2 SYNC. Input PCLK range is from 37.5 MHz
to 75 MHz. Note: No HS/VS restrictions.
10–bit mode– (50 – 100 MHz operation):
In this mode, the Serializer and Deserializer can accept up to 10-bits DATA + 2 SYNC. Input
PCLK frequency can range from 50 MHz to 100 MHz. Note: HS/VS restricted to no more
than one transition per 10 PCLK cycles.
Please refer to Table 2 on how to configure the MODE pin on the Deserializer.
IDx[0:1]
35,34
Device ID Address Select
Input, analog The IDx[0] and IDx[1] pins on the Deserializer are used to assign the I2C slave device
address. Resistor to Ground and 10-kΩ pullup to 1.8 V rail. See Table 6
CONTROL AND CONFIGURATION
PDB
30
Input,
LVCMOS
w/ pulldown
Power Down Mode Pin
PDB = H, Deserializer is enabled and is ON.
PDB = L, Deserializer is in power down mode. When the Deserializer is in power down
mode, programmed control register data are NOT retained and reset to default values.
LOCK Status Output Pin
LOCK = H, PLL is Locked, outputs are active.
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by OSS_SEL
control register. May be used as Link Status.
In the 12-bit low frequency mode and 10-bit mode, the PCLK will become active before
LOCK goes high.
In the 12-bit high frequency mode, the PCLK and LOCK become active at the same time.
LOCK
48
Output,
LVCMOS
BISTEN
6
Input
LVCMOS w/
pulldown
PASS
47
Output,
LVCMOS
OEN
5
Input
LVCMOS w/
pulldown
Output Enable Input
Refer to Table 3.
OSS_SEL
4
Input
LVCMOS w/
pulldown
Output Sleep State Select Pin
Refer to Table 3.
6
BIST Enable Pin
BISTEN=H, BIST Mode is enabled.
BISTEN=L, BIST Mode is disabled.
See Built-In Self Test for more information.
PASS Output Pin
PASS = H, ERROR FREE Transmission.
PASS = L, one or more errors were detected in the received payload.
See Built-In Self Test for more information. Leave Open if unused. Route to test point (pad)
recommended.
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Pin Functions: DS90UB914A-Q1 Deserializer (continued)
PIN
NAME
SEL
NO.
46
I/O
Input
LVCMOS w/
pulldown
DESCRIPTION
MUX Select Line
SEL = L, RIN0+/- input. This selects input A as the active channel on the Deserializer.
SEL = H, RIN1+/- input. This selects input B as the active channel on the Deserializer.
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Pin Functions: DS90UB914A-Q1 Deserializer (continued)
PIN
NAME
I/O
NO.
DESCRIPTION
FPD–Link III INTERFACE
RIN0+
41
Input/Output, Noninverting Differential input, bidirectional control channel. The IO must be AC-coupled with
CML
a 0.1-µF capacitor. Leave open if unused.
RIN0-
42
Inverting Differential input, bidirectional control channel. The IO must be AC-coupled with a
Input/Output, 0.1-µF capacitor. For applications using single-ended coaxial interconnect, a 0.047-µF, ACCML
coupling capacitor should be placed in series with a 50-Ω resistor before terminating to GND.
Leave open if unused.
RIN1+
32
Input/Output, Noninverting Differential input, bidirectional control channel. The IO must be AC-coupled with
CML
a 0.1-µF capacitor. Leave open if unused.
RIN1-
33
Inverting Differential input, bidirectional control channel. The IO must be AC coupled with a
Input/Output, 0.1-µF capacitor. For applications using single-ended coaxial interconnect, a 0.047-µF, ACCML
coupling capacitor should be placed in series with a 50-Ω resistor before terminating to GND.
Leave open if unused.
RES
43,44
CMLOUTP/N
38,39
POWER AND GROUND
—
Output, CML
Reserved. This pin must always be tied low.
Route to test point or leave open if unused.
(1)
29, 20, 7
Power,
Digital
LVCMOS I/O Buffer Power, The single-ended outputs and control input are powered from
VDDIO. VDDIO can be connected to a 1.8 V ±5% or 3.3 V ±10%.
VDDD
17
Power,
Digital
Digital Core Power, 1.8 V ±5%.
VDDSSCG
3
Power,
Analog
SSCG PLL Power, 1.8 V ±5%.
VDDR
36
Power,
Analog
Rx Analog Power, 1.8 V ±5%.
40,31
Power,
Analog
CML and Bidirectional control channel Drive Power, 1.8 V ±5%.
45
Power,
Analog
PLL Power, 1.8 V ±5%.
DAP
Ground, DAP
VDDIO1/2/3
VDDCML0/1
VDDPLL
VSS
(1)
8
DAP must be grounded. DAP is the large metal contact at the bottom side, located at the
center of the WQFN package. Connected to the ground plane (GND) with at least 16 vias.
See Power-Up Requirements and PDB Pin.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply voltage – VDD_n (1.8 V)
–0.3
2.5
V
Supply voltage – VDDIO
–0.3
4
V
LVCMOS input voltage
–0.3
VDDIO + 0.3
V
CML receiver I/O voltage (VDD)
–0.3
VDD + 0.3
V
150
°C
150
°C
Junction temperature
Storage temperature, Tstg
(1)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
Electrostatic
discharge
Human body model (HBM), per AEC Q100-002 (1)
±8000
Charged device model (CDM), per AEC Q100-011
±1000
(IEC 61000-4-2)
RD = 330 Ω, Cs = 150pF
(ISO10605)
RD = 330 Ω, Cs = 150/330 pF
RD = 2 KΩ, Cs = 150/330 pF
(1)
Air Discharge
(DOUT+, DOUT–, RIN+, RIN–)
±25000
Contact Discharge
(DOUT+, DOUT–, RIN+, RIN–)
±8000
Air Discharge
(DOUT+, DOUT–, RIN+, RIN–)
±15000
Contact Discharge
(DOUT+, DOUT–, RIN+, RIN–)
±7000
UNIT
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Supply Voltage (VDD_n)
1.71
1.8
1.89
V
LVCMOS Supply Voltage (VDDIO= 1.8 V) OR
1.71
1.8
1.89
3
3.3
3.6
LVCMOS Supply Voltage (VDDIO= 3.3 V)
Supply Noise (1)
Power-Over-Coax Supply
Noise
VDD_n (1.8 V)
25
VDDIO (1.8 V)
25
VDDIO (3.3 V)
50
mVp-p
ƒ = 30 Hz - 1 KHz, trise > 100 µs
Measured differentially between DOUT+ and DOUT–
(coax mode only)
10
mVp-p
ƒ = 1 KHz - 50 MHz
Measured differentially between DOUT+ and DOUT(coax mode only)
10
mVp-p
Operating Free Air Temperature (TA)
–40
PCLK Clock Frequency
(1)
V
25
25
105
°C
100
MHz
Supply noise testing was done with minimum capacitors (as shown on Pin Configuration and Functions and Figure 34 on the PCB. A
sinusoidal signal is AC coupled to the VDD_n (1.8 V) supply with amplitude = 25 mVp-p measured at the device VDD_n pins. Bit error rate
testing of input to the Ser and output of the Des with 10-meter cable shows no error when the noise frequency on the Ser is less than 1
MHz. The Des on the other hand shows no error when the noise frequency is less than 750 kHz.
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7.4 Thermal Information
DS90UB914A-Q1
THERMAL METRIC (1)
RHS (WQFN)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
29.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
10.9
°C/W
RθJB
Junction-to-board thermal resistance
6.7
°C/W
ψJT
Junction-to-top characterization parameter
0.1
°C/W
ψJB
Junction-to-board characterization parameter
6.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVCMOS DC SPECIFICATIONS 3.3-V I/O (DES OUTPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input Voltage
VIN = 3 V to 3.6 V
2
VIN
VIL
Low Level Input Voltage
VIN = 3 V to 3.6 V
GND
0.8
V
IIN
Input Current
VIN = 0 V or 3.6 V, VIN = 3 V to 3.6 V
20
µA
VOH
High Level Output Voltage VDDIO = 3 V to 3.6 V, IOH = −4 mA
2.4
VDDIO
V
VOL
Low Level Output Voltage
GND
0.4
V
VDDIO = 3 V to 3.6 V, IOL = 4 mA
Output Short Circuit
Current
VOUT = 0 V
IOZ
TRI-STATE Output
Current
PDB = 0 V,
VOUT = 0 V or VDD
CGPIO
Pin Capacitance
GPIO [3:0]
IOS
–20
±1
Deserializer
GPO Outputs
–15
LVCMOS Outputs
–35
LVCMOS Outputs,
GPO Outputs
–20
V
mA
20
1.5
µA
pF
LVCMOS DC SPECIFICATIONS 1.8-V I/O (DES OUTPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input Voltage
VIN = 1.71 V to 1.89 V
0.65 VIN
VIN
VIL
Low Level Input Voltage
VIN = 1.71 V to 1.89 V
GND
0.35 VIN
IIN
Input Current
VIN = 0 V or 1.89 V, VIN = 1.71 V to 1.89 V
VOH
High Level Output Voltage VDDIO = 1.71 V to 1.89 V, IOH = −4 mA
VOL
Low Level Output Voltage
VDDIO = 1.71 V to 1.89 V IOL = 4 mA
Output Short Circuit
Current
VOUT = 0 V
IOZ
TRI-STATE Output
Current
PDB = 0 V,
VOUT = 0 V or VDD
CGPIO
Pin Capacitance
GPIO [3:0]
IOS
(1)
(2)
(3)
10
–20
±1
20
µA
VDDIO –
0.45
VDDIO
V
GND
0.45
V
Deserializer
GPO Outputs
–11
LVCMOS Outputs
–17
LVCMOS Outputs,
GPO Outputs
V
-20
mA
20
1.5
µA
pF
The Electrical Characteristics tables list verified specifications under the listed Recommended Operating Conditions except as otherwise
modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not
verified.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA = 25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not verified.
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
–20
1
20
UNIT
CML RECEIVER DC SPECIFICATIONS (RIN0+, RIN0–, RIN1+, RIN1– )
IIN
Input Current
VIN = VDD or 0 V, VDD = 1.89 V,
Differential Internal
Termination Resistance
Differential across RIN+ and RIN–
80
100
120
Single-ended
Termination Resistance
RIN+ or RIN–
40
50
60
VID
Differential Input Voltage
Back Channel Disabled, (Figure 4)
210
mV
VIN
Single-Ended Input
Voltage
Back Channel Disabled, (Figure 4)
105
mV
ƒBC
Back Channel
Frequency (4)
3.3
4.2
MHz
VOD-BC
Back Channel Differential
Output Voltage
350
540
mV
VOUT-BC
Back Channel SingleEnded Output Voltage
182
270
mV
RT
µA
Ω
CML MONITOR OUTPUT DRIVER SPECIFICATIONS (CMLOUTP, CMLOUTN)
Ew
Differential Output
Eye Opening (5)
EH
Differential Output
Eye Height
(4)
(5)
RL = 100 Ω
Jitter Frequency > f/15 (Figure 9)
0.45
UI
200
mV
The back channel frequency (MHz) listed is the frequency of the internal clock used to generate the encoded back channel data stream.
The data rate (Mbps) of the encoded back channel stream is the back channel frequency divided by 2.
UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
10-bit mode: 1 UI = 1 / ( PCLK_Freq. /2 x 28 )
12-bit HF mode: 1 UI = 1 / ( PCLK_Freq. x 2/3 x 28 )
12-bit LF mode: 1 UI = 1 / ( PCLK_Freq. x 28 )
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
f = 100 MHz,
10–bit mode
22
42
f = 75 MHz, 12–bit
high freq mode
19
39
f = 50 MHz, 12–bit
low freq mode
16
32
f = 100 MHz,
10–bit mode
15
f = 75 MHz, 12–bit
high freq mode
12
f = 50 MHz, 12–bit
low freq mode
10
f = 100 MHz,
10–bit mode
42
55
f = 75 MHz, 12–bit
high freq mode
37
50
f = 50 MHz, 12–bit
low freq mode
25
38
f = 100 MHz,
10–bit mode
35
f = 75 MHz, 12–bit
high freq mode
30
f = 50 MHz, 12–bit
low freq mode
18
f = 100 MHz,
10–bit mode
15
f = 75 MHz, 12–bit
high freq mode
11
f = 50 MHz, 12–bit
low freq mode
16
UNIT
DESERIALIZER SUPPLY CURRENT
VDDIO=1.89 V
CL=8 pF
Worst Case Pattern
VDDIO=1.89 V
CL=8 pF
Random Pattern
VDDIO=3.6 V
CL=8 pF
Worst Case Pattern
VDDIO= 3.6 V
CL= 8 pF
Random Pattern
IDDIOR
Deserializer (Rx)
Total Supply Current
(includes load current)
VDDIO= 1.89 V
CL= 4 pF
Worst Case Pattern
VDDIO= 1.89 V
CL= 4 pF
Random Pattern
VDDIO= 3.6 V
CL= 4 pF
Worst Case Pattern
VDDIO= 3.6 V
CL= 4 pF
Random Pattern
12
f = 100 MHz,
10–bit mode
8
f = 75 MHz, 12–bit
high freq mode
4
f = 50 MHz, 12–bit
low freq mode
9
f = 100 MHz,
10–bit mode
36
f = 75 MHz, 12–bit
high freq mode
29
f = 50 MHz, 12–bit
low freq mode
20
f = 100 MHz, 10–bit
mode
29
f = 75 MHz, 12–bit
high freq mode
22
f = 50 MHz, 12–bit
low freq mode
13
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mA
mA
mA
mA
mA
mA
mA
mA
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
PARAMETER
TEST CONDITIONS
TYP
MAX
f = 100 MHz,
10–bit mode
64
110
f = 75 MHz,
12–bit high freq
mode
67
114
f = 50 MHz,
12–bit low freq mode
63
96
f = 100 MHz,
10–bit mode
69
f = 75 MHz,
12–bit high freq
mode
71
f = 50 MHz,
12–bit low freq mode
67
PDB = 0 V, All other
LVCMOS Inputs=0 V
VDDIO = 1.89 V
Default Registers
42
900
PDB = 0 V, All other
LVCMOS Inputs = 0 V
VDDIO=3.6 V
Default Registers
42
900
VDD_n = 1.89 V
CL= 4 pF
Worst Case Pattern
IDDR
Deserializer (Rx) VDD_n
Supply Current (includes
load current)
VDD_n= 1.89 V
CL= 4 pF
Random Pattern
IDDRZ
IDDIORZ
Deserializer (Rx) Supply
Current Power Down
Deserializer (Rx) VDDIO
Supply Current Power
Down
PDB = 0 V, All other
LVCMOS Inputs = 0 V
VDDIO = 1.89 V
VDDIO = 3.6 V
MIN
mA
µA
8
40
360
800
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µA
13
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7.6 AC Timing Specifications (SCL, SDA) - I2C-Compatible
Over recommended supply and temperature ranges unless otherwise specified. (See Figure 2)
MIN
NOM
MAX
UNIT
Standard Mode
100
kHz
Fast Mode
400
kHz
RECOMMENDED INPUT TIMING REQUIREMENTS
fSCL
tLOW
SCL Clock Frequency
SCL Low Period
Standard Mode
4.7
µs
Fast Mode
1.3
µs
4
µs
0.6
µs
Standard Mode
tHIGH
SCL High Period
tHD:STA
Hold time for a start or a repeated start
condition
Standard Mode
4
µs
Fast Mode
0.6
µs
Set Up time for a start or a repeated
start condition
Standard Mode
4.7
µs
Fast Mode
0.6
tSU:STA
tHD:DAT
tSU:DAT
Data Hold Time
Data Set Up Time
tSU:STO
Set Up Time for STOP Condition
tBUF
Bus Free time between Stop and Start
tr
tf
14
SCL & SDA Rise Time
SCL & SDA Fall Time
Fast Mode
µs
Standard Mode
0
3.45
µs
Fast Mode
0
900
ns
Standard Mode
250
Fast Mode
100
ns
4
µs
Fast Mode
0.6
µs
Standard Mode
4.7
µs
Fast Mode
1.3
Standard Mode
Standard Mode
ns
µs
1000
ns
Fast Mode
300
ns
Standard Mode
300
ns
Fast Mode
300
ns
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Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible
7.7
Over recommended supply and temperature ranges unless otherwise specified (1)
MIN
NOM
MAX
UNIT
0.7 ×
VDDIO
VDDIO
V
GND
0.3 ×
VDDIO
V
RECOMMENDED INPUT TIMING REQUIREMENTS
VIH
Input High Level
VIL
Input Low Level
VHY
Input Hysteresis
VOL
Output Low Level (2)
IIN
Input Current
tR
SDA Rise Time-READ
tF
SDA Fall Time-READ
SDA and SCL
SDA and SCL
>50
0
0.36
SDA, VDDIO = 3.3 V, IOL= 1.6 mA
0
0.4
−10
SDA or SCL, VIN= VDDIO OR GND
SDA, RPU = 10 kΩ, Cb ≤ 400 pF
(Figure 2)
tSP
CIN
(1)
(2)
mV
SDA, VDDIO = 1.8 V, IOL= 0.9 mA
SDA or SCL
V
10
µA
430
ns
20
ns
50
ns
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