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DS90UB913Q-Q1, DS90UB914Q-Q1
SNLS420D – JULY 2012 – REVISED JULY 2015
DS90UB91xQ-Q1 10- to 100-MHz, 10- and 12-Bit DC-Balanced FPD-Link III Serializer and
Deserializer With Bidirectional Control Channel
1 Features
2 Applications
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
10-MHz to 100-MHz Input Pixel Clock Support
Single Differential Pair Interconnect
Programmable Data Payload:
– 10-bit Payload up to 100 MHz
– 12-bit Payload up to 75 MHz
Continuous Low Latency Bidirectional Control
Interface Channel With I2C Support at 400 kHz
2:1 Multiplexer to Choose Between Two Input
Imagers
Embedded Clock With DC-Balanced Coding to
Support AC-Coupled Interconnects
Capable of Driving up to 25 Meters Shielded
Twisted-Pair
Receive Equalizer Automatically Adapts for
Changes in Cable Loss
Four Dedicated General-Purpose Input/Output
Pins (GPIO) Available on Both Serializer and
Deserializer
LOCK Output Reporting Pin and AT-SPEED BIST
Diagnosis Feature to Validate Link Integrity
1.8-V, 2.8-V or 3.3-V Compatible Parallel Inputs
on Serializer
Single Power Supply at 1.8 V
ISO 10605 and IEC 61000-4-2 ESD Compliant
Automotive-Grade Product: AEC-Q100 Grade 2
Qualified
Temperature Range −40°C to +105°C
Small Serializer Footprint (5 mm × 5 mm)
EMI/EMC Mitigation on Deserializer
– Programmable Spread Spectrum (SSCG)
Outputs
– Receiver Staggered Outputs
•
Front- or Rear-View Camera for Collision
Mitigation
Surround View for Parking Assistance
3 Description
The DS90UB91xQ-Q1 chipset offers an FPD-Link III
interface with a high-speed forward channel and a
bidirectional control channel for data transmission
over a single differential pair. The DS90UB91xQ-Q1
chipsets incorporate differential signaling on both the
high-speed forward channel and bidirectional control
channel data paths. The serializer and deserializer
pair is targeted for connections between imagers and
video processors in an electronic control unit (ECU).
This chipset is ideally suited for driving video data
that requires up to 12-bit pixel depth plus two
synchronization signals along with bidirectional
control channel bus.
There is a multiplexer at the deserializer to choose
between two input imagers. The deserializer can
have only one active input imager. The primary video
transport converts 10- and 12-bit data over a single
high-speed serial stream, along with a separate low
latency bidirectional control channel transport that
accepts control information from an I2C port and is
independent of video blanking period.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS90UB913Q-Q1
WQFN (32)
5.00 mm × 5.00 mm
DS90UB914Q-Q1
WQFN (48)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit
Parallel
Data In
10 or 12
Parallel
Data Out
10 or 12
FPD-Link III
2
Megapixel
Imager/Sensor
HSYNC,
VSYNC
2
DS90UB913Q
Bidirectional
Control Channel
4
GPO
2
Bidirectional
Control Bus
DS90UB914Q
Serializer
HSYNC,
VSYNC
4
DSP, FPGA/
µ-Processor/
ECU
GPIO
2
Deserializer
Bidirectional
Control Bus
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90UB913Q-Q1, DS90UB914Q-Q1
SNLS420D – JULY 2012 – REVISED JULY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description continued ...........................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
9
8.1
8.2
8.3
8.4
8.5
8.6
Absolute Maximum Ratings ...................................... 9
ESD Ratings.............................................................. 9
Recommended Operating Conditions....................... 9
Thermal Information ................................................ 10
Electrical Characteristics ........................................ 10
Timing Requirements: Recommended for Serializer
PCLK ....................................................................... 14
8.7 AC Timing Specifications (SCL, SDA) - I2C
Compliant ................................................................. 15
8.8 Bidirectional Control Bus DC Timing Specifications
(SCL, SDA) - I2C Compliant..................................... 15
8.9 Switching Characteristics: Serializer ....................... 16
8.10 Switching Characteristics: Deserializer................. 17
8.11 Typical Characteristics .......................................... 19
9
Parameter Measurement Information ................ 20
9.1 AC Timing Diagrams and Test Circuits................... 20
10 Detailed Description ........................................... 25
10.1
10.2
10.3
10.4
10.5
Overview ...............................................................
Functional Block Diagram .....................................
Feature Description...............................................
Device Functional Modes......................................
Register Maps .......................................................
25
25
26
33
41
11 Application and Implementation........................ 56
11.1 Applications Information........................................ 56
11.2 Typical Application ................................................ 56
12 Power Supply Recommendations ..................... 60
13 Layout................................................................... 60
13.1 Layout Guidelines ................................................. 60
13.2 Layout Example .................................................... 61
14 Device and Documentation Support ................. 63
14.1
14.2
14.3
14.4
14.5
14.6
Documentation Support .......................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
63
63
63
63
63
63
15 Mechanical, Packaging, and Orderable
Information ........................................................... 63
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (January 2014) to Revision D
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Updated datasheet to new TI layout....................................................................................................................................... 1
•
Added text and graphic to Power Up Requirements ........................................................................................................... 39
Changes from Revision B (April 2013) to Revision C
Page
•
Changed "PCLK from imager mode" value in DS90UB913Q Serializer MODE Resistor Value table from 0 kΩ to 100
kΩ ......................................................................................................................................................................................... 35
•
Changed Falling to Rising in RRFB...................................................................................................................................... 47
•
Changed Rising to Falling in RRFB...................................................................................................................................... 47
Changes from Revision A (April 2013) to Revision B
•
2
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 61
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Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1
DS90UB913Q-Q1, DS90UB914Q-Q1
www.ti.com
SNLS420D – JULY 2012 – REVISED JULY 2015
5 Description continued
Using TI’s embedded-clock technology allows transparent full-duplex communication over a single differential
pair, carrying asymmetrical bidirectional control channel information in both directions. This single serial stream
simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between
parallel data and clock paths. This significantly saves system cost by narrowing paths, which reduces PCB
layers, cable width, connector size and pins. In addition, the deserializer inputs provide adaptive equalization to
compensate for loss from the media over longer distances. Internal DC-balanced encoding and decoding is used
to support AC-coupled interconnects. The Serializer is offered in a 32-pin WQFN package and the deserializer is
offered in a 48-pin WQFN package.
6 Device Comparison Table
PART NUMBER
FPD-III FUNCTION
PACKAGE
TRANSMISSION MEDIA
PCLK FREQUENCY
DS90UB913Q-Q1
Serializer
32-Pin RTV (WQFN)
STP
10 to 100 MHz
DS90UB913A-Q1
Serializer
32-Pin RTV (WQFN)
Coax or STP
25 to 100 MHz
DS90UB914Q-Q1
Deserializer
48-Pin RHS (WQFN)
STP
10 to 100 MHz
DS90UB914A-Q1
Deserializer
48-Pin RHS (WQFN)
Coax or STP
25 to 100 MHz
Copyright © 2012–2015, Texas Instruments Incorporated
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3
DS90UB913Q-Q1, DS90UB914Q-Q1
SNLS420D – JULY 2012 – REVISED JULY 2015
www.ti.com
7 Pin Configuration and Functions
DIN[1]
21
20
16
GPO[1]
DIN[6]
26
15
GPO[0]
DIN[7]
27
14
VDDCML
VDDD
28
13
DOUT+
DIN[8]
29
12
DOUT-
DIN[9]
11
VDDT
10
VDDPLL
9
17
30
18
31
VDDIO
19
GPO[2]/
CLKOUT
DIN[2]
22
GPO[3]/
CLKIN
DIN[3]
23
DIN[0]
DIN[4]
24
25
DIN[5]
RTV Package
32-Pin WQFN
Top View
PDB
DS90UB913Q
Serializer
2
3
4
5
6
7
PCLK
SCL
SDA
ID[x]
RES
8
MODE
1
VSYNC
DIN[11]
HSYNC
32
DIN[10]
DAP = GND
DS90UB913Q-Q1 Serializer Pin Functions
PIN
NAME
I/O
NO.
DESCRIPTION
LVCMOS PARALLEL INTERFACE
19, 20, 21,
22, 23, 24,
26, 27, 29,
30, 31, 32
Inputs,
LVCMOS
with pulldown
Parallel data inputs
HSYNC
1
Inputs,
LVCMOS
with pulldown
Horizontal SYNC input
PCLK
3
Input, LVCMOS
with pulldown
VSYNC
2
Inputs,
LVCMOS
with pulldown
DIN[0:11]
4
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Pixel clock input pin
Strobe edge set by TRFB control register.
Vertical SYNC input
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1
DS90UB913Q-Q1, DS90UB914Q-Q1
www.ti.com
SNLS420D – JULY 2012 – REVISED JULY 2015
DS90UB913Q-Q1 Serializer Pin Functions (continued)
PIN
NAME
I/O
DESCRIPTION
Output,
LVCMOS
General-purpose output pins can be configured as outputs; used to control and respond
to various commands. GPO[0:1] can be configured to be the outputs for input signals
coming from GPIO[0:1] pins on the deserializer or can be configured to be outputs of
the local register on the serializer.
Output,
LVCMOS
GPO2 pin can be configured to be the output for input signal coming from the GPIO2
pin on the deserializer or can be configured to be the output of the local register on the
serializer. It can also be configured to be the output clock pin when the DS90UB913QQ1 device is used in the External Oscillator mode. See Applications Information for a
detailed description of the DS90UB91xQ-Q1 chipsets working with the external
oscillator.
Input/Output,
LVCMOS
GPO3 can be configured to be the output for input signals coming from the GPIO3 pin
on the deserializer or can be configured to be the output of the local register setting on
the serializer. It can also be configured to be the input clock pin when the
DS90UB913Q-Q1 serializer is working with an external oscillator. See Applications
Information section for a detailed description of the DS90UB91xQ-Q1 chipsets working
with an external oscillator.
NO.
GENERAL-PURPOSE OUTPUT (GPO)
GPO[1:0]
GPO[2]/
CLKOUT
GPO[3]/
CLKIN
16, 15
17
18
BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE
SCL
4
Input/Output,
Open-Drain
Clock line for the bidirectional control bus communication
SCL requires an external pullup resistor to VDDIO.
SDA
5
Input/Output,
Open-Drain
Data line for the bidirectional control bus communication
SDA requires an external pullup resistor to VDDIO.
MODE
8
Input, LVCMOS
with pulldown
ID[x]
6
Input, analog
Device mode select
Resistor to Ground and 10-kΩ pullup to 1.8-V rail. MODE pin on the serializer can be
used to select whether the system is running off the PCLK from the imager or an
external oscillator. See details in Table 3.
Device ID address select
The ID[x] pin on the serializer is used to assign the I2C device address. Resistor to
Ground and 10-kΩ pullup to 1.8-V rail. See Table 1.
CONTROL AND CONFIGURATION
PDB
9
Input, LVCMOS
with pulldown
RES
7
Input, LVCMOS
with pulldown
Power down Mode Input Pin
PDB = H, serializer is enabled and is ON.
PDB = L, Serailizer is in power-down mode. When the serializer is in power-down, the
PLL is shutdown, and IDD is minimized. Programmed control register data are NOT
retained and reset to default values
Reserved
This pin MUST be tied LOW.
FPD-Link III INTERFACE
DOUT+
13
Input/Output,
CML
Noninverting differential output, bidirectional control channel input. The interconnect
must be AC-coupled with a 100-nF capacitor.
DOUT–
12
Input/Output,
CML
Inverting differential output, bidirectional control channel input. The interconnect must be
AC-coupled with a 100-nF capacitor.
POWER AND GROUND
VDDPLL
10
Power, Analog
PLL Power, 1.8 V ±5%
VDDT
11
Power, Analog
Tx Analog Power, 1.8 V ±5%
VDDCML
14
Power, Analog
CML and bidirectional channel driver power, 1.8 V ±5%
VDDD
28
Power, Digital
Digital power, 1.8 V ±5%
VDDIO
25
Power, Digital
Power for I/O stage. The single-ended inputs and SDA, SCL are powered from VDDIO.
VDDIO can be connected to a 1.8 V ±5% or 2.8 V ±10% or 3.3 V ±10%
DAP
Ground, DAP
DAP must be grounded. DAP is the large metal contact at the bottom side, located at
the center of the WQFN package. Connected to the ground plane (GND) with at least 9
vias.
VSS
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SNLS420D – JULY 2012 – REVISED JULY 2015
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MODE
37
CMLOUTP
38
VDDR
IDx[0]
IDx[1]
RIN1-
RIN1+
VDDCML1
PDB
VDDIO1
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
36
35
34
33
32
31
30
29
28
27
26
25
RHS Package
48-Pin WQFN
Top View
24
DAP = GND
ROUT[0]
23
ROUT[1]
39
22
ROUT[2]
40
21
ROUT[3]
RIN0+
41
20
VDDIO2
RIN0-
42
19
ROUT[4]
18
ROUT[5]
CMLOUTN
VDDCML0
DS90UB914Q
Deserializer
RES
43
RES
44
17
VDDD
VDDPLL
45
16
ROUT[6]
12
ROUT[10]
9
VSYNC
11
8
PCLK
10
7
VDDIO3
HSYNC
6
ROUT[11]
5
OEN
BISTEN
ROUT[9]
4
13
OSS_SEL
48
3
LOCK
VDDSSCG
ROUT[8]
2
ROUT[7]
14
SCL
15
47
1
46
SDA
SEL
PASS
DS90UB914Q-Q1 Deserializer Pin Functions
PIN
NAME
I/O
NO.
DESCRIPTION
LVCMOS PARALLEL INTERFACE
11, 12, 13,
14, 15, 16,
18, 19, 21,
22, 23, 24
Outputs,
LVCMOS
Parallel data outputs
HSYNC
10
Output,
LVCMOS
Horizontal SYNC output
PCLK
8
Output,
LVCMOS
Pixel clock output pin
Strobe edge set by RRFB control register
VSYNC
9
Output,
LVCMOS
Vertical SYNC output
ROUT[11:0]
GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
GPIO[1:0]
GPIO[3:2]
6
27, 28
Digital
Input/Output,
LVCMOS
General-purpose input/output pins can be used to control and respond to various
commands. They may be configured to be the input signals for the corresponding
GPOs on the serializer or they may be configured to be outputs to follow local
register settings.
25, 26
Digital
Input/Output
LVCMOS
General-purpose input/output pins GPO[2:3] can be configured to be input signals
for GPOs on the serializer. In addition they can also be configured to be outputs
to follow the local register settings. When the SerDes chipsets are working with
an external oscillator, these pins can be configured only to be outputs to follow
the local register settings.
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SNLS420D – JULY 2012 – REVISED JULY 2015
DS90UB914Q-Q1 Deserializer Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE
SCL
2
Input/Output,
Open-Drain
Clock line for the bidirectional control bus communication
SCL requires an external pullup resistor to VDDIO.
SDA
1
Input/Output,
Open-Drain
Data line for bidirectional control bus communication
SDA requires an external pullup resistor to VDDIO.
MODE
IDx[0:1]
37
35, 34
Device mode select pin
Resistor-to-Ground and 10-kΩ pullup to 1.8-V rail. The MODE pin on the
deserializer can be used to configure the serializer and deserializer to work in
different input PCLK range. See details in Table 8.
12-bit low-frequency mode (10- to 50-MHz operation):
In this mode, the serializer and deserializer can accept up to 12 bits DATA+2
SYNC. Input PCLK range is from 10 MHz to 50 MHz.
Input, LVCMOS
12-bit high-frequency mode (15- to 75-MHz operation): In this mode, the
with pullup
serializer and deserializer can accept up to 12 bits DATA + 2 SYNC. Input PCLK
range is from 15 MHz to 75 MHz.
10-bit mode (20- to 100-MHz operation):
In this mode, the serializer and deserializer can accept up to 10 bits DATA + 2
SYNC. Input PCLK frequency can range from 20 MHz to 100 MHz.
Refer to Table 4 in the Applications Information section on how to configure the
MODE pin on the deserializer.
Input, analog
The IDx[0] and IDx[1] pins on the deserializer are used to assign the I2C device
address. Resistor-to-Ground and 10-kΩ pullup to 1.8-V rail. See Table 2
Input pin to select the slave device address.
Input is connect to external resistor divider to set programmable Device ID
address.
CONTROL AND CONFIGURATION
Power-down mode input pin
PDB = H, deserializer is enabled and is ON.
Input, LVCMOS
PDB = L, deserializer is in sleep (power-down mode). When the deserializer is in
with pulldown
sleep, programmed control register data are NOT retained and reset to default
values.
PDB
30
LOCK
48
Output,
LVCMOS
BISTEN
6
Input
LVCMOS with
pulldown
PASS
47
Output,
LVCOMS
OEN
5
Input
LVCMOS with
pulldown
Output enable input
Refer to Table 5
OSS_SEL
4
Input
LVCMOS with
pulldown
Output sleep state select pin
Refer to Table 5
46
Input
LVCMOS with
pulldown
MUX select line
SEL = L, RIN0± input. This selects input A as the active channel on the
deserializer.
SEL = H, RIN1± input. This selects input B as the active channel on the
deserializer.
SEL
Copyright © 2012–2015, Texas Instruments Incorporated
LOCK status output pin
LOCK = H, PLL is Locked, outputs are active
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by
OSS_SEL control register. May be used as link status.
BIST enable pin
BISTEN=H, BIST mode enabled
BISTEN=L, BIST mode is disabled
PASS output pin for BIST mode.
PASS = H, ERROR FREE transmission
PASS = L, one or more errors were detected in the received payload.
See Built-In Self Test section for more information. Leave open if unused. Route
to test point (pad) recommended.
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SNLS420D – JULY 2012 – REVISED JULY 2015
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DS90UB914Q-Q1 Deserializer Pin Functions (continued)
PIN
NAME
I/O
NO.
DESCRIPTION
FPD-LINK III INTERFACE
RIN0+
41
Input/Output,
CML
Noninverting differential input, bidirectional control channel. The IO must be AC
coupled with a 100-nF capacitor
RIN0-
42
Input/Output,
CML
Inverting differential input, bidirectional control channel. The IO must be AC
coupled with a 100-nF capacitor
RIN1+
32
Input/Output,
CML
Noninverting differential input, bidirectional control channel. The IO must be AC
coupled with a 100-nF capacitor
RIN1-
33
Input/Output,
CML
Inverting differential input, bidirectional control channel. The IO must be AC
coupled with a 100-nF capacitor
RES
43, 44
—
Reserved; This pin must always be tied low.
CMLOUTP/N
38, 39
—
Route to test point or leave open if unused
POWER AND GROUND
VDDIO1/2/3
29, 20, 7
Power, Digital
LVCMOS I/O buffer power, The single-ended outputs and control input are
powered from VDDIO. VDDIO can be connected to a 1.8 V ±5% or 3.3 V ±10%
VDDD
17
Power, Digital
Digital core power, 1.8 V ±5%
VDDSSCG
3
Power, Analog
SSCG PLL power, 1.8 V ±5%
VDDR
36
Power, Analog
RX analog power, 1.8 V ±5%
40, 31
Power, Analog
CML and bidirectional control channel drive power, 1.8 V±5%
45
Power, Analog
PLL Power, 1.8 V ±5%
DAP
Ground, DAP
DAP must be grounded. DAP is the large metal contact at the bottom side,
located at the center of the WQFN package. Connected to the ground plane
(GND) with at least 16 vias.
VDDCML0/1
VDDPLL
VSS
8
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SNLS420D – JULY 2012 – REVISED JULY 2015
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2) (3)
MIN
MAX
UNIT
Supply voltage – VDDn (1.8 V)
−0.3
2.5
V
Supply voltage – VDDIO
−0.3
4.0
V
LVCMOS input voltage
−0.3
VDDIO + 0.3
V
CML driver I/O voltage (VDD)
−0.3
VDD + 0.3
V
CML receiver I/O voltage (VDD)
−0.3
VDD + 0.3
V
150
°C
1/θJA above
+25°
°C/W
Junction temperature
Maximum package power dissipation capacity package
Air discharge (DOUT+, DOUT–, RIN+, RIN–)
−25
25
kV
Contact discharge (DOUT+, DOUT–, RIN+, RIN–)
−7
7
kV
Storage temperature Tstg
−65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
For soldering specifications: see product folder at www.ti.com and SNOA549.
8.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002 (1)
±8000
Charged-device model (CDM), per AEC Q100-011
±1000
Machine model (MM)
V(ESD)
Electrostatic
discharge
IEC 61000-4-2 (2)
ISO10605 (3) (4)
(1)
(2)
(3)
(4)
UNIT
±250
≥±25 000
Air Discharge (DOUT+, DOUT-, RIN+, RIN-)
V
≥±7000
Contact Discharge (DOUT+, DOUT-, RIN+, RIN-)
≥±15 000
Air Discharge
≥±8000
Contact Discharge
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
RD = 330 Ω, CS = 150 pF
RD = 330 Ω, CS = 150 / 330 pF
RD = 2 KΩ, CS = 150 / 330 pF
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Supply voltage (VDDn)
1.71
1.8
1.89
V
LVCMOS supply voltage (VDDIO) OR
1.71
1.8
1.89
LVCMOS supply voltage (VDDIO) OR
3.0
3.3
3.6
2.52
2.8
3.08
LVCMOS supply voltage (VDDIO) only serializer
Supply noise (1)
VDDn (1.8 V)
25
VDDIO (1.8 V)
25
VDDIO (3.3 V)
Operating free-air temperature (TA)
(1)
mVp-p
50
–40
PCLK clock frequency
V
25
10
105
°C
100
MHz
Supply noise testing was done with minimum capacitors (as shown on Figure 49 and Figure 48) on the PCB. A sinusoidal signal is AC
coupled to the VDDn (1.8-V) supply with amplitude = 25 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the
serializer and output of the deserializer with 10 meter cable shows no error when the noise frequency on the serializer is less than
1 MHz. The deserializer on the other hand shows no error when the noise frequency is less than 750 kHz.
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8.4 Thermal Information
THERMAL METRIC (1)
DS90UB913Q-Q1
DS90UB914Q-Q1
RTV (WQFN)
RHS (WQFN)
32 PINS
48 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
38.4
26.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
6.9
4.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
8.5 Electrical Characteristics
over recommended operating supply and temperature ranges unless otherwise specified. (1)
PARAMETER
TEST CONDITIONS
MIN
(2) (3)
TYP
MAX
UNIT
LVCMOS DC SPECIFICATIONS 3.3V I/O (SERIALIZER INPUTS, DESERIALIZER OUTPUTS, GPI, GPO, CONTROL INPUTS AND
OUTPUTS)
VIH
High level input
voltage
VIN = 3 V to 3.6 V
2
VIN
V
VIL
Low level input
voltage
VIN = 3 V to 3.6 V
GND
0.8
V
IIN
Input current
VIN = 0 V or 3.6 V, VIN = 3 V to 3.6 V
20
µA
VOH
High level output
voltage
VDDIO = 3 V to 3.6 V, IOH = −4 mA
2.4
VDDIO
V
VOL
Low level output
voltage
VDDIO = 3 V to 3.6 V, IOL = +4 mA
GND
0.4
V
IOS
Output short circuit
current
VOUT = 0 V
TRI-STATE output
current
PDB = 0 V,
VOUT = 0 V or VDD
IOZ
−20
±1
Serializer
GPO outputs
–15
Deserializer LVCMOS
outputs
–35
LVCMOS outputs
mA
–20
20
µA
LVCMOS DC SPECIFICATIONS 1.8V I/O (SERIALIZER INPUTS, DESERIALIZER OUTPUTS, GPI, GPO, CONTROL INPUTS AND
OUTPUTS)
VIH
High level input
voltage
VIN = 1.71 V to 1.89 V
0.65 VIN
VIN
VIL
Low level input
voltage
VIN = 1.71 V to 1.89 V
GND
0.35 VIN
IIN
Input current
VIN = 0 V or 1.89 V, VIN = 1.71 V to 1.89 V
VOH
High level output
voltage
VDDIO = 1.71 V to 1.89 V, IOH = −4 mA
VOL
Low level output
voltage
VDDIO = 1.71 V to 1.89
V
IOL = 4 mA
IOS
Output short circuit
current
VOUT = 0 V
TRI-STATE output
current
PDB = 0 V,
VOUT = 0 V or VDD
IOZ
(1)
(2)
(3)
10
V
Deserializer LVCMOS
outputs
–20
±1
20
µA
VDDIO –
0.45
VDDIO
V
GND
0.45
V
Serializer
GPO outputs
–11
Deserializer LVCMOS
outputs
–17
LVCMOS outputs
mA
–20
20
µA
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA = 25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not specified.
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SNLS420D – JULY 2012 – REVISED JULY 2015
Electrical Characteristics (continued)
over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVCMOS DC SPECIFICATIONS 2.8-V I/O (SERIALIZER INPUTS, GPI, GPO, CONTROL INPUTS AND OUTPUTS)
VIH
High level input
voltage
VIN = 2.52 V to 3.08 V
0.7 VIN
VIN
VIL
Low level input
voltage
VIN = 2.52 V to 3.08 V
GND
0.3 VIN
IIN
Input current
VIN = 0 V or 3.08 V, VIN = 2.52 V to 3.08 V
VOH
High level output
voltage
VDDIO = 2.52 V to 3.08 V, IOH = −4 mA
VOL
Low level output
voltage
VDDIO =2.52 V to 3.08
V
IOL = 4 mA
IOS
Output short circuit
current
VOUT = 0 V
TRI-STATE output
current
PDB = 0 V,
VOUT = 0 V or VDD
IOZ
V
Deserializer LVCMOS
outputs
−20
±1
20
µA
VDDIO – 0.4
VDDIO
V
GND
0.4
V
Serializer
GPO outputs
−11
Deserializer LVCMOS
outputs
−20
LVCMOS outputs
mA
−20
20
µA
340
412
mV
1
50
mV
CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT–)
|VOD|
Output differential
voltage
RL = 100 Ω (see Figure 9)
ΔVOD
Output differential
voltage unbalance
RL = 100 Ω
VOS
Output differential
offset voltage
RL = 100 Ω (see Figure 9)
ΔVOS
Offset voltage
unbalance
RL = 100 Ω
IOS
Output short
circuit current
DOUT± = 0 V
RT
Differential internal
termination
resistance
Differential across DOUT+ and DOUT–
268
VDD – VOD/2
1
V
50
–26
mV
mA
80
100
120
Ω
−20
1
20
µA
80
100
120
Ω
CML RECEIVER DC SPECIFICATIONS (RIN0+, RIN0–, RIN1+, RIN1– )
IIN
Input current
VIN = VDD or 0 V, VDD = 1.89 V
RT
Differential internal
termination
resistance
Differential across RIN+ and RIN-
CML RECEIVER AC SPECIFICATIONS (RIN0+, RIN0–, RIN1+, RIN1– )
|Vswing|
Minimum allowable
swing for 1010
pattern (4)
Line rate = 1.4 Gbps (see Figure 11)
135
mV
CML MONITOR OUTPUT DRIVER SPECIFICATIONS (CMLOUTP, CMLOUTN)
Ew
Differential output
eye opening
EH
Differential output
eye height
(4)
RL = 100 Ω
Jitter frequency > f / 40 (see Figure 20)
0.45
UI
200
mV
Specification is ensured by characterization and is not tested in production.
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Electrical Characteristics (continued)
over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VDDn = 1.89 V
VDDIO = 3.6 V
f = 100 MHz,
10-bit mode
default registers
61
80
VDDn = 1.89 V
VDDIO = 3.6 V
f = 75 MHz,
12-bit high-frequency
mode
default registers
61
80
VDDn = 1.89 V
VDDIO = 3.6 V
f = 50 MHz,
12-bit low-frequency
mode
default registers
61
VDDn = 1.89 V
VDDIO = 3.6 V
f = 100 MHz,
10-bit mode
default registers
54
VDDn = 1.89 V
VDDIO = 3.6 V
f = 75 MHz,
12-bit high-frequency
mode
default registers
54
VDD = 1.89 V
VDDIO = 3.6 V
f = 50 MHz,
12-bit low-frequency
mode
default registers
54
VDDIO = 1.89 V
f = 75 MHz,
12-bit high-freq mode
default registers
1.5
UNIT
SERIALIZER AND DESERIALIZER SUPPLY CURRENT *DIGITAL, PLL, AND ANALOG VDD
RL = 100 Ω
WORST CASE pattern
(see Figure 6)
IDDT
Serializer (TX)
VDDn supply current
(includes load
current)
RL = 100 Ω
RANDOM PRBS-7
pattern
IDDIOT
IDDTZ
IDDIOTZ
12
Serializer (TX)
VDDIO supply
current (includes
load current)
RL = 100 Ω
WORST CASE pattern
(see Figure 6)
Serializer (TX)
supply current
power-down
PDB = 0 V; all other
LVCMOS inputs = 0 V
Serializer (TX)
VDDIO supply
current power-down
PDB = 0 V; All other
LVCMOS Inputs = 0 V
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mA
mA
80
mA
3
mA
VDDIO = 3.6 V
f = 75 MHz,
12-bit high-frequency
mode default registers
5
8
VDDIO = 1.89 V
Default registers
300
900
µA
VDDIO = 3.6 V
Default registers
300
900
µA
VDDIO = 1.89 V
Default registers
15
100
µA
VDDIO = 3.6 V
Default registers
15
100
µA
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SNLS420D – JULY 2012 – REVISED JULY 2015
Electrical Characteristics (continued)
over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3)
PARAMETER
TEST CONDITIONS
VDDIO = 1.89 V
CL = 8 pF
WORST CASE pattern
VDDIO = 1.89 V
CL=8pF
Random pattern
VDDIO = 3.6 V
CL = 8 pF
WORST CASE pattern
VDDIO = 3.6 V
CL = 8 pF
Random pattern
IDDIOR
Deserializer (RX)
total supply current
(includes load
current)
VDDIO = 1.89 V
CL = 4 pF
WORST CASE pattern
VDDIO = 1.89 V
CL = 4 pF
Random pattern
VDDIO = 3.6 V
CL = 4 pF
WORST CASE pattern
VDDIO = 3.6 V
CL = 4 pF
Random pattern
Copyright © 2012–2015, Texas Instruments Incorporated
MIN
TYP
MAX
f = 100 MHz, 10-bit
mode
22
42
f = 75 MHz, 12-bit highfreq mode
19
39
f = 50 MHz, 12-bit lowfreq mode
21
32
f = 100 MHz, 10–bit
mode
15
f = 75 MHz, 12-bit highfreq mode
12
f = 50 MHz, 12-bit lowfreq mode
14
f = 100 MHz, 10-bit
mode
42
55
f = 75 MHz, 12-bit highfreq mode
37
50
f = 50 MHz, 12-bit lowfreq mode
25
38
f = 100 MHz, 10-bit
mode
35
f = 75 MHz, 12-bit highfreq mode
30
f = 50 MHz, 12-bit lowfreq mode
18
f = 100 MHz, 10-bit
mode
15
f = 75 MHz, 12-bit highfreq mode
11
f = 50 MHz, 12-bit lowfreq mode
16
f = 100 MHz, 10-bit
mode
8
f = 75 MHz, 12-bit highfreq mode
4
f = 50 MHz, 12-bit lowfreq mode
9
f = 100 MHz, 10-bit
mode
36
f = 75 MHz, 12-bit highfreq mode
29
f = 50 MHz, 12-bit lowfreq mode
20
f = 100 MHz, 10-bit
mode
29
f = 75 MHz, 12-bit highfreq mode
22
f = 50 MHz, 12-bit lowfreq mode
13
UNIT
mA
mA
mA
mA
mA
mA
mA
mA
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Electrical Characteristics (continued)
over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3)
PARAMETER
TEST CONDITIONS
TYP
MAX
f = 100 MHz,
10-bit mode
64
110
f = 75 MHz,
12-bit high-frequency
mode
67
114
f = 50 MHz,
12-bit low-frequency
mode
63
96
f = 100 MHz,
10-bit mode
57
f = 75 MHz, 12–bit
high-frequency mode
60
f = 50 MHz, 12-bit
low-frequency mode
56
PBB = 0 V, all other
LVCMOS Inputs=0 V
VDDIO = 1.89 V
Default registers
42
400
PBB = 0 V, all other
LVCMOS Inputs=0 V
VDDIO = 3.6 V
Default registers
42
400
VDDn = 1.89 V
CL = 4 pF
WORST CASE pattern
IDDR
Deserializer (RX)
VDDn supply current
(includes load
current)
VDDn = 1.89 V
CL = 4 pF
Random pattern
IDDRZ
IDDIORZ
Deserializer (RX)
supply current
power-down
Deserializer (RX)
VDD supply current
power-down
PDB = 0 V, all other
LVCMOS Inputs = 0 V
MIN
UNIT
mA
µA
VDDIO = 1.89 V
8
40
360
800
MIN
NOM
MAX
10
T
50
13.33
T
66.66
20
T
100
VDDIO = 3.6 V
µA
8.6 Timing Requirements: Recommended for Serializer PCLK
over recommended operating supply and temperature ranges unless otherwise specified. (1)
TEST CONDITIONS
PIN/FREQ
10-bit mode
tTCP
Transmit clock period
12-bit high-frequency
mode
12-bit low-frequency
mode
UNIT
ns
tTCIH
Transmit clock
input high time
0.4T
0.5T
0.6T
ns
tTCIL
Transmit clock
input low time
0.4T
0.5T
0.6T
ns
20 MHz–100 MHz,
10-bit mode
0.5T
2.5T
0.3T
15 MHz to 75 MHz, 12-bit
high-frequency mode
0.5T
2.5T
0.3T
10 MHz to 50 MHz, 12-bit
low-frequency mode
0.5T
2.5T
0.3T
tCLKT
PCLK input transition
time (Figure 12)
ns
tJIT0
PCLK input jitter
(PCLK from imager
mode)
Refer to jitter freq > f / 40
f = 10 to 100 MHz
0.1T
ns
tJIT1
PCLK input jitter (external
Refer to jitter freq > f / 40
oscillator mode)
f = 10 to 100 MHz
1T
ns
tJIT2
External oscillator jitter
0.1
UI
(1)
14
Recommended input timing requirements are input specifications and not tested in production.
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SNLS420D – JULY 2012 – REVISED JULY 2015
AC Timing Specifications (SCL, SDA) - I2C Compliant
8.7
over recommended supply and temperature ranges unless otherwise specified. (See Figure 5)
TEST CONDITIONS
MIN
NOM
MAX
UNIT
RECOMMENDED INPUT TIMING REQUIREMENTS
Standard mode
>0
100
Fast mode
>0
400
Standard mode
4.7
Fast mode
1.3
Standard mode
4.0
Fast mode
0.6
fSCL
SCL clock frequency
tLOW
SCL low period
tHIGH
SCL high period
tHD:STA
Hold time for a start or a
repeated start condition
Standard mode
Fast mode
0.6
tSU:STA
Setup time for a start or a
repeated start condition
Standard mode
4.7
Fast mode
0.6
tHD:DAT
Data hold time
tSU:DAT
Data setup time
tSU:STO
Setup time for STOP
condition
Standard mode
Fast mode
0.6
tBUF
Bus free time between
stop and start
Standard mode
4.7
Fast mode
1.3
tr
SCL and SDA rise time
tf
SCL and SDA fall time
kHz
µs
µs
4
µs
µs
Standard mode
0
3.45
Fast mode
0
900
Standard mode
250
Fast mode
100
µs
ns
4
µs
µs
Standard mode
1000
Fast mode
300
Standard mode
300
Fast mode
300
ns
ns
Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C Compliant
8.8
over recommended supply and temperature ranges unless otherwise specified (1)
TEST CONDITIONS
MIN
NOM
MAX
UNIT
VDDIO
V
RECOMMENDED INPUT TIMING REQUIREMENTS
VIH
Input high level
SDA and SCL
0.7 × VDDIO
VIL
Input low level
SDA and SCL
GND
VHY
Input hysteresis
VOL
Output low level
SDA, IOL = 0.5 mA
IIN
Input current
SDA or SCL, VIN = VDDOP OR GND
tR
SDA rise time-READ
ns
SDA fall time-READ
SDA, RPU = 10 kΩ, Cb ≤ 400 pF (see
Figure 5)
430
tF
20
ns
tSU;DAT
See Figure 5
560
ns
tHD;DAT
See Figure 5
615
ns
0.3 × VDDIO
>50
0
0.4
V
−10
10
µA
tSP
CIN
(1)
V
mV
SDA or SCL
50
ns
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