DS90UB925QSQ/NOPB

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents DS90UB925Q-Q1 SNLS407D – APRIL 2012 – REVISED OCTOBER 2014 DS90UB925Q-Q1 5 to 85 MHz 24-Bit Color FPD-Link III Serializer With Bidirectional Control Channel 1 Features 3 Description • The DS90UB925Q-Q1 serializer, in conjunction with the DS90UB926Q-Q1 deserializer, provides a complete digital interface for concurrent transmission of high-speed video, audio, and control data for automotive display and image sensing applications. 1 • • • • • • • • • • • • • • Bidirectional Control Interface Channel Interface with I2C Compatible Serial Control Bus Supports High Definition (720 p) Digital Video Format RGB888 + VS, HS, DE and I2S Audio Supported Supports Two 10–bit Camera Video Streams 5 – 85MHz PCLK Supported Single 3.3 V Operation with 1.8 V or 3.3 V Compatible LVCMOS I/O Interface AC-Coupled STP Interconnect Up to 10 Meters Parallel LVCMOS Video Inputs DC-Balanced and Scrambled Data with Embedded Clock Supports Repeater Application Internal Pattern Generation Low Power Modes Minimize Power Dissipation Automotive Grade Product: AEC-Q100 Grade 2 Qualified >8kV HBM and ISO 10605 ESD Rating Backward Compatible to FPD-Link II The DS90UB925Q-Q1 serializer embeds the clock, DC scrambles & balances the data payload, and level shifts the signals to high-speed low voltage differential signaling. Up to 24 data bits are serialized along the video control signals. Serial transmission is optimized by a user selectable de-emphasis. EMI is minimized by the use of low voltage differential signaling, data scrambling and randomization and spread spectrum clocking compatibility. 2 Applications • • • • The chipset is ideally suited for automotive videodisplay systems with HD formats and automotive vision systems with megapixel resolutions. The DS90UB925Q-Q1 incorporates an embedded bidirectional control channel and low latency GPIO controls. This chipset translates a parallel interface into a single pair high-speed serialized interface. The serial bus scheme, FPD-Link III, supports full duplex of high-speed video data transmission and bidirectional control communication over a single differential link. Consolidation of video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design. Automotive Display for Navigation Rear Seat Entertainment Systems Automotive Driver Assistance Automotive Megapixel Camera Systems Device Information(1) PART NUMBER DS90UB925Q-Q1 PACKAGE WQFN (48) BODY SIZE (NOM) 7.00 mm × 7.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. VDDIO VDD33 (3.3V) (1.8V or 3.3V) HOST Graphics Processor RGB Digital Display Interface VDDIO VDD33 (1.8V or 3.3V) (3.3V) R[7:0] G[7:0] B[7:0] HS VS DE PCLK DOUT+ SCL SDA IDx RIN+ DOUT- RIN100: STP Cable DS90UB925Q-Q1 Serializer PDB I2S AUDIO (STEREO) R[7:0] G[7:0] B[7:0] HS VS DE PCLK FPD-Link III 1 Pair / AC Coupled 0.1 PF 0.1 PF 3 MODE_SEL INTB DAP PDB OSS_SEL OEN MODE_SEL DS90UB926Q-Q1 Deserializer SCL SDA IDx LOCK PASS 3 INTB_IN RGB Display 720p 24-bit color depth I2S AUDIO (STEREO) MCLK DAP 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DS90UB925Q-Q1 SNLS407D – APRIL 2012 – REVISED OCTOBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7 1 1 1 2 4 7 Absolute Maximum Ratings ..................................... 7 Handling Ratings....................................................... 7 Recommended Operating Conditions....................... 7 Thermal Information .................................................. 8 DC Electrical Characteristics .................................... 8 AC Electrical Characteristics................................... 10 Recommended Timing for the Serial Control Bus .. 11 Switching Characteristics ........................................ 13 Typical Charateristics ............................................. 14 Detailed Description ............................................ 15 7.1 Overview ................................................................. 15 7.2 Functional Block Diagram ....................................... 15 7.3 Feature Description................................................. 15 7.4 Device Functional Modes........................................ 22 7.5 Programming .......................................................... 25 7.6 Register Maps ........................................................ 27 8 Application and Implementation ........................ 38 8.1 Application Information............................................ 38 8.2 Typical Application .................................................. 38 9 Power Supply Recommendations...................... 41 9.1 Power Up Requirements and PDB Pin ................... 41 9.2 CML Interconnect Guidelines.................................. 41 10 Layout................................................................... 42 10.1 Layout Guidelines ................................................. 42 10.2 Layout Example .................................................... 43 11 Device and Documentation Support ................. 45 11.1 11.2 11.3 11.4 Documentation Support ........................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 45 45 45 45 12 Mechanical, Packaging, and Orderable Information ........................................................... 45 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (April 2013) to Revision D Page • Added data sheet flow and layout to conform with new TI standards. Added the following sections: Handling Ratings, Device Functional Modes; Programming; Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical, Packaging and Ordering Information.......................................................................... 1 • Added Device Information table ............................................................................................................................................. 1 • Fixed typo for GPIO configuration ........................................................................................................................................ 19 • Removed two MODE_SEL modes: I2S Channel B, and Backward Compatible.................................................................. 23 • Removed IDx addresses 0x22, 0x24, 0x2E, 0x30, 0x32, 0x34............................................................................................ 26 • Changed suggested resistor values for IDx addresses 0x1E, 0x20, 0x26, 0x28, 0x2A....................................................... 26 Changes from Revision B (August 2012) to Revision C • Page Changed layout of National datasheet to TI format................................................................................................................ 1 Changes from Revision A (July 2012) to Revision B Page • Added typical charateristic graphics ..................................................................................................................................... 14 • Added” Note: frequency range = 15 - 65MHz when LFMODE = 0 and frequency range = 5 - 50 VOL SDA, IOL = 1.25 mA Iin SDA or SCL, VIN = VDD33 or GND Cin Input Capacitance mV 0 0.36 V -10 10 µA SDA or SCL