DS90UB953TRHBRQ1

厂商：
BURR-BROWN(德州仪器)
封装：
QFN32
描述：
适用于 2.3MP/60fps 摄像头、雷达和其他传感器并具有 CSI-2 接口的 FPD-Link III 4.16Gbps 串行器

数据手册：

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数据手册
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DS90UB953TRHBRQ1 数据手册

Order Now Product Folder Support & Community Tools & Software Technical Documents DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 DS90UB953-Q1 适用于 2.3MP/60fps 摄像头、雷达和其他传感器并具有 CSI-2 接口的 FPD-Link III 4.16Gbps 串行器 1 特性 • 1 • • • • • • • • • • • • • • 2 应用符合面向汽车应用的 AEC-Q100 标准： – 器件温度等级 2：环境工作温度范围为 –40°C 至 +105°C 符合 ISO 10605 和 IEC 61000-4-2 ESD 标准同轴电缆供电 (PoC) 兼容收发器 4.16Gbps 级串行器支持高速传感器包括全高清 1080p 2MP 60fps 和 4MP 30fps 成像器符合 D-PHY v1.2 和 CSI-2 v1.3 标准的系统接口 – 多达 4 条数据通道，每通道速率为 832Mbps – 支持多达四个虚拟通道精密多传感器时钟和同步灵活的可编程输出时钟发生器高级数据保护和诊断，包括 CRC 数据保护、传感器数据完整性检查、I2C 写保护、电压和温度测量、可编程警报器以及线路故障检测支持单端同轴或屏蔽双绞线 (STP) 电缆超低延迟双向 I2C 和 GPIO 控制通道支持从 ECU 侧进行 ISP 控制， 1.8V 单电源低功耗（0.25W 典型值）兼容 DS90UB954-Q1、DS90UB960-Q1、 DS90UB934-Q1、DS90UB914A-Q1 解串器宽温度范围：–40°C 至 105°C 小型 5mm × 5mm VQFN 封装和 PoC 解决方案尺寸，适合紧凑型摄像头模块设计 • • • 汽车驾驶员辅助系统 (ADAS) – 环视系统 (SVS) – 摄像头监控系统 (CMS) – 前视摄像头 (FC) – 驾驶员监控系统 (DMS) – 后视摄像头 (RVC) – 汽车卫星雷达和激光雷达模块 – 飞行时间 (ToF) 传感器安防和监控摄像头工业和医疗成像 3 说明 DS90UB953-Q1 串行器是 TI FPD-Link III 器件系列的一部分，旨在支持高速原始数据传感器，包括 60fps 的 2MP 成像器以及 4MP 30fps 摄像头、卫星雷达、激光雷达和飞行时间 (ToF) 传感器。该芯片提供 4.16Gbps 正向通道和超低延迟的 50Mbps 双向控制通道，并支持单根同轴 (PoC) 或 STP 电缆进行供电。 DS90UB953-Q1 具有高级数据保护和诊断特性，可支持 ADAS 和自主驾驶。DS90UB953-Q1 与配套的解串器一起提供精确的多摄像头传感器时钟和传感器同步。 DS90UB953-Q1 完全符合 AEC-Q100 标准，具有 –40°C 至 105°C 的宽温度范围。该串行器采用 5mm × 5mm 的小型 VQFN 封装，非常适合空间受限型传感器应用。器件信息(1) 器件型号 DS90UB953-Q1 封装 VQFN (32) 封装尺寸（标称值） 5.00mm × 5.00mm (1) 要了解所有可用封装，请见产品说明书末尾的可订购产品附录。典型应用 MIPI CSI-2 D3P/N Full HD Image Sensor MIPI CSI-2 DS90UB953-Q1 D2P/N FPD-Link III (over Coax or STP) Serializer D1P/N D0P/N CLKP/N DOUT+/- DS90UB954-Q1 or DS90UB960-Q1 Deserializer RIN+/- D3P/N D2P/N D1P/N D0P/N Image Signal Processor (ISP) CLKP/N I2C I2C HS-GPIO HS-GPIO 1 本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。 English Data Sheet: SNLS552 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn 目录 1 2 3 4 5 6 特性 .......................................................................... 应用 .......................................................................... 说明 .......................................................................... 修订历史记录 ........................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 7 1 1 1 2 5 7 Absolute Maximum Ratings ...................................... 7 ESD Ratings.............................................................. 7 Recommended Operating Conditions....................... 7 Thermal Information .................................................. 8 Electrical Characteristics........................................... 9 Recommended Timing for the Serial Control Bus .. 13 Timing Diagrams ..................................................... 14 Typical Characteristics ............................................ 14 Detailed Description ............................................ 15 7.1 7.2 7.3 7.4 7.5 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Programming........................................................... 7.6 Pattern Generation ................................................. 28 7.7 Register Maps ........................................................ 32 8 Application and Implementation ........................ 69 8.1 Application Information............................................ 69 8.2 Typical Applications ................................................ 72 9 Power Supply Recommendations...................... 75 9.1 Power-Up Sequencing ............................................ 75 9.2 Power Down (PDB) ................................................. 76 10 Layout................................................................... 76 10.1 Layout Guidelines ................................................. 76 10.2 Layout Examples................................................... 77 11 器件和文档支持 ..................................................... 80 11.1 11.2 11.3 11.4 11.5 11.6 11.7 器件支持................................................................ 文档支持 ............................................................... 接收文档更新通知 ................................................. 社区资源................................................................ 商标 ....................................................................... 静电放电警告......................................................... 术语表 ................................................................... 80 80 80 80 80 80 80 15 15 16 22 26 12 机械、封装和可订购信息 ....................................... 81 Changes from Revision A (February 2018) to Revision B Page 4 修订历史记录 • Updated GPIO pin descriptions. ............................................................................................................................................ 6 • Replace CLK_IN with clock throughout document. ............................................................................................................... 6 • Changed Supply voltage from 2.5V to 2.16V ......................................................................................................................... 7 • Changed asynchronous to non-synchronous ......................................................................................................................... 8 • Deleted "for synchronous mode" ............................................................................................................................................ 8 • Added internal reference frequency in EC table................................................................................................................... 10 • Added Internal AON Clock to Block Diagram....................................................................................................................... 15 • 已更改 mode to modes. ....................................................................................................................................................... 18 • Changed 130ns to 225ns. .................................................................................................................................................... 22 • Changed latency to 1.5us and jitter to 0.7us. ...................................................................................................................... 22 • Changed CLK_IN Mode to Modes. ..................................................................................................................................... 22 • Added DVP Mode ................................................................................................................................................................ 22 • Changed table formatting. ................................................................................................................................................... 23 • 已更改 REFLCK to Back Channel ....................................................................................................................................... 23 • 已添加 Frequency for Synchronous Mode .......................................................................................................................... 23 • 已更改 naming convention from "asynchronous CLK_IN" to "Non-Synchronous external CLK_IN" mode column dor CLKIN_DIV = 2 ..................................................................................................................................................................... 23 • 已更改 from CLK_IN to Back Channel (Half Rate). .............................................................................................................. 23 • 已添加 Non-Synchronous Internal Clock Mode ................................................................................................................... 23 • 已更改 the value from 24.2 - 25.5 MHz to 48.4 - 51 MHz ................................................................................................... 23 • 已更改 the value from 25 - 52 MHz to 24.2 to 25.5 MHz .................................................................................................... 23 • Added DVP External Clock................................................................................................................................................... 23 • 已添加 text "Deserializer Mode" to clarify mode RAW10 .................................................................................................... 23 • 已添加 additional information to note. ................................................................................................................................. 23 2 版权 © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 修订历史记录 (接接下页) • 已添加 text "Deserializer Mode" to clarify mode RAW12 HF .............................................................................................. 23 • 已更改 CLK_IN to Clock. ...................................................................................................................................................... 23 • Added Non-Synchronous Internal Clocking Mode section. ................................................................................................. 24 • 已更改 the internal clock 25 MHz to 24.2 MHz .................................................................................................................... 24 • 已更改 forward channel rate to1.936 Gbps instead of 2 Gbps ............................................................................................ 24 • 已更改 the average CSI-2 throughput value to 3.1 Gbps instead of 1.6 Gbps ................................................................... 24 • Added DVP Backwards Compatibility Mode section. ........................................................................................................... 24 • 已更改 "asynchronous CLK_IN" to "Non-Synchronous external CLK_IN" ........................................................................... 24 • Added sentence "CLK_OUT functionality is not..."............................................................................................................... 24 • 已添加 Non-Synchronous Internal Clock Mode ................................................................................................................... 26 • Deleted "with accuracy of 25 MHz ±10%. ............................................................................................................................ 28 • Changed clock to from 25 MHz ±10% to 26.25 MHz. ......................................................................................................... 28 • Changed clock to from 25 MHz ±10% to 26.25 MHz. ......................................................................................................... 28 • Updated registers map ........................................................................................................................................................ 32 • Added information for DVP mode to register 0x04. ............................................................................................................. 33 • Added "operating with Non-Synchronous internal clock or" ................................................................................................. 34 • Changed the frequency value from 26 MHz to range value (24.2 MHz to 25.5 MHz) ........................................................ 34 • Added "set for 2 Gbps line rate" .......................................................................................................................................... 34 • Changed the frequency value from 52 MHz to range value (48.4 MHz to 51 MHz) ........................................................... 34 • Added "set for 4 Gbps line rate" .......................................................................................................................................... 34 • Updated unit time and clock frequency. .............................................................................................................................. 36 • Added DVP information to register 0x10. ............................................................................................................................ 37 • Added DVP information to register 0x11. ............................................................................................................................ 37 • 已删除 the value -25dB and added -20dB in typcial ............................................................................................................ 71 • 已更改 –26.4+14.4f to log equation –12+8*log(f) ................................................................................................................ 71 • Moved Return Loss, S11 MAX values to TYP ..................................................................................................................... 71 • 已添加 Typical connection diagram for STP ........................................................................................................................ 72 • 已更改 the capacitance value from 33nF to 33nF – 100 nF. ............................................................................................... 73 • 已更改 the capacitance value from 15 nF to 15 nF – 47 nF................................................................................................. 73 • 已更改 the capacitance value from 33nF to 33nF – 100 nF. ............................................................................................... 73 Changes from Original (September 2017) to Revision A Page • Changed RES1 pin description from "Leave OPEN" to "Do not connect" ............................................................................ 5 • Added "Internal 1-MΩ pulldown" text to PDB pin description................................................................................................. 5 • Expanded MODE pin description .......................................................................................................................................... 6 • Changed "Requires" to "Typically connected to" in the Power and Ground pin descriptions ............................................... 6 • Changed "and should not be connected to an external supply" to "Do not connect to an external supply rail" in the Power and Ground pin descriptions ...................................................................................................................................... 6 • Changed the CSI_ERR_COUNT (0x5C) text to CSI_ERR_CNT (0x5C) ............................................................................. 18 • Changed DS90UBUB954-Q1 to DS90UB954-Q1 ................................................................................................................ 20 • Changed the GPIO_INPUT_CTL text to GPIO_INPUT_CTRL in the GPIO Input Control and GPIO Output Control sections................................................................................................................................................................................. 21 • Changed CLK_IN lower limit with CLKIN_DIV =1 from 46 MHz to 25 MHz and CLK_IN lower limit from 92 MHz to 50 MHz. ................................................................................................................................................................................ 23 • Corrected typo in MODE description saying the number of modes is 3 to the correct value of 2 ....................................... 25 版权 © 2017–2018, Texas Instruments Incorporated 3 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn • Changed I2C START description to "A START occurs when SDA transitions Low while SCLK is High" .......................... 27 • Added registers tables for reserved registers 0x04, 0x0F-0x12, 0x16, 0x1F, 0x25-0x30, 0x34, 0x36, 0x38, 0x4A0x4F, 0x5B, 0x65-0xAF, and 0xB3-0xEF. ............................................................................................................................ 32 • Changed bit 6 and bit 7 in the MODE_SEL register to RESERVED.................................................................................... 33 • Changed the SENSE_VO_HI and SENSE_VO_LO registers to SENSE_V0_HI and SENSE_V0_LO to match the title in Table 36 ..................................................................................................................................................................... 39 • Changed the SENSE_V0_HI and SENSE_V0_LO bit descriptions ..................................................................................... 39 • Changed the SENSOR_V0_THRESH bit description ......................................................................................................... 39 • Changed the SENSE_T_HI and SENSE_T_LO bit descriptions.......................................................................................... 39 • Combined the CSI_EN_HSRX register bits 6–0 into one row.............................................................................................. 41 • Combined the CSI_EN_LPRX register bits 6–0 into one row .............................................................................................. 41 • Combined the CSI_EN_RXTERM register bits 7–4 into one row ........................................................................................ 42 • Changed serializer to deserializer in SLAVE_ID_ALIAS_x bit descriptions ........................................................................ 47 • Changed Slave 0 to Slave 1 in the SLAVE_AUTO_ACK_1 bit description ......................................................................... 48 • Changed Slave 0 to Slave 2 in the SLAVE_AUTO_ACK_2 bit description ......................................................................... 48 • Changed Slave 0 to Slave 3 in the SLAVE_AUTO_ACK_3 bit description ......................................................................... 48 • Changed Slave 0 to Slave 4 in the SLAVE_AUTO_ACK_4 bit description ......................................................................... 49 • Changed Slave 0 to Slave 5 in the SLAVE_AUTO_ACK_5 bit description ......................................................................... 49 • Changed Slave 0 to Slave 6 in the SLAVE_AUTO_ACK_6 bit description ......................................................................... 49 • Changed Slave 0 to Slave 7 in the SLAVE_AUTO_ACK_7 bit description ......................................................................... 50 • Changed CRC_ERR bit description in GENERAL_STATUS to match CRC_ERR_CLR register name ............................ 51 • Changed the CNTRL_ERR_HSRQST_2 bit description ...................................................................................................... 54 • Changed 图 17 caption......................................................................................................................................................... 72 • Added PIN(S) column to 表 178 .......................................................................................................................................... 73 • Changed large bulk capacitor typical range lower limit from 50 µF to 47 µF, removed mentions of dedicated power plane and tantalum capacitors, and changed recommended power rating for capacitors in layout guidelines .................. 76 • Changed recommended CSI-2 guidelines on matching trace lengths and routing to help trace impedance ...................... 77 • Changed routing guidelines for the DOUT+ and DOUT– pins ............................................................................................ 78 • 在相关文档部分添加了新链接 .............................................................................................................................................. 80 4 Copyright © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 5 Pin Configuration and Functions VDDD I2C_SDA RES1 MODE CLKIN CLK_OUT/IDX GPIO_1 GPIO_0 23 22 21 20 19 18 17 24 I2C_SCL RHB Package 32-Pin VQFN Top View 25 16 VDDDRV 15 VDDDRV_CAP 14 DOUT+ 13 DOUT- DAP = GND VDDD_CAP 26 GPIO_2 27 DS90UB953-Q1 32L QFN (Top View) 9 LPF1 8 32 PDB CSI_D2N 7 VDDPLL_CAP RES0 10 6 31 CSI_CLKN CSI_D2P 5 VDDPLL CSI_CLKP 11 4 30 CSI_D0N CSI_D3N 3 LPF2 CSI_D0P 12 2 29 CSI_D1N CSI_D3P 1 28 CSI_D1P GPIO_3 Pin Functions PIN NAME NO. I/O DESCRIPTION CSI INTERFACE CSI_CLKP 5 I, DPHY CSI_CLKN 6 I, DPHY CSI_D0P 3 I, DPHY CSI_D0N 4 I, DPHY CSI_D1P 1 I, DPHY CSI_D1N 2 I, DPHY CSI_D2P 31 I, DPHY CSI_D2N 32 I, DPHY CSI_D3P 29 I, DPHY CSI_D3N 30 I, DPHY CSI-2 clock input pins. Connect to a CSI-2 clock source with matched 100-Ω (±5%) impedance interconnects. CSI-2 data input pins. Connect to a CSI-2 data sources with matched 100-Ω (±5%) impedance interconnects. If unused, these pins may be left floating. SERIAL CONTROL INTERFACE I2C_SDA 23 OD I2C_SCL 24 OD I2C Data and Clock Pins. Typically pulled up by 470-Ω to 4.7-kΩ resistors to either 1.8-V or 3.3-V supply rail depending on IDX setting. See I2C Interface Configuration for further details on the I2C implementation of the DS90UB953-Q1. CONFIGURATION and CONTROL RES0 7 I Reserved pin – Connect to GND RES1 22 I Reserved pin – Do not connect (leave floating) PDB 8 I, PD Power-down inverted Input Pin. Internal 1-MΩ pulldown. Typically connected to processor GPIO with pull down. When PDB input is brought HIGH, the device is enabled and internal register and state machines are reset to default values. Asserting PDB signal low will power down the device and consume minimum power. The default function of this pin is PDB = LOW; POWER DOWN. PDB should remain low until after power supplies are applied and reach minimum required levels. See Power Down (PDB) for further details on the function of PDB. PDB INPUT IS NOT 3.3-V TOLERANT. PDB = 1.8 V, device is enabled (normal operation) PDB = 0, device is powered down. Copyright © 2017–2018, Texas Instruments Incorporated 5 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn Pin Functions (continued) PIN I/O DESCRIPTION I, S Mode select configuration input. Default operational mode will be strapped at start-up based on the MODE input voltage when PDB transitions LOW to HIGH. Typically connected to voltage divider through external pullup to VDD18 and pulldown to GND applying an appropriate bias voltage. See MODE for detail. 19 I/O, S IDX pin sets the I2C pullup voltage and device address; connect to external pullup to VDD and pulldown to GND to create a voltage divider. When PDB transitions LOW to HIGH, the strap input voltage is sensed at the CLOCK_OUT/IDX pin to determine functionality and then converted to CLK_OUT. See I2C Interface Configuration for detail. If CLK_OUT is used, the minimum resistance on the pin is 35 kΩ. If unused, CLK_OUT/IDX may be tied to GND. DOUT- 13 I/O DOUT+ 14 I/O VDDD_CAP 26 D, P A connection for internal analog regulator decoupling capacitor. Typically connected to 10-µF, 0.1-µF, and 0.01-µF capacitors to GND. Do not connect to an external supply rail. See Typical Application for more details. VDDDRV_CAP 15 D, P A connection for internal analog regulator decoupling capacitor. Typically connected to 10-µF, 0.1-µF, and 0.01-µF capacitors to GND. Do not connect to an external supply rail. See Typical Application for more details. VDDPLL_CAP 10 D, P A connection for internal analog regulator decoupling capacitor. Typically connected to 10-µF, 0.1-µF, and 0.01-µF capacitors to GND. Do not connect to an external supply rail. See Typical Application for more details. VDDD 25 P 1.8-V (±5%) Power Supply pin. Typically connected to 1-µF and 0.01-µF capacitors to GND. VDDDRV 16 P 1.8-V (±5%) Analog Power Supply pin. Typically connected to 1-µF and 0.01-µF capacitors to GND. VDDPLL 11 P 1.8-V (±5%) Analog Power Supply pin. Typically connected to 1-µF and 0.01-µF capacitors to GND. DAP G DAP is the large metal contact at the bottom side, located at the center of the VQFN package. Connect to the ground plane (GND). LPF1 9 P Loop Filter 1: Connect as described in Loop Filter Decoupling. LPF2 12 P Loop Filter 2: Connect as described in Loop Filter Decoupling. NAME NO. MODE 21 CLK_OUT/IDX FPD-LINK III INTERFACE FPD-Link III Input/Output pins. These pins must be AC-coupled. See 图 19 and 图 20 for typical connection diagrams and 表 178 for recommended capacitor values. POWER AND GROUND GND LOOP FILTER CLOCK INTERFACE and GPIO GPIO_0 17 I/O, PD GPIO_1 18 I/O, PD GPIO_2 27 I/O, PD GPIO_3 28 I/O. PD CLKIN 20 I 6 General-Purpose Input/Output pins. These pins can also be configured to sense the voltage at their inputs. See Voltage and Temperature Sensing. At power-up these GPIO pins default to inputs with a 300 kΩ (typical) internal pulldown resistor. If unused, these pins may be left floating, however, it is recommended to disable them by setting the GPIOx_INPUT_EN to 0. See GPIO Support for programmability. General-Purpose Input/Output pins. At power-up these GPIO pins default to inputs with a 300 kΩ (typical) internal pulldown resistor. If unused, these pins may be left floating, however, it is recommended to disable them by setting the GPIOx_INPUT_EN to 0. See GPIO Support for programmability. Reference Clock Input pin. If operating in Non Sync external clock mode, connect this pin to a local clock source. If unused (other clocking modes), this pin may be left open. See 表 6 for more information on clocking modes. Copyright © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) PIN OR FREQUENCY MIN MAX UNIT VDDD, VDDDRV, VDDPLL –0.3 2.16 V GPIO[3:0], PDB, CLKIN, IDX, MODE, CSI_CLKP/N, CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N –0.3 VDD + 0.3 V DOUT+, DOUT- –0.3 1.21 V I2C_SDA, I2C_SCL –0.3 3.96 V 150 °C 150 °C Supply voltage, VDD Input voltage FPD-Link III output voltage Open-drain voltage Junction temperature, TJ Storage termperature, Tstg (1) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings Human body model (HBM) ESD Classification Level 3A, per AEC Q100-002 (1) VALUE UNIT ±4000 V ±1500 V Contact Discharge (DOUT+ and DOUT-) ±8000 V Air Discharge (DOUT+ and DOUT-) ±18000 V Contact Discharge (DOUT+ and DOUT-) ±8000 V Air Discharge (DOUT+ and DOUT-) ±18000 V All pins except Media Dependent Interface Pins Media Dependent Interface Pins Charged-device model (CDM) ESD Classification Level C6, per AEC Q100011 V(ESD) Electrostatic discharge IEC 61000-4-2 RD = 330 Ω, CS = 150 pF ISO 10605 RD = 330 Ω, CS = 150 pF and 330 pF RD = 2 kΩ, CS = 150 pF and 330 pF (1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.3 Recommended Operating Conditions Over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Supply voltage VDD (VDDD, VDDDRV, VDDPLL) 1.71 1.8 1.89 V Open-drain voltage I2C_SDA, I2C_SCL = V(I2C) 1.71 3.6 V 25 105 °C Operating free-air temperature (TA) –40 Mipi data rate (per CSI-2 lane) 80 832 Mbps Reference clock input frequency 25 104 MHz 1 MHz Local I2C frequency (fI2C) Copyright © 2017–2018, Texas Instruments Incorporated 7 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn Recommended Operating Conditions (continued) Over operating free-air temperature range (unless otherwise noted) MIN Supply noise Differential supply noise between DOUT+ and DOUT(PSR) MAX UNIT VDD (VDDD, VDDDRV, VDDPLL) 25 mVp-p f = 10 KHz - 50 MHz (coax mode only) 25 mVp-p f = 30 Hz, 10-90% Rise/Fall Time > 100µs (coax mode only) 25 mVp-p Input clock jitter for non-synchronous mode (tJIT) CLKIN Back channel input jitter (tJIT-BC) DOUT+, DOUT- (1) (2) NOM 0.05 UI_CLK_I N (1) 0.4 UI_BC (2) Non-synchronous mode - For a given clock, the UI is defined as 1/clock_freq. For example when the clock = 50Mhz, the typical UI_CLK_IN is 1/50 MHz = 20 ns. The back channel unit interval (UI_BC) is 1/(BC line-rate). For example, the typical UI_BC is 1/100 MHz = 10 ns. If the jitter tolerance is 0.4 UI, convert the jitter in UI to seconds using this equation: 10 ns × 0.4 UI = 4 ns 6.4 Thermal Information DS90UB953Q-Q1 THERMAL METRIC (1) RHB (VQFN) UNIT 32 PINS RθJA Junction-to-ambient thermal resistance 31.5 °C/W RθJB Junction-to-board thermal resistance 10.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 20 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1 °C/W ΨJT Junction-to-top characterization parameter 0.2 °C/W ΨJB Junction-to-board characterization parameter 10.9 °C/W (1) 8 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Copyright © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 6.5 Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwisespecified. PARAMETER TEST CONDITIONS PIN OR FREQUENCY MIN TYP MAX VDDPLL, VDDD, VDDDRV 160 225 VDDPLL 55 80 VDDD 45 70 VDDDRV 60 75 UNIT POWER CONSUMPTION IDD_TOTAL IDDPLL Supply current 416-MHz CSI Input Clock, 4 Lane Mode, Checkerboard Pattern IDDD IDDDRV mA 1.8-V LVCMOS I/O (VDD) = 1.71 V to 1.89 V) VOH High level output voltage IOH = –4 mA GPIO[3:0], CLK_OUT V(VDD) – 0.45 V(VDD) V VOL Low level output voltage GPIO[3:0], CLK_OUT GND 0.45 V VIH High level input voltage GPIO[3:0], PDB, CLKIN V(VDD) × 0.65 V(VDD) V VIL Low level input voltage GPIO[3:0], PDB, CLKIN GND V(VDD) × 0.35 V IIH Input high current VIN = V(VDD) GPIO[3:0], PDB, CLKIN 20 µA IIL Input low current VIN = GND GPIO[3:0], PDB, CLKIN IOS Output short-circuit current VOUT = 0 V IOZ TRI-STATE output current VOUT = V(VDD), VOUT = GND CIN Input capacitance IOL = +4 mA Copyright © 2017–2018, Texas Instruments Incorporated -20 µA -36 GPIO[3:0], CLK_OUT mA ±20 5 µA pF 9 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwisespecified. PARAMETER TEST CONDITIONS PIN OR FREQUENCY MIN TYP MAX UNIT FPD-LINK III INPUT/OUTPUT VIN-BC Single-ended input voltage Coaxial configuration, 50 Ω, maximum cable length DOUT+, DOUT- 120 VID-BC Differential input voltage STP configuration, 100 Ω, maximum cable length DOUT+, DOUT- 240 Coaxial configuration, FPD-Link forward channel = 4.16 Gbps DOUT+, DOUT- 425 EH-FC Forward channel eye height STP configuration, FPD-Link forward channel = 4.16 Gbps DOUT+, DOUT- 850 FPD-Link forward channel = 4.16Gbps; 20% to 80% DOUT+, DOUT- 65 Synchronous mode, measured with f/15 –3dB CDR Loop BW DOUT+, DOUT- 0.21 Non-synchronous mode, measured with f/15 –3dB CDR Loop BW DOUT+, DOUT- 0.22 tTR-FC Forward channel output transition time tJIT-FC Forward channel output jitter fREF Internal reference frequency Non-synchronous internal clocking mode mV mVp-p ps UI 24.2 25.5 MHz FPD-LINK III DRIVER SPECIFICATIONS (DIFFERENTIAL) VODp-p Output differential voltage ΔVOD Output voltage imbalance DOUT+, DOUT- 5 VOS Output differential offset voltage DOUT+, DOUT- 575 mV ΔVOS Offset voltage imbalance DOUT+, DOUT- 2 mV IOS Output short-circuit current DOUT = 0 V DOUT+, DOUT- –22 mA RT Internal termination resistance Between DOUT+ and DOUT- DOUT+, DOUT- 80 100 120 520 575 670 mVp-p RL = 100 Ω DOUT+, DOUT- 1040 1150 1340 mVp-p 24 mV Ω FPD-LINK III DRIVER SPECIFICATIONS (SINGLE-ENDED) VOUT Output single-ended voltage RL = 50 Ω DOUT+, DOUT- IOS Output short-circuit current DOUT = 0 V DOUT+, DOUT- RT Single-ended termination resistance DOUT+, DOUT- –22 40 50 mA 60 Ω VOLTAGE AND TEMPERATURE SENSING VACC Voltage accuracy See Voltage and Temperature Sensing TACC Temperature accuracy See Voltage and Temperature Sensing 10 GPIO[1:0] ±1 LSB ±1 LSB Copyright © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwisespecified. PIN OR FREQUENCY MIN Common-mode voltage HS receive mode CSI_D3P/N, CSI_D2P/N, CSI_D1P/N, CSI_D0P/N, CSI_CLKP/N 70 Differential input high threshold CSI_D3P/N, CSI_D2P/N, CSI_D1P/N, CSI_D0P/N, CSI_CLKP/N VIDTL Differential input low threshold CSI_D3P/N, CSI_D2P/N, CSI_D1P/N, CSI_D0P/N, CSI_CLKP/N –70 ZID Differential input impedance CSI_D3P/N, CSI_D2P/N, CSI_D1P/N, CSI_D0P/N, CSI_CLKP/N 80 Data to clock setup time CSI_D3P/N, CSI_D2P/N, CSI_D1P/N, CSI_D0P/N, CSI_CLKP/N 0.15 UI Data to clock hold time CSI_D3P/N, CSI_D2P/N, CSI_D1P/N, CSI_D0P/N, CSI_CLKP/N 0.15 UI Logic high input voltage CSI_D3P/N, CSI_D2P/N, CSI_D1P/N, CSI_D0P/N, CSI_CLKP/N 880 Logic low input voltage CSI_D3P/N, CSI_D2P/N, CSI_D1P/N, CSI_D0P/N, CSI_CLKP/N Input hysteresis CSI_D3P/N, CSI_D2P/N, CSI_D1P/N, CSI_D0P/N, CSI_CLKP/N PARAMETER TEST CONDITIONS TYP MAX UNIT 330 mV 70 mV CSI-2 HS INTERFACE DC SPECIFICATIONS VCMRX(DC) VIDTH mV 100 125 Ω CSI-2 HS INTERFACE AC SPECIFICATIONS tHOLD tSETUP CSI-2 LP INTERFACE DC SPECIFICATIONS VIH VIL VHYST Copyright © 2017–2018, Texas Instruments Incorporated 790 710 25 75 mV 550 mV mV 11 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwisespecified. PARAMETER TEST CONDITIONS PIN OR FREQUENCY MIN TYP MAX UNIT LVCMOS I/O tCLH LVCMOS low-to-high transition time V(VDD) = 1.71 to 1.89 V GPIO[3:0] 2 ns tCHL LVCMOS high-to-low transition time V(VDD) = 1.71 to 1.89 V GPIO[3:0] 2 ns tPDB PDB reset pulse width Voltage supplies applied and stable PDB 3 ms SERIAL CONTROL BUS VIH Input high level I2C_SCL, I2C_SDA 0.7 × V(I2C) V(I2C) mV VIL Input low level I2C_SCL, I2C_SDA GND 0.3 × V(I2C) mV VHY Input hysteresis I2C_SCL, I2C_SDA VOL Output low level >50 mV V(I2C) < 2 V, IOL = 3 mA, Standardmode/Fast-mode I2C_SCL, I2C_SDA 0 0.2 × V(I2C) V V(I2C) < 2 V, IOL = 20 mA, Fast-mode plus I2C_SCL, I2C_SDA 0 0.2 × V(I2C) V V(I2C) > 2 V, IOL = 3 mA, Standardmode/Fast-mode I2C_SCL, I2C_SDA 0 0.4 V V(I2C) > 2 V, IOL = 20 mA, Fast-mode plus I2C_SCL, I2C_SDA 0 0.4 V IIH Input high current VIN = V(I2C) I2C_SCL, I2C_SDA -10 10 µA IIL Input low current VIN = 0 V I2C_SCL, I2C_SDA -10 10 µA IIL Input low current VIN = 0 V I2C_SCL, I2C_SDA -10 10 µA CIN Input capacitance 12 I2C_SCL, I2C_SDA 5 pf Copyright © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 6.6 Recommended Timing for the Serial Control Bus Over I2C supply and temperature ranges unless otherwise specified. MIN fSCL tLOW tHIGH tHD;STA tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF SCL Clock Frequency SCL Low Period SCL High Period Hold time for a start or a repeated start condition Data set up time Set up time for STOP condition Bus free time between STOP and START tf Cb tVD:DAT SCL & SDA rise time SCL & SDA fall time Capacitive load for each bus line Data valid time Data vallid acknowledge time 100 >0 400 kHz Fast-mode Plus >0 1 MHz Standard-mode 4.7 µs Fast-mode 1.3 µs Fast-mode Plus 0.5 µs Standard-mode 4.0 µs Fast-mode 0.6 µs Fast-mode Plus 0.26 µs Standard-mode 4.0 µs Fast-mode 0.6 µs Fast-mode Plus 0.26 µs Standard-mode 4.7 µs 0.6 µs Fast-mode Plus 0.26 µs Standard-mode 0 µs Fast-mode 0 µs Fast-mode Plus 0 µs Standard-mode 250 ns Fast -mode 100 ns Fast-mode Plus 50 ns Standard-mode 4.0 µs Fast-mode 0.6 µs Fast-mode Plus 0.26 µs Standard-mode 4.7 µs Fast-mode 1.3 µs Fast-mode Plus 0.5 µs 1000 ns Fast-mode 300 ns Fast-mode Plus 120 ns Standard-mode 300 ns Fast-mode 300 ns Fast-mode Plus 120 ns Standard-mode 400 pF Fast-mode 400 pF Fast-mode Plus 550 pF Standard-mode 3.45 µs 0.9 µs Fast-mode Plus 0.45 µs Standard-mode 3.45 µs Fast-mode 0.9 µs 0.45 µs Fast-mode 50 ns Fast-mode Plus 50 ns Fast-mode Plus tSP Input filter Copyright © 2017–2018, Texas Instruments Incorporated kHz >0 Fast-mode tVD;ACK UNIT Fast-mode Standard-mode tr MAX Standard-mode Set up time for a start or a repeated start condition Fast-mode Data hold time TYP 13 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn 6.7 Timing Diagrams V(VDD18) 80% 20% GND tCLH tCHL 图 1. LVCMOS Transition Times SDA tf tHD;STA tLOW tr tr tBUF tf SCL tSU;STA tHD;STA tHIGH tHD;DAT START tSU;STO tSU;DAT REPEATED START STOP START 图 2. I2C Serial Control Bus Timing 6.8 Typical Characteristics 图 3. Eye Diagram at 4-Gbps FPD-Link III Forward Channel Rate From Serializer Output Vertical Scale: 100 mV/DIV Horizontal Scale: 62.5 ps/DIV 14 版权 © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 7 Detailed Description 7.1 Overview The DS90UB953-Q1 serializes data from high-resolution image sensors or other sensors using the MIPI CSI-2 interface. The DS90UB953-Q1 serializer is optimized to interface with the DS90UB954-Q1 deserializer (dual hub) or the DS90UB960-Q1 deserializer (quad hub) as well as potential future deserializers. The interconnect between the serializer and the deserializer can be either a coaxial cable or shielded-twisted pair (STP) cable. The DS90UB953-Q1 was designed to support multi-sensor systems such as surround view, and as such has the ability to synchronize sensors through the DS90UB954-Q1 and DS90UB960-Q1 hubs. The DS90UB953-Q1 serializer and companion deserializer incorporate an I2C-compatible interface. The I2Ccompatible interface allows programming of serializer or deserializer devices from a local host controller. In addition, the devices incorporate a bidirectional control channel (BCC) that allows communication between the serializer and deserializer as well as remote I2C slave devices. The bidirectional control channel (BCC) is implemented through embedded signaling in the high-speed forward channel (serializer to deserializer) combined with lower speed signaling in the reverse channel (deserializer to serializer). Through this interface, the BCC provides a mechanism to bridge I2C transactions across the serial link from one I2C bus to another. 7.2 Functional Block Diagram Vbias_internal CSI-2 DPHY Receiver FIFO Encoder/ Formatter Serializer Cable Driver DOUT+ DOUT- Internal AON Clock Clock Gen CLKIN CLK_OUT / IDX MODE Controller PDB I2C_SDA I2C_SCL I2C Controller 版权 © 2017–2018, Texas Instruments Incorporated FIFO Decode/ Encode Clock/Data Recovery BCC Receiver 15 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn 7.3 Feature Description The DS90UB953-Q1 FPD-Link III serializer is designed to support high-speed raw data sensors including 2-MP imagers at 60 fps as well as 4-MP, 30-fps cameras, satellite RADAR, LIDAR, and Time-of-Flight (ToF) sensors. The chip features a forward channel capable of up to 4.16 Gbps and an ultra-low latency 50-Mbps bidirectional control channel. The transmission of the forward channel, bidirectional control channel, and power is supported over coaxial (Power-over-Coax) or STP cables. The DS90UB953-Q1 features advanced data protection and diagnostic features to support ADAS and autonomous driving. Together with a companion deserializer, the DS90UB953-Q1 delivers precise multi-camera sensor clock and sensor synchronization. 7.3.1 CSI-2 Receiver The DS90UB953-Q1 receives CSI-2 video data from the Sensor. During CSI-2 operation, the D-PHY consists of a clock lane and one or more data lanes. The DS90UB953-Q1 is a Slave Device and only supports Unidirectional Lane in the Forward direction. Low Power Escape mode is not supported. 7.3.1.1 CSI-2 Receiver Operating Modes During normal operation a Data Lane will be in either Control or High-Speed mode. In High-Speed mode, the data transmission happens in a burst and starts and ends at a Stop state (LP-11). There is a transition state to take the D-PHY from a Normal mode to the Low-Power state. The sequence to enter High-Speed mode is: LP-11, LP-01, LP-00. After the sequence is entered, the Data Lane remains in High-Speed mode until a Stop state (LP-11) is received. 7.3.1.2 CSI-2 Receiver High-Speed Mode During high-speed data transmission, the digital D-PHY will enable termination signal to allow proper termination of the HS RX of the Analog D-PHY, and the LP RX should stay at LP-00 state. Both CSI-2 data lane and clock lane operate in the same manner. The DS90UB953-Q1 supports CSI-2 continuous clock lane mode where the clock lane remains in high-speed mode. 7.3.1.3 CSI-2 Protocol Layer There are two different types of CSI-2 packets: a short packet and a long packet. Short packets have information such as the Frame Start/ Line Start, and long packets carry the data after the frame start is asserted. 图 4 shows the structure of the CSI-2 protocol layer with short and long packets. The DS90UB953-Q1 supports 1, 2, and 4 lane configurations. DATA: Short Packet ST SP ET Long Packet LPS ST PH DATA Long Packet PF ET KEY: ST ± Start of Transmission ET ± End of Transmission LPS ± Low Power State LPS ST PH DATA Short Packet PF ET LPS ST SP ET PH ± Packet Header PF ± Packet Footer 图 4. CSI-2 Protocol Layer With Short and Long Packets 7.3.1.4 CSI-2 Short Packet The short packet provides frame or line synchronization. 图 5 shows the structure of a short packet. A short packet is identified by data types 0x00 to 0x0F. 16 版权 © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 VCX + ECC Data ID 16-Bit Short Packet Data Field Feature Description (接接下页) 32-bit SHORT PACKET (SH) Data Type (DT) = 0x00 ± 0x0F 图 5. CSI-2 Short Packet Structure 7.3.1.5 CSI-2 Long Packet 32-bit PACKET HEADER (PH) PACKET DATA: Length = Word Count (WC) * Data Word Width (8-bits). There are NO restrictions on the values of the data words 16-bit Checksum Data WC-1 Data WC-2 Data WC-3 Data WC-4 Data 3 Data 2 Data 1 Data 0 ECC 16-Bit Word Count Data ID A long packet consists of three elements: a 32-bit packet header (PH), an application-specific data payload with a variable number of 8-bit data words, and a 16-bit packet footer (PF). The packet header is further composed of three elements: an 8-bit data identifier, a 16-bit word count field, and an 8-bit ECC. The packet footer only has one element—a 16-bit checksum. 图 6 shows the structure of a long packet. 16-bit PACKET FOOTER (PF) 图 6. CSI-2 Long Packet Structure 表 1. CSI-2 Long Packet Structure Description PACKET PART FIELD NAME SIZE (BIT) VC / Data ID 8 Contains the virtual channel identifier and the data-type information. Word Count 16 Number of data words in the packet data. A word is 8 bits. ECC 8 ECC for data ID and WC field. Allows 1-bit error recovery and 2-bit error detection. Data Data WC × 8 Footer Checksum 16 Header DESCRIPTION Application-specific payload (WC words of 8 bits). 16-bit cyclic redundancy check (CRC) for packet data. 7.3.1.6 CSI-2 Errors and Detection 7.3.1.6.1 CSI-2 ECC Detection and Correction CSI-2 packet header contains 6-bit Error Correction Code (ECC). ECC code in the 32-bit long packet header can be corrected when there is a 1-bit error and detected when there is a 2-bit error. This feature is added to monitor the CSI-2 input for ECC 1-bit error correction. When ECC error is detected, ECC error detection register will be set and an alarm indicator bit can be sent to the Deserializer to indicate the ECC error has been detected. A register control can be used to either enable or disable the alarm. See Specifications. 版权 © 2017–2018, Texas Instruments Incorporated 17 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn 7.3.1.6.2 CSI-2 Check Sum Detection A CSI-2 long packet header contains a 16-bit check sum before the end of transmission. The DS90UB953-Q1 calculates the check sum of the incoming CSI-2 data. If a check sum error is detected, the check sum error status will be saved in the CSI_ERR_STATUS register (0x5D) and can also be forwarded to the deserializer through the bidirectional control channel. 7.3.1.6.3 D-PHY Error Detection DS90UB953-Q1 detect and reports SoT and SoT Sync errors. 7.3.1.6.4 CSI-2 Receiver Status For the Receive ports, several status functions can be tracked and monitored through register access. The status indications are available for error conditions as well as indications of change in line length measurements. These are available through the CSI_ERR_CNT (0x5C), CSI_ERR_STATUS (0x5D), CSI_ERR_DLANE01 (0x5E), CSI_ERR_DLANE23 (0x5F), and CSI_ERR_CLK_LANE (0x60) registers. 7.3.2 FPD-Link III Forward Channel Transmitter The DS90UB953-Q1 features a high-speed signal transmitter capable of driving signals at rates of up to 4.16 Gbps. 7.3.2.1 Frame Format The DS90UB953-Q1 formats the data into 40-bit long frames. Each frame is encoded to ensure DC balance and to ensure sufficient data line transitions. Each frame contains video payload data, I2C forward channel data, CRC information, framing information, and information regarding the state of the CSI-2 interface. 7.3.3 FPD-Link III Back Channel Receiver The FPD-Link III back channel receives an encoded back channel signal over the FPD-Link III interface. The back channel frame is a 30-bit frame that contains I2C commands and GPIO data. The back channel frame receives an encoded clock and data from the deserializer, thus the data bit rate is one-half the frequency of the highest frequency received. The back channel frequency is programmable for operation with compatible deserializers. The default setting is determined by the MODE strap pin. For operation with the DS90UB954-Q1 or DS90UB960-Q1, the back channel should be programmed for 50-Mbps operation in DS90UB953-Q1 Synchronous mode and programmed for 10Mbps operation for non-synchronous modes. 7.3.4 Serializer Status and Monitoring The DS90UB953-Q1 features enhanced FPD-Link III diagnostics, system monitoring, and Built-In Self Test capabilities. It monitors forward channel and back channel data for errors and reports them in the status registers. It also supports voltage and temperature measurement for system level diagnostics. The Built-In Self Test feature allows testing of the forward channel and back channel data transmissions without external data connections. 7.3.4.1 Forward Channel Diagnostics The DS90UB953-Q1 monitors the status of the forward channel link. The forward channel high-speed PLL lock status is reported in the HS_PLL_LOCK bit (Register 0x52[2]). When paired with the DS90UB954-Q1, the FPDLink III deserializer LOCK status is also reported in the RX_LOCK_DETECT bit (Register 0x52[6]). 7.3.4.2 Back Channel Diagnostics The DS90UB953-Q1 monitors the status of the back channel link. The back channel CRC errors are reported in the CRC_ERR bit (Register 0x52[1]). The number of CRC errors are stored in the CRC error counters and reported in the CRC_ERR_CNT1 (Register 0x55) and CRC_ERR_CNT2 (Register 0x56) registers. The CRC error counters are reset by setting the CRC_ERR_CLR (Register 0x49[3]) to 1. 18 版权 © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 When running the BIST function, the DS90UB953-Q1 reports if a BIST CRC error is detected in the BIST_CRC_ERR bit (Register 0x52[3]). The number of BIST errors are reported in the BIST_ERR_CNT field (Register 0x54). The BIST CRC error counter is reset by setting the BIST_CRC_ERR_CLR (Register 0x49[5]) to 1. 7.3.4.3 Voltage and Temperature Sensing The DS90UB953-Q1 supports voltage measurement and temperature measurement. The temperature and voltage sensors are both equipped with a 3-bit ADC. These sensors can be configured to monitor a signal and raise a flag when a signal goes outside of a set limit. For example, a voltage sensor can be used to monitor the 1.8-V line and raise a flag if the voltage goes above 1.85 V or below 1.75 V. This flag can then be transferred to the deserializer and can set an interrupt at the deserializer end of the link. In a similar manner, the temperature sensor will trigger an alarm bit when the internal temperature of DS90UB953-Q1 is outside the range. Both GPIO0 and GPIO1 can be configured to sense the voltage applied at their inputs. Table 32 through Table 38 cover the registers specific to this section. For a given voltage or temperature, the measurement accuracy is ±1 LSB. This means that for a given input voltage or temperature corresponding to the nearest value in 表 2 and 表 3, the resulting ADC output code will be accurate to the nearest ±1 code. 表 2. ADC Code vs Input Voltage GPIO VIN (V) CODE VIN < 0.85 000 0.85 < VIN < 0.90 001 0.90 < VIN < 0.95 010 0.95 < VIN < 1.00 011 1.00 < VIN < 1.05 100 1.05 < VIN < 1.10 101 1.10 < VIN < 1.15 110 1.15 < VIN 111 表 3. ADC Code vs Temperature TEMPERATURE (°C) CODE T < –30 000 –30 < T < –10 001 –10 < T < 15 010 15 < T < 35 011 35 < T < 55 100 版权 © 2017–2018, Texas Instruments Incorporated 55 < T < 75 101 75 < T < 100 110 100 < T 111 19 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn 7.3.4.3.1 Programming Example This section provides an example of configuring the DS90UB953-Q1 and DS90UB954-Q1 for monitoring the voltage on the DS90UB953-Q1 GPIO1 and setting an alarm which results in the INT pin being asserted on the DS90UB954-Q1. # DS90UB953-Q1 Settings WriteI2C(0x17,0x3E) WriteI2C(0x18,0xB2) WriteI2C(0x1A,0x62) WriteI2C(0x1D,0x3F) WriteI2C(0x1E,0x7F) # # # # # Enable Sensor, Select GPIO1 to sense Enable Sensor Gain Setting (Use Default) Set Sensor Upper and Lower Limits (Use Default) Enable Sensor Alarms Enable Sending Alarms over BCC # Register 0x57 readout (bits 2 and 3), indicates if the voltage on the GPIO1 is below or above the thresholds set in the register 0x1A. # DS90UB954-Q1 Settings WriteI2C(0x23,0x81) # Enable Interrupts, Enable Interrupts for the camera attached to RX0 WriteI2C(0x4C,0x01) # Enable Writes to RX0 registers WriteI2C(0xD8,0x08) # Interrupt on change in Sensor Status # Register 0x51 and 0x52 readouts indicate Sensor data. Register 0x24[7] bit readout indicates the Alarm bit. The alarm bit can be routed to GPIO3/INT through GPIO_PIN_CTL and GPIO_OUT_SRC registers. 7.3.4.4 Built-In Self Test An optional At-Speed Built-In Self Test (BIST) feature supports testing of the high-speed serial link and back channel without external data connections. This is useful in the prototype stage, equipment production, in-system test, and system diagnostics. BIST mode is enabled by BIST configuration register 0xB3[0] on the deserializer and should be run in the synchronous mode. When BIST is activated at the deserializer, a BIST enable signal is sent to the serializer through the back channel. The serializer outputs a continuous stream of a pseudo-random sequence and drives the link at speed. The deserializer detects the test pattern and monitors it for errors. The serializer also tracks errors indicated by the CRC fields in each back channel frame. While the lock indications are required to identify the beginning of proper data reception, the best indication of any link failures or data corruption is the content of the error counter in the BIST_ERR_COUNT register 0x57 for each RX port on the deserializer side. BIST mode is useful in the prototype stage, equipment production, in-system test, and system diagnostics. 7.3.5 FrameSync Operation When paired with compatible deserializers, any of the DS90UB953-Q1 GPIO pins can be use for frame synchronization. This feature is useful when multiple sensors are connected to a deserializer hub. A frame synchronization signal (FrameSync) can be sent through the back channel using any of the back channel GPIOs. The FrameSync signal arrives at the serializers with limited skew. 7.3.5.1 External FrameSync In External FrameSync mode, an external signal is input to the deserializer through one of the GPIO pins on the device. The external FrameSync signal may be propagated to one or more of the attached FPD-Link III Serializers through a GPIO signal in the back channel. The expected skew timing for external FrameSync mode is on the order of one back channel frame period or 600 ns when operating at 50 Mbps. Deserializer GPIOx GPIOx FPD-Link III Serializer FPD-Link III Serializer BC_GPIOx BC_GPIOx GPIOy External Frame Sync 图 7. External FrameSync 20 版权 © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 Enabling the external FrameSync mode is done on the deserializer side. Refer to the deserializer data sheet for more information. 7.3.5.2 Internally Generated FrameSync In Internal FrameSync mode, an internally generated FrameSync signal is sent to one or more of the attached FPD-Link III Serializers through a GPIO signal in the back channel. Deserializer GPIOx GPIOx Serializer Serializer FPD-Link III FPD-Link III BC_GPIOx BC_GPIOx FrameSync Generator 图 8. Internal FrameSync FrameSync operation is controlled by the deserializer registers. Refer to the deserializer data sheet for more information. 7.3.6 GPIO Support The DS90UB953-Q1 supports four pins, GPIO0 through GPIO3, which can be monitored, configured, and controlled through the I2C bus in registers 0x0D, 0x0E, and 0x53. These GPIOs are programmable for use in multiple situations. GPIO0 and GPIO1 have additional diagnostics functionality and may be programmed to sense external voltage levels. 7.3.6.1 GPIO Status The status HIGH or LOW of each GPIO pin 0 through 3 may be read through the GPIO_PIN_STS register 0x53. This register read operation provides the status of the GPIO pin independent of whether the GPIO pin is configured as an input or output. 7.3.6.2 GPIO Input Control Upon initialization, GPIO0 through GPIO3 are enabled as inputs by default. The GPIO_INPUT_CTRL (0x0E) register, bits 3:0, allows control of the input enable. If a GPIO_INPUT_CTRL[3:0] bit is set to 1, then the corresponding GPIO_INPUT_CTRL[7:4] bit must be set to 0. 7.3.6.3 GPIO Output Control Individual GPIO output control is programmable through the GPIO_INPUT_CTRL (0x0E) register, bits 7:4 Table 25. If a GPIO_INPUT_CTRL[7:4] bit is set to 1, then the corresponding GPIO_INPUT_CTRL[3:0] bit must be set to 0. 版权 © 2017–2018, Texas Instruments Incorporated 21 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn 7.3.6.4 Forward Channel GPIO The input on the DS90UB953-Q1 GPIO pins can be forwarded to compatible deserializers over the FPD-Link III interface. Up to four GPIOs are supported in the forward direction. The timing for the forward channel GPIO is dependent on the number of GPIOs assigned at the serializer. When a single GPIO input from the DS90UB953-Q1 serializer is linked to a compatible deserializer GPIO output the value is sampled every forward channel transmit frame. Two linked GPIO are sampled every two forward channel frames and three or four linked GPIO are sampled every five frames. The typical minimum latency for the GPIO remains consistent (approximately 225 ns) but as the information gets spread over multiple frames the jitter is typically increased on the order of the sampling period (number of forward channel frames). TI recommends that the user maintains a 4x oversampling ratio for linked GPIO throughput. For example, when operating in 4-Gbps synchronous mode with REFCLK = 25 MHz, the maximum recommended GPIO input frequency based on the number of GPIO linked over the forward channel is shown in 表 4. 表 4. Forward Channel GPIO Typical Timing NUMBER OF LINKED FORWARD CHANNEL GPIOs (FC_GPIO_EN) SAMPLING FREQUENCY (MHz) AT FPD-Link III LINE RATE = 4 Gbps MAXIMUM RECOMMENDED FORWARD CHANNEL GPIO FREQUENCY (MHz) TYPICAL JITTER (ns) 1 100 25 12 2 50 12.5 24 4 20 5 60 7.3.6.5 Back Channel GPIO When enabled as an output, each DS90UB953-Q1 GPIO pin can be programed to output remote data coming from the compatible deserializer using the LOCAL_GPIO_DATA register (0x0D). The maximum signal frequency that can be received over the FPD-Link III back channel is dependent on the DS90UB953-Q1 Clocking Mode as shown in 表 5. 表 5. Back Channel GPIO Typical Timing MAXIMUM RECOMMENDED BACK CHANNEL GPIO FREQUENCY (kHz) TYPICAL LATENCY (µs) TYPICAL JITTER (µs) 0.7 BACK CHANNEL RATE (Mbps) SAMPLING FREQUENCY (kHz) Synchronous Mode 50 1670 416 1.5 Non-Synchronous Modes 10 334 83.5 3.2 3 DVP Mode 2.5 83.5 20 12.2 12 DS90UB953-Q1 Clocking Mode 7.4 Device Functional Modes 7.4.1 Clocking Modes The DS90UB953-Q1 supports several clocking schemes, which are selected through the MODE pin. In the DS90UB953-Q1, the forward channel operates at a higher bandwidth than the requirement set by the video data being transported, and the forward channel data rate is set by a reference clock. The clocking mode determines what the device uses as its reference clock, and the most common configuration is Synchronous Mode, in which no local reference oscillator is required. See 表 6 for more information. The default mode of the DS90UB953-Q1 is set by the application of a bias on the MODE pin during power up. More information on setting operation modes can be found in MODE. 22 版权 © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 Device Functional Modes (接接下页) 表 6. Clocking Modes MODE DIVIDE REFERENCE SOURCE REF FREQUENCY (MHz) FC DATA RATE CSI BANDWIDTH ≤ N/A Back Channel (2) 23 - 26 f × 160 f × 128 f × 160 / HS_CLK_DIV × (M/N) N/A Back Channel (2) 11.5 - 13 f × 160 f × 128 f × 160 / HS_CLK_DIV × (M/N) CLKIN_DIV = 1, Back Channel (Half Rate) (3) 25 - 52 f × 80 f × 64 f × 80 / HS_CLK_DIV × (M/N) 50 - 104 f × 40 f × 32 f × 40 / HS_CLK_DIV × (M/N) Synchronous (Half-rate) NonSynchronous external clock CLKIN_DIV = 2, External clock (3) CLK_OUT (1) NonSynchronous Internal Clock CLKIN_DIV = 1, OSCCLK_SEL = 1 953 Internal Clock 48.4 - 51 f × 80 f × 64 N/A DVP External Clock Deserializer Mode: RAW10 CLKIN_DIV = 1, External clock 25 - 66.5 f × 28 f × 20 f × 28 / HS_CLK_DIV × (M/N) DVP External Clock Deserializer Mode: RAW12 HF CLKIN_DIV = 1, External clock 25 - 70 f × 28 f × 20 f × 28 / HS_CLK_DIV × (M/N) (1) (2) (3) HS_CLK_DIV typically should be set to either 16, 8, or 4 (default). The Back Channel is recovered from the FPD-Link III bidirectional control channel. Local reference clock source is not needed. Refer to the Deserializer data sheet for Back Channel frequency settings. Local reference clock source is needed. Provide a clock source to the DS90UB953-Q1's CLKIN pin. FPD-Link III 1920 x 1080 60fps Image Sensor Forward Channel (FC) MIPI CSI-2 DS90UB953 Serializer Internal AON Clock CLK_OUT Bi-directional Control Channel (BCC) DS90UB954 Deserializer MIPI CSI-2 Image Signal Processor (ISP) CLK GEN Clock REFCLK Optional for Non Sync external Clock Mode, Mandatory for DVP Mode 图 9. Clocking System Diagram 版权 © 2017–2018, Texas Instruments Incorporated 23 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn 7.4.1.1 Synchronous Mode Operation in synchronous mode offers the advantage that the receiver and all of the sensors in a multi-sensor system are locked to a common clock in the same clock domain, which reduces or eliminates the need for data buffering and resynchronization. The synchronous clocking mode also eliminates the cost, space, and potential failure point of a reference oscillator within the sensor module. In this mode, a clock is passed from the deserializer to the serializer through the FPD-Link III back channel, and the serializer is able to use this clock both as a reference clock for an attached image sensor, and as a reference clock for the link back to the deserializer (FPD-Link III forward channel). For operation in this mode, the DS90UB953-Q1 must be paired with a deserializer that can support this feature such as the DS90UB954-Q1 or DS90UB60-Q1. 7.4.1.2 Non-Synchronous Clock Mode In the Non-Synchronous Clock mode, the external reference clock is supplied to the serializer, and it uses this clock to derive the FPD-Link III forward channel and an external reference clock for an attached image sensor. When in CSI-2 mode, the CSI-2 interface may be synchronous to this clock. The CSI-2 rate must be lower than the line rate. For example, with a 50-MHz clock the FPD-Link III forward channel rate is 4 Gbps, the CSI-2 throughput must be ≤ 3.32 Gbps (See 表 6). 7.4.1.3 Non-Synchronous Internal Mode In the Non-Synchronous Internal Clocking mode, the serializer uses the internal Always on Clock (AON) as the reference clock for the forward channel. The OSCCLK_SEL select must be asserted 0x05[3]=1, to enable maximum data rate when using internal clock mode, and the CLK_OUT function is disabled. A separate reference is provided to the image sensor or ISP. When in CSI-2 mode, the CSI-2 interface may be synchronous to this clock. The CSI-2 rate must be lower than the line rate. For example, with the internal clock of 24.2 MHz the FPD-Link III forward channel rate is 3.872 Gbps, the CSI-2 throughput must be ≤ 3.1 Gbps (See 表 6). 7.4.1.4 DVP Backwards Compatibility Mode The DS90UB953-Q1 can be placed into DVP mode to be backwards compatible with the DS90UB934-Q1 or DS90UB914A-Q1. While the Mode should have been configured using the Mode pin on the DS90UB953-Q1, the register MODE_SEL register 0x03[2:0] can be used to verify or override the current mode. This field always indicates the MODE setting of the device. When bit 4 of this register is 0, this field is read-only and shows the Mode Setting. Mode is latched from strap value when PDB transitions LOW to HIGH and the value should read back 101 (0x5) if the resistive strap is set correctly to DVP External Clock Backwards Compatible Mode. Alternatively when bit 4 of this register is set to 1, the MODE field is read/write and can be programmed to 101 to assign the correct backwards compatible MODE. This is shown in Table 14. CSI-2 input data provided to the DS90UB953-Q1 must be synchronized to the input frequency applied to CLKIN when using DVP external clock mode. The PCLK frequency output from the DS90UB934-Q1 or DS90UB914AQ1 deserializer will also be related to CLKIN when in DVP external clock mode. See Backwards Compatibility Modes for Operation With Parallel Output Deserializers (SNLA270) for more information. 表 7. List of Registers Used for DVP Configuration REGISTER REGISTER NAME REGISTER DESCRIPTION Used to override and verify strapped value if necessary and configure for DVP with an external clock. 0X03 MODE_SEL 0X04 BC_MODE_SELE CT 0X10 DVP_CFG Allows configuration of data in DVP mode. This includes data types like long, YUV, and specified types. 0X11 DVP_DT Allows packets with certain data type regardless of RAW 10 or 12 mode if DVP_DT_MATCH_EN is asserted. Allows DVP mode overwrites to RAW 10 or RAW 12. 7.4.1.5 Configuring CLK_OUT When using the DS90UB953-Q1 in either Synchronous or Non-Synchronous external clock modes, CLK_OUT is intended as a reference clock for the image sensor. CLK_OUT functionality is disabled when operating in NonSynchronous internal clocking mode. The frequency of the external CLK_OUT is set by 公式 1 and 公式 2. 24 版权 © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 CLK_OUT FC u M HS_CLK_DIV u N where • FC is the forward channel data rate, and M, HS_CLK_DIV, and N are parameters set by registers 0x06 and 0x07 (1) SPACER FC HS_CLK_DIV 1.05 GHz (2) The PLL that generates CLK_OUT is a digital PLL, and as such, has very low jitter if the ratio N/M is an integer. If N/M is not an integer, then the jitter on the signal is approximately equal to HS_CLK_DIV/FC—so if it is not possible to have an integer ratio of N/M, it is best to select a smaller value for HS_CLK_DIV. If a particular CLK_OUT frequency such as 37.125 MHz is required for a system, selecting values of M=9, N=0xF2, and HS_CLK_DIV=4 results in an output frequency of 37.190 MHz and a frequency error of 0.175% with an associate jitter of approximately 1 ns. Alternately, the designer could use M=1, N=0x1E, HS_CLK_DIV=4 for CLK_OUT = 37.037 MHz, and a frequency error of 0.24% for less jitter. A third alternative would be to use M=1, N=0x1E, and HS_CLK_DIV=4, but rather than using a 25.000-MHz reference clock frequency (REFCLK) for the deserializer in synchronous mode, use a frequency of 25.059 MHz. The 2x reference then fed to the DS90UB953-Q1 from the deserializer back channel will allow generating CLK_OUT = 37.124 MHz with both low jitter and a low frequency error. 7.4.2 MODE The DS90UB953-Q1 can operate in one of four different modes. The user can apply the bias voltage to the MODE pin during power up to operate in Default mode. To set this voltage, a potential divider between VDDPLL and GND is used to apply the appropriate bias. This potential divider should be referenced to the potential on the VDDD pin. After power up, the MODE can be read or changed through register access. 1.8V RHIGH MODE RLOW DS90UB953-Q1 图 10. MODE Configuration 版权 © 2017–2018, Texas Instruments Incorporated 25 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn 表 8. Strap Configuration Mode Select MODE SELECT VTARGET VOLTAGE RANGE VTARGET STRAP VOLTAGE SUGGESTED STRAP RESISTORS (1% TOL) MODE NAME 0 Synchronous 0 0 0.133 x V(VDD) 0 OPEN 10 CSI-2 Synchronous mode – FPD-Link III Clock reference derived from deserializer. 2 Non-Synchronous External Clock 0.288 x V(VDD) 0.325 x V(VDD) 0.367 x V(VDD) 0.586 75 35.7 CSI-2 Non-synchronous clock – FPD-Link III Clock reference derived from external clock reference input on CLKIN pin. 3 Non-Synchronous Internal Clock 0.412 x V(VDD) 0.443 x V(VDD) 0.474 x V(VDD) 0.792 71.5 56.2 CSI-2 Non-synchronous – FPD-Link III Clock reference derived from internal AON clock. 5 (1) DVP Mode 0.642 x V(VDD) 0.673 x V(VDD) 0.704 x V(VDD) 1.202 39.2 78.7 DVP with External clock. (1) RATIO TYP RATIO MAX V(VDD) = 1.8 V RHIGH (kΩ ) RLOW (kΩ ) DESCRIPTION RATIO MIN The DS90UB934-Q1 and DS90UB914A-Q1 deserializers also contain a Mode pin (21). However, the mode pin on the deserializer determines the expected data format: RAW10, RAW12 LF, or RAW12 HF. Note that RAW12 LF is not supported on the DS90UB953Q1. 7.5 Programming 7.5.1 I2C Interface Configuration This serializer may be configured by the use of an I2C-compatible serial control bus. Multiple devices may share the serial control bus (up to two device addresses are supported). The device address is set through a resistor divider (RHIGH and RLOW – see 图 11) connected to the IDX pin. 7.5.1.1 CLK_OUT/IDX The CLK_OUT/IDX pin serves two functions. At power up, the voltage on the IDX pin is compared to VDD and the ratio sets various parameters for configuration of the DS90UB953-Q1. Once the DS90UB953-Q1 has been configured, the CLK_OUT/IDX pin switches over to a clock source, intended to provide a reference clock to the image sensor. A minimum load impedance at the CLK_OUT/IDX pin of 35 kΩ is required when using the CLK_OUT function. 7.5.1.1.1 IDX The IDX pin configures the control interface to one of two possible device addresses—either the 1.8-V or 3.3-V referenced I2C address. A pullup resistor and a pulldown resistor must be used to set the appropriate voltage on the IDX input pin (see ). The IDX resistor divider must be referred to Pin #25 (after the ferrite filter on the DS90UB953-Q1 pin side). 表 9. IDX Configuration Setting VTARGET VOLTAGE RANGE IDX 26 VIDX TARGET VOLTAGE SUGGESTED STRAP RESISTORS (1% TOL) I2C 7I2C 8-BIT BIT ADDRES ADDRE S SS V(I2C) (I2C I/O VOLTAGE) RATIO MIN RATIO TYP RATIO MAX VVDD = 1.8 V RHIGH (kΩ ) RLOW (kΩ ) 1 0 0 0.131 x V(VDD18) 0 Open 40.2 0x30 0x18 1.8 V 2 0.178 x V(VDD18) 0.214 x V(VDD18) 0.256 x V(VDD18) 0.385 180 47.5 0x32 0x19 1.8 V 3 0.537 x V(VDD18) 0.564 x V(VDD18) 0.591 x V(VDD18) 1.015 82.5 102 0x30 0x18 3.3 V 4 0.652 x V(VDD18) 0.679 x V(VDD18) 0.706 x V(VDD18) 1.223 68.1 137 0x32 0x19 3.3 V 版权 © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 Programming (接接下页) VI2C RPU RPU Host (Optional) SDA SDA SCL SCL Image Sensor DS90UB953-Q1 SDA SCL 1.8V RHIGH CLK_OUT/IDX Ref Clock In RLOW 图 11. Circuit to Bias IDX Pin 7.5.2 I2C Interface Operation The serial control bus consists of two signals: SCL and SDA. SCL is a Serial Bus Clock Input / Output signal and the SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external pullup resistor to VI2C, chosen to be either 1.8 V or 3.3 V. For the standard and fast I2C modes, a pullup resistor RPU = 4.7 kΩ is recommended, while a pullup resistor RPU = 470 Ω is recommended for the fast plus mode. However, the pullup resistor value may be additionally adjusted for capacitive loading and data rate requirements. The signals are either pulled High or driven Low. The IDX pin configures the control interface to one of two possible device addresses. A pullup resistor (RHIGH) and a pulldown resistor (RLOW) may be used to set the appropriate voltage on the IDX input pin. The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when SDA transitions Low while SCL is High. A STOP occurs when SDA transitions High while SCL is also HIGH. See 图 12. SDA SCL S START condition, or START repeat condition P STOP condition 图 12. Start and Stop Conditions To communicate with an I2C slave, the host controller (master) sends the slave address and listens for a response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is addressed correctly, the slave Acknowledges (ACKs) the master by driving the SDA bus low. If the address does not match a slave address of the device, the slave Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after every data byte is successfully received. When the master is reading data, the master ACKs 版权 © 2017–2018, Texas Instruments Incorporated 27 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn Programming (接接下页) after every data byte is received to let the slave know that the master wants to receive another data byte. When the master wants to stop reading, the master NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop condition. A READ is shown in 图 13 and a WRITE is shown in 图 14. 图 13. I2C Bus Read 图 14. I2C Bus Write Any I2C Master located at the serializer must support I2C clock stretching. For more information on I2C interface requirements and throughput considerations, refer to TI Application Note I2C Communication Over FPD-Link III with Bidirectional Control Channel (SNLA131). 7.5.3 I2C Timing The proxy master timing parameters are based on the internal reference clock. The I2C Master regenerates the I2C read or write access using timing controls in the registers 0x0B and 0x0C to regenerate the clock and data signals to meet the desired I2C timing in standard, fast, or fast-plus modes of operation. I2C Master SCL High Time is set in register 0x0B. This field configures the high pulse width of the SCL output when the serializer is the master on the local I2C bus. The default value is set to provide a minimum 5-µs SCL high time with the internal reference clock at 26.25 MHz including five additional oscillator clock periods or synchronization and response time. Units are 38.1 ns for the nominal oscillator clock frequency, giving Min_delay = 38.1 ns × (SCL_HIGH_TIME + 5). I2C Master SCL Low Time is set in register 0x0C. This field configures the low pulse width of the SCL output when the serializer is the master on the local deserializer I2C bus. This value is also used as the SDA setup time by the I2C Slave for providing data prior to releasing SCL during accesses over the BiDirectional Control Channel. The default value is set to provide a minimum 5-µs SCL high time with the reference clock at 26.25 MHz including five additional oscillator clock periods or synchronization and response time. Units are 38.1 ns for the nominal oscillator clock frequency, giving Min_delay = 38.1 ns × (SCL_HIGH_TIME + 5). See 表 10 example settings for Standard mode, Fast mode, and Fast Mode Plus timing. 表 10. Typical I2C Timing Register Settings I2C MODE SCL HIGH TIME SCL LOW TIME 0x0B NOMINAL DELAY 0x0C NOMINAL DELAY Standard 0x7F 5.03 µs 0x7F 5.03 µs Fast 0x13 0.914 µs 0x26 1.64 µs Fast - Plus 0x06 0.419 µs 0x0B 0.648 µs 7.6 Pattern Generation The DS90UB953-Q1 supports an internal pattern generation feature to provide a simple way to generate video test patterns for the CSI-2 transmitter outputs. Two types of patterns are supported: Reference Color Bar patterns and Fixed Color patterns accessed by the Pattern Generator page 0 in the indirect register set. See Indirect Access Registers for more information on internal registers. 28 版权 © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 Pattern Generation (接接下页) 7.6.1 Reference Color Bar Pattern The Reference Color Bar Patterns are based on the pattern defined in Appendix D of the mipi_CTS_for_DPHY_v1-1_r03 specification. The pattern is an 8 color bar pattern designed to provide high, low, and medium frequency outputs on the CSI-2 transmit data lanes. The CSI-2 Reference pattern provides 8 color bars by default with the following byte data for the color bars: X bytes of 0xAA (high-frequency pattern, inverted), X bytes of 0x33 (mid-frequency pattern), X bytes of 0xF0 (lowfrequency pattern, inverted), X bytes of 0x7F (lone 0 pattern), X bytes of 0x55 (high-frequency pattern), X bytes of 0xCC (mid-frequency pattern, inverted), X bytes of 0x0F (low-frequency pattern), and Y bytes of 0x80 (long 1 pattern). In most cases, Y will be the same as X. For certain data types, the last color bar may need to be larger than the others to properly fill the video line dimensions. The Pattern Generator is programmable with the following options: • Number of color bars (1, 2, 4, or 8) • Number of bytes per line • Number of bytes per color bar • CSI-2 DataType field and VC-ID • Number of active video lines per frame • Number of total lines per frame (active plus blanking) • Line period (possibly program in units of 10 ns) • Vertical front porch – number of blank lines prior to FrameEnd packet • Vertical back porch – number of blank lines following FrameStart packet The pattern generator relies on proper programming by software to ensure the color bar widths are set to multiples of the block (or word) size required for the specified DataType. For example, for RGB888, the block size is 3 bytes which also matches the pixel size. In this case, the number of bytes per color bar must be a multiple of 3. The Pattern Generator is implemented in the CSI-2 Transmit clock domain, providing the pattern directly to the CSI-2 Transmitter. The circuit generates the CSI-2 formatted data. 7.6.2 Fixed Color Patterns When programmed for Fixed Color Pattern mode, the Pattern Generator can generate a video image with a programmable fixed data pattern. The basic programming fields for image dimensions are the same as used with the Color Bar Patterns. When sending Fixed Color Patterns, the color bar controls allow alternating between the fixed pattern data and the bit-wise inverse of the fixed pattern data. The Fixed Color patterns assume a fixed block size for the byte pattern to be sent. The block size is programmable through a register and is designed to support most 8-bit, 10-bit, and 12-bit pixel formats. The block size should be set based on the pixel size converted to blocks that are an integer multiple of bytes. For example, an RGB888 pattern would consist of 3-byte pixels and therefore require a 3-byte block size. A 2x12-bit pixel image would also require 3-byte block size, while a 3x12-bit pixel image would require 9 bytes (2 pixels) to send an integer number of bytes. Sending a RAW10 pattern typically requires a 5-byte block size for 4 pixels, so 1x10-bit and 2x10-bit could both be sent with a 5-byte block size. For 3x10-bit, a 15-byte block size would be required. The Fixed Color patterns support block sizes up to 16 bytes in length, allowing additional options for patterns in some conditions. For example, an RGB888 image could alternate between four different pixels by using a twelvebyte block size. An alternating black and white RGB888 image could be sent with a block size of 6-bytes and setting the first three bytes to 0xFF and the next three bytes to 0x00. To support up to 16-byte block sizes, a set of sixteen registers are implemented to allow programming the value for each data byte. 7.6.3 Packet Generator Programming The information in this section provides details on how to program the Pattern Generator to provide a specific color bar pattern, based on datatype, frame size, and line size. 版权 © 2017–2018, Texas Instruments Incorporated 29 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn Pattern Generation (接接下页) Most basic configuration information is determined directly from the expected video frame parameters. The requirements should include the datatype, frame rate (frames per second), number of active lines per frame, number of total lines per frame (active plus blanking), and number of pixels per line. • PGEN_ACT_LPF – Number of active lines per frame • PGEN_TOT_LPF – Number of total lines per frame • PGEN_LSIZE – Video line length size in bytes. Compute based on pixels per line multiplied by pixel size in bytes • CSI-2 DataType field and VC-ID. • Optional: PGEN_VBP – Vertical back porch. This is the number of lines of vertical blanking following Frame Valid. • Optional: PGEN_VFP – Vertical front porch. This is the number of lines of vertical blanking preceding Frame Valid. • PGEN_LINE_PD – Line period in 10-ns units. Compute based on Frame Rate and total lines per frame. • PGEN_BAR_SIZE – Color bar size in bytes. Compute based on datatype and line length in bytes (see details below). 7.6.3.1 Determining Color Bar Size The color bar pattern should be programmed in units of a block or word size dependent on the datatype of the video being sent. The sizes are defined in the MIPI CSI-2 specification. For example, RGB888 requires a 3-byte block size which is the same as the pixel size. RAW10 requires a 5-byte block size which is equal to 4 pixels. RAW12 requires a 3-byte block size which is equal to 2 pixels. When programming the Pattern Generator, software should compute the required bar size in bytes based on the line size and the number of bars. For the standard 8 color bar pattern, that would require the following algorithm: • Select the desired datatype, and a valid length for that datatype (in pixels). • Convert pixels/line to blocks/line (by dividing by the number of pixels/block, as defined in the datatype specification). • Divide the blocks/line result by the number of color bars (8), giving blocks/bar. • Round result down to the nearest integer. • Convert blocks/bar to bytes/bar and program that value into the PGEN_BAR_SIZE register. As an alternative, the blocks/line can be computed by converting pixels/line to bytes/line and dividing by bytes/block. 30 版权 © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 Pattern Generation (接接下页) 7.6.4 Code Example for Pattern Generator #Patgen RGB888 1920x1080p30 Fixed 8 Colorbar WriteI2C(0xB0,0x00) # Indirect Pattern Gen Registers WriteI2C(0xB1,0x01) # PGEN_CTL WriteI2C(0xB2,0x01) WriteI2C(0xB1,0x02) # PGEN_CFG WriteI2C(0xB2,0x33) WriteI2C(0xB1,0x03) # PGEN_CSI_DI WriteI2C(0xB2,0x24) # RGB888 WriteI2C(0xB1,0x04) # PGEN_LINE_SIZE1 WriteI2C(0xB2,0x16) WriteI2C(0xB1,0x05) # PGEN_LINE_SIZE0 WriteI2C(0xB2,0x80) WriteI2C(0xB1,0x06) # PGEN_BAR_SIZE1 WriteI2C(0xB2,0x02) WriteI2C(0xB1,0x07) # PGEN_BAR_SIZE0 WriteI2C(0xB2,0xD0) WriteI2C(0xB1,0x08) # PGEN_ACT_LPF1 WriteI2C(0xB2,0x04) WriteI2C(0xB1,0x09) # PGEN_ACT_LPF0 WriteI2C(0xB2,0x38) WriteI2C(0xB1,0x0A) # PGEN_TOT_LPF1 WriteI2C(0xB2,0x04) WriteI2C(0xB1,0x0B) # PGEN_TOT_LPF0 WriteI2C(0xB2,0x65) WriteI2C(0xB1,0x0C) # PGEN_LINE_PD1 WriteI2C(0xB2,0x0B) WriteI2C(0xB1,0x0D) # PGEN_LINE_PD0 WriteI2C(0xB2,0x93) WriteI2C(0xB1,0x0E) # PGEN_VBP WriteI2C(0xB2,0x21) WriteI2C(0xB1,0x0F) # PGEN_VFP WriteI2C(0xB2,0x0A) Copyright © 2017–2018, Texas Instruments Incorporated 31 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn 7.7 Register Maps In the register definitions under the TYPE and DEFAULT heading, the following definitions apply: • R = Read only access • R/W = Read / Write access • R/RC = Read only access, Read to Clear • (R/W)/SC = Read / Write access, Self-Clearing bit • (R/W)/S = Read / Write access, Set based on strap pin configuration at start-up • LL = Latched Low and held until read • LH = Latched High and held until read • S = Set based on strap pin configuration at start-up 7.7.1 I2C Device ID Register Table 11. Device ID Register (Address 0x00) BIT FIELD 7:1 0 TYPE DEFAULT DESCRIPTION DEVICE_ID S, R/W S 7-bit I2C ID of Serializer. This field always indicates the current value of the I2C ID. When bit 0 of this register is 0, this field is read-only and shows the strapped ID. When bit 0 of this register is 1, this field is read/write and can be used to assign any valid I2C ID. SER_ID_OVERRIDE R/W 0x0 0: Device ID is from strap 1: Register I2C Device ID overrides strapped value 7.7.2 Reset Table 12. RESET_CTL Register (Address 0x01) BIT FIELD TYPE DEFAULT DESCRIPTION 7:3 RESERVED R/W 0x00 Reserved RESTART_AUTOLOAD (R/W)/SC 0x0 Restart ROM Auto-load Setting this bit to 1 causes a reload of the ROM. This bit is selfclearing. 0x0 Digital Reset 1 Resets the entire digital block including registers. This bit is selfclearing. 1: Reset 0: Normal operation 0x0 Digital Reset 0 Resets the entire digital block except registers. This bit is selfclearing. 1: Reset 0: Normal operation 2 1 DIGITAL_RESET_1 0 DIGITAL_RESET_0 (R/W)/SC (R/W)/SC 7.7.3 General Configuration Table 13. General_CFG (Address 0x02) BIT 32 FIELD TYPE DEFAULT DESCRIPTION 7 RESERVED R/W 0x0 Reserved 6 CONTS_CLK R/W 0x0 CSI-2 Clock Lane Configuration 0 : Non Continuous Clock 1 : Continuous Clock 5:4 CSI_LANE_SEL R/W 0x3 CSI-2 Data lane configuration 00: 1-lane configuration 01: 2-lane configuration 11: 4-lane configuration 3:2 RESERVED R/W 0x0 Reserved Copyright © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 Table 13. General_CFG (Address 0x02) (continued) BIT 1 0 FIELD TYPE DEFAULT DESCRIPTION CRC_TX_GEN_ ENABLE R/W 0x1 Transmitter CRC Generator 0: Disable 1: Enable S I2C Strap Mode This field indicates the I2C voltage level of the device. Upon device start-up, this field will display the I2C voltage level setting from the strapped IDX pin. This field is write capable and can be used to assign the I2C voltage level. Programming this bit to change the I2C voltage level should only be performed remotely over the back channel from a connected deserializer. 0: 3.3 V 1: 1.8 V I2C_STRAP_MODE S, R/W 7.7.4 Forward Channel Mode Selection Table 14. MODE_SEL (Address 0x03) BIT FIELD TYPE DEFAULT DESCRIPTION 7 RESERVED R/W 0x0 Reserved 6 RESERVED S, R S Reserved 5 RESERVED R/W 0x0 Reserved 4 MODE_OV R/W 0x0 0: Serializer Mode from the strapped MODE pin 1: Register Mode overrides strapped value 3 MODE_DONE R 0x0 Indicates MODE value has stabilized and been latched S This field always indicates the MODE setting of the device. When bit 4 of this register is 0, this field is read-only and shows the Mode Setting. When bit 4 of this register is 1, this field is read/write and can be used to assign MODE. Mode is latched from strap value when PDB transitions LOW to HIGH. Mode of operation: 000: CSI-2 Synchronous Mode 001: Reserved 010: CSI-2 Non-synchronous external clock Mode (Requires a local clock source) 011: CSI-2 Non-synchronous Internal AON Clock 101: DVP External Clock Backwards Compatible Mode (Requires local clock source) 2:0 MODE S, R/W 7.7.5 BC_MODE_SELECT Table 15. BC_MODE_SELECT (Address 0x04) BIT FIELD TYPE DEFAULT DESCRIPTION 7:3 RESERVED R/W 0x0 Reserved. 0x0 28-bit RAW 10 Mode operation Backwards compatible RAW 10 DVP mode (28-bit) is automatically configured by the Bidirectional Control Channel once RX lock has been detected. Software may overwrite the value, but must also set the DVP_MODE_OVER_EN to prevent overwriting by the Bidirectional Control Channel 2 MODE_OVERWRITE R/W _100m 1 MODE_OVERWRITE R/W _75m 0x0 28-bit RAW 12 Mode operation Backwards compatible RAW 12 HF DVP mode (28-bit) is automatically configured by the Bidirectional Control Channel once RX lock has been detected. Software may overwrite the value, but must also set the DVP_MODE_OVER_EN to prevent overwriting by the Bidirectional Control Channel 0 DVP_MODE_OVER_ EN 0x0 Prevent auto-loading of the backwards compatible DVP mode (28bit) operation by the Bidirectional Control Channel R/W Copyright © 2017–2018, Texas Instruments Incorporated 33 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn 7.7.6 PLL Clock Control Table 16. PLLCLK_CTRL Register (Address 0x05) BIT 7 6:4 3 2:0 FIELD TYPE DEFAULT DESCRIPTION RESERVED R/W 0x0 Reserved 0x0 CLKIN clock divide ratio to generate internal reference 3'b000 : CLKIN Div by 1 3'b001 : CLKIN Div by 2 3'b010 : CLKIN Div by 4 3'b011 : CLKIN Div by 8 3'b100 - 3'b111 : RESERVED CLKIN_DIV R/W OSCCLK_SEL R/W 0x0 Internally generated OSC clock reference when operating with NonSynchronous internal clock or external system clock not detected. 0: 24.2 MHz to 25.5 MHz, set for 2 Gbps line rate 1: 48.4 MHz to 51 MHz, set for 4 Gbps line rate mode RESERVED R/W 0x3 Reserved 7.7.7 Clock Output Control 0 The DS90UB953-Q1 provides an option for a programmable reference output clock to meet the system clock input requirements of various sensors. The control of the clock output frequency is set by the input divider and M value in register 0x06 and the N value in register 0x07. Table 17. CLKOUT_CTRL0 (Address 0x06) BIT 7:5 4:0 FIELD HS_CLK_DIV DIV_M_VAL TYPE R/W R/W DEFAULT DESCRIPTION 0x2 Clock source of M/N divider is based on the forward channel data rate divided by this register field. 000: Div by 1 001: Div by 2 010: Div by 4 011: Div by 8 100: Div by 16 0x01 M value for M/N divider for CLKOUT. CLKOUT can be programmed using the M/N ratio of an internal high-speed clock to generate a clock output based on the system sensor requirement. When selecting the M/N ratio, they should be set to yield the CLKOUT frequency less than 100 MHz. The M value should be ≥ 0. If set to 0, the design will get reset the M internally to default of 1. 7.7.8 Clock Output Control 1 The DS90UB953-Q1 provides option for a programmable reference output clock to meet the system clock input requirements of various sensors. The control of the clock output frequency is set by the input divider and M value in register 0x06 and the N value in register 0x07. Table 18. CLKOUT_CTRL1 (Address 0x07) BIT 7:0 34 FIELD DIV_N_VAL TYPE R/W DEFAULT DESCRIPTION 0x28 N value for M/N divider for CLKOUT. CLKOUT can be programmed using the M/N ratio of an internal high-speed clock to generate a clock output based on the system sensor requirement. When selecting the M/N ratio, they should be set to yield the CLKOUT frequency less than 100 MHz. N must be set to non-zero value. Copyright © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 7.7.9 Back Channel Watchdog Control Table 19. BCC_WATCHDOG (Address 0x08) BIT FIELD TYPE DEFAULT DESCRIPTION 7:1 BCC_WD_TIMER R/W 0x7F BCC_WD_TIMER sets the Bidirectional Control Channel Watchdog Timeout value in units of 2 milliseconds. This field should not be set to 0. The watchdog timer allows termination of a control channel transaction if it fails to complete within a programmed amount of time. 0 BCC_WD_TIMER_ DISABLE R/W 0x0 Disable Bidirectional Control Channel Watchdog Timer 1: Disables BCC Watchdog Timer operation 0: Enables BCC Watchdog Timer operation 7.7.10 I2C Control 1 Table 20. I2C_CONTROL1 (Address 0x09) BIT FIELD TYPE DEFAULT DESCRIPTION LCL_WRITE_ DISABLE R/W 0x0 Disable Remote Writes to Local Registers Setting this bit to a 1 prevents remote writes to local device registers from across the control channel. This prevents writes to the Serializer registers from an I2C master attached to the deserializer. Setting this bit does not affect remote access to I2C slaves at the Serializer. 6:4 I2C_SDA_HOLD R/W 0x1 Internal SDA Hold Time This field configures the amount of internal hold time provided for the SDA input relative to the SCL input. Units are 50 nanoseconds. 3:0 I2C_FILTER_DEPTH R/W 0xE I2C Glitch Filter Depth This field configures the maximum width of glitch pulses on the SCL and SDA inputs that are rejected. Units are 5 nanoseconds. 7 7.7.11 I2C Control 2 Table 21. I2C_CONTROL2 (Address 0x0A) BIT 7:4 3:2 1 0 FIELD DEFAULT DESCRIPTION 0x1 Remote Ack SDA Output Setup When a Control Channel (remote) access is active, this field configures setup time from the SDA output relative to the rising edge of SCL during ACK cycles. Setting this value increases setup time in units of 640 ns. The nominal output setup time value for SDA to SCL when this field is 0 is 80 ns. SDA_OUTPUT_DELAY R/W 0x0 SDA Output Delay This field configures additional delay on the SDA output relative to the falling edge of SCL. Setting this value increases output delay in units of 40 ns. Nominal output delay values for SCL to SDA are: 00 : 240 ns 01: 280 ns 10: 320 ns 11: 360 ns I2C_BUS_TIMER_ SPEEDUP 0x0 Speed up I2C Bus Watchdog Timer 1: Watchdog Timer expires after approximately 50 microseconds 0: Watchdog Timer expires after approximately 1 second. 0x0 Disable I2C Bus Watchdog Timer When the I2C Bus Watchdog Timer may be used to detect when the I2C bus is free or hung up following an invalid termination of a transaction. If SDA is high and no signalling occurs for approximately 1 second, the I2C bus is assumed free. If SDA is low and no signaling occurs, the device attempts to clear the bus by driving 9 clocks on SCL. SDA_OUTPUT_ SETUP I2C_BUS_TIMER_ DISABLE TYPE R/W R/W R/W Copyright © 2017–2018, Texas Instruments Incorporated 35 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn 7.7.12 SCL High Time Table 22. SCL_HIGH_TIME (Address 0x0B) BIT 7:0 FIELD SCL_HIGH_TIME TYPE R/W DEFAULT DESCRIPTION 0x7F I2C Master SCL High Time This field configures the high pulse width of the SCL output when the Serializer is the Master on the local I2C bus. Units are 38.1 ns for the nominal oscillator clock frequency of 26.25 MHz. The default value is set to provide a minimum 5-µs SCL high time with the internal oscillator clock running at 26.25 MHz. Delay includes 5 additional oscillator clock periods. Min_delay = 38.0952 ns × (SCL_HIGH_TIME + 5) 7.7.13 SCL Low Time Table 23. SCL_LOW_TIME (Address 0x0C) BIT 7:0 FIELD SCL_LOW_TIME TYPE R/W DEFAULT DESCRIPTION 0x7F I2C SCL Low Time This field configures the low pulse width of the SCL output when the Serializer is the Master on the local I2C bus. This value is also used as the SDA setup time by the I2C Slave for providing data prior to releasing SCL during accesses over the Bidirectional Control Channel. Units are 38.1 ns for the nominal oscillator clock frequency of 26.25 MHz. The default value is set to provide a minimum 5-µs SCL low time with the internal oscillator clock running at 26.25 MHz. Delay includes 5 additional clock periods. Min_delay = 38.0952 ns × (SCL_LOW_TIME + 5) 7.7.14 Local GPIO DATA Table 24. LOCAL_GPIO_DATA (Address 0x0D) BIT 7:4 3:0 FIELD GPIO_RMTEN GPIO_OUT_SRC TYPE R/W R/W DEFAULT DESCRIPTION 0xF Enable remote deserializer GPIO data on local GPIO Bit 7: Enable remote GPIO3 when this bit is set to 1 Bit 6: Enable remote GPIO2 when this bit is set to 1 Bit 5: Enable remote GPIO1 when this bit is set to 1 Bit 4: Enable remote GPIO0 when this bit is set to 1 0x0 GPIO Output Source This register sets the logical output of 4 GPIOs, GPIO_RMTEN must be disabled and GPIOx_OUT_EN must be enabled. Bit 3 write 0/1 on GPIO3 Bit 2 write 0/1 on GPIO2 Bit 1 write 0/1 on GPIO1 Bit 0 write 0/1 on GPIO0 7.7.15 GPIO Input Control Table 25. GPIO_INPUT_CTRL (Address 0x0E) BIT 36 FIELD TYPE DEFAULT DESCRIPTION 7 GPIO3_OUT_EN R/W 0x0 GPIO3 Output Enable 0: Disabled 1: Enabled 6 GPIO2_OUT_EN R/W 0x0 GPIO2 Output Enable 0: Disabled 1: Enabled 5 GPIO1_OUT_EN R/W 0x0 GPIO1 Output Enable 0: Disabled 1: Enabled Copyright © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 Table 25. GPIO_INPUT_CTRL (Address 0x0E) (continued) BIT FIELD TYPE DEFAULT DESCRIPTION 4 GPIO0_OUT_EN R/W 0x0 GPIO0 Output Enable 0: Disabled 1: Enabled 3 GPIO3_INPUT_EN R/W 0x1 GPIO3 Input Enable 0: Disabled 1: Enabled 2 GPIO2_INPUT_EN R/W 0x1 GPIO2 Input Enable 0: Disabled 1: Enabled 1 GPIO1_INPUT_EN R/W 0x1 GPIO1 Input Enable 0: Disabled 1: Enabled 0 GPIO0_INPUT_EN R/W 0x1 GPIO0 Input Enable 0: Disabled 1: Enabled 7.7.16 RESERVED Register Table 26. RESERVED (Address 0x0F) BIT FIELD TYPE DEFAULT DESCRIPTION 7:4 RESERVED R 0x0 Reserved. 3:0 RESERVED R/W 0x0 Reserved. 7.7.17 DVP_CFG Table 27. DVP_CFG (Address 0x10) BIT FIELD TYPE DEFAULT DESCRIPTION 7:5 RESERVED R/W 0x0 Reserved. 4 DVP_DT_ANY_EN R/W 0x0 When asserted, allows any packet with a Long data type (DT) packet through DVP. 3 DVP_DT_MATCH_E N R/W 0x0 When asserted, allows data type matching based on the value in the DVP_DT register. Note: When this bit is asserted, writes to the DVP_DT register are blocked. 2 DVP_DT_YUV_EN R/W 0x0 When asserted, allows YUV 10-bit DTs through DVP when mode_100m is also asserted (YUV 10-bit DTs are 0x19, 0x1d, and 0x1f). 1 DVP_FV_IN R/W 0x0 Invert Frame Valid Polarity. 0 DVP_LV_INV R/W 0x0 Invert Line Valid Polarity. 7.7.18 DVP_DT Table 28. DVP_DT (Address 0x11) BIT FIELD TYPE DEFAULT DESCRIPTION 7:6 RESERVED R/W 0x0 Reserved. 5:0 DVP_DT_MATCH_V AL R/W 0x0 When the DVP_CFG.dvp_dt_match_en is asserted, the DVP block will allow packets with this DT through regardless of the mode_75m or mode_100m setting. The DT value must be a Long DT value (either bit 5 or 4 must be set) for a match to occur. Copyright © 2017–2018, Texas Instruments Incorporated 37 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn 7.7.19 RESERVED Register Table 29. RESERVED (Address 0x12) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 RESERVED R/W 0x00 Reserved. 7.7.20 Force BIST Error Table 30. FORCE_BIST_ERR (Address 0x13) BIT FIELD TYPE DEFAULT DESCRIPTION 7 FORCE_FC_ERR SC 0x0 FORCE_ERR_CNT allows forcing a number of forward channel parity errors based on the value in FORCE_FC_CNT. When in BIST mode, the parity errors will be generated automatically upon entering BIST mode. When in normal operation this bit must be set to one to inject the parity errors. 0: Force Disabled 1: Force Enabled 6:0 FORCE_FC_CNT R/W 0x00 Force Error Count. Set this value to the desired number of forced parity errors. 7.7.21 Remote BIST Control Table 31. REMOTE_BIST_CTRL (Address 0x14) BIT FIELD TYPE DEFAULT DESCRIPTION 7:4 FORCE_ERR_CNT R/W 0x0 Set to force FC error based on the FORCE_ERR_CNT. 0: Force Disabled 1: Force Enabled LOCAL_BIST_EN R/W 0x0 Force DS90UB953-Q1 to Enter BIST Mode 3 2:1 0 BIST_CLOCK R/W 0x0 BIST clock source selection 00: External/System clock 01: 50 MHz internal clock 1X: 25 MHz internal clock REMOTE_BIST_EN R/W 0x0 Backwards-Compatible Remote BIST Enable Register 7.7.22 Sensor Voltage Gain Table 32. SENSOR_VGAIN (Address 0x15) BIT FIELD TYPE DEFAULT DESCRIPTION 7 RESERVED R/W 0x0 Reserved 6:0 VOLT_GAIN R/W 0x20 Voltage Sensor Gain Setting. VOLT_GAIN = (128 / REG_VALUE) 0x40 = Gain of 2 0x20 = Gain of 4 0x10 = Gain of 8 7.7.23 RESERVED Register Table 33. RESERVED (Address 0x16) 38 BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 RESERVED R/W 0x18 Reserved. Copyright © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 7.7.24 Sensor Control 0 Table 34. SENSOR_CTRL0 (Address 0x17) BIT FIELD TYPE DEFAULT DESCRIPTION 7:4 RESERVED R/W 0x0 Reserved 3:2 SENSOR_ENABLE R/W 0x3 Temperature and Voltage Sensor Enable 00: Disabled 11: Enabled 0x0 Enable GPIO 0/1 for input Voltage Sensor 0/1 measurement 00: No voltage sensing 01: GPIO0 Voltage Sensing 10: GPIO1 Voltage Sensing 11: GPIO0 and GPIO1 Voltage Sensing 1:0 SENSE_V_GPIO R/W 7.7.25 Sensor Control 1 Table 35. SENSOR_CTRL1 (Address 0x18) BIT 7 6:0 FIELD TYPE DEFAULT DESCRIPTION SENSE_GAIN_EN R/W 0x1 Enable Gain Setting of the Sensor RESERVED R/W 0x00 Reserved 7.7.26 Voltage Sensor 0 Thresholds Table 36. SENSOR_V0_THRESH (Address 0x19) BIT 7 6:4 3 2:0 FIELD TYPE DEFAULT DESCRIPTION RESERVED R/W 0x0 Reserved SENSE_V0_HI R/W 0x6 GPIO0/V0 sensor upper limit. When the GPIO0 is configured as a voltage sensor, and the voltage measured is above the SENSE_V0_HI, it triggers the V0_SENSOR_HI alarm in the SENSOR_STATUS register. RESERVED R/W 0x0 Reserved SENSE_V0_LO R/W 0x2 GPIO0/V0 sensor lower limit. When the GPIO0 is configured as a voltage sensor, and the voltage measured is below the SENSE_V0_LO, it triggers the V0_SENSOR_LOW alarm in the SENSOR_STATUS register. 7.7.27 Voltage Sensor 1 Thresholds Table 37. SENSOR_V1_THRESH (Address 0x1A) BIT 7 6:4 3 2:0 FIELD TYPE DEFAULT DESCRIPTION RESERVED R/W 0x0 Reserved SENSE_V1_HI R/W 0x6 GPIO1/V1 alarm upper limit. When the GPIO1 is configured as a voltage sensor, V1_MAX sets the upper limit for V1_SENSOR_HI status to be triggered RESERVED R/W 0x0 Reserved SENSE_V1_LO R/W 0x2 GPIO1/V1 alarm lower limit. When the GPIO1 is configured as a voltage sensor, V1_MIN sets the lower limit for V1_SENSOR_LOW status to be triggered 7.7.28 Temperature Sensor Thresholds Table 38. SENSOR_T_THRESH (Address 0x1B) BIT 7 FIELD TYPE DEFAULT DESCRIPTION RESERVED R/W 0x0 Reserved Copyright © 2017–2018, Texas Instruments Incorporated 39 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn Table 38. SENSOR_T_THRESH (Address 0x1B) (continued) BIT FIELD TYPE DEFAULT DESCRIPTION 6:4 SENSE_T_HI R/W 0x6 Temp sensor upper threshold. When the Temp sensor is enabled, and the temperature measured above the SENSE_T_HI limit, it triggers the T_SENSOR_HI alarm in SENSOR_STATUS. RESERVED R/W 0x0 Reserved SENSE_T_LO R/W 0x2 Temp sensor lower threshold. When the Temp sensor is enabled, and the temperature measured below the SENSE_T_LO limit, it triggers the T_SENSOR_LOW alarm in SENSOR_STATUS. 3 2:0 7.7.29 CSI-2 Alarm Enable Table 39. ALARM_CSI_EN (Address 0x1C) BIT FIELD TYPE DEFAULT DESCRIPTION 7:6 RESERVED R/W 0x0 Reserved 5 CSI_NO_FV_EN R/W 0x1 CSI-2 No Frame Valid Alarm Enable 1: Enabled 0: Disabled 4 DPHY_SYNC_ERR_ R/W EN 0x1 DPHY_SYNC_ERR Alarm Enable 1: Enabled 0: Disabled 3 DPHY_CTRL_ERR_ EN R/W 0x1 DPHY_CTRL_ERR Alarm Enable 1: Enabled 0: Disabled 2 CSI_ECC_2_EN R/W 0x1 CSI_ECC2 Alarm Enable 1: Enabled 0: Disabled 1 CSI_CHKSUM_ERR R/W _EN 0x1 CSI-2 Checksum Error Alarm Enable 1: Enabled 0: Disabled 0 CSI_LENGTH_ERR _EN 0x1 CSI-2 Length Error Alarm Enable 1: Enabled 0: Disabled R/W 7.7.30 Alarm Sense Enable Table 40. ALARM_SENSE_EN (Address 0x1D) BIT FIELD TYPE DEFAULT DESCRIPTION 7:6 RESERVED R/W 0x0 Reserved 5 T_OVER R/W 0x0 Enable Temp Sensor over the high limit alarm 4 T_UNDER R/W 0x0 Enable Temp Sensor under the low limit alarm 3 V1_OVER R/W 0x0 Enable Voltage1 Sensor over the high limit alarm 2 V1_UNDER R/W 0x0 Enable Voltage1 Sensor under the low limit alarm 1 V0_OVER R/W 0x0 Enable Voltage0 Sensor over the high limit alarm 0 V0_UNDER R/W 0x0 Enable Voltage0 Sensor under the low limit alarm 7.7.31 Back Channel Alarm Enable Table 41. ALARM_BC_EN (Address 0x1E) 40 BIT FIELD TYPE DEFAULT DESCRIPTION 7:2 RESERVED R/W 0x00 Reserved 1 CRC_ERR_EN R/W 0x0 Enable CRC_ERR alarm 0 LINK_DETECT_EN R/W 0x0 Enable LINK_DETECT alarm Copyright © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 7.7.32 RESERVED Register Table 42. RESERVED (Address 0x1F) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 RESERVED R/W 0x00 Reserved. 7.7.33 CSI-2 Polarity Select The CSI-2 Polarity Select register allows for changing P/N input polarity for each data lane. Table 43. CSI_POL_SEL (Address 0x20) BIT FIELD TYPE DEFAULT DESCRIPTION 7:5 RESERVED R 0x0 Reserved 4 POLARITY_CLK0 R/W 0x0 CSI-2 CLK lane 0 Polarity 3 POLARITY_D3 R/W 0x0 CSI-2 Data lane 3 Polarity 2 POLARITY_D2 R/W 0x0 CSI-2 Data lane 2 Polarity 1 POLARITY_D1 R/W 0x0 CSI-2 Data lane 1 Polarity 0 POLARITY_D0 R/W 0x0 CSI-2 Data lane 0 Polarity 7.7.34 CSI-2 LP Mode Polarity The CSI-2 LP Mode Polarity register allows for changing polarity for all clocks and data lanes in Low power mode. Table 44. CSI_LP_POLARITY (Address 0x21) BIT FIELD TYPE DEFAULT DESCRIPTION 7:5 RESERVED R/W 0x0 Reserved 4 POL_LP_CLK0 R/W 0x0 LP CSI-2 Clock lane Polarity 3:0 POL_LP_DATA R/W 0x0 LP CSI-2 Data lane Polarity 7.7.35 CSI-2 High-Speed RX Enable The CSI-2 High Speed RX Enable register is intended for system debugging and should be set to 0x00 for normal operation. Table 45. CSI_EN_HSRX (Address 0x22) BIT FIELD TYPE DEFAULT DESCRIPTION 7 RESERVED R 0x0 Reserved 6:0 RESERVED R/W 0x00 Reserved 7.7.36 CSI-2 Low Power Enable The CSI-2 Low Power Enable register is intended for system debugging. Table 46. CSI_EN_LPRX (Address 0x23) BIT FIELD TYPE DEFAULT DESCRIPTION 7 RESERVED R 0x0 Reserved 6:0 RESERVED R/W 0x00 Reserved Copyright © 2017–2018, Texas Instruments Incorporated 41 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn 7.7.37 CSI-2 Termination Enable The CSI-2 Termination Enable register is intended for system debugging. Table 47. CSI_EN_RXTERM (Address 0x24) BIT FIELD TYPE DEFAULT DESCRIPTION 7:4 RESERVED R/W 0x0 Reserved 3 EN_RXTERM_D3 R/W 0x0 Reserved 2 EN_RXTERM_D2 R/W 0x0 Reserved 1 EN_RXTERM_D1 R/W 0x0 Reserved 0 EN_RXTERM_D0 R/W 0x0 Reserved 7.7.38 RESERVED Register Table 48. RESERVED (Address 0x25) BIT FIELD TYPE DEFAULT DESCRIPTION 7 RESERVED R 0x0 Reserved. 6:4 RESERVED R/W 0x0 Reserved. 3 RESERVED R 0x0 Reserved. 2:0 RESERVED R/W 0x2 Reserved. 7.7.39 RESERVED Register Table 49. RESERVED (Address 0x26) BIT FIELD TYPE DEFAULT DESCRIPTION 7 RESERVED R 0x0 Reserved. 6:4 RESERVED R/W 0x0 Reserved. 3 RESERVED R 0x0 Reserved. 2:0 RESERVED R/W 0x0 Reserved. 7.7.40 RESERVED Register Table 50. RESERVED (Address 0x27) BIT FIELD TYPE DEFAULT DESCRIPTION 7:3 RESERVED R 0x00 Reserved. 2:0 RESERVED R/W 0x0 Reserved. 7.7.41 RESERVED Register Table 51. RESERVED (Address 0x28) BIT 42 FIELD TYPE DEFAULT DESCRIPTION 7 RESERVED R 0x0 Reserved. 6:4 RESERVED R/W 0x0 Reserved. 3 RESERVED R 0x0 Reserved. 2:0 RESERVED R/W 0x7 Reserved. Copyright © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 7.7.42 RESERVED Register Table 52. RESERVED (Address 0x29) BIT FIELD TYPE DEFAULT DESCRIPTION 7 RESERVED R 0x0 Reserved. 6:4 RESERVED R/W 0x3 Reserved. 3 RESERVED R 0x0 Reserved. 2:0 RESERVED R/W 0x3 Reserved. 7.7.43 RESERVED Register Table 53. RESERVED (Address 0x2A) BIT FIELD TYPE DEFAULT DESCRIPTION 7 RESERVED R 0x0 Reserved. 6:4 RESERVED R/W 0x0 Reserved. 3 RESERVED R 0x0 Reserved. 2:0 RESERVED R/W 0x1 Reserved. 7.7.44 RESERVED Register Table 54. RESERVED (Address 0x2B-0x2D) BIT FIELD TYPE DEFAULT DESCRIPTION 7 RESERVED R 0x0 Reserved. 6:4 RESERVED 0x0 Reserved. 3 RESERVED 0x0 Reserved. 2:0 RESERVED 0x0 Reserved. R 7.7.45 RESERVED Register Table 55. RESERVED (Address 0x2E-0x30) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 RESERVED R/W 0x00 Reserved. 7.7.46 CSI-2 Packet Header Control Table 56. CSI_PKT_HDR_TINIT_CTRL (Address 0x31) BIT FIELD TYPE DEFAULT DESCRIPTION 7:6 PKT_HDR_SEL_ VC R/W 0x0 For interleaved VC packet select the VC ID to display the packet header. This is effective only if bit4 is set high (PKT_HDR_VCI_ENABLE) 5 PKT_HDR_ CORRECTED R/W 0x1 1: Displays the corrected CSI-2 packet header (in case of error) sent to the receiver 0: Displays the received CSI-2 packet header from imager 4 PKT_HDR_VCI_ ENABLE R/W 0x0 Enable the CSI-2 packet header selection based on VC for interleaved mode. For interleaved VC packet set this bit to record the packet headers for each VC. For regular data packet ignore this bit. 3 RESERVED R/W 0x0 Reserved Copyright © 2017–2018, Texas Instruments Incorporated 43 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn Table 56. CSI_PKT_HDR_TINIT_CTRL (Address 0x31) (continued) BIT 2:0 FIELD TINIT_TIME TYPE R/W DEFAULT DESCRIPTION 0x0 CSI-2 Initial Time after power up. Any LP control data are ignored during this time for all CSI-2 lanes. 000 = 100 µs 001 = 200 µs 010 = 300 µs 111 = 800 µs and so forth 7.7.47 Back Channel Configuration Table 57. BCC_CONFIG (Address 0x32) BIT FIELD TYPE DEFAULT DESCRIPTION 7 I2C_PASS_ THROUGH_ALL R/W 0x0 I2C Pass-Through All Transactions 0: Disabled 1: Enabled 6 I2C_PASS_ THROUGH R/W 0x0 I2C Pass-Through to Deserializer if decode matches 0: Pass-Through Disabled 1: Pass-Through Enabled 5 AUTO_ACK_ALL R/W 0x0 Automatically Acknowledge all I2C writes independent of the forward channel lock state or status of the remote Acknowledge 1: Enable 0: Disable 4 RESERVED R/W 0x0 Reserved 3 RX_PARITY_ CHECKER_ ENABLE R/W 0x1 Parity Checker Enable 0: Disable 1: Enable 2 RESERVED R/W 0x0 Reserved 1 RESERVED R/W 0x0 Reserved 0 RESERVED R/W 0x1 Reserved 7.7.48 Datapath Control 1 Table 58. DATAPATH_CTL1 (Address 0x33) BIT FIELD TYPE DEFAULT DESCRIPTION 7:3 RESERVED R/W 0x00 Reserved 0x1 DCA CRC Enable If set to a 1, the Forward Channel sends a CRC as part of the DCA sequence. The DCA CRC protects the first 8 bytes of the DCA sequence. The CRC is sent as the 9th byte. 0x0 Forward Channel GPIO Enable Configures the number of enabled forward channel GPIOs 00: GPIOs disabled 01: One GPIO 10: Two GPIOs 11: Four GPIOs 2 DCA_CRC_EN 1:0 FC_GPIO_EN R/W R/W 7.7.49 RESERVED Register Table 59. RESERVED (Address 0x34) 44 BIT FIELD TYPE DEFAULT DESCRIPTION 7:4 RESERVED R/W 0x0 Reserved. 3 RESERVED R/W 0x0 Reserved. Copyright © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 Table 59. RESERVED (Address 0x34) (continued) BIT FIELD TYPE DEFAULT DESCRIPTION 2 RESERVED R/W 0x0 Reserved. 1:0 RESERVED R/W 0x0 Reserved. 7.7.50 Remote Partner Capabilities 1 Table 60. REMOTE_PAR_CAP1 (Address 0x35) BIT FIELD TYPE DEFAULT DESCRIPTION 7 FREEZE_DES_ CAP R/W 0x0 Freeze Partner Capabilities Prevent auto-loading of the Partner Capabilities by the Bidirectional Control Channel. The Capabilities are frozen at the values written in registers 0x1E and 0x1F. 6 RESERVED R/W 0x0 Reserved 0x0 Link BIST Enable This bit indicates the remote partner is requesting BIST operation over the FPD-Link III interface. This field is automatically configured by the Bidirectional Control Channel once back channel link has been detected. Software may overwrite this value, but must also set the FREEZE_DES_CAP bit to prevent overwriting by the Bidirectional Control Channel. 0x0 Remote Partner Multi-Port capable 0 : Remote partner is a single-port deserializer device 1 : Remote partner is a multi-port deserializer device This field is automatically configured by the Bidirectional Control Channel once back channel link has been detected. Software may overwrite this value, but must also set the FREEZE_DES_CAP bit to prevent overwriting by the Bidirectional Control Channel. 0x0 Remote Partner port number When connected to a multi-port device, this field indicates the port number to which the Serializer is connected. This field is automatically configured by the Bidirectional Control Channel once back channel link has been detected. Software may overwrite this value, but must also set the FREEZE_DES_CAP bit to prevent overwriting by the Bidirectional Control Channel. 5 4 3:0 BIST_EN MPORT PORT_NUM R/W R/W R/W 7.7.51 RESERVED Register Table 61. RESERVED (Address 0x36) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 RESERVED R/W 0x00 Reserved. 7.7.52 Partner Deserializer ID Table 62. DES_ID (Address 0x37) BIT FIELD TYPE DEFAULT DESCRIPTION 7:1 DES_ID R/W 0x3D Remote Deserializer ID This field is normally loaded automatically from the remote Deserializer. FREEZE_ DEVICE_ID R/W 0x0 Freeze Deserializer Device ID Prevent auto-loading of the Deserializer Device ID from the back channel. The ID is frozen at the value written. 0 Copyright © 2017–2018, Texas Instruments Incorporated 45 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn 7.7.53 RESERVED Register Table 63. RESERVED (Address 0x38) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 RESERVED R/W 0x00 Reserved. 7.7.54 Slave 0 ID Table 64. SLAVE_ID_0 (Address 0x39) BIT FIELD TYPE DEFAULT DESCRIPTION 7:1 SLAVE_ID_0 R/W 0x00 7-bit Remote Slave Device ID 0 Configures the physical I2C address of the remote I2C Slave device attached to the remote Deserializer. If an I2C transaction is addressed to the Slave Alias ID0, the transaction is remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. 0 RESERVED R 0x0 Reserved 7.7.55 Slave 1 ID Table 65. SLAVE_ID_1 (Address 0x3A) BIT FIELD TYPE DEFAULT DESCRIPTION 7:1 SLAVE_ID_1 R/W 0x00 7-bit Remote Slave Device ID 1 Configures the physical I2C address of the remote I2C Slave device attached to the remote Deserializer. If an I2C transaction is addressed to the Slave Alias ID1, the transaction is remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer 0 RESERVED R 0x0 Reserved 7.7.56 Slave 2 ID Table 66. SLAVE_ID_2 (Address 0x3B) BIT FIELD TYPE DEFAULT DESCRIPTION 7:1 SLAVE_ID_2 R/W 0x00 7-bit Remote Slave Device ID 2 Configures the physical I2C address of the remote I2C Slave device attached to the remote Deserializer. If an I2C transaction is addressed to the Slave Alias ID2, the transaction is remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. 0 RESERVED R 0x0 Reserved 7.7.57 Slave 3 ID Table 67. SLAVE_ID_3 (Address 0x3C) BIT 46 FIELD TYPE DEFAULT DESCRIPTION 7:1 SLAVE_ID_3 R/W 0x00 7-bit Remote Slave Device ID 3 Configures the physical I2C address of the remote I2C Slave device attached to the remote Deserializer. If an I2C transaction is addressed to the Slave Alias ID3, the transaction is remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. 0 RESERVED R 0x0 Reserved Copyright © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 7.7.58 Slave 4 ID Table 68. SLAVE_ID_4 (Address 0x3D) BIT FIELD TYPE DEFAULT DESCRIPTION 7:1 SLAVE_ID_4 R/W 0x00 7-bit Remote Slave Device ID 4 Configures the physical I2C address of the remote I2C Slave device attached to the remote Deserializer. If an I2C transaction is addressed to the Slave Alias ID4, the transaction is remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. 0 RESERVED R 0x0 Reserved 7.7.59 Slave 5 ID Table 69. SLAVE_ID_5 (Address 0x3E) BIT FIELD TYPE DEFAULT DESCRIPTION 7:1 SLAVE_ID_5 R/W 0x00 7-bit Remote Slave Device ID 5 Configures the physical I2C address of the remote I2C Slave device attached to the remote Deserializer. If an I2C transaction is addressed to the Slave Alias ID5, the transaction is remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. 0 RESERVED R 0x0 Reserved 7.7.60 Slave 6 ID Table 70. SLAVE_ID_6 (Address 0x3F) BIT FIELD TYPE DEFAULT DESCRIPTION 7:1 SLAVE_ID_6 R/W 0x00 7-bit Remote Slave Device ID 6 Configures the physical I2C address of the remote I2C Slave device attached to the remote Deserializer. If an I2C transaction is addressed to the Slave Alias ID6, the transaction is remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. 0 RESERVED R 0x0 Reserved 7.7.61 Slave 7 ID Table 71. SLAVE_ID_7 (Address 0x40) BIT FIELD TYPE DEFAULT DESCRIPTION 7:1 SLAVE_ID_7 R/W 0x00 7-bit Remote Slave Device ID 7 Configures the physical I2C address of the remote I2C Slave device attached to the remote Deserializer. If an I2C transaction is addressed to the Slave Alias ID7, the transaction is remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. 0 RESERVED R 0x0 Reserved 7.7.62 Slave 0 Alias Table 72. SLAVE_ID_ALIAS_0 (Address 0x41) BIT FIELD 7:1 SLAVE_ID_ ALIAS_0 TYPE R/W Copyright © 2017–2018, Texas Instruments Incorporated DEFAULT DESCRIPTION 0x00 7-bit Remote Slave Device Alias ID 0 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Deserializer. The transaction is remapped to the address specified in the Slave ID0 register. A value of 0 in this field disables access to the remote I2C Slave. 47 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn Table 72. SLAVE_ID_ALIAS_0 (Address 0x41) (continued) BIT 0 FIELD SLAVE_AUTO_ ACK_0 TYPE R/W DEFAULT DESCRIPTION 0x0 Automatically Acknowledge all I2C writes to the remote Slave 0 independent of the forward channel lock state or status of the remote Deserializer Acknowledge 1: Enable 0: Disable This is intended for debugging only and not recommended for normal operation. 7.7.63 Slave 1 Alias Table 73. SLAVE_ID_ALIAS_1 (Address 0x42) BIT FIELD 7:1 SLAVE_ID_ALIAS _1 0 SLAVE_AUTO_ ACK_1 TYPE R/W R/W DEFAULT DESCRIPTION 0x00 7-bit Remote Slave Device Alias ID 1 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Deserializer. The transaction is remapped to the address specified in the Slave ID1 register. A value of 0 in this field disables access to the remote I2C Slave. 0x0 Automatically Acknowledge all I2C writes to the remote Slave 1 independent of the forward channel lock state or status of the remote Deserializer Acknowledge 1: Enable 0: Disable This is intended for debugging only and not recommended for normal operation. 7.7.64 Slave 2 Alias Table 74. SLAVE_ID_ALIAS_2 (Address 0x43) BIT 7:1 0 FIELD SLAVE_ID_ALIAS _2 SLAVE_AUTO_ ACK_2 TYPE R/W R/W DEFAULT DESCRIPTION 0x00 7-bit Remote Slave Device Alias ID 2 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Deserializer. The transaction is remapped to the address specified in the Slave ID2 register. A value of 0 in this field disables access to the remote I2C Slave. 0x0 Automatically Acknowledge all I2C writes to the remote Slave 2 independent of the forward channel lock state or status of the remote Deserializer Acknowledge 1: Enable 0: Disable This is intended for debugging only and not recommended for normal operation. 7.7.65 Slave 3 Alias Table 75. SLAVE_ID_ALIAS_3 (Address 0x44) BIT FIELD 7:1 SLAVE_ID_ALIAS _3 0 48 SLAVE_AUTO_ ACK_3 TYPE R/W R/W DEFAULT DESCRIPTION 0x00 7-bit Remote Slave Device Alias ID 3 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Deserializer. The transaction is remapped to the address specified in the Slave ID3 register. A value of 0 in this field disables access to the remote I2C Slave. 0x0 Automatically Acknowledge all I2C writes to the remote Slave 3 independent of the forward channel lock state or status of the remote Deserializer Acknowledge 1: Enable 0: Disable This is intended for debugging only and not recommended for normal operation. Copyright © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 7.7.66 Slave 4 Alias Table 76. SLAVE_ID_ALIAS_4 (Address 0x45) BIT 7:1 0 FIELD SLAVE_ID_ALIAS _4 SLAVE_AUTO_ ACK_4 TYPE R/W R/W DEFAULT DESCRIPTION 0x00 7-bit Remote Slave Device Alias ID 4 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Deserializer. The transaction is remapped to the address specified in the Slave ID4 register. A value of 0 in this field disables access to the remote I2C Slave. 0x0 Automatically Acknowledge all I2C writes to the remote Slave 4 independent of the forward channel lock state or status of the remote Deserializer Acknowledge 1: Enable 0: Disable This is intended for debugging only and not recommended for normal operation. 7.7.67 Slave 5 Alias Table 77. SLAVE_ID_ALIAS_5 (Address 0x46) BIT FIELD 7:1 SLAVE_ID_ALIAS _5 0 SLAVE_AUTO_ ACK_5 TYPE R/W R/W DEFAULT DESCRIPTION 0x00 7-bit Remote Slave Device Alias ID 5 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Deserializer. The transaction is remapped to the address specified in the Slave ID5 register. A value of 0 in this field disables access to the remote I2C Slave. 0x0 Automatically Acknowledge all I2C writes to the remote Slave 5 independent of the forward channel lock state or status of the remote Deserializer Acknowledge 1: Enable 0: Disable This is intended for debugging only and not recommended for normal operation. 7.7.68 Slave 6 Alias Table 78. SLAVE_ID_ALIAS_6 (Address 0x47) BIT 7:1 0 FIELD SLAVE_ID_ALIAS _6 SLAVE_AUTO_ ACK_6 TYPE R/W R/W Copyright © 2017–2018, Texas Instruments Incorporated DEFAULT DESCRIPTION 0x00 7-bit Remote Slave Device Alias ID 6 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Deserializer. The transaction is remapped to the address specified in the Slave ID6 register. A value of 0 in this field disables access to the remote I2C Slave. 0x0 Automatically Acknowledge all I2C writes to the remote Slave 6 independent of the forward channel lock state or status of the remote Deserializer Acknowledge 1: Enable 0: Disable This is intended for debugging only and not recommended for normal operation. 49 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn 7.7.69 Slave 7 Alias Table 79. SLAVE_ID_ALIAS_7 (Address 0x48) BIT 7:1 0 FIELD TYPE SLAVE_ID_ALIAS _7 R/W SLAVE_AUTO_ ACK_7 R/W DEFAUL DESCRIPTION T 0x00 7-bit Remote Slave Device Alias ID 7 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Deserializer. The transaction is remapped to the address specified in the Slave ID7 register. A value of 0 in this field disables access to the remote I2C Slave. 0x0 Automatically Acknowledge all I2C writes to the remote Slave 7 independent of the forward channel lock state or status of the remote Deserializer Acknowledge 1: Enable 0: Disable This is intended for debugging only and not recommended for normal operation. 7.7.70 Back Channel Control Table 80. BC_CTRL (Address 0x49) BIT FIELD TYPE DEFAUL T DESCRIPTION 7:6 RESERVED R 0x0 Reserved 5 BIST_CRC_ERR _CLR (R/W)/SC 0x0 Clear BIST CRC error counter 0: Disable clear 1: Enable Clear 4 RESERVED R/W Reserved 3 CRC_ERR_CLR (R/W)/SC 0x0 Clear CRC error 0: Disable clear 1: Enable clear LINK_DET_ TIMER R/W TX-RX link detect timer val 2:0 0x0 0x0 7.7.71 Revision ID Table 81. REV_MASK_ID (Address 0x50) BIT FIELD TYPE DEFAULT DESCRIPTION 7:4 REVISION_ID R 0x2 Revision ID 3:0 MASK_ID R 0x0 Mask ID 7.7.72 Device Status Table 82. Device STS (Address 0x51) FIELD TYPE DEFAUL DESCRIPTION T 7 CFG_CKSUM_ STS R 0x0 Config Checksum Passed This bit is set following initialization if the Configuration data in the eFuse ROM had a valid checksum 6 CFG_INIT_DONE R 0x0 Power-up initialization complete This bit is set after Initialization is complete. Configuration from eFuse ROM has completed. RESERVED 0x00 Reserved BIT 5:0 50 R Copyright © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 7.7.73 General Status Table 83. GENERAL_STATUS (Address 0x52) BIT FIELD TYPE DEFAULT DESCRIPTION 7 RESERVED R 0x0 Reserved 6 RX_LOCK_ DETECT R 0x0 Deserializer LOCK status This bit indicates the LOCK status of the Deserializer. 5 RESERVED R 0x0 Reserved 4 LINK_LOST_ FLAG R 0x0 Back Channel Link lost Status changed This bit is set if a change in BC LINK DET lost status has been detected. This bit is cleared upon read of CRC ERR CLR register or HS PLL loses lock. 3 BIST_CRC_ERR R 0x0 BIST Error is detected. The BIST_ERR_CNT register contain the number of Back Channel BIST errors. 2 HS_PLL_LOCK R 0x1 Forward Channel High speed PLL lock flag 1 CRC_ERR R 0x0 Back Channel CRC error detected This bit is set when the back channel errors detected when BC LINK DET is asserted. This bit is cleared upon read of CRC_ERR_CLR register. 0 LINK_DET R 0x1 Back Channel Link detect This bit is set when BC link is valid. 7.7.74 GPIO Pin Status Table 84. GPIO_PIN_STS (Address 0x53) BIT FIELD TYPE DEFAULT DESCRIPTION 7:4 RESERVED R 0x0 Reserved 0x0 GPIO Pin Status This register reads the current values on GPIO pins. Bit 3 reads GPIO3 pin status Bit 2 reads GPIO2 pin status Bit 1 reads GPIO1 pin status Bit 0 reads GPIO0 pin status 3:0 GPIO_STS R 7.7.75 BIST Error Count Table 85. BIST_ERR_CNT (Address 0x54) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 BIST_BC_ ERRCNT R 0x00 CRC error count in BIST mode. 7.7.76 CRC Error Count 1 Table 86. CRC_ERR_CNT1 (Address 0x55) BIT FIELD 7:0 CRC_ERR_CNT1 R TYPE DEFAULT DESCRIPTION 0x00 CRC Error count (LSB) 7.7.77 CRC Error Count 2 Table 87. CRC_ERR_CNT2 (Address 0x56) BIT FIELD TYPE 7:0 CRC_ERR_CNT2 R DEFAULT DESCRIPTION 0x00 CRC Error count (MSB) Copyright © 2017–2018, Texas Instruments Incorporated 51 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn 7.7.78 Sensor Status Table 88. SENSOR_STATUS (Address 0x57) BIT FIELD TYPE DEFAULT DESCRIPTION 7:6 RESERVED R 0x0 Reserved 5 T_SENSOR_HI R 0x0 When set, this bit indicates that GPIO0 Sensor is above SENSE_T_HI limit. This bit is cleared upon read. 4 T_SENSOR_ LOW R 0x0 When set, this bit indicates that GPIO0 Sensor is below SENSE_T_LO limit. This bit is cleared upon read. 3 V1_SENSOR_ HI R 0x0 When set, this bit indicates that GPIO1 input is above SENSE_V1_HI limit. This bit is cleared upon read. 2 V1_SENSOR_ LOW R 0x0 When set, this bit indicates that GPIO1 input is below SENSO_V1_LO limit. This bit is cleared upon read. 1 V0_SENSOR_ HI R 0x0 When set, this bit indicates that GPIO0 input is above SENSE_V0_HI limit. This bit will be cleared upon read. 0 V0_SENSOR_ LOW R 0x0 When set, this bit indicates that GPIO0 input is below SENSO_V0_LO limit. This bit will be cleared upon read. 7.7.79 Sensor V0 Table 89. SENSOR_V0 (Address 0x58) BIT 7 6:4 3 2:0 FIELD TYPE DEFAULT DESCRIPTION RESERVED R/W 0x0 Reserved VOLTAGE_ SENSOR_V0_ MAX RC 0x0 GPIO0 Voltage sensor max reading when the GPIO0 voltage is above SENSE_V0_HI limit. This bit is cleared upon read. 0 indicates alarm has not been triggered. RESERVED R/W 0x0 Reserved VOLTAGE_ SENSOR_V0_ MIN RC 0x7 GPIO0 Voltage sensor min reading when GPIO0 voltage is below SENSE_V0_LO limit. This bit is cleared upon read. 7 indicates alarm has not been triggered. 7.7.80 Sensor V1 Table 90. SENSOR_V1 (Address 0x59) BIT 7 6:4 3 2:0 FIELD TYPE DEFAULT DESCRIPTION RESERVED R/W 0x0 Reserved VOLTAGE_ SENSOR_V1_ MAX RC 0x0 GPIO1 Voltage sensor max reading when the GPIO1 voltage is above SENSE_V1_HI limit. This bit is cleared upon read. 0 indicates alarm has not been triggered. RESERVED R/W 0x0 Reserved VOLTAGE_ SENSOR_V1_ MIN RC 0x7 GPIO1 Voltage sensor min reading when GPIO1 voltage is below SENSE_V1_LO limit. This bit is cleared upon read. 7 indicates alarm has not been triggered. 7.7.81 Sensor T Table 91. SENSOR_T (Address 0x5A) BIT 52 FIELD TYPE DEFAULT DESCRIPTION 7 RESERVED R/W 0x0 Reserved 6:4 TEMP_MAX RC 0x0 Internal Temperature sensor maximum reading when temperature is above SENSE_T_HI limit. This bit is cleared upon read. 0 indicates alarm has not been triggered. Copyright © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 Table 91. SENSOR_T (Address 0x5A) (continued) BIT FIELD TYPE DEFAULT DESCRIPTION 3 RESERVED R/W 0x0 Reserved 2:0 TEMP_MIN RC 0x7 Internal Temperature sensor minimum reading when temperature is below SENSE_T_LO limit. This bit is cleared upon read. 7 indicates alarm has not been triggered. 7.7.82 RESERVED Register Table 92. RESERVED (Address 0x5B) BIT FIELD TYPE DEFAULT DESCRIPTION 7:2 RESERVED R/W 0x00 Reserved. 1 RESERVED RC 0x0 Reserved. 0 RESERVED RC 0x0 Reserved. 7.7.83 CSI-2 Error Count Table 93. CSI_ERR_CNT (Address 0x5C) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 CSI_ERR_CNT RC 0x00 CSI-2 Error Counter Register This register counts the number of CSI-2 packets received with errors since the last read of the counter. 7.7.84 CSI-2 Error Status Table 94. CSI_ERR_STATUS (Address 0x5D) BIT FIELD TYPE DEFAULT DESCRIPTION 7:4 RESERVED R 0x0 Reserved 3 LINE_LEN_ MISMATCH R/RC 0x0 Indicates Line length less than the received Packet header Word count 2 CHKSUM_ERR R/RC 0x0 Indicates a checksum error detected in the incoming data (uncorrectable) 1 ECC_2BIT_ERR R/RC 0x0 Indicates a 2-Bit Ecc error (uncorrectable) in the Packet header 0 ECC_1BIT_ERR R/RC 0x0 Indicates a 1-Bit Ecc error detected in the Packet header 7.7.85 CSI-2 Errors Data Lanes 0 and 1 Table 95. CSI_ERR_DLANE01 (Address 0x5E) BIT FIELD TYPE DEFAULT DESCRIPTION 7 SOT_ERROR_1 R 0x0 Lane 1: Single-bit Error in SYNC Sequence - Correctable 6 SOT_SYNC_ ERROR_1 R 0x0 Lane 1: Multi-bit Error in SYNC Sequence - Uncorrectable 5 CNTRL_ERR_ HSRQST_1 R 0x0 Lane 1: Control Error in HS Request Mode 4 RESERVED R 0x0 Reserved 3 SOT_ERROR_0 R 0x0 Lane 0: Single-bit Error in SYNC Sequence - Correctable 2 SOT_SYNC_ ERROR_0 R 0x0 Lane 0: Multi-bit Error in SYNC Sequence - Uncorrectable 1 CNTRL_ERR_ HSRQST_0 R 0x0 Lane 0: Control Error in HS Request Mode 0 RESERVED R 0x0 Reserved Copyright © 2017–2018, Texas Instruments Incorporated 53 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn 7.7.86 CSI-2 Errors Data Lanes 2 and 3 Table 96. CSI_ERR_DLANE23 (Address 0x5F) BIT DEFAULT DESCRIPTION 7 FIELD SOT_ERROR_3 R TYPE 0x0 Lane 3: Single-bit Error in SYNC Sequence - Correctable 6 SOT_SYNC_ ERROR_3 R 0x0 Lane 3: Multi-bit Error in SYNC Sequence - Uncorrectable 5 CNTRL_ERR_ HSRQST_3 R 0x0 Lane 3: Control Error in HS Request Mode 4 RESERVED R 0x0 Reserved 3 SOT_ERROR_2 R 0x0 Lane 2: Single-bit Error in SYNC Sequence - Correctable 2 SOT_SYNC_ ERROR_2 R 0x0 Lane 2: Multi-bit Error in SYNC Sequence - Uncorrectable 1 CNTRL_ERR_ HSRQST_2 R 0x0 Lane 2: Control Error in HS Request Mode 0 RESERVED R 0x0 Reserved 7.7.87 CSI-2 Errors Clock Lane Table 97. CSI_ERR_CLK_LANE (Address 0x60) BIT FIELD TYPE DEFAULT DESCRIPTION 7:2 RESERVED R 0x00 Reserved 1 CNTRL_ERR_ HSRQST_CK0 R 0x0 Clk Lane: Control Error in HS Request Mode 0 RESERVED R 0x0 Reserved 7.7.88 CSI-2 Packet Header Data Table 98. CSI_PKT_HDR_VC_ID (Address 0x61) BIT FIELD TYPE DEFAULT DESCRIPTION 7:6 LONG_PKT_ VCHNL_ID R 0x0 Virtual Channel ID from CSI-2 Packet header 5:0 LONG_PKT_ DATA_ID R 0x00 Data ID from CSI-2 Packet header 7.7.89 Packet Header Word Count 0 Table 99. PKT_HDR_WC_LSB (Address 0x62) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 LONG_PKT_ WRD_CNT_ LSB R 0x00 Payload count lower byte from CSI-2 Packet header 7.7.90 Packet Header Word Count 1 Table 100. PKT_HDR_WC_MSB (Address 0x63) 54 BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 LONG_PKT_ WRD_CNT_ MSB R 0x00 Payload count upper byte from CSI-2 Packet header Copyright © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 7.7.91 CSI-2 ECC Table 101. CSI_ECC (Address 0x64) BIT FIELD TYPE DEFAULT DESCRIPTION 7 LINE_ LENGTH_ CHANGE R 0x0 Indicates Line length change detected per frame 6 RESERVED R 0x0 Reserved 5:0 CSI-2_ECC R 0x00 CSI-2 ECC byte from packet header 7.7.92 RESERVED Register Table 102. RESERVED (Address 0x65-67) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 RESERVED R 0x00 Reserved. 7.7.93 RESERVED Register Table 103. RESERVED (Address 0x68-6F) BIT FIELD 7:0 RESERVED TYPE DEFAULT DESCRIPTION 0x00 Reserved. 7.7.94 RESERVED Register Table 104. RESERVED (Address 0x70-0x71) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 RESERVED R/W 0x00 Reserved. 7.7.95 RESERVED Register Table 105. RESERVED (Address 0x72) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 RESERVED R/W 0x25 Reserved. 7.7.96 RESERVED Register Table 106. RESERVED (Address 0x73) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 RESERVED R/W 0x00 Reserved. 7.7.97 RESERVED Register Table 107. RESERVED (Address 0x74) BIT FIELD 7:4 RESERVED 3:0 RESERVED TYPE R/W Copyright © 2017–2018, Texas Instruments Incorporated DEFAULT DESCRIPTION 0x0 Reserved. 0x0 Reserved. 55 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn 7.7.98 RESERVED Register Table 108. RESERVED (Address 0x75) BIT FIELD TYPE DEFAULT DESCRIPTION 7:1 RESERVED R/W 0x00 Reserved. 0 RESERVED 0x0 Reserved. 7.7.99 RESERVED Register Table 109. RESERVED (Address 0x76) BIT FIELD TYPE DEFAULT DESCRIPTION 7 RESERVED R/W 0x0 Reserved. 6:4 RESERVED R 0x0 Reserved. 3:0 RESERVED R/W 0x0 Reserved. 7.7.100 RESERVED Register Table 110. RESERVED (Address 0x77) BIT FIELD TYPE DEFAULT DESCRIPTION 7 RESERVED R 0x0 Reserved. 6:0 RESERVED R/W 0x00 Reserved. 7.7.101 RESERVED Register Table 111. RESERVED (Address 0x78) BIT FIELD TYPE DEFAULT DESCRIPTION 7 RESERVED R 0x0 Reserved. 6 RESERVED SC 0x0 Reserved. 5:0 RESERVED R/W 0x00 Reserved. 7.7.102 RESERVED Register Table 112. RESERVED (Address 0x79) BIT FIELD TYPE DEFAULT DESCRIPTION 7:5 RESERVED R/W 0x0 Reserved. 4:0 RESERVED R/RC 0x00 Reserved. 7.7.103 RESERVED Register Table 113. RESERVED (Address 0x7A) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 RESERVED R/W 0x04 Reserved. 7.7.104 RESERVED Register Table 114. RESERVED (Address 0x7B-0x85) 56 BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 RESERVED R/W 0x00 Reserved. Copyright © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 7.7.105 RESERVED Register Table 115. RESERVED (Address 0x86) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 RESERVED R/W 0x90 Reserved. 7.7.106 RESERVED Register Table 116. RESERVED (Address 0x87-0x88) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 RESERVED R/W 0x00 Reserved. 7.7.107 RESERVED Register Table 117. RESERVED (Address 0x89-0x8B) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 RESERVED R 0x00 Reserved. 7.7.108 RESERVED Register Table 118. RESERVED (Address 0x8C-0x8F) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 RESERVED R/W 0x00 Reserved. 7.7.109 RESERVED Register Table 119. RESERVED (Address 0x90) BIT FIELD 7 RESERVED 6 RESERVED 5:0 RESERVED TYPE DEFAULT DESCRIPTION 0x0 Reserved. R/W 0x0 Reserved. R/W 0x32 Reserved. 7.7.110 RESERVED Register Table 120. RESERVED (Address 0x91) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 RESERVED R/W 0xE2 Reserved. 7.7.111 RESERVED Register Table 121. RESERVED (Address 0x92) BIT FIELD TYPE DEFAULT DESCRIPTION 7 RESERVED R 0x0 Reserved. 6:0 RESERVED R/W 0x64 Reserved. Copyright © 2017–2018, Texas Instruments Incorporated 57 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn 7.7.112 RESERVED Register Table 122. RESERVED (Address 0x93) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 RESERVED R/W 0x01 Reserved. 7.7.113 RESERVED Register Table 123. RESERVED (Address 0x94-0x99) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 RESERVED R/W 0x00 Reserved. 7.7.114 RESERVED Register Table 124. RESERVED (Address 0x9A-0x9E) BIT FIELD TYPE DEFAULT DESCRIPTION 7:6 RESERVED R 0x0 Reserved. 5:0 RESERVED R/W 0x00 Reserved. 7.7.115 RESERVED Register Table 125. RESERVED (Address 0x9F) BIT FIELD TYPE DEFAULT DESCRIPTION 7:5 RESERVED R 0x0 Reserved. 4:0 RESERVED R/W 0x10 Reserved. 7.7.116 RESERVED Register Table 126. RESERVED (Address 0xA0) BIT FIELD 7:0 RESERVED TYPE DEFAULT DESCRIPTION 0x0 Reserved. 7.7.117 RESERVED Register Table 127. RESERVED (Address 0xA1-0xA4) BIT FIELD TYPE DEFAULT DESCRIPTION 7:5 RESERVED R 0x0 Reserved. 4:0 RESERVED R/W 0x00 Reserved. 7.7.118 RESERVED Register Table 128. RESERVED (Address 0xA5) 58 BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 RESERVED R/W 0x10 Reserved. Copyright © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 7.7.119 RESERVED Register Table 129. RESERVED (Address 0xA6) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 RESERVED R/W 0x42 Reserved. 7.7.120 RESERVED Register Table 130. RESERVED (Address 0xA7-0xA9) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 RESERVED R/W 0x10 Reserved. 7.7.121 RESERVED Register Table 131. RESERVED (Address 0xAA-0xAB) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 RESERVED R/W 0x00 Reserved. 7.7.122 RESERVED Register Table 132. RESERVED (Address 0xAC-0xAF) BIT FIELD TYPE 7:0 RESERVED DEFAULT DESCRIPTION 0x00 Reserved. 7.7.123 IND_ACC_CTL Table 133. IND_ACC_CTL (Address 0xB0) BIT FIELD TYPE DEFAULT DESCRIPTION 7:5 RESERVED R 0x0 Reserved R/W 0x0 Indirect Register Select: Selects target for register access 000 : PATGEN 001 : FPD3 TX Registers 010: DIE ID Data IA_AUTO_INC R/W 0x0 Indirect Access Auto Increment: Enables auto-increment mode. Upon completion of a read or write, the register address is automatically incremented by 1 0x0 Indirect Access Read: Setting this allows generation of a read strobe to the selected register block upon setting of the IND_ACC_ADDR register. In auto-increment mode, read strobes are also asserted following a read of the IND_ACC_DATA register. This function is only required for blocks that need to pre-fetch register data. 4:2 1 0 IA_SEL IA_READ R/W 7.7.124 IND_ACC_ADDR Table 134. IND_ACC_ADDR (Address 0xB1) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 IND_ACC_ ADDR R/W 0x00 Indirect Access Register Offset: This register contains the 8-bit register offset for the indirect access. Copyright © 2017–2018, Texas Instruments Incorporated 59 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn 7.7.125 IND_ACC_DATA Table 135. IND_ACC_DATA (Address 0xB2) BIT FIELD TYPE 7:0 IND_ACC_ DATA R/W DEFAULT DESCRIPTION 0x00 Indirect Access Register Data: Writing this register causes an indirect write of the IND_ACC_DATA value to the selected analog block register. Reading this register returns the value of the selected analog block register. 7.7.126 RESERVED Register Table 136. RESERVED (Address 0xB3-0xEF) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 RESERVED R 0x00 Reserved. 7.7.127 FPD3_RX_ID0 Table 137. FPD3_RX_ID0 (Address 0xF0) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 FPD3_RX_ ID0 R 0x5F FPD3_TX_ID0: First byte ID code: ‘_’ 7.7.128 FPD3_RX_ID1 Table 138. FPD3_RX_ID1 (Address 0xF1) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 FPD3_RX_ ID1 R 0x55 FPD3_TX_ID1: 2nd byte of ID code: ‘U’ 7.7.129 FPD3_RX_ID2 Table 139. FPD3_RX_ID2 (Address 0xF2) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 FPD3_RX_ ID2 R 0x42 FPD3_TX_ID2: 3rd byte of ID code: ‘B’ 7.7.130 FPD3_RX_ID3 Table 140. FPD3_RX_ID3 (Address 0xF3) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 FPD3_RX_ ID3 R 0x39 FPD3_TX_ID3: 4th byte of ID code: ‘9’ 7.7.131 FPD3_RX_ID4 Table 141. FPD3_RX_ID4 (Address 0xF4) 60 BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 FPD3_RX_ ID4 R 0x35 FPD3_TX_ID4: 5th byte of ID code: '5' Copyright © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 7.7.132 FPD3_RX_ID5 Table 142. FPD3_RX_ID5 (Address 0xF5) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 FPD3_RX_ ID5 R 0x33 FPD3_TX_ID5: 6th byte of ID code: '3' Copyright © 2017–2018, Texas Instruments Incorporated 61 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn 7.7.133 Indirect Access Registers Several functional blocks include register sets contained in the Indirect Access map (Table 143); that is, Pattern Generator, and Analog controls. Register access is provided through an indirect access mechanism through the Indirect Access registers (IND_ACC_CTL, IND_ACC_ADDR, and IND_ACC_DATA). These registers are located at offsets 0xB0-0xB2 in the main register space. The indirect address mechanism involves setting the control register to select the desired block, setting the register offset address, and reading or writing the data register. In addition, an auto-increment function is provided in the control register to automatically increment the offset address following each read or write of the data register. For writes, the process is as follows: 1. Write to the IND_ACC_CTL register to select the desired register block 2. Write to the IND_ACC_ADDR register to set the register offset 3. Write the data value to the IND_ACC_DATA register If auto-increment is set in the IND_ACC_CTL register, repeating step 3 writes additional data bytes to subsequent register offset locations. For reads, the process is as follows: 1. Write to the IND_ACC_CTL register to select the desired register block 2. Write to the IND_ACC_ADDR register to set the register offset 3. Read from the IND_ACC_DATA register If auto-increment is set in the IND_ACC_CTL register, repeating step 3 reads additional data bytes from subsequent register offset locations. Table 143. Indirect Register Map Description IA SELECT 0xB0[4:2] PAGE/BLOCK INDIRECT REGISTERS ADDRESS RANGE 000 0 Digital Page 0 Indirect Registers 0x01 - 0x1F Pattern Gen Registers 010 2 Indirect Registers: Die ID Data 0x00 - 0x040 Hold 16 bytes that correspond to Die ID data. DESCRIPTION 7.7.133.1 Reserved Table 144. Reserved (Address 0x00) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 RESERVED R 0x00 Reserved 7.7.133.2 PGEN_CTL Table 145. PGEN_CTL (Address 0x01) BIT FIELD TYPE DEFAULT DESCRIPTION 7:1 RESERVED R/W 0x0 Reserved PGEN_ ENABLE R/W 0x0 Pattern Generator Enable 1: Enable Pattern Generator 0: Disable Pattern Generator 0 62 Copyright © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 7.7.133.3 PGEN_CFG Table 146. PGEN_CFG (Address 0x02) BIT FIELD TYPE DEFAULT DESCRIPTION 7 PGEN_ FIXED_EN R/W 0x0 Fixed Pattern Enable Setting this bit enables Fixed Color Patterns. 0 : Send Color Bar Pattern 1 : Send Fixed Color Pattern 6 RESERVED R/W 0x0 Reserved 5:4 NUM_ CBARS R/W 0x3 Number of Color Bars 00 : 1 Color Bar 01 : 2 Color Bars 10 : 4 Color Bars 11 : 8 Color Bars 3:0 BLOCK_SIZE R/W 0x3 Block Size For Fixed Color Patterns, this field controls the size of the fixed color field in bytes. Allowed values are 1 to 15. 7.7.133.4 PGEN_CSI_DI Table 147. PGEN_CSI_DI (Address 0x03) BIT FIELD TYPE DEFAULT DESCRIPTION 7:6 PGEN_CSI_ VC R/W 0x0 CSI-2 Virtual Channel Identifier This field controls the value sent in the CSI-2 packet for the Virtual Channel Identifier 5:0 PGEN_CSI_ DT R/W 0x24 CSI-2 Data Type This field controls the value sent in the CSI-2 packet for the Data Type. The default value (0x24) indicates RGB888. 7.7.133.5 PGEN_LINE_SIZE1 Table 148. PGEN_LINE_SIZE1 (Address 0x04) BIT FIELD TYPE 7:0 PGEN_LINE_ R/W SIZE[15:8] DEFAULT DESCRIPTION 0x07 Most significant byte of the Pattern Generator line size. This is the active line length in bytes. Default setting is for 1920 bytes for a 640 pixel line width. 7.7.133.6 PGEN_LINE_SIZE0 Table 149. PGEN_LINE_SIZE0 (Address 0x05) BIT FIELD 7:0 PGEN_LINE_ R/W SIZE[7:0] TYPE DEFAULT DESCRIPTION 0x80 Least significant byte of the Pattern Generator line size. This is the active line length in bytes. Default setting is for 1920 bytes for a 640 pixel line width. 7.7.133.7 PGEN_BAR_SIZE1 Table 150. PGEN_BAR_SIZE1 (Address 0x06) BIT FIELD TYPE 7:0 PGEN_BAR_ R/W SIZE[15:8] DEFAULT DESCRIPTION 0x00 Most significant byte of the Pattern Generator color bar size. This is the active length in bytes for the color bars. This value is used for all except the last color bar. The last color bar is determined by the remaining bytes as defined by the PGEN_LINE_SIZE value. Copyright © 2017–2018, Texas Instruments Incorporated 63 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn 7.7.133.8 PGEN_BAR_SIZE0 Table 151. PGEN_BAR_SIZE0 (Address 0x07) BIT FIELD TYPE 7:0 PGEN_BAR_ R/W SIZE[7:0] DEFAULT DESCRIPTION 0xF0 Least significant byte of the Pattern Generator color bar size. This is the active length in bytes for the color bars. This value is used for all except the last color bar. The last color bar is determined by the remaining bytes as defined by the PGEN_LINE_SIZE value. 7.7.133.9 PGEN_ACT_LPF1 Table 152. PGEN_ACT_LPF1 (Address 0x08) BIT FIELD TYPE 7:0 PGEN_ACT_ R/W LPF[15:8] DEFAULT DESCRIPTION 0x01 Active Lines Per Frame Most significant byte of the number of active lines per frame. Default setting is for 480 active lines per frame. 7.7.133.10 PGEN_ACT_LPF0 Table 153. PGEN_ACT_LPF0 (Address 0x09) BIT FIELD TYPE 7:0 PGEN_ACT_ R/W LPF[7:0] DEFAULT DESCRIPTION 0xE0 Active Lines Per Frame Least significant byte of the number of active lines per frame. Default setting is for 480 active lines per frame. 7.7.133.11 PGEN_TOT_LPF1 Table 154. PGEN_TOT_LPF1 (Address 0x0A) BIT FIELD 7:0 PGEN_TOT_ R/W LPF[15:8] TYPE DEFAULT DESCRIPTION 0x02 Total Lines Per Frame Most significant byte of the number of total lines per frame including vertical blanking 7.7.133.12 PGEN_TOT_LPF0 Table 155. PGEN_TOT_LPF0 (Address 0x0B) BIT FIELD TYPE 7:0 PGEN_TOT_ R/W LPF[7:0] DEFAULT DESCRIPTION 0x0D Total Lines Per Frame Least significant byte of the number of total lines per frame including vertical blanking 7.7.133.13 PGEN_LINE_PD1 Table 156. PGEN_LINE_PD1 (Address 0x0C) 64 BIT FIELD TYPE 7:0 PGEN_LINE_ R/W PD[15:8] DEFAULT DESCRIPTION 0x0C Line Period Most significant byte of the line period in 10-ns units. The default setting for the line period registers sets a line period of 31.75 microseconds. Copyright © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 7.7.133.14 PGEN_LINE_PD0 Table 157. PGEN_LINE_PD0 (Address 0x0D) BIT FIELD TYPE 7:0 PGEN_LINE_ R/W PD[7:0] DEFAULT DESCRIPTION 0x67 Line Period Least significant byte of the line period in 10-ns units. The default setting for the line period registers sets a line period of 31.75 microseconds. 7.7.133.15 PGEN_VBP Table 158. PGEN_VBP (Address 0x0E) BIT 7:0 FIELD PGEN_VBP TYPE R/W DEFAULT DESCRIPTION 0x21 Vertical Back Porch This value provides the vertical back porch portion of the vertical blanking interval. This value provides the number of blank lines between the FrameStart packet and the first video data packet. 7.7.133.16 PGEN_VFP Table 159. PGEN_VFP (Address 0x0F) BIT 7:0 FIELD PGEN_VFP TYPE R/W DEFAULT DESCRIPTION 0x0A Vertical Front Porch This value provides the vertical front porch portion of the vertical blanking interval. This value provides the number of blank lines between the last video line and the FrameEnd packet. 7.7.133.17 PGEN_COLOR0 Table 160. PGEN_COLOR0 (Address 0x10) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 PGEN_ COLOR0 R/W 0xAA Pattern Generator Color 0 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 0. For Fixed Color Patterns, this register controls the first byte of the fixed color pattern. 7.7.133.18 PGEN_COLOR1 Table 161. PGEN_COLOR1 (Address 0x11) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 PGEN_ COLOR1 R/W 0x33 Pattern Generator Color 1 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 1. For Fixed Color Patterns, this register controls the second byte of the fixed color pattern. 7.7.133.19 PGEN_COLOR2 Table 162. PGEN_COLOR2 (Address 0x12) BIT FIELD 7:0 PGEN_ COLOR2 TYPE R/W DEFAULT DESCRIPTION 0xF0 Pattern Generator Color 2 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 2. For Fixed Color Patterns, this register controls the third byte of the fixed color pattern. Copyright © 2017–2018, Texas Instruments Incorporated 65 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn 7.7.133.20 PGEN_COLOR3 Table 163. PGEN_COLOR3 (Address 0x13) BIT FIELD 7:0 PGEN_ COLOR3 TYPE R/W DEFAULT DESCRIPTION 0x7F Pattern Generator Color 3 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 3. For Fixed Color Patterns, this register controls the fourth byte of the fixed color pattern. 7.7.133.21 PGEN_COLOR4 Table 164. PGEN_COLOR4 (Address 0x14) BIT FIELD 7:0 PGEN_ COLOR4 TYPE R/W DEFAULT DESCRIPTION 0x55 Pattern Generator Color 4 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 4. For Fixed Color Patterns, this register controls the fifth byte of the fixed color pattern. 7.7.133.22 PGEN_COLOR5 Table 165. PGEN_COLOR5 (Address 0x15) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 PGEN_ COLOR5 R/W 0xCC Pattern Generator Color 5 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 5. For Fixed Color Patterns, this register controls the sixth byte of the fixed color pattern. 7.7.133.23 PGEN_COLOR6 Table 166. PGEN_COLOR6 (Address 0x16) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 PGEN_ COLOR6 R/W 0x0F Pattern Generator Color 6 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 6. For Fixed Color Patterns, this register controls the seventh byte of the fixed color pattern. 7.7.133.24 PGEN_COLOR7 Table 167. PGEN_COLOR7 (Address 0x17) BIT FIELD 7:0 PGEN_ COLOR7 TYPE R/W DEFAULT DESCRIPTION 0x80 Pattern Generator Color 7 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 7. For Fixed Color Patterns, this register controls the eighth byte of the fixed color pattern. 7.7.133.25 PGEN_COLOR8 Table 168. PGEN_COLOR8 (Address 0x18) 66 BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 PGEN_ COLOR8 R/W 0x00 Pattern Generator Color 8 For Fixed Color Patterns, this register controls the ninth byte of the fixed color pattern. Copyright © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 7.7.133.26 PGEN_COLOR9 Table 169. PGEN_COLOR9 (Address 0x19) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 PGEN_ COLOR9 R/W 0x00 Pattern Generator Color 9 For Fixed Color Patterns, this register controls the tenth byte of the fixed color pattern. 7.7.133.27 PGEN_COLOR10 Table 170. PGEN_COLOR10 (Address 0x1A) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 PGEN_ COLOR10 R/W 0x00 Pattern Generator Color 10 For Fixed Color Patterns, this register controls the eleventh byte of the fixed color pattern. 7.7.133.28 PGEN_COLOR11 Table 171. PGEN_COLOR11 (Address 0x1B) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 PGEN_ COLOR11 R/W 0x00 Pattern Generator Color 11 For Fixed Color Patterns, this register controls the twelfth byte of the fixed color pattern. 7.7.133.29 PGEN_COLOR12 Table 172. PGEN_COLOR12 (Address 0x1C) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 PGEN_ COLOR12 R/W 0x00 Pattern Generator Color 12 For Fixed Color Patterns, this register controls the thirteenth byte of the fixed color pattern. 7.7.133.30 PGEN_COLOR13 Table 173. PGEN_COLOR13 (Address 0x1D) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 PGEN_ COLOR13 R/W 0x00 Pattern Generator Color 13 For Fixed Color Patterns, this register controls the fourteenth byte of the fixed color pattern. 7.7.133.31 PGEN_COLOR14 Table 174. PGEN_COLOR14 (Address 0x1E) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 PGEN_ COLOR14 R/W 0x00 Pattern Generator Color 14 For Fixed Color Patterns, this register controls the fifteenth byte of the fixed color pattern. Copyright © 2017–2018, Texas Instruments Incorporated 67 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn 7.7.133.32 PGEN_COLOR15 Table 175. PGEN_COLOR15 (Address 0x1F) 68 BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 PGEN_ COLOR15 R/W 0x00 Pattern Generator Color 15 For Fixed Color Patterns, this register controls the sixteenth byte of the fixed color pattern. 版权 © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 8 Application and Implementation 注 Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The link between the DS90UB953-Q1 and the companion deserializer has two distinct data paths. The first path is a forward channel which is nominally running at up to 4.16 Gbps and is encoded such that the channel occupies a bandwidth from 20 MHz to 2.1 GHz. The second path is a back channel from the deserializer to the serializer which occupies a frequency range nominally from 10 MHz to 50 MHz. For these two communications links to operate properly, the circuit between the serializer and the deserializer must present a characteristic impedance of 50 Ω. Deviations from this 50-Ω characteristic will lead to signal reflections either at the serializer or deserializer, which will result in bit errors. 8.1.1 Power Over Coax The DS90UB953-Q1 is designed to support the Power-over-Coax (PoC) method of powering remote sensor systems. With this method, the power is delivered over the same medium (a coaxial cable) used for high-speed digital video data and bidirectional control and diagnostics data transmission. This method uses passive networks or filters that isolate the transmission line from the loading of the DC-DC regulator circuits and their connecting power traces on both sides of the link as shown in 图 15. Sensor Module Automotive ECU DC-DC Regulators Power Source PoC Coaxial Cable POWER CAC1 Image Sensor PoC FPD-Link III Serializer CAC1 FPD-Link III Deserializer FPD-Link III CAC2 RTERM Braided Shield Processor SoC CAC2 RTERM 图 15. Power-over-Coax (PoC) System Diagram The PoC network impedance of ≥ 2 kΩ over a specific frequency band is typically sufficient to isolate the transmission line from the loading of the regulator circuits. The lower limit of the frequency band is defined as ½ of the frequency of the bidirectional control channel' (fBCC). The upper limit of the frequency band is the frequency of the forward high-speed channel (fFC). 图 16 shows an example PoC network suitable for a "4G" FPD-Link III consisting of DS90UB953-Q1 and DS90UB954-Q1 or DS90UB960-Q1 pair with the bidirectional channel operating at 50 Mbps (½ fBCC = 25 MHz) and the forward channel operating at 4.16 Gbps (fFC ≈ 2.1 GHz). Other PoC networks are possible and may be different on the serializer and the deserializer boards as long as the printed-circuit board return loss requirements given in 表 177 are met. 版权 © 2017–2018, Texas Instruments Incorporated 69 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn Application Information (接接下页) VPoC R1 4.02 k: L1 10 PH C1 0.1 PF C2 > 10 PF FB3 FB2 FB1 CAC1 DOUT+ 33 nF to 100 nF R2 CAC2 49.9 : 15 nF to 47 nF DOUT- 图 16. Typical PoC Network for a "4G" FPD-Link III 表 176 lists essential components for this particular PoC network. Note that the impedance characteristic of the ferrite beads deviates with the bias current. Therefore, keeping the current going through the network below 150 mA is recommended. 表 176. Suggested Components for a "4G" FPD-Link III PoC Network Count Ref Des Description Part Number MFR LQH3NPN100MJR Murata LQH3NPZ100MJR Murata Inductor, 10 µH, 0.360 Ω max, 450 mA MIN(Isat, Itemp) 30 MHz SRF min, 3.2 mm x 2.5 mm, AEC-Q200 NLCV32T-100K-EFD TDK Inductor, 10 µH, 0.400 Ω typ, 550 mA MIN(Isat, Itemp) 39 MHz SRF typ, 3 mm x 3 mm, AEC-Q200 TYS3010100M-10 Laird Inductor, 10 µH, 0.325 Ω max, 725 mA MIN(Isat, Itemp) 41 MHz SRF typ, 3 mm x 3 mm, AEC-Q200 TYS3015100M-10 Laird Ferrite Bead, 1.5 kΩ at 1 GHz, 0.5 Ω max @ DC 500 mA @ 85°C, 0603 SMD , General Purpose BLM18HE152SN1 Murata Ferrite Bead, 1.5 kΩ at 1 GHz, 0.5 Ω max @ DC 500 mA at 85°C, 0603 SMD , AEC-Q200 BLM18HE152SZ1 Murata Inductor, 10 µH, 0.288 Ω max, 530 mA MIN(Isat, Itemp) 30 MHz SRF min, 3 mm x 3 mm, General Purpose Inductor, 10 µH, 0.288 Ω max, 530 mA MIN(Isat, Itemp) 30 MHz SRF min, 3 mm x 3 mm, AEC-Q200 1 3 L1 FB1-FB3 In addition to the selection of PoC network components, their placement and layout play a critical role as well. • Place the smallest component, typically a ferrite bead or a chip inductor, as close to the connector as possible. Route the high-speed trace through one of its pads to avoid stubs. • Use the smallest component pads as allowed by manufacturer's design rules. Add anti-pads in the inner planes below the component pads to minimize impedance drop. • Consult with the connector manufacturer for optimized connector footprint. If the connector is mounted on the same side as the IC, minimize the impact of the through-hole connector stubs by routing the high-speed signal traces on the opposite side of the connector mounting side. • Use coupled 100-Ω differential signal traces from the device pins to the AC-coupling caps. Use 50-Ω single70 版权 © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn • ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 ended traces from the AC-coupling capacitors to the connector. Terminate the inverting signal traces close to the connectors with standard 49.9-Ω resistors. The suggested characteristics for single-ended PCB traces (microstrips or striplines) for serializer or deserializer boards are detailed in 表 177. The effects of the PoC networks must be accounted for when testing the traces for compliance to the suggested limits. 表 177. Suggested Characteristics for Single-Ended PCB Traces With Attached PoC Networks PARAMETER MIN Ltrace Single-ended PCB trace length from the device pin to the connector pin Ztrace Single-ended PCB trace characteristic impedance 45 Zcon Connector (mounted) characteristic impedance 40 ½ fBCC < f < 0.1 GHz RL Return Loss, S11 0.1 GHz < f < 1 GHz (f in GHz) 1 GHz < f < fFC f < 0.5 GHz IL Insertion Loss, S12 TYP MAX UNIT 5 cm 50 55 Ω 50 60 Ω -20 dB –12+8*log(f) dB –12 dB –0.35 dB f =1 GHz –0.6 dB f =2.1 GHz –1.2 dB The VPOC fluctuations on the serializer side, caused by the transient current draw of the sensor, the DC resistance of cables, and PoC components, must be kept to a minimum as well. Increasing the VPOC voltage and adding extra decoupling capacitance (> 10 µF) help reduce the amplitude and slew rate of the VPOC fluctuations. 版权 © 2017–2018, Texas Instruments Incorporated 71 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn 8.2 Typical Applications DS90UB953-Q1 VDDD_CAP 10µF 0.1µF 10µF 0.1µF 10µF 0.1µF 1.8V VDDD 0.01µF VDDDRV_CAP VDDDRV VDDPLL_CAP VDDPLL 0.01µF 0.01µF 0.01µF 1µF FB1 0.01µF 1µF FB2 0.01µF 1µF FB3 0.022µF External Clock Input for NonSync Mode LPF1 CLKIN CSI_CLKN CSI_CLKP CSI_D0N CSI_D0P CSI_D1N CSI_D1P CSI_D2N CSI_D2P CSI_D3N CSI_D3P CSI-2 Inputs LPF2 0.1µF C1 Serial FPD-Link III Interface DOUT+ DOUTC2 49.9Ÿ 1.8V Optional HW Control 1.8V R1 1.8V MODE R2 R3 CLK_OUT / IDX 10kŸ SW Control R4 PDB >10µF GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO Control Interface NOTE: C1, C2 (Design Parameters Table) 1.8V or 3.3V 4.7NŸ 4.7NŸ I2C Bus Interface I2C_SCL RES1 RES0 DAP (GND) I2C_SDA R1, R2 (see MODE Setting Table) R3, R4 (see IDX Setting Table) FB1-FB3: Z = 1 kŸ (@ 100 MHz) RDC < 25 mŸ Copyright © 2018, Texas Instruments Incorporated 图 17. Typical Connection Diagram Coaxial DS90UB953-Q1 VDDD_CAP 10µF 0.1µF 10µF 0.1µF 10µF 0.1µF VDDD 0.01µF VDDDRV_CAP VDDDRV VDDPLL_CAP VDDPLL 0.01µF 0.01µF 1.8V 0.01µF 1µF FB1 0.01µF 1µF FB2 0.01µF 1µF FB3 0.022µF External Clock Input for NonSync Mode CLKIN CSI_CLKN CSI_CLKP CSI_D0N CSI_D0P CSI_D1N CSI_D1P CSI_D2N CSI_D2P CSI_D3N CSI_D3P CSI-2 Inputs LPF1 LPF2 0.1µF C1 Serial FPD-Link III Interface DOUT+ DOUTC2 1.8V Optional HW Control 1.8V R1 1.8V MODE R2 R3 CLK_OUT / IDX 10kŸ SW Control R4 PDB >10µF GPIO Control Interface GPIO[0] GPIO[1] GPIO[2] GPIO[3] NOTE: C1, C2 (Design Parameters Table) 1.8V or 3.3V 4.7NŸ I2C Bus Interface 4.7NŸ I2C_SCL I2C_SDA RES1 RES0 DAP (GND) R1, R2 (see MODE Setting Table) R3, R4 (see IDX Setting Table) FB1-FB3: Z = 1 kŸ (@ 100 MHz) RDC < 25 mŸ Copyright © 2018, Texas Instruments Incorporated 图 18. Typical Connection Diagram STP 72 版权 © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 Typical Applications (接接下页) 8.2.1 Design Requirements For a typical design application, use the parameters listed in 表 178. 表 178. Design Parameters DESIGN PARAMETER PIN(S) VALUE V(VDD) VDDD, VDDDRV, VDDPLL 1.8 V DOUT+ 33nF – 100 nF (50 V / X7R / 0402) DOUT- 15nF – 47 nF (50 V / X7R / 0402) DOUT+, DOUT- 33 – 100 nF (50 V / X7R / 0402) DOUT+ 100 nF (50 V / X7R / 0402) DOUT- 47 nF (50 V / X7R / 0402) DOUT+, DOUT- 100 nF (50 V / X7R / 0402) AC-Coupling Capacitor for Synchronous Modes, Coaxial Connection AC-Coupling Capacitor for Synchronous Modes, STP Connection AC-Coupling Capacitor for NonSynchronous and DVP Backwards Compatible Modes, Coaxial Connection AC-Coupling Capacitor for NonSynchronous and DVP Backwards Compatible Modes, STP Connection The SER/DES only supports AC-coupled interconnects through an integrated DC-balanced decoding scheme. External AC-coupling capacitors must be placed in series in the FPD-Link III signal path as shown in 图 19 and 图 20. For applications using single-ended 50-Ω coaxial cable, terminate the unused data pins (DOUT+, DOUT-) with an AC-coupling capacitor and a 50-Ω resistor. DOUT+ RIN+ DOUT- RIN- SER DES 50Q 50Q 图 19. AC-Coupled Connection (Coaxial) DOUT+ RIN+ DOUT- RIN- SER DES 图 20. AC-Coupled Connection (STP) For high-speed FPD–Link III transmissions, use the smallest available package for the AC-coupling capacitor to help minimize degradation of signal quality due to package parasitics. 8.2.2 Detailed Design Procedure 图 17 shows a typical application circuit of the DS90UB953-Q1. The next sections highlight recommendations for the critical device pins. 8.2.2.1 CSI-2 Interface The CSI-2 input port on the DS90UB953-Q1 is compliant with the MIPI D-PHY v1.2 and CSI-2 v1.3 specifications. The CSI-2 interface consists of a clock and an option of one, two, or four data lanes. The clock and each of the data lanes are differential lines. The DS90UB953-Q1 CSI-2 input needs to be DC coupled to a compatible CSI-2 transmitter. Follow PCB layout guidelines given in CSI-2 Guidelines. 8.2.2.2 FPD-Link III Input / Output The DS90UB953-Q1 serial data out signal operates at different data rates depending upon the mode in which the device is operating. In synchronous mode, where the reference clock is provided by the deserializer, the serial data rate is up to 4.16 Gbps. 版权 © 2017–2018, Texas Instruments Incorporated 73 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn The signals at DOUT+ and DOUT- must be AC-coupled. The AC-coupling capacitor values used on DOUT+ and DOUT- depends on the mode and cable used as shown in 表 178. When connecting to a coax cable, the ACcoupling capacitor on the negative terminal (DOUT-) should be approximately ½ of the AC-coupling capacitor value on DOUT+ and be terminated to a 50-Ω load. Adhering to the PCB layout guidelines given in Layout Examples is critical. 8.2.2.3 Internal Regulator Bypassing The DS90UB953-Q1 features three internal regulators that must be bypassed to GND. The VDDD_CAP, VDDDRV_CAP, and VDDPLL_CAP are the pins that expose the outputs of the internal regulators for bypassing. TI recommends that each pin has a 10-µF, 0.1-µF, and a 0.01-µF capacitor to GND. The 0.01-µF caps must be placed as close as practical to the bypass pins. 8.2.2.4 Loop Filter Decoupling The LPF1 and LPF2 pins are for connecting filter capacitors to the internal PLL circuits. LPF1 should have a 0.022-µF capacitor connected to the VDD_PLL pin (pin 11). The capacitor connected between LPF1 and VDDPLL must enclose as small of a loop as possible. LPF2 must have a 0.1-µF capacitor connecting the pin to GND. One of these PLLs generates the high-speed clock used in the serialization of the output, while the other PLL is used in the CSI-2 receive port. Noise coupled into these pins degrades the performance of the PLLs in the DS90UB953-Q1, so the caps must be placed close to the pins they are connected to, and the area of the loop enclosed must be minimized. 8.2.3 Application Curve The falling edge of the blue trace indicates that the device should shift from LP to HS mode – the rise that comes about one division later is when the DS90UB953-Q1 turns on the internal termination so the device is ready to receive HS data. The transitions are the CSI-2 data, and then the drop of the blue trace indicates that the termination has been turned off. 图 21. CSI-2 LP to HS Mode Transition 74 版权 © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 9 Power Supply Recommendations This device provides separate power and ground pins for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. The Pin Configuration and Functions section provides guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs. 9.1 Power-Up Sequencing The power-up sequence for the DS90UB953-Q1 is as follows: VDD18 T0 T2 T1 T3 Hard Reset PDB 图 22. Power Supply Sequencing 表 179. Timing Diagram for the Power Supply Start-Up and Initialization Sequences PARAMETER MIN TYP MAX UNIT NOTES T0 VDD18 rise time 0.05 ms at 10/90% T1 VDD18 to PDB 0 ms After VDD18 is stable T2 PDB high time before PDB hard reset 1 ms T3 PDB high to low pulse width 3 ms Hard reset T4 PDB to I2C Ready 2 ms See 图 23 9.1.1 System Initialization When initializing the communications link between a deserializer hub and a DS90UB953-Q1 serializer, the system timing will depend on the mode selected for generating the serializer reference clock. When synchronous clocking mode is selected, the serializer will relock onto the extracted back channel reference clock when available, so there is no need for local crystal oscillator at the sensor module. The initialization sequence follows the illustration given in 图 23. 版权 © 2017–2018, Texas Instruments Incorporated 75 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn PoC Supply VDD18 PDB T4 MODE, IDX Valid DES Back Channel DES Lock Time LOCK 953 Config Sensor Config Valid Image I2C Remote I2C Local DES config Pass through CLKOUT DOUT+ Sensor CSI-2 图 23. Initialization Sequence: Synchronous Clocking Mode 9.2 Power Down (PDB) The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin may be controlled by an external device, or through VDD where VDD = 1.71 V to 1.89 V. PDB should be brought high after all power supplies on the board have stabilized. When PDB is driven low, ensure that the pin is driven to 0 V for at least 3 ms before releasing or driving high. In the case where PDB is pulled up to VDD directly, a 10-kΩ pullup resistor and a > 1-μF capacitor to ground are required. Toggling PDB low powers down the device and resets all control registers to default. After power up, if there are any errors seen, TI recommends clearing the registers to reset the errors. Make sure to power up the VDDDRV before or at the same time as the VDDPLL. 10 Layout 10.1 Layout Guidelines Circuit board layout and stack-up for the FPD-Link III devices must be designed to provide low-noise power feed to the device. Good layout practice also separates high frequency or high-level inputs and outputs to minimize unwanted stray noise pickup, feedback, and interference. External bypassing should be low-ESR ceramic capacitors with high-quality dielectric. The voltage rating of the ceramic capacitors must be at least 2× the power supply voltage being used. 76 版权 © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 Layout Guidelines (接接下页) TI recommends surface-mount capacitors due to their smaller parasitics. When using multiple capacitors per supply pin, place the smaller value closest to the pin. A large bulk capacitor is recommend at the point of power entry. This is typically in the 47-µF to 100-µF range, which smooths low-frequency switching noise. TI recommends connecting power and ground pins directly to the power and ground planes with bypass capacitors connected to the plane. TI also recommends that the user place a via on both ends of the capacitors. Connecting power or ground pins to an external bypass capacitor increases the inductance of the path. A small body size X7R chip capacitor, such as 0603 or 0402, is recommended for external bypass. The small body size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20 to 30 MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing the impedance at high frequency. Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs (see Pin Configuration and Functions for more information). In some cases, an external filter may be used to provide clean power to sensitive circuits such as PLLs. Use at least a four-layer board with a dedicated ground plane. Place CSI-2 signals away from the single-ended or differential FPD-Link III RX input traces to prevent coupling from the CSI-2 lines to the Rx input lines. A singleended impedance of 50 Ω is typically recommended for coaxial interconnect, and a differential impedance of 100 Ω is typically recommended for STP interconnect. The closely coupled lines help to ensure that coupled noise appears as common-mode and thus is rejected by the receivers. The tightly coupled lines also radiate less. 10.1.1 CSI-2 Guidelines 1. Route CSI0_D*P/N pairs with controlled 100-Ω differential impedance (±20%) or 50-Ω single-ended impedance (±15%). 2. Keep away from other high-speed signals. 3. Keep length difference between a differential pair to 5 mils of each other. 4. Length matching should be near the location of mismatch. 5. Match trace lengths between the clock pair and each data pair to be < 25 mils. 6. Separate each pair by at least 3 times the signal trace width. 7. Keep the use of bends in differential traces to a minimum. When bends are used, the number of left and right bends must be as equal as possible, and the angle of the bend should be ≥ 135 degrees. This arrangement minimizes any length mismatch caused by the bends and therefore minimizes the impact that bends have on EMI. 8. Route all differential pairs on the same layer to help match trace impedance characteristics. 9. Keep the number of VIAS to a minimum—TI recommends keeping the VIA count to two or fewer. 10. Keep traces on layers adjacent to ground plane. 11. Do NOT route differential pairs over any plane split. 注 Adding Test points causes impedance discontinuity and therefore negatively impacts signal performance. If test points are used, place them in series and symmetrically. Test points must not be placed in a manner that causes a stub on the differential pair. 10.2 Layout Examples The board layout for the DS90UB953-Q1EVM is shown in 图 24 and 图 25. All EVM layers are included in DS90UB953-Q1EVM User's Guide (SNLU224). 版权 © 2017–2018, Texas Instruments Incorporated 77 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn Layout Examples (接接下页) Routing the FPD-Link III signal traces between the DOUT pins and the connector, as well as connecting the PoC filter to these traces, are the most critical pieces of a successful DS90UB953-Q1 PCB layout. The following list provides essential recommendations for routing the FPD-Link III signal traces between the driver output pins and the FAKRA connector, as well as connecting the PoC filter. • The routing of the FPD-Link III traces may be all on the top layer or partially embedded in middle layers if EMI is a concern. • The AC-coupling capacitors should be on the top layer and very close to the receiver input pins to minimize the length of coupled differential trace pair between the pins and the capacitors. • Route the DOUT+ trace between the AC-coupling capacitor and the FAKRA connector as a 50-Ω singleended micro-strip with tight impedance control (±10%). Calculate the proper width of the trace for a 50-Ω impedance based on the PCB stack-up. Ensure that the trace can carry the PoC current for the maximum load presented by the remote sensor module. • The PoC filter should be connected to the DOUT+ trace through the ferrite bead or an RF inductor. The ferrite bead should be touching the high-speed trace to minimize the stub length seen by the transmission line. Create an anti-pad or a moat under the ferrite bead pad that touches the trace. The anti-pad should be a plane cutout of the ground plane directly underneath the top layer without cutting out the ground reference under the trace. The purpose of the anti-pad is to maintain the impedance as close to 50 Ω as possible. • When routing DOUT+ on inner layers, length matching for single-ended traces does not provide a significant benefit. If the user wants to route the DOUT+ on the top or bottom layer, route the DOUT- trace loosely coupled to the DOUT+ trace for the length similar to the DOUT+ trace length. This may help the differential nature of the receiver to cancel out any common-mode noise that may be present in the environment that may couple on to the signal traces. AC-Coupling Capacitor on Top Layer Buried FPD-Link III High-speed Trace on Signal Layer 1 图 24. DS90UB953-Q1 Serializer DOUT+ Trace Layout 78 版权 © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 Layout Examples (接接下页) Power-over-Coax Network Placed Close to Connector Coax Connector 图 25. DS90UB953-Q1 Power-over-Coax Layout 版权 © 2017–2018, Texas Instruments Incorporated 79 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn 11 器件和文档支持 11.1 器件支持 11.1.1 开发支持相关开发支持，请参见以下文档： DS90UB953-Q1 11.2 文档支持 11.2.1 相关文档请参阅如下相关文档： • 《如何设计 FPD-Link III 系统》(SNLA267) • 《通过具有双向控制通道的 FPD-Link III 进行 I2C 通信》(SNLA131) • 《I2C 总线上拉电阻器计算》(SLVA689) • FPD-Link 学习中心培训材料 • 《一种适用于 FPD-Link III SerDes 的 EMC/EMI 系统设计和测试方法》(SLYT719) • 《按照车用 EMC/EMI 要求进行成功设计的 10 个技巧》(SLYT636) • 《可与并行输出解串器搭配运行的后向兼容模式》(SNLA270) • 《同轴电缆供电设计指南》(SNLA272) • 《原理图和布局检查清单》(SNLA271) 11.3 接收文档更新通知要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。 11.4 社区资源下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。 TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在 e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。设计支持 TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。 11.5 商标 E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.6 静电放电警告 ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可能会损坏集成电路。 ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可能会导致器件与其发布的规格不相符。 11.7 术语表 SLYZ022 — TI 术语表。这份术语表列出并解释术语、缩写和定义。 80 版权 © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 12 机械、封装和可订购信息以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。版权 © 2017–2018, Texas Instruments Incorporated 81 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn PACKAGE OUTLINE RHB0032P VQFN - 1 mm max height SCALE 2.500 PLASTIC QUAD FLATPACK - NO LEAD 5.1 4.9 A B 0.5 0.3 0.3 0.2 PIN 1 INDEX AREA DETAIL 5.1 4.9 OPTIONAL TERMINAL TYPICAL 0.1 MIN (0.05) SECTION A-A SECTION A-A SCALE 25.000 TYPICAL C 1 MAX SEATING PLANE 0.05 0.00 0.08 C 3.7 0.1 2X 3.5 (0.2) TYP 16 9 8 EXPOSED THERMAL PAD 17 SEE TERMINAL DETAIL 2X 3.5 33 A A 1 24 32X 28X 0.5 32 PIN 1 ID (OPTIONAL) SYMM 25 SYMM 0.5 32X 0.3 0.3 0.2 0.1 0.05 C A B 4223198/A 08/2016 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com 82 版权 © 2017–2018, Texas Instruments Incorporated DS90UB953-Q1 www.ti.com.cn ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 EXAMPLE BOARD LAYOUT RHB0032P VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 3.7) SYMM 25 32 32X (0.6) 1 24 32X (0.25) 4X (1.6) (R0.05) TYP SYMM 33 (1.26) TYP (4.8) 28X (0.5) 17 8 ( 0.2) TYP VIA 16 9 (1.26) TYP 4X (1.6) (4.8) LAND PATTERN EXAMPLE SCALE:15X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4223198/A 08/2016 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com 版权 © 2017–2018, Texas Instruments Incorporated 83 DS90UB953-Q1 ZHCSGW1B – SEPTEMBER 2017 – REVISED SEPTEMBER 2018 www.ti.com.cn EXAMPLE STENCIL DESIGN RHB0032P VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD (1.26) TYP 9X ( 1.06) 32 25 32X (0.6) 1 33 24 32X (0.25) (R0.05) TYP (1.26) TYP SYMM (4.8) 28X (0.5) 17 8 METAL TYP 16 9 SYMM (4.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 33 74% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X 4223198/A 08/2016 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com 84 版权 © 2017–2018, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) DS90UB953TRHBRQ1 ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAU | SN Level-3-260C-168 HR -40 to 105 UB953 DS90UB953TRHBTQ1 ACTIVE VQFN RHB 32 250 RoHS & Green NIPDAU | SN Level-3-260C-168 HR -40 to 105 UB953 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of

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