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DS90UH927Q-Q1
SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
DS90UH927Q-Q1 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP
1 Features
3 Description
•
The DS90UH927Q-Q1 serializer, in conjunction with
a
DS90UH928Q-Q1
or
DS90UH926Q-Q1
deserializer, provides a solution for secure distribution
of content-protected digital video within automotive
entertainment systems. This chipset translates a
FPD-Link video interface into a single-pair high-speed
serialized interface. The digital video data is protected
using the industry standard High-Bandwidth Digital
Content Protection (HDCP) copy protection scheme.
The FPD-Link III serial bus scheme supports full
duplex, high speed forward channel data
transmission
and
low-speed
back
channel
communication over a single differential link.
Consolidation of audio, video, and control data over a
single differential pair reduces the interconnect size
and weight, while also eliminating skew issues and
simplifying system design.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Integrated HDCP Cipher Engine with On-Chip Key
Storage
Bidirectional Control Channel Interface with I2C
Compatible Serial Control Bus
Low EMI FPD-Link Video Input
Supports High Definition (720p) Digital Video
Format
5-MHz to 85-MHz PCLK Supported
RGB888 + VS, HS, DE and I2S Audio Supported
Up to 4 I2S Digital Audio Inputs for Surround
Sound Applications
4 Bidirectional GPIO Channels with 2 Dedicated
Pins
Single 3.3-V Supply with 1.8-V or 3.3-V
Compatible LVCMOS I/O Interface
AC-Coupled STP Interconnect up to 10 Meters
DC-Balanced & Scrambled Data with Embedded
Clock
Supports HDCP Repeater Application
Internal Pattern Generation
Low Power Modes Minimize Power Dissipation
Automotive Grade Product: AEC-Q100 Grade 2
Qualified
> 8-kV HBM and ISO 10605 ESD Rating
Backward Compatible Modes
2 Applications
•
•
The DS90UH927Q-Q1 serializer embeds the clock,
content protects the data payload, and level shifts the
signals to high-speed differential signaling. Up to 24
RGB data bits are serialized along with three video
control signals, and up to four I2S data inputs.
The FPD-Link data interface allows for easy
interfacing with data sources while also minimizing
EMI and bus width. EMI on the high-speed FPD-Link
III bus is minimized using low voltage differential
signaling, data scrambling and randomization, and
dc-balancing.
The HDCP cipher engine is implemented in both the
serializer and deserializer. HDCP keys are stored in
on-chip memory.
Automotive Displays for Navigation
Rear Seat Entertainment Systems
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS90UH927Q-Q1
WQFN (40)
6.00 mm x 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Application Diagram
FPD-Link
FPD-Link
VDDIO
VDD33
(3.3V) (1.8V or 3.3V)
HOST
Graphics
Processor
FPD-Link Display Interface
VDD33
VDDIO
(1.8V or 3.3V) (3.3V)
RxIN3+/-
RxIN1+/RxIN0+/RxCLKIN+/-
TxOUT2+/-
DOUT+
RIN+
DOUT-
RIN100Q STP Cable
DS90UH927Q-Q1
Serializer
PDB
INTB
I2S 6
SCL
SDA
IDx
TxOUT3+/-
FPD-Link III
1 Pair/AC Coupled
RxIN2+/-
MAPSEL
LFMODE
REPEAT
BKWD
OEN
OSS_SEL
PDB
MAPSEL
LFMODE
BISTEN
MODE_SEL
DS90UH928Q-Q1
Deserializer
TxOUT1+/TxOUT0+/-
RGB Display
720p
24-bit Color Depth
TxCLKOUT+/INTB_IN
LOCK
PASS
6
I2S
MCLK
SCL
SDA
IDx
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90UH927Q-Q1
SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
DC Electrical Characteristics .................................... 7
AC Electrical Characteristics..................................... 9
DC and AC Serial Control Bus Characteristics....... 10
Recommended Timing Requirements for the Serial
Control Bus .............................................................. 10
6.9 Timing Requirements .............................................. 11
6.10 Typical Characteristics .......................................... 14
7
Detailed Description ............................................ 15
7.1 Overview ................................................................. 15
7.2
7.3
7.4
7.5
7.6
8
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
15
16
24
30
32
Application and Implementation ........................ 52
8.1 Application Information............................................ 52
8.2 Typical Application .................................................. 52
9 Power Supply Recommendations...................... 54
10 Layout................................................................... 55
10.1 Layout Guidelines ................................................. 55
10.2 Layout Example .................................................... 56
11 Device and Documentation Support ................. 60
11.1
11.2
11.3
11.4
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
60
60
60
60
12 Mechanical, Packaging, and Orderable
Information ........................................................... 60
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June 2013) to Revision C
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Changes from Revision A (November 2012) to Revision B
•
2
Page
Page
Changed layout of National data sheet to TI format............................................................................................................. 56
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SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
5 Pin Configuration and Functions
RxIN0+
RxIN0-
CAPLVD12
INTB
VDD33_B
LFMODE
VDDIO
MAPSEL
BKWD
REPEAT
30
29
28
27
26
25
24
23
22
21
RTA Package
40-Pin WQFN With Exposed Thermal Pad
Top View
RxIN1-
31
20
CMF
RxIN1+
32
19
VDD33_A
RxIN2-
33
18
PDB
RxIN2+
34
17
DOUT+
16
DOUT-
15
RES1
RxCLKINRxCLKIN+
DS90UH927Q-Q1
35
TOP VIEW
36
DAP = GND
9
10
SCL
SDA
8
IDx
CAPL12
11
7
40
VDDIO
GPIO1
6
CAPP12
I2S_DD/GPI03
12
5
39
I2S_DC/GPI02
GPIO0
4
RES0
I2S_DB/GPIO_REG5
13
3
38
I2S_DA/GPIO_REG6
RxIN3+
2
CAPHS12
I2S_CLK/GPIO_REG8
14
1
37
I2S_WC/GPIO_REG7
RxIN3-
Pin Functions
PIN
NAME
I/O, TYPE
NO.
DESCRIPTION
FPD-LINK INPUT INTERFACE
RxCLKIN-
35
I, LVDS
Inverting LVDS Clock Input
The pair requires external 100-Ω differential termination for standard LVDS levels
RxCLKIN+
36
I, LVDS
True LVDS Clock Input
The pair requires external 100-Ω differential termination for standard LVDS levels
RxIN[3:0]-
37, 33, 31, 29
I, LVDS
Inverting LVDS Data Inputs
Each pair requires external 100-Ω differential termination for standard LVDS levels
RxIN[3:0]+
38, 34, 32, 30
I, LVDS
True LVDS Data Inputs
Each pair requires external 100-Ω differential termination for standard LVDS levels
LVCMOS PARALLEL INTERFACE
BKWD
GPIO[1:0]
22
40, 39
I, LVCMOS
w/ pull down
Backward Compatible Mode Select
BKWD = 0, interfacing to DS90UH926/8Q-Q1 (Default)
BKWD = 1, interfacing to DS90UR906/8Q-Q1, DS90UR916Q
Requires a 10-kΩ pullup if set HIGH
I/O, LVCMOS General Purpose I/O
w/ pull down See Table 1
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SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
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Pin Functions (continued)
PIN
I/O, TYPE
DESCRIPTION
NAME
NO.
I2S_DA
I2S_DB
I2S_DC
I2S_DD
3
4
5
6
I, LVCMOS
w/ pull down
Digital Audio Interface I2S Data Inputs
Shared with GPIO_REG6, GPIO_REG5, GPIO2, GPIO3
I2S_WC
I2S_CLK
1
2
I, LVCMOS
w/ pull down
Digital Audio Interface I2S Word Clock and I2S Bit Clock Inputs
Shared with GPIO_REG7 and GPIO_REG8
Table 3
LFMODE
25
I, LVCMOS
w/ pull down
Low Frequency Mode Select
LFMODE = 0, 15 MHz ≤ RxCLKIN ≤ 85 MHz (Default)
LFMODE = 1, 5 MHz ≤ RxCLKIN < 15 MHz
Requires a 10-kΩ pullup if set HIGH
MAPSEL
23
I, LVCMOS
w/ pull down
FPD-Link Input Map Select
MAPSEL = 0, LSBs on RxIN3± (Default)
MAPSEL = 1, MSBs on RxIN3±
See Figure 19 and Figure 20
Requires a 10-kΩ pullup if set HIGH
REPEAT
21
I, LVCMOS
w/ pull down
Repeater Mode Select
REPEAT = 0, Repeater Mode disabled (Default)
REPEAT = 1, Repeater Mode enabled
Requires a 10-kΩ pullup if set HIGH
OPTIONAL PARALLEL INTERFACE
GPIO[3:2]
GPIO_REG[
8:5]
6, 5
2, 1, 3, 4
I/O, LVCMOS General Purpose I/O
w/ pull down Shared with I2S_DD and I2S_DC
See Table 1
I/O, LVCMOS Register-Only General Purpose I/O
w/ pull down Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB
See Table 2
CONTROL AND CONFIGURATION
I2C Address Select
External pullup to VDD33 is required under all conditions. DO NOT FLOAT.
Connect to external pullup to VDD33 and pulldown to GND to create a voltage divider.
See Figure 25 and Table 4
IDx
11
I, Analog
PDB
18
I, LVCMOS
w/ pulldown
SCL
9
I/O, LVCMOS I2C Clock Input / Output Interface
Open Drain Must have an external pullup to VDD33. DO NOT FLOAT.
Recommended pullup: 4.7 kΩ.
SDA
10
I/O, LVCMOS I2C Data Input / Output Interface
Open Drain Must have an external pullup to VDD33. DO NOT FLOAT.
Recommended pullup: 4.7 kΩ.
27
O, LVCMOS
Open Drain
Power-down Mode Input Pin
Must be driven or pulled up to VDD33. Refer to Power Supply Recommendations.
PDB = H, device is enabled (normal operation)
PDB = L, device is powered down.
When the device is in the powered down state, the Driver Outputs are both HIGH, the PLL is
shutdown, and IDD is minimized. Control Registers are RESET.
STATUS
INTB
HDCP Interrupt
INTB = H, normal
INTB = L, Interrupt request
Recommended pullup: 4.7 kΩ to VDDIO. DO NOT FLOAT.
FPD-LINK III SERIAL INTERFACE
CMF
20
Analog
DOUT-
16
I/O, LVDS
Inverting Output
The output must be AC-coupled with a 0.1-µF capacitor.
DOUT+
17
I/O, LVDS
True Output
The output must be AC-coupled with a 0.1-µF capacitor.
4
Common Mode Filter.
Connect 0.1 µF to GND (required)
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SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
Pin Functions (continued)
PIN
NAME
NO.
I/O, TYPE
DESCRIPTION
POWER AND GROUND (1)
GND
VDD33_A
VDD33_B
VDDIO
DAP
Ground
Large metal contact at the bottom center of the device package Connect to the ground
plane (GND) with at least 9 vias.
19
26
Power
Power to on-chip regulator 3.0 V - 3.6 V. Each pin requires a 4.7 µF capacitor to GND
7, 24
Power
LVCMOS I/O Power 1.8 V ±5% OR 3.0 V - 3.6 V. Each pin requires 4.7 µF capacitor to GND
REGULATOR CAPACITOR
CAPP12
CAPHS12
CAPLVD12
12
14
28
CAP
Decoupling capacitor connection for on-chip regulator
Each requires a 4.7-µF decoupling capacitor to GND.
CAPL12
8
CAP
Decoupling capacitor connection for on-chip regulator
Requires two 4.7-µF decoupling capacitors to GND
15, 13
GND
Reserved
Connect to GND.
OTHER
RES[1:0]
(1)
The VDD (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise.
6 Specifications
6.1 Absolute Maximum Ratings (1) (2) (3)
MIN
MAX
UNIT
Supply Voltage – VDD33 (4)
−0.3
4.0
V
Supply Voltage – VDDIO (4)
−0.3
4.0
V
−0.3
(VDDIO +
0.3)
V
−0.3
2.75
V
150
°C
150
°C
LVCMOS I/O Voltage
Serializer Output Voltage
Junction Temperature
−65
Storage Temperature, Tstg
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For soldering specifications, see product folder at www.ti.com and www.ti.com/lit/an/snoa549c/snoa549c.pdf.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
The DS90UH927Q-Q1 VDD33 and VDDIO voltages require a specific ramp rate during power up. The power supply ramp time must be
less than 1.5 ms with a monotonic rise
6.2 ESD Ratings
VALUE
V(ESD)
Electrostatic
discharge
Human body model (HBM), per AEC Q100-002 (1)
±8000
Charged device model (CDM), per AEC Q100-011
±1250
Machine model (MM)
±250
(IEC 61000-4-2, powered-up only)
RD = 330 Ω, CS = 150 pF
(ISO 10605)
RD = 330 Ω, CS = 150 pF/330 pF
RD = 2 kΩ, CS = 150 pF/330 pF
(1)
Air Discharge
(Pin 16 and 17)
±15000
Contact Discharge
(Pin 16 and 17)
±8000
Air Discharge
(Pin 16 and 17)
±15000
Contact Discharge
(Pin 16 and 17)
±8000
UNIT
V
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
MIN
NOM
MAX
3
3.3
3.6
V
Connect VDDIO to 3.3 V and use 3.3-V IOs
3
3.3
3.6
V
Connect VDDIO to 1.8 V and use 1.8-V IOs
1.71
1.8
1.89
V
−40
+25
+105
Supply Voltage (VDD33)
LVCMOS Supply Voltage (VDDIO) (1)
Operating Free Air Temperature (TA)
PCLK Frequency
5
Supply Noise (2)
(1)
(2)
UNIT
°C
85
MHz
100
mVP-P
VDDIO < VDD33 + 0.3 V
Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDD33 and VDDIOsupplies
with amplitude = 100 mVp-p measured at the device VDD33 and VDDIO pins. Bit error rate testing of input to the Ser and output of the
Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 50 MHz. The Des on the other hand shows no
error when the noise frequency is less than 50 MHz.
6.4 Thermal Information
DS90UH927Q-Q1
THERMAL METRIC (1)
RTA (WQFN)
UNIT
40 PINS
RθJA
Junction-to-ambient thermal resistance
29.0
RθJC(top)
Junction-to-case (top) thermal resistance
14.4
RθJB
Junction-to-board thermal resistance
5.1
ψJT
Junction-to-top characterization parameter
0.2
ψJB
Junction-to-board characterization parameter
5.1
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.4
(1)
6
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
6.5 DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX
UNIT
LVCMOS I/O
VIH
High Level Input Voltage
VDDIO = 3.0 V to 3.6 V (4)
2.0
VDDIO
V
VIL
Low Level Input Voltage
VDDIO = 3.0 V to 3.6 V (4)
GND
0.8
V
IIN
Input Current
VIN = 0 V or VDDIO = 3.0 V to
3.6 V (4)
+15
μA
2.0
VDDIO
V
VIH
High Level Input Voltage
0.65×
VDDIO
VDDIO
V
GND
0.8
V
VIL
Low Level Input Voltage
GND
0.35*
VDDIO
V
IIN
Input Current
PDB
−15
VDDIO = 3.0 V to 3.6 V
VOH
GPIO[1:0]
I2S_CLK
I2S_WC
VDDIO = 3.0 V to 3.6 V
I2S_D
[A,B,C,D]
VDDIO = 1.71 V to 1.89 V
LFMODE
VDDIO = 3.0 V MAPSEL
BKWD
to 3.6 V
VIN = 0 V or
REPEAT
VDDIO
VDDIO = 1.71
V to 1.89 V
VDDIO = 1.71 V to 1.89 V
IOH = −4 mA
High Level Output Voltage
IOL = +4 mA
VOL
Low Level Output Voltage
(5)
IOS
Output Short Circuit Current
IOZ
TRI-STATE® Output Current
VDDIO = 3.0 V
to 3.6 V
VDDIO = 1.71
V to 1.89 V
VDDIO = 3.0 V GPIO[3:0],
GPO_REG
to 3.6 V
[8:5]
VDDIO = 1.71
V to 1.89 V
±1
−15
±1
+15
μA
−15
±1
+15
μA
2.4
VDDIO
V
VDDIO 0.45
VDDIO
V
GND
0.4
V
GND
0.45
V
−55
VOUT = 0 V
−15
VOUT = 0 V or VDDIO, PDB = L,
mA
+15
μA
+100
mV
FPD-LINK LVDS RECEIVER
VTH
Threshold High Voltage
VTL
Threshold Low Voltage
|VID|
Differential Input Voltage Swing
VCM
Common Mode Voltage
IIN
Input Current
(1)
(2)
(3)
(4)
(5)
−100
VCM = 1.2 V
RxCLKIN±
RxIN[3:0]±
mV
200
0
−10
600
1.2
mV
2.4
V
+10
μA
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD33 = 3.3V, VDDIO = 1.8V or 3.3V, TA = 25°C, and at the Recommended
Operating Conditions at the time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages. Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal
signal is AC coupled to the supply pins with amplitude = 100 mVp-p measured at the device VDD33 and VDDIO pins. Bit error rate testing
of input to the serializer and output of the deserializer with 10 meter cable shows no error when the noise frequency is less than 50
MHz.
PDB is specified to 3.3-V LVCMOS only and must be driven or pulled up to VDD33 or to VDDIO ≥ 3.0 V
IOS is not specified for an indefinite period of time. Do not hold in short circuit for more than 500 ms or part damage may result
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DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX
UNIT
800
1000
1200 mVp-p
FPD-LINK III CML DRIVER
VODp-p
Differential Output Voltage
(DOUT+) – (DOUT-)
ΔVOD
Output Voltage Unbalance
VOS
Offset Voltage – Single-ended
RL = 100 Ω
1
2.50.25*
VODp-p
RL = 100 Ω
DOUT±
ΔVOS
Offset Voltage Unbalance
Single-ended
IOS
Output Short Circuit Current
RT
Internal Termination Resistance Differential
50
mV
V
(TYP)
1
50
DOUT+/- = 0V, PDB = L or H
mV
mA
100
120
Ω
VDD33= 3.6 V
135
160
mA
VDDIO = 3.6 V
100
500
μA
VDDIO = 1.89 V
200
600
VDD33= 3.6 V
133
mA
VDDIO = 3.6 V
100
μA
VDDIO = 1.89 V
100
VDD33 = 3.6 V
1.2
2.4
mA
VDDIO = 3.6 V
4
30
μA
VDDIO = 1.89 V
5
30
μA
VDD33 = 3.6 V
1
2.2
mA
VDDIO = 3.6 V
8
20
μA
VDDIO = 1.89 V
4
20
μA
80
SUPPLY CURRENT
IDD1
IDDIO1
IDD2
Checkerboard Pattern
Supply Current
RL = 100Ω,
PCLK = 85MHz
IDDIO2
Random Pattern
PRBS7
IDDS
IDDIOS
Supply Current — Remote Auto
Power Down
reg_0x01[7]=1, Back channel
Idle
IDDZ
IDDIOZ
8
Supply Current — Power Down
PDB = 0 V, All other LVCMOS
inputs = 0 V
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μA
μA
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SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
6.6 AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX
UNIT
0.25
0.5
0.75
UI
100
140
ps
100
140
ps
5
ms
FPD-LINK LVDS INPUT
tRSP
Receiver Strobe Position
See Figure 4
RxCLKIN±,
RXIN[3:0]±
FPD-LINK III CML I/O
tLHT
tHLT
CML Output Low-to-High Transition
Time
CML Output High-to-Low Transition
Time
tPLD
Serializer PLL Lock Time
tSD
Delay — Latency
tTJIT
tIJIT
DOUT+,
DOUT-
See Figure 3
See Figure 5,
(4)
PCLK = 5 MHz
to 85 MHz
See Figure 6
Output Total Jitter,
Bit Error Rate ≤1E-9, see Figure 7,
(5)
Checkerboard Pattern
PCLK=5 MHz, see Figure 8
Checkerboard Pattern
PCLK=85 MHz, see Figure 8
(6) (7) (8) (9)
f/40 < Jitter Freq < f/20, DES =
DS90UH926Q-Q1
Input Jitter Tolerance, Bit Error Rate
≤1E-9 (8) (10)
f/40 < Jitter Freq < f/20, DES =
DS90UH928Q-Q1
146*T
ns
0.17
0.2
UI
0.26
0.29
UI
RxCLKIN±
RxCLKIN±, f =
78 MHz
0.6
UI
0.5
UI
>4 /
PCLK or
>77
ns
2
I S RECEIVER
TI2S
I2S Clock Period, see Figure 10,
(7) (11)
THC
I2S Clock High Time, see Figure 10,
RxCLKIN± f=5 MHz to 85 MHz
I2S_CLK,
PCLK = 5 MHz
to 85 MHz
I2S_CLK
0.35
TI2S
I2S_CLK
0.35
TI2S
(11)
TLC
I2S Clock Low Time, see Figure 10,
(11)
2
tsr
I S Set-up Time
I2S_WC
I2S_D[A,B,C,D]
0.2
TI2S
thtr
I2S Hold Time
I2S_WC
I2S_D[A,B,C,D]
0.2
TI2S
OTHER I/O
tGPIO,FC
GPIO Pulse Width, Forward Channel
GPIO[3:0],
PCLK = 5 MHz
to 85 MHz
tGPIO,BC
GPIO Pulse Width, Back Channel
GPIO[3:0]
>2/PCLK
s
20
µs
(1)
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms at VDD33 = 3.3V, VDDIO = 1.8V or 3.3V, TA = 25°C, and at the Recommended
Operating Conditions at the time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages. Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal
signal is AC coupled to the supply pins with amplitude = 100 mVp-p measured at the device VDD33 and VDDIO pins. Bit error rate testing
of input to the serializer and output of the deserializer with 10 meter cable shows no error when the noise frequency is less than 50
MHz.
(4) tPLD is the time required by the device to obtain lock when exiting power-down state with an active PCLK.
(5) Output jitter specs are dependent upon the input clock jitter at the SER.
(6) UI – Unit Interval is equivalent to one ideal serialized bit width. The UI scales with PCLK frequency.
(7) Specification is ensured by design and is not tested in production.
(8) Specification is ensured by characterization and is not tested in production.
(9) tTJIT (@BER of 1E-9) specifies the allowable jitter on RxCLKIN±.
(10) Jitter Frequency is specified in conjunction with DS90UH928Q-Q1 PLL bandwidth.
(11) I2S specifications for tLC and tHC pulses must each be greater than 2 PCLK periods to ensure sampling and supersedes the
0.35*TI2S_CLK requirement. tLC and tHC must be longer than the greater of either 0.35*TI2S_CLK or 2*PCLK.
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Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DS90UH927Q-Q1
9
DS90UH927Q-Q1
SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
www.ti.com
6.7 DC and AC Serial Control Bus Characteristics
Over 3.3-V supply and temperature ranges unless otherwise specified. (1) (2) (3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIH
Input High Level
SDA and SCL
0.7*
VDDIO
VDD33
V
VIL
Input Low Level Voltage
SDA and SCL
GND
0.3*
VDD33
V
VHY
Input Hysteresis
>50
VOL
SDA or SCL, IOL = 1.25 mA
Iin
SDA or SCL, Vin = VDDIO or GND
Cin
(1)
(2)
(3)
Input Capacitance
mV
0
0.36
V
-10
+10
µA
SDA or SCL
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