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DS90UH928Q-Q1
SNLS440C – MARCH 2013 – REVISED JULY 2016
DS90UH928Q-Q1 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With
HDCP
1 Features
2 Applications
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications AEC-Q100
– Device Temperature Grade 2: -40°C to +105°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level ±8 kV
– Device CDM ESD Classification Level C6
Integrated HDCP Cipher Engine with On-Chip Key
Storage
Supports HDCP Repeater Application
Bidirectional Control Channel Interface with I2C
Compatible Serial Control Bus
Low EMI FPD-Link Video Output
Supports High Definition (720p) Digital Video
RGB888 + VS, HS, DE and I2S Audio Supported
5 MHz to 85 MHz Pixel Clock Support
Up to 4 I2S Digital Audio Outputs for Surround
Sound Applications
4 Bidirectional GPIO Channels with 2 Dedicated
Pins
Single 3.3 V supply with 1.8 V or 3.3 V
Compatible LVCMOS I/O Interface
AC-Coupled STP Interconnect Up to 10 Meters
DC-Balanced and Scrambled Data with
Embedded Clock
Adaptive Cable Equalization
Image Enhancement (White Balance & Dithering)
and Internal Pattern Generation
Backward Compatible Modes
Automotive Displays for Navigation
Rear Seat Entertainment Systems
3 Description
The DS90UH928Q-Q1 deserializer, in conjunction
with a DS90UH925Q-Q1 or DS90UH927Q-Q1
serializer, provides a solution for secure distribution of
content-protected digital video and audio within
automotive infotainment systems. The device
converts a high-speed serialized interface with an
embedded clock, delivered over a single signal pair
(FPD-Link III), to four LVDS data/control streams, one
LVDS clock pair (OpenLDI (FPD-Link)), and I2S
audio data. The digital video and audio data is
protected using the industry standard HDCP copy
protection scheme.The serial bus scheme, FPD-Link
III, supports high-speed forward channel data
transmission and low-speed full duplex back channel
communication over a single differential link.
Consolidation of audio, video data and control over a
single differential pair reduces the interconnect size
and weight, while also eliminating skew issues and
simplifying system design.
Adaptive input equalization of the serial input stream
provides compensation for transmission medium
losses and deterministic jitter. EMI is minimized by
the use of low voltage differential signaling.
The HDCP cipher engine is implemented in both the
serializer and deserializer. HDCP keys are stored in
on-chip memory.
Device Information(1)
PART NUMBER
DS90UH928Q-Q1
PACKAGE
WQFN (48)
BODY SIZE (NOM)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Application Diagram
FPD-Link
(OpenLDI)
FPD-Link
VDDIO
VDD33
(3.3V) (1.8V or 3.3V)
HOST
Graphics
Processor
RGB Style Display Interface
VDD33
VDDIO
(1.8V or 3.3V) (3.3V)
RxIN3+/-
RxIN1+/RxIN0+/RxCLKIN+/-
PDB
I2S AUDIO
(Surround)
SCL
SDA
IDx
6
TxOUT3+/-
FPD-Link III
1 Pair/AC Coupled
RxIN2+/-
DOUT+
DOUT-
DS90UH927Q
Serializer
TxOUT2+/-
RIN+
TxOUT1+/TxOUT0+/-
RIN100Q STP Cable
CMF
CMF
OEN
OSS_SEL
PDB
MAPSEL
MAPSEL
LFMODE
LFMODE
REPEAT
REPEAT
BISTEN
BACKWD
MODE_SEL
DS90UH928Q
Deserializer
LVDS Display
720p or Graphic
Processor
TxCLKOUT+/-
6
LOCK
PASS
I2S AUDIO
(Surround)
MCLK
SCL
SDA
IDx
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90UH928Q-Q1
SNLS440C – MARCH 2013 – REVISED JULY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Application Diagram ..............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
8
1
1
1
1
2
4
7
Absolute Maximum Ratings ..................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 8
DC Electrical Characteristics .................................... 9
AC Electrical Characteristics................................... 11
Timing Requirements for the Serial Control Bus .... 12
Timing Requirements .............................................. 12
DC and AC Serial Control Bus Characteristics....... 13
Typical Characteristics .......................................... 17
Detailed Description ............................................ 18
8.1 Overview ................................................................. 18
8.2 Functional Block Diagram ....................................... 18
8.3 Feature Description................................................. 19
8.4 Device Functional Modes........................................ 31
8.5 Programming........................................................... 36
8.6 Register Maps ......................................................... 38
9
Application and Implementation ........................ 55
9.1
9.2
9.3
9.4
Application Information............................................
Typical Application ..................................................
AV Mute Prevention ................................................
OEN Toggling Limitation .........................................
55
55
58
58
10 Power Supply Recommendations ..................... 58
10.1 Power Up Requirements and PDB Pin ................. 58
11 Layout................................................................... 60
11.1 Layout Guidelines ................................................. 60
11.2 Layout Example .................................................... 61
12 Device and Documentation Support ................. 63
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
63
63
63
63
63
63
13 Mechanical, Packaging, and Orderable
Information ........................................................... 63
5 Revision History
Changes from Revision B (January 2015) to Revision C
Page
•
Added "OpenLDI". ................................................................................................................................................................. 1
•
Added AV Mute Prevention section. ...................................................................................................................................... 2
•
Added OEN Toggling Limitation. ........................................................................................................................................... 2
•
Changed the shared function. ............................................................................................................................................... 4
•
Added the shared function ..................................................................................................................................................... 5
•
Changed Pin name .............................................................................................................................................................. 11
•
Added Input Jitter specification. ........................................................................................................................................... 11
•
Added I2S Set-up Time. ...................................................................................................................................................... 12
•
Added I2S Hold Time. ......................................................................................................................................................... 12
•
Added Read Register at the first step. ................................................................................................................................ 26
•
Changed the updated GPIO Configuration table. ................................................................................................................ 27
•
Changed to one tenth of Resistor value ............................................................................................................................... 33
•
Changed and swapped IDEAL RATIO and IDEAL VR2 values. .......................................................................................... 37
•
Changed to one tenth of Resistor value ............................................................................................................................... 37
•
Changed and Revised data to 0x01 ..................................................................................................................................... 43
•
Changed and revised GPIO Direction description. .............................................................................................................. 45
•
Changed and revised Register Type to RW from R. ........................................................................................................... 46
•
Added and disclosed Link Error Count Register. ................................................................................................................ 49
•
Added and disclosed LVDS Setting Register. ..................................................................................................................... 50
•
Changed and revised Register Address. ............................................................................................................................. 52
•
Added AV Mute Prevention section. .................................................................................................................................... 58
•
Added OEN Toggling Limitation. ......................................................................................................................................... 58
•
Changed and updated Power-Up Requirements and PDB. ................................................................................................. 58
2
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SNLS440C – MARCH 2013 – REVISED JULY 2016
Revision History (continued)
Changes from Revision A (April 2013) to Revision B
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
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SNLS440C – MARCH 2013 – REVISED JULY 2016
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6 Pin Configuration and Functions
MAPSEL
CAPLV25
26
25
OEN
30
LOCK
VDD33_B
31
27
LFMODE
32
28
CAPL12
33
CAPLV12
RES0
34
PASS
OSS_SEL
35
29
I2S_DD/GPIO3
36
RHS Package
48-Pin WQFN
Top View
I2S_DC/GPIO2
37
24
TxOUT0-
VDD33_A
38
23
TxOUT0+
RES1
39
22
TxOUT1-
RIN+
40
21
TxOUT1+
RIN-
41
20
TxOUT2-
CMF
42
19
TxOUT2+
BISTC/INTB_IN
43
18
TxCLKOUT-
CMLOUTP
44
17
TxCLKOUT+
CMLOUTN
45
16
TxOUT3-
CAPR12
46
15
TxOUT3+
CAPP12
47
14
GPIO0/SWC
MODE_SEL
48
13
GPIO1/SDOUT
DS90UH928Q-Q1
TOP VIEW
10
11
12
I2S_WC/GPIO_REG7
MCLK
IDx
8
I2S_CLK/GPIO_REG8
9
7
I2S_DA/GPIO_REG6
BISTEN
6
4
SDA
VDDIO
3
I2S_DB/GPIO_REG5
5
2
CAPI2S
SCL
1
PDB
DAP = GND
Pin Functions
PIN
NAME
NO.
I/O, TYPE
DESCRIPTION
FPD-LINK OUTPUT INTERFACE
TxCLKOUT-
18
O, LVDS
Inverting LVDS Clock Output
The pair requires external 100 Ω differential termination for standard LVDS levels
TxCLKOUT+
17
O, LVDS
True LVDS Clock Output
The pair requires external 100 Ω differential termination for standard LVDS levels
TxOUT[3:0]-
16, 20, 22,
24
O, LVDS
Inverting LVDS Data Outputs
Each pair requires external 100 Ω differential termination for standard LVDS levels
TxOUT[3:0]+
15, 19, 21,
23
O, LVDS
True LVDS Data Outputs
Each pair requires external 100 Ω differential termination for standard LVDS levels
LVCMOS INTERFACE
GPIO[1:0]
13, 14
I/O, LVCMOS General Purpose IO
with pulldown Shared with SDOUT, SWC
GPIO[3:2]
36, 37
I/O, LVCMOS General Purpose I/O
with pulldown Shared with I2S_DA I2S_WC
4
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SNLS440C – MARCH 2013 – REVISED JULY 2016
Pin Functions (continued)
PIN
NAME
GPIO_REG[8
:5]
NO.
8, 10, 7, 3
I/O, TYPE
DESCRIPTION
I/O, LVCMOS General Purpose I/O, register access only
with pulldown Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB
I2S_DA
I2S_DB
I2S_DC
I2S_DD
7
3
37
36
O, LVCMOS
Digital Audio Interface I2S Data Outputs
Shared with GPIO_REG6, GPIO_REG5, GPIO2, GPIO3
INTB_IN
43
I, LVCMOS HDCP Interrupt Input
with pulldown Shared with BISTC
MCLK
I2S_WC
I2S_CLK
11
10
8
O, LVCMOS
SDOUT
SWC
13, 14
Digital Audio Interface I2S Master Clock, Word Clock and I2S Bit Clock Outputs
I2S_WC and I2S_CLK are shared with GPIO_REG7 and GPIO_REG8
I/O, LVCMOS Auxiliary Digital Audio Interface I2S Data Output and Word Clock
with pulldown Shared with GPIO1 and GPIO0
CONTROL AND CONFIGURATION
BISTC
43
I, LVCMOS BIST Clock Select
with pulldown Shared with INTB_IN
Requires a 10 kΩ pullup if set HIGH
BISTEN
9
I, LVCMOS BIST Enable
with pulldown Requires a 10 kΩ pullup if set HIGH
IDx
12
LFMODE
32
I, LVCMOS Low Frequency Mode Select
with pulldown LFMODE = 0, 15 MHz ≤ TxCLKOUT ≤ 85 MHz (Default)
LFMODE = 1, 5 MHz ≤ TxCLKOUT < 15 MHz
Requires a 10 kΩ pullup if set HIGH
MAPSEL
26
I, LVCMOS FPD-Link Output Map Select
with pulldown MAPSEL = 0, LSBs on TxOUT3± (Default)
MAPSEL = 1, MSBs on TxOUT3±
Requires a 10 kΩ pullup if set HIGH
MODE_SEL
48
OEN
30
I, LVCMOS Output Enable
with pulldown Requires a 10 kΩ pullup if set HIGH
See Table 5
OSS_SEL
35
I, LVCMOS Output Sleep State Select
with pulldown Requires a 10 kΩ pullup if set HIGH
See Table 5
PDB
1
I, LVCMOS
SCL
5
I/O, Open
Drain
I2C Clock Input/Output Interface
Must have an external pullup to VDD33. DO NOT FLOAT
Recommended pullup: 4.7 kΩ
SDA
4
I/O, Open
Drain
I2C Data Input/Output Interface
Must have an external pullup to VDD33. DO NOT FLOAT
Recommended pullup: 4.7 kΩ
I, Analog
I, Analog
I2C Address Select
External pullup to VDD33 is required under all conditions. DO NOT FLOAT.
Connect to external pullup to VDD33 and pulldown to GND to create a voltage divider.
See Table 7
Device Configuration Select
Configures Backwards Compatibility (BKWD), Repeater (REPEAT), I2S 4-channel (I2S_B),
and Long Cable (LCBL) modes
Connect to external pullup to VDD33 and pulldown to GND resistors to create a voltage
divider. DO NOT FLOAT
See Table 6
Power-down Mode Input Pin
Must be driven or pulled up to VDD33. Refer to Power Up Requirements and PDB PinPower
Up Requirements and PDB Pin in .
PDB = H, device is enabled (normal operation)
PDB = L, device is powered down
When the device is in the powered down state, the LVDS and LVCMOS outputs are tri-state,
the PLL is shutdown, and IDD is minimized. Control Registers are RESET.
STATUS
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Pin Functions (continued)
PIN
I/O, TYPE
DESCRIPTION
NAME
NO.
LOCK
27
O, LVCMOS
LOCK Status Output
0: PLL is unlocked, I2S, GPIO, TxOUT[3:0]±, and TxCLKOUT± are idle with output states
controlled by OEN and OSS_SEL. May be used to indicate Link Status or Display Enable.
1: PLL is locked, outputs are active with output states controlled by OEN and OSS_SEL
Route to test point or pad (Recommended). Float if unused.
PASS
28
O, LVCMOS
PASS Status Output
0: One or more errors were detected in the received BIST payload (BIST Mode)
1: Error-free transmission (BIST Mode)
Route to test point or pad (Recommended). Float if unused.
FPD-LINK III SERIAL INTERFACE
CMF
42
Analog
Common Mode Filter
Requires a 0.1 µF capacitor to GND
CMLOUTN
45
O, LVDS
Inverting Loop-through Driver Output
Monitor point for equalized forward channel differential signal. Connect a 100 Ω resistor
between CMLOUTN and CMLOUTP pins to monitor.
CMLOUTP
44
O, LVDS
True Loop-through Driver Output
Monitor point for equalized forward channel differential signal. Connect a 100 Ω resistor
between CMLOUTN and CMLOUTP pins to monitor.
RIN-
41
I/O, LVDS
FPD-Link III Inverting Input
The output must be AC-coupled with a 0.1 µF capacitor. This pin has 100 Ω (typ.) internal
termination between RIN- and RIN+ pins.
RIN+
40
I/O, LVDS
FPD-Link III True Input
The output must be AC-coupled with a 0.1 µF capacitor. This pin has 100 Ω (typ.) internal
termination between RIN- and RIN+ pins.
POWER AND GROUND (1)
GND
DAP
Ground
Large metal contact at the bottom center of the device package
Connect to the ground plane (GND) with at least 9 vias
VDD33_A
VDD33_B
38
31
Power
3.3 V Power to on-chip regulator
Each pin requires a 4.7 µF capacitor to GND
VDDIO
6
Power
1.8 V/3.3 V LVCMOS I/O Power
Requires a 4.7 µF capacitor to GND
REGULATOR CAPACITOR
CAPI2S
CAPLV25
CAPLV12
CAPR12
CAPP12
2
25
29
46
47
CAP
Decoupling capacitor connection for on-chip regulator
Each requires a 4.7 µF decoupling capacitor to GND
CAPL12
33
CAP
Decoupling capacitor connection for on-chip regulator
Requires two 4.7 µF decoupling capacitors to GND
39, 34
GND
Reserved
Connect to GND
OTHER
RES[1:0]
(1)
6
The VDD (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise.
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SNLS440C – MARCH 2013 – REVISED JULY 2016
7 Specifications
7.1 Absolute Maximum Ratings (1)
(2)
MIN
MAX
UNIT
Supply Voltage – VDD33
(3)
−0.3
4
V
Supply Voltage – VDDIO
(3)
−0.3
4
V
−0.3
(VDDIO +
0.3)
V
−0.3
2.75
V
150
°C
150
°C
LVCMOS I/O Voltage
Deserializer Input Voltage
Junction Temperature
−65
Storage temperature, Tstg
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For soldering specifications, see product folder at www.ti.com and SNOA549.
The DS90UH928Q-Q1VDD33 and VDDIO voltages require a specific ramp rate during power up. The power supply ramp time must be
less than 1.5 ms with a monotonic rise.
7.2 ESD Ratings
V(ESD)
(1)
Electrostatic
discharge
VALUE
UNIT
Human body model (HBM), per AEC Q100-002, all pins (1)
±8000
V
Charged device model (CDM), per AEC Q100-011, all pins
±1250
V
Machine model (MM)
±250
V
±15000
V
(IEC, powered-up only)
RD = 330 Ω, CS = 150 pF
Air Discharge (Pins 40, 41, 44, and 45)
Contact Discharge (Pins 40, 41, 44, and 45)
±8000
V
(ISO10605)
RD = 330 Ω, CS = 150 pF
Air Discharge (Pins 40, 41, 44, and 45)
±15000
V
Contact Discharge (Pins 40, 41, 44, and 45)
±8000
V
(ISO10605)
RD = 2 kΩ, CS = 150 pF or
330 pF
Air Discharge (Pins 40, 41, 44, and 45)
±15000
V
Contact Discharge (Pins 40, 41, 44, and 45)
±8000
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
MIN
NOM
MAX
3
3.3
3.6
V
Connect VDDIO to 3.3 V and use 3.3 V IOs
3
3.3
3.6
V
Connect VDDIO to 1.8 V and use 1.8 V IOs
1.71
1.8
1.89
V
−40
25
105
°C
85
MHz
Supply Voltage (VDD33) (1)
LVCMOS Supply Voltage (VDDIO)
(1) (2)
Operating Free Air
Temperature (TA)
PCLK Frequency (out of TxCLKOUT±)
5
Supply Noise (3)
(1)
(2)
(3)
UNIT
100 mVP-P
The DS90UH928Q-Q1VDD33 and VDDIO voltages require a specific ramp rate during power up. The power supply ramp time must be
less than 1.5 ms with a monotonic rise.
VDDIO should not exceed VDD33 by more than 300 mV (VDDIO < VDD33 + 0.3 V).
Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC-coupled to the VDD33 and VDDIO supplies
with amplitude >100 mVp-p measured at the device VDD33 and VDDIO pins. Bit error rate testing of input to the Ser and output of the
Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 50 MHz. The Des on the other hand shows no
error when the noise frequency is less than 50 MHz.
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7.4 Thermal Information
DS90UH928Q-Q1
THERMAL METRIC (1)
RHS (WQFN)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
26.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
4.4
°C/W
RθJB
Junction-to-board thermal resistance
4.3
°C/W
ψJT
Junction-to-top characterization parameter
0.1
°C/W
ψJB
Junction-to-board characterization parameter
4.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.8
°C/W
(1)
8
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SNLS440C – MARCH 2013 – REVISED JULY 2016
7.5 DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN/FREQ.
(1) (2) (3)
MIN
TYP
MAX
UNIT
2.0
VDDIO
V
GND
0.8
V
+10
μA
3.3 V LVCMOS I/O
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IIN
Input Current
VIH
High Level Input Voltage
2.0
VDDIO
V
VIL
Low Level Input Voltage
GND
0.7
V
IIN
Input Current
VIN = 0 V or VIN = 3.0 V to 3.6 V
+10
μA
VOH
HIGH Level Output Voltage
IOH = -4 mA
VDDIO
V
VOL
LOW Level Output Voltage
IOL = +4 mA
IOS
Output Short Circuit Current
VOUT = 0 V (5)
IOZ
Tri-state Output Current
VOUT = 0 V or VDDIO, PDB = L
(1)
(2)
(3)
(4)
(5)
GPIO[3:0],
REG_GPIO[8:
5], LFMODE,
MAPSEL,
BISTEN,
BISTC,
= 3.0 V to 3.6 V
INTB_IN,
OEN,
OSS_SEL
VDDIO = 3.0 V to 3.6 V
VIN = 0 V or VIN
(4)
PDB
−10
−10
(4)
GPIO[3:0],
REG_GPIO[8:
5], MCLK,
I2S_WC,
I2S_CLK,
I2S_D[A:D],
LOCK, PASS
±1
±1
2.4
0
0.4
−55
−20
V
mA
+20
μA
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD33 = 3.3 V, VDDIO = 1.8 V or 3.3 V, TA = 25°C, and at the Recommended
Operating Conditions at the time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
PDB is specified to 3.3 V LVCMOS only and must be driven or pulled up to VDD33 or to VDDIO ≥ 3.0 V.
IOS is not specified for an indefinite period of time. Do not hold in short circuit for more than 500 ms or part damage may result.
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DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN/FREQ.
(1) (2) (3)
MIN
TYP
MAX
UNIT
1.8 V LVCMOS I/O
VIH
High Level Input Voltage
VDDIO = 1.71 V to 1.89 V
VIL
Low Level Input Voltage
IIN
Input Current
VIN = 0 V or VIN = 1.71 V to
1.89 V
VOH
HIGH Level Output Voltage
IOH = -4 mA
VOL
LOW Level Output Voltage
IOL = +4 mA
IOS
Output Short Circuit Current
VOUT = 0 V (5)
IOZ
TRI-STATE® Output Current
VOUT = 0 V or VDDIO, PDB = L,
GPIO[3:0],
REG_GPIO[8:
5], LFMODE,
MAPSEL,
BISTEN,
BISTC,
INTB_IN,
OEN,
OSS_SEL
0.65 *
VDDIO
VDDIO
V
0
0.35 *
VDDIO
V
-10
10
μA
GPIO[3:0],
REG_GPIO[8:
5], MCLK,
I2S_WC,
I2S_CLK,
I2S_D[A:D],
LOCK, PASS
VDDIO 0.45
VDDIO
V
0
0.45
-35
-20
V
mA
20
μA
FPD-LINK (OpenLDI) LVDS OUTPUT
VOD
VODp-p
Output Voltage Swing (singleended)
Differential Output Voltage
Register 0x4B[1:0] = b'00
RL = 100 Ω
140
200
300
Register 0x4B[1:0] = b'01
RL = 100 Ω
220
300
380
Register 0x4B[1:0] = b'00
RL = 100 Ω
mV
TxCLK±,
TxOUT[3:0]±
400
mV
Register 0x4B[1:0] = b'01
RL = 100 Ω
ΔVOD
Output Voltage Unbalance
VOS
Common Mode Voltage
ΔVOS
Offset Voltage Unbalance
IOS
Output Short Circuit Current
VOUT = GND
IOZ
Output TRI-STATE® Current
OEN = GND, VOUT = VDDIO or
GND, 0.8 V≤VIN≤1.6 V
600
RL = 100 Ω
1.125
1
50
1.25
1.375
1
50
-5
-500
mV
V
mV
mA
500
μA
50
mV
FPD-LINK III RECEIVER
VTH
Input Threshold High
VTL
Input Threshold Low
VID
Input Differential Threshold
VCM
Common-mode Voltage
RT
Internal Termination Resistance
(Differential)
VCM = 2.1 V (Internal VBIAS)
-50
mV
100
RIN±
2.1
80
mV
V
100
120
Ω
VDD33= 3.6 V
190
250
mA
VDDIO = 3.6 V
0.1
1
mA
VDDIO = 1.89 V
0.1
1
mA
VDD33= 3.6 V
185
mA
VDDIO = 3.6 V
0.1
mA
VDDIO = 1.89 V
0.1
SUPPLY CURRENT
IDD1
IDDIO1
IDD2
Checkerboard Pattern
Supply Current
RL = 100 Ω,
PCLK = 85 MHz
Random Pattern
IDDIO2
IDDZ
IDDIOZ
10
Supply Current — Power Down
PDB = 0 V, All other LVCMOS
inputs = 0 V
mA
VDD33 = 3.6 V
3
8
mA
VDDIO = 3.6 V
100
500
μA
VDDIO = 1.89 V
50
250
μA
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7.6 AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
(1) (2) (3)
PIN/FREQ.
MIN
TYP
MAX
UNIT
GPIO[3:0],
PCLK = 5
MHz to 85
MHz
2/PCLK
s
20
µs
2
ms
GPIO
tGPIO,FC
GPIO Pulse Width, Forward
Channel
See
(4)
tGPIO,BC
GPIO Pulse Width, Back Channel
See
(4)
GPIO[3:0]
PDB Reset Low Pulse
See
(4)
PDB
RESET
tLRST
LOOP-THROUGH MONITOR OUTPUT
EW
Differential Output Eye Opening
Width
EH
Differential Output Eye Height
RL = 100 Ω, Jitter freq > f/40
CMLOUTP,
CMLPUTN
0.4
UI
300
mV
FPD-LINK LVDS OUTPUT
tTLHT
Low to High Transition Time
tTHLT
High to Low Transition Time
tDCCJ
Cycle-to-Cycle Output Jitter
RL = 100 Ω
TxCLK±,
TxOUT[3:0]±
0.25
PCLK = 5 MHz
TxCLK±
PCLK = 85 MHz
tTTPn
Transmitter Pulse Position
5 MHz ≤ PCLK ≤ 85 MHz
n = [6:0] for bits [6:0]
See Figure 13
ΔtTTP
Offset Transmitter Pulse Position
(bit 6 - bit 0)
PCLK = 85 MHz
tDD
Delay Latency
tTPDD
Power Down Delay Active to OFF
tTXZR
Enable Delay OFF to Active
TxOUT[3:0]±
0.5
ns
0.25
0.5
ns
170
275
ps
35
55
0.5 + n
UI
0.1
UI
147*T
T
900
µs
6
ns
FPD-LINK III INPUT
IJT
Input Jitter (5)
PCLK = 5 MHz to 85 MHz
Sinusoidal Jitter Frequency >
PCLK / 15
RIN±
tDDLT
Lock Time (4)
5 MHz ≤ PCLK ≤ 85 MHz
RIN±, LOCK
CL = 8 pF
LOCK, PASS
0.35
UI
6
40
ms
3
7
ns
2
5
ns
LVCMOS OUTPUTS
tCLH
Low-to-High Transition Time
tCHL
High-to-Low Transition Time
BIST MODE
tPASS
BIST PASS Valid Time
PASS
800
ns
2
ns
2/PCLK
or >77
ns
I2S TRANSMITTER
tJ
Clock Output Jitter
TI2S
I2S Clock Period
Figure 10, (4) (6)
THC
I2S Clock High Time
Figure 10, (6)
(1)
(2)
(3)
(4)
(5)
(6)
MCLK
PCLK=5 MHz to 85 MHz
I2S_CLK,
PCLK = 5
MHz to 85
MHz
I2S_CLK
0.35
TI2S
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD33 = 3.3 V, VDDIO = 1.8 V or 3.3 V, TA = 25°C, and at the Recommended
Operating Conditions at the time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
Specification is ensured by design and is not tested in production.
UI – Unit Interval is equivalent to one serialized data bit width 1UI = 1 / (35 × PCLK). The UI scales with PCLK frequency.
I2S specifications for tLC and tHC pulses must each be greater than 1 PCLK period to ensure sampling and supersedes the 0.35*TI2S_CLK
requirement. tLC and tHC must be longer than the greater of either 0.35*TI2S_CLK or 2*PCLK.
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AC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN/FREQ.
TLC
I2S Clock Low Time
Figure 10, (6)
I2S_CLK
tSR_I2S
I2S Set-up Time
Figure 10, (6)
tHR_I2S
I2S Hold Time
Figure 10, (6)
(1) (2) (3)
MIN
TYP
MAX
UNIT
0.35
TI2S
I2S_WC
I2S_D[A:D]
0.2
TI2S
I2S_WC
I2S_D[A:D]
0.2
TI2S
7.7 Timing Requirements for the Serial Control Bus
Over 3.3-V supply and temperature ranges unless otherwise specified.
(1) (2)
MIN
fSCL
SCL Clock Frequency
tLOW
tHIGH
tHD;STA
tSU:STA
tHD;DAT
tBUF
tr
(1)
(2)
(3)
100
kHz
Fast Mode
0
400
kHz
µs
Fast Mode
1.3
µs
Standard Mode
4.0
µs
Fast Mode
0.6
µs
Hold time for a start or a
repeated start condition
Standard Mode
4.0
µs
(3)
Fast Mode
0.6
µs
Set Up time for a start or a
repeated start condition
Standard Mode
4.7
µs
(3)
Fast Mode
0.6
µs
Data Hold Time
Standard Mode
SCL Low Period
SCL High Period
Data Set Up Time
Fast Mode
0
3.45
µs
0
0.9
µs
Standard Mode
250
Fast Mode
100
ns
ns
4
µs
Set Up Time for STOP
Condition
Standard Mode
(3)
Fast Mode
0.6
µs
Bus Free Time
Between STOP and START
Standard Mode
4.7
µs
(3)
Fast Mode
1.3
µs
SCL & SDA Rise Time,
Standard Mode
(3)
SCL & SDA Fall Time,
tf
TYP
4.7
(3)
tSU;STO
UNIT
0
Standard Mode
(3)
tSU;DAT
MAX
Standard Mode
(3)
1000
ns
Fast Mode
300
ns
Standard Mode
300
ns
Fast mode
300
ns
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD33 = 3.3 V, VDDIO = 1.8 V or 3.3 V, TA = +25°C, and at the Recommended
Operating Conditions at the time of product characterization and are not ensured.
Specification is ensured by design and is not tested in production.
7.8 Timing Requirements
MIN
tR
SDA RiseTime – READ
tF
SDA Fall Time – READ
tSU;DAT
Set Up Time – READ
tHD;DAT
Hold Up Time – READ
12
NOM
MAX
UNIT
430
ns
20
ns
Figure 16
560
ns
Figure 16
615
ns
SDA, RPU = 10 kΩ, Cb ≤
400 pF, Figure 16
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7.9 DC and AC Serial Control Bus Characteristics
Over 3.3 V supply and temperature ranges unless otherwise specified.
PARAMETER
(1) (2) (3)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIH
Input High Level
SDA and SCL
0.7*
VDDIO
VDD33
V
VIL
Input Low Level Voltage
SDA and SCL
GND
0.3*
VDD33
V
VHY
Input Hysteresis
50
VOL
SDA or SCL, IOL = 1.25 mA
Iin
SDA or SCL, VIN = VDDIO or GND
tSP
Input Filter
Cin
Input Capacitance
(1)
(2)
(3)
mV
0
0.36
V
-10
10
µA
SDA or SCL
50
ns
5
pF
The Electrical Characteristics tables list specifications under the listed Recommended Operating Conditions except as otherwise
modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not
ensured.
Typical values represent most likely parametric norms at VDD33 = 3.3 V, VDDIO = 1.8 V or 3.3 V, TA = +25°C, and at the Recommended
Operating Conditions at the time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
+VOD
TxCLKOUT
-VOD
+VOD
TxOUT3
-VOD
+VOD
TxOUT2
-VOD
+VOD
TxOUT1
-VOD
+VOD
TxOUT0
-VOD
Cycle N+1
Cycle N
Figure 1. Checkerboard Data Pattern
EW
VOD (+)
RIN
(Diff.)
EH
0V
EH
VOD (-)
tBIT (1 UI)
Figure 2. CML Output Driver
VDDIO
80%
20%
GND
tCLH
tCHL
Figure 3. LVCMOS Transition Times
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START
STOP
BIT SYMBOL N+3 BIT
§
§
§
START
STOP
BIT SYMBOL N+2 BIT
§
§
START
STOP
BIT SYMBOL N+1 BIT
§
START
STOP
BIT SYMBOL N BIT
RIN
§
§
DCA, DCB
tDD
TxCLKOUT
TxOUT[3:0]
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
SYMBOL N
Figure 4. Latency Delay
PDB
VILmax
RIN
X
tTPDD
LOCK
Z
PASS
Z
TxCLKOUT
Z
TxOUT[3:0]
Z
Figure 5. FPD-Link & LVCMOS Power Down Delay
PDB
LOCK
tTXZR
OEN
VIHmin
Z
TxCLKOUT
Z
TxOUT[3:0]
Figure 6. FPD-Link Outputs Enable Delay
PDB
VIH(min)
RIN±
tDDLT
LOCK
VOH(min)
TRI-STATE
Figure 7. CML PLL Lock Time
14
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RIN+
VTL
VCM
VTH
RIN-
GND
Figure 8. FPD-Link III Receiver DC VTH/VTL Definition
VDDIO
I2S_CLK,
MCLK
1/2 VDDIO
GND
GPIO,
I2S_WC,
I2S_D[D:A]
VDDIO
VOHmin
VOLmax
GND
tROH
tROS
Figure 9. Output Data Valid (Setup and Hold) Times
tI2S
tLC_I2S
tHC_I2S
VIH
I2S_CLK
VIL
tSR_I2S
tHR_I2S
VIH
I2S_WC
I2S_D[A,B,C,D]
VIL
Figure 10. Output State (Setup and Hold) Times
+VOD
80%
TxOUT[3:0]
TxCLKOUT
(Differential)
0V
20%
-VOD
tLHT
tHLT
TxOUT[3:0]+
TxCLKOUT+
TxOUT[3:0]TxCLKOUT-
Single-Ended
Figure 11. Input Transition Times
VOD-
VOD+
VOS
(TxOUT[3:0]+) (TxOUT[3:0]-) or
(TxCLKOUT+) (TxCLKOUT-)
VOD+
VODp-p
0V
VOD-
Differential
GND
Figure 12. FPD-Link Single-Ended and Differential Waveforms
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T
TxCLKOUT±
bit 1
TxOUT[3:0]±
bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
tTTP1
0.5UI
tTTP2
1.5UI
tTTP3
2.5UI
3.5UI
2¨tTTP
tTTP4
tTTP5
4.5UI
tTTP6
5.5UI
tTTP7
6.5UI
Figure 13. FPD-Link Transmitter Pulse Positions
Ideal Data
Bit End
Sampling
Window
Ideal Data Bit
Beginning
RxIN_TOL
Left
VTH
0V
VTL
RxIN_TOL
Right
Ideal Center Position (tBIT/2)
tBIT (1 UI)
tIJIT
= RxIN_TOL (Left + Right)
- tIJIT
Sampling Window = 1 UI
Figure 14. Receiver Input Jitter Tolerance
BISTEN
1/2 VDDIO
tPASS
PASS
(w/errors)
1/2 VDDIO
Prior BIST Result
Current BIST Test - Toggle on Error
Result Held
Figure 15. BIST PASS Waveform
SDA
tf
tHD;STA
tLOW
tr
tr
tBUF
tf
SCL
tSU;STA
tHD;STA
tHIGH
tHD;DAT
START
tSU;STO
tSU;DAT
STOP
REPEATED
START
START
Figure 16. Serial Control Bus Timing Diagram
16
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7.10 Typical Characteristics
Input to Serializer
Output at Deserializer
Figure 17. Serializer Output Stream with 48 MHz Input Clock
Figure 18. 48 MHz Clock at Serializer and Deserializer
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8 Detailed Description
8.1 Overview
The DS90UH928Q-Q1 receives a 35-bit symbol over a single serial FPD-Link III pair operating at up to 2.975
Gbps line rate and converts this stream into an FPD-Link Interface (4 LVDS data channels + 1 LVDS Clock). The
FPD-Link III serial stream contains an embedded clock, video control signals, and the DC-balanced video data
and audio data which enhance signal quality to support AC coupling.
The DS90UH928Q-Q1 deserializer attains lock to a data stream without the use of a separate reference clock
source, which greatly simplifies system complexity and overall cost. The deserializer also synchronizes to the
serializer regardless of the data pattern, delivering true automatic plug and lock performance. It can lock to the
incoming serial stream without the need of special training patterns or sync characters. The deserializer recovers
the clock and data by extracting the embedded clock information, validating then deserializing the incoming data
stream. It also applies decryption through a High-Bandwidth Digital Content Protection (HDCP) Cipher to this
video and audio data stream following reception of the data from the FPD-Link III decoder. On-chip non-volatile
memory stores the HDCP keys. All key exchange is done through the FPD-Link III bidirectional control interface.
The decrypted FPD-Link LVDS video bus is provided to the display.
The DS90UH928Q-Q1 deserializer incorporates an I2C-compatible interface. The I2C-compatible interface allows
programming of serializer or deserializer devices from a local host controller. In addition, the
serializer/deserializer devices incorporate a bidirectional control channel (BCC) that allows communication
between serializer/deserializer as well as remote I2C slave devices.
The bidirectional control channel (BCC) is implemented via embedded signaling in the high-speed forward
channel (serializer to deserializer) combined with lower speed signaling in the reverse channel (deserializer to
serializer). Through this interface, the BCC provides a mechanism to bridge I2C transactions across the serial link
from one I2C bus to another. The implementation allows for arbitration with other I2C compatible masters at either
side of the serial link.
The DS90UH928Q-Q1 deserializer is intended for use with DS90UH925Q-Q1 or DS90UH927Q-Q1 serializers,
but is also backward compatible with DS90UR905Q and DS90UR907Q FPD-Link II serializers.
8.2 Functional Block Diagram
OEN
OSS_SEL
REGULATOR
Parallel to Serial
RIN-
TxOUT3±
HDCP Cipher
RIN+
DC Balance Decoder
Serial to Parallel
CMF
TxOUT2±
TxOUT1±
TxOUT0±
TxCLKOUT±
8
BISTEN
BISTC
LFMODE
MAPSEL
PDB
SCL
SCA
IDx
MODE_SEL
18
Error
Detector
Timing and
Control
Clock and
Data
Recovery
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PASS
LOCK
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8.3 Feature Description
8.3.1 High Speed Forward Channel Data Transfer
The High-Speed Forward Channel is composed of a 35-bit frame containing video data, sync signals, HDCP, I2C,
and I2S audio transmitted from serializer to deserializer. Figure 19 illustrates the serial stream PCLK cycle. This
data payload is optimized for signal transmission over an AC-coupled link. Data is randomized, DC-balanced and
scrambled.
C0
C1
Figure 19. FPD-Link III Serial Stream
The device supports pixel clock ranges of 5 MHz to 15 MHz (LFMODE=1) and 15 MHz to 85 MHz (LFMODE=0).
This corresponds to an application payload rate range of 175 Mbps to 2.975 Gbps, with an actual line rate range
of 525 Mbps to 2.975 Gbps.
8.3.2 Low-Speed Back Channel Data Transfer
The Low-Speed Back Channel of the DS90UH928Q-Q1 provides bidirectional communication between the
display and host processor. The back channel control data is transferred over the single serial link along with the
high-speed forward data, DC balance coding and embedded clock information. Together, the forward channel
and back channel for the bidirectional control channel (BCC). This architecture provides a backward path across
the serial link together with a high speed forward channel. The back channel contains the I2C, HDCP, CRC and 4
bits of standard GPIO information with 10 Mbps line rate.
8.3.3 Backward Compatible Mode
The DS90UH928Q-Q1 is also backward compatible to the DS90UR905Q and DS90UR907Q FPD-Link II
serializes with 15 MHz to 65 MHz PCLK frequencies supported. It receives 28-bits of data over a single serial
FPD-Link II pair operating at a payload rate of 420 Mbps to 1.82 Gbps. This backward compatibility configuration
is provided through the MODE_SEL pin or programmed through the device control registers (Table 8). The
bidirectional control channel, HDCP, bidirectional GPIOs, I2S, and interrupt (INTB) are not active in this mode.
However, local I2C access to the serializer is still available.
8.3.4 Input Equalization
An FPD-Link III input adaptive equalizer provides compensation for transmission medium losses and reduces
medium-induced deterministic jitter. It supports STP cables up to 10 meters total cable length with 3 inline
connectors at maximum serializer stream payload rate of 2.975 Gbps.
The adaptive equalizer may be set to a Long Cable Mode (LCBL), using the MODE_SEL pin (Table 6). This
mode is typically used with longer cables where it may be desirable to start adaptive equalization from a higher
default gain. In this mode, the device attempts to lock from a minimum floor AEQ value, defined by a value
stored in the control registers (Table 8).
8.3.5 Common Mode Filter Pin (CMF)
The deserializer provides access to the center tap of the internal CML termination. A 0.1 μF capacitor must be
connected from this pin to GND for additional common-mode filtering of the differential pair (Figure 39). This
increases noise rejection capability in high-noise environments.
8.3.6 Power Down (PDB)
The deserializer has a PDB input pin to enable or power down the device. This pin may be controlled by an
external device, or through VDDIO, where VDDIO = 3 V to 3.6 V or VDD33. To save power, disable the link when the
display is not needed (PDB = LOW). Ensure that this pin is not driven HIGH before VDD33 and VDDIO have
reached final levels. When PDB is driven low, ensure that the pin is driven to 0 V for at least 1.5 ms before
releasing or driving high (See ). If the PDB is pulled up to VDDIO = 3 V to 3.6 V or VDD33 directly, a 10 kΩ pullup
resistor and a >10 µF capacitor to ground are required (see Figure 39 ).
Toggling PDB low will POWER DOWN the device and RESET all control registers to default. During this time,
PDB must be held low for a minimum of 2 ms (see ).
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Feature Description (continued)
8.3.7 Video Control Signals
The video control signal bits embedded in the high-speed FPD-Link LVDS are subject to certain limitations
relative to the video pixel clock period (PCLK). By default, the device applies a minimum pulse width filter on
these signals to help eliminate spurious transitions.
Normal Mode Control Signals (VS, HS, DE) have the following restrictions:
• Horizontal Sync (HS): The video control signal pulse width must be 3 PCLKs or longer when the Control
Signal Filter (register bit 0x03[4]) is enabled (default). Disabling the Control Signal Filter removes this
restriction (minimum is 1 PCLK). See Table 8. HS can have at most two transitions per 130 PCLKs.
• Vertical Sync (VS): The video control signal pulse is limited to 1 transition per 130 PCLKs. Thus, the minimum
pulse width is 130 PCLKs.
• Data Enable Input (DE): The video control signal pulse width must be 3 PCLKs or longer when the Control
Signal Filter (register bit 0x03[4]) is enabled (default). Disabling the Control Signal Filter removes this
restriction (minimum is 1 PCLK). See Table 8. DE can have at most two transitions per 130 PCLKs.
8.3.8 EMI Reduction Features
8.3.8.1 LVCMOS VDDIO Option
The 1.8 V/3.3 V LVCMOS inputs and outputs are powered from a separate VDDIO supply pin to offer
compatibility with external system interface signals. Note: When configuring the VDDIO power supplies, all the
single-ended control input pins (except PDB) for device need to scale together with the same operating VDDIO
levels. If VDDIO is selected to operate in the 3.0 V to 3.6 V range, VDDIO must be operated within 300 mV of VDD33
(See Recommended Operating Conditions).
8.3.9 Built In Self Test (BIST)
An optional At-Speed Built-In Self Test (BIST) feature supports testing of the high-speed serial link and the lowspeed back channel without external data connections. This is useful in the prototype stage, equipment
production, in-system test, and system diagnostics.
8.3.9.1 BIST Configuration and Status
The BIST mode is enabled at the deserializer by pin (BISTEN) or BIST configuration register. The test may
select either an external PCLK or the 33 MHz internal oscillator clock (OSC) frequency. In the absence of PCLK,
the user can select the internal OSC frequency at the deserializer through the BISTC pin or BIST configuration
register.
When BIST is activated at the deserializer, a BIST enable signal is sent to the serializer through the back
channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test
pattern and monitors it for errors. The deserializer PASS output pin toggles to flag each frame received
containing one or more errors. The serializer also tracks errors indicated by the CRC fields in each back channel
frame.
The BIST status can be monitored real time on the deserializer PASS pin, with each detected error resulting in a
half pixel clock period toggled LOW. After BIST is deactivated, the result of the last test is held on the PASS
output until reset (new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low
on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width
applied to the deserializer BISTEN pin. LOCK status is valid throughout the entire duration of BIST.
See Figure 20 for the BIST mode flow diagram.
8.3.9.1.1 Sample BIST Sequence
1. BIST Mode is enabled via the BISTEN pin of Deserializer. The desired clock source is selected through the
deserializer BISTC pin.
2. The serializer is awakened through the back channel if it is not already on. An all-zeros pattern is balanced,
scrambled, randomized, and sent through the FPD-Link III interface to the deserializer. Once the serializer
and the deserializer are in BIST mode and the deserializer acquires LOCK, the PASS pin of the deserializer
goes high, and BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the
PASS pin switches low for one half of the clock period. During the BIST test, the PASS output can be
20
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Feature Description (continued)
monitored and counted to determine the payload error rate.
3. To stop BIST mode, set the BISTEN pin LOW. The deserializer stops checking the data, and the final test
result is held on the PASS pin. If the test ran error free, the PASS output remains HIGH. If there one or more
errors were detected, the PASS output outputs constant LOW. The PASS output state is held until a new
BIST is run, the device is RESET, or the device is powered down. BIST duration is user-controlled and may
be of any length.
The link returns to normal operation after the deserializer BISTEN pin is low. Figure 21 shows the waveform
diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In
most cases it is difficult to generate errors due to the robustness of the link (differential data transmission, and so
forth), thus they may be introduced by greatly extending the cable length, faulting the interconnect medium, or
reducing signal condition enhancements (Rx equalization).
Normal
Step 1: DES in BIST
BIST
Wait
Step 2: Wait, SER in BIST
BIST
start
Step 3: DES in Normal
Mode - check PASS
BIST
stop
Step 4: DES/SER in Normal
Figure 20. BIST Mode Flow Diagram
8.3.9.2 Forward Channel and Back Channel Error Checking
The deserializer, on locking to the serial stream, compares the recovered serial stream with all zeroes and
records any errors in status registers. Errors are also dynamically reported on the PASS pin of the deserializer.
Forward channel errors may also be read from register 0x25 (Table 8).
The back-channel data is checked for CRC errors once the serializer locks onto the back-channel serial stream,
as indicated by link detect status (register bit 0x1C[0] - Table 8). CRC errors are recorded in an 8-bit register in
the deserializer. The register is cleared when the serializer enters the BIST mode. As soon as the serializer
enters BIST mode, the functional mode CRC register starts recording any back channel CRC errors. The BIST
mode CRC error register is active in BIST mode only and keeps the record of the last BIST run until cleared or
the serializer enters BIST mode again.
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Feature Description (continued)
DES Outputs
BISTEN
(DES)
TxCLKOUT
Case 1 - Pass
TxOUT[3:0]
7 bits/frame
DATA
(internal)
PASS
Prior Result
PASS
DATA
(internal)
PASS
X
X
X
FAIL
Prior Result
Normal
SSO
Case 2 - Fail
X = bit error(s)
BIST Test
BIST Duration
BIST
Result
Held
Normal
Figure 21. BIST Waveforms
8.3.10 Internal Pattern Generation
The DS90UH928Q-Q1 deserializer features an internal pattern generator. It allows basic testing and debugging
of an integrated panel. The test patterns are simple and repetitive and allow for a quick visual verification of
panel operation. As long as the device is not in power down mode, the test pattern will be displayed even if no
input is applied. If no clock is received, the test pattern can be configured to use a programmed oscillator
frequency. For detailed information, refer to TI Application Note: (AN-2198).
8.3.10.1 Pattern Options
The DS90UH928Q-Q1 deserializer pattern generator is capable of generating 17 default patterns for use in basic
testing and debugging of panels. Each pattern can be inverted using register bits (see Table 8). The 17 default
patterns are listed as follows:
1. White/Black (default/inverted)
2. Black/White
3. Red/Cyan
4. Green/Magenta
5. Blue/Yellow
6. Horizontally Scaled Black to White/White to Black
7. Horizontally Scaled Black to Red/Cyan to White
8. Horizontally Scaled Black to Green/Magenta to White
9. Horizontally Scaled Black to Blue/Yellow to White
10. Vertically Scaled Black to White/White to Black
11. Vertically Scaled Black to Red/Cyan to White
12. Vertically Scaled Black to Green/Magenta to White
13. Vertically Scaled Black to Blue/Yellow to White
14. Custom Color / Inverted configured in PGRS
15. Black-White/White-Black Checkerboard (or custom checkerboard color, configured in PGCTL)
16. YCBR/RBCY VCOM pattern, orientation is configurable from PGCTL
17. Color Bars (White, Yellow, Cyan, Green, Magenta, Red, Blue, Black) – Note: not included in the autoscrolling feature
22
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Feature Description (continued)
8.3.10.2 Color Modes
By default, the Pattern Generator operates in 24-bit color mode, where all bits of the Red, Green, and Blue
outputs are enabled. 18-bit color mode can be activated from the configuration registers (Table 8). In 18-bit
mode, the 6 most significant bits (bits 7-2) of the Red, Green, and Blue outputs are enabled; the 2 least
significant bits are 0.
8.3.10.3 Video Timing Modes
The Pattern Generator has two video timing modes – external and internal. In external timing mode, the Pattern
Generator detects the video frame timing present on the DE and VS inputs. If Vertical Sync signaling is not
present on VS, the Pattern Generator determines Vertical Blank by detecting when the number of inactive pixel
clocks (DE = 0) exceeds twice the detected active line length. In internal timing mode, the Pattern Generator
uses custom video timing as configured in the control registers. The internal timing generation may also be
driven by an external clock. By default, external timing mode is enabled. Internal timing or Internal timing with
External Clock are enabled by the control registers (Table 8). If internal clock generation is used, register 0x39
bit 1 must be set.
8.3.10.4 External Timing
In external timing mode, the pattern generator passes the incoming DE, HS, and VS signals unmodified to the
video control outputs after a two-pixel clock delay. It extracts the active frame dimensions from the incoming
signals in order to properly scale the brightness patterns. If the incoming video stream does not use the VS
signal, the Pattern Generator determines the Vertical Blank time by detecting a long period of pixel clocks without
DE asserted.
8.3.10.5 Pattern Inversion
The Pattern Generator also incorporates a global inversion control, located in the PGCFG register, which causes
the output pattern to be bitwise-inverted. For example, the full-screen Red pattern becomes full-screen cyan, and
the Vertically Scaled Black to Green pattern becomes Vertically Scaled White to Magenta.
8.3.10.6 Auto Scrolling
The Pattern Generator supports an Auto-Scrolling mode, in which the output pattern cycles through a list of
enabled pattern types. A sequence of up to 16 patterns may be defined in the registers. The patterns may
appear in any order in the sequence and may also appear more than once.
8.3.10.7 Additional Features
Additional pattern generator features can be accessed through the Pattern Generator Indirect Register Map. It
consists of the Pattern Generator Indirect Address (PGIA — Table 8) and the Pattern Generator Indirect Data
(PGID — Table 8).
8.3.11 Image Enhancement Features
Several image enhancement features are provided. The White Balance LUTs allow the user to define and map
the color profile of the display. Adaptive Hi-FRC Dithering enables the presentation of 'true color' images on an
18-bit display.
8.3.11.1 White Balance
The White Balance feature enables similar display appearance when using LCD’s from different vendors. It
compensates for native color temperature of the display, and adjusts relative intensities of R, G, and B to
maintain specified color temperature. Programmable control registers are used to define the contents of three
LUTs (8-bit color value for Red, Green and Blue) for the White Balance Feature. The LUTs map input RGB
values to new output RGB values. There are three LUTs, one LUT for each color. Each LUT contains 256
entries, 8-bits per entry with a total size of 6144 bits (3 x 256 x 8). All entries are readable and writable.
Calibrated values are loaded into registers through the I2C interface (deserializer is a slave device). This feature
may also be applied to lower color depth applications such as 18–bit (666) and 16–bit (565). White balance is
enabled and configured via serial control bus register.
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Feature Description (continued)
8.3.11.1.1 LUT Contents
The user must define and load the contents of the LUT for each color (R,G,B). Regardless of the color depth
being driven (888, 666, 656), the user must always provide contents for 3 complete LUTs - 256 colors x 8 bits x 3
tables. Unused bits - LSBs -shall be set to “0” by the user.
When 24-bit (888) input data is being driven to a 24-bit display, each LUT (R, G and B) must contain 256 unique
8-bit entries. The 8-bit white balanced data is then available at the output of the deserializer, and driven to the
display.
The user must define and load the contents of the LUT for each color (R,G,B). Regardless of the color depth
being driven (888, 666, 656), the user must always provide contents for 3 complete LUTs - 256 colors x 8 bits x 3
tables. Unused bits - LSBs -shall be set to “0” by the user. When 24-bit (888) input data is being driven to a 24bit display, each LUT (R, G and B) must contain 256 unique 8-bit entries. The 8-bit white balanced data is then
available at the output of the deserializer, and driven to the display.
Alternatively, with 6-bit input data the user may choose to load complete 8-bit values into each LUT. This mode
of operation provides the user with finer resolution at the LUT output to more closely achieve the desired white
point of the calibrated display. Although 8-bit data is loaded, only 64 unique 8-bit white balance output values are
available for each color (R, G and B). The result is 8-bit white balanced data. Before driving to the output of the
deserializer, the 8-bit data must be reduced to 6-bit with an FRC dithering function. To operate in this mode, the
user must configure the deserializer to enable the FRC2 function.
Examples of the three types of LUT configurations described are shown in Figure 22.
8.3.11.1.2 Enabling White Balance
The user must load all 3 LUTs prior to enabling the white balance feature. The following sequence must be
followed by the user.
To initialize white balance after power-on:
1. Load contents of all 3 LUTs . This requires a sequential loading of LUTs - first RED, second GREEN, third
BLUE. 256, 8-bit entries must be loaded to each LUT. Page registers must be set to select each LUT.
2. Enable white balance. By default, the LUT data may not be reloaded after initialization at power-on.
An option does exist to allow LUT reloading after power-on and initial LUT loading (as described above). This
option may only be used after enabling the white balance reload feature via the associated serial control bus
register. In this mode the LUTs may be reloaded by the master controller via I2C. This provides the user with the
flexibility to refresh LUTs periodically , or upon system requirements to change to a new set of LUT values. The
host controller loads the updated LUT values via the serial bus interface. There is no need to disable the white
balance feature while reloading the LUT data. Refreshing the white balance to the new set of LUT data will be
seamless - no interruption of displayed data.
It is important to note that initial loading of LUT values requires that all 3 LUTs be loaded sequentially. When
reloading, partial LUT updates may be made.
24
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Feature Description (continued)
8-bit in / 8 bit out
Gray level
Entry
Data Out
(8-bits)
00000000b
N/A
N/A
N/A
00000100b
N/A
N/A
N/A
00001000b
N/A
N/A
N/A
248
249
250
251
252
253
254
255
11111000b
N/A
N/A
N/A
11111100b
N/A
N/A
N/A
0
1
2
3
4
5
6
7
8
9
10
11
00000001b
N/A
N/A
N/A
00000110b
N/A
N/A
N/A
00001011b
N/A
N/A
N/A
248
249
250
251
252
253
254
255
11111010b
N/A
N/A
N/A
11111111b
N/A
N/A
N/A
«
«
0
1
2
3
4
5
6
7
8
9
10
11
Data Out
(8-bits)
«
11111010b
11111010b
11111011b
11111011b
11111110b
11111101b
11111101b
11111111b
Data Out
(8-bits)
«
248
249
250
251
252
253
254
255
6-bit in / 8 bit out
Gray level
Entry
«
00000000b
00000001b
00000011b
00000011b
00000110b
00000110b
00000111b
00000111b
00001000b
00001010b
00001001b
00001011b
«
0
1
2
3
4
5
6
7
8
9
10
11
6-bit in / 6 bit out
Gray level
Entry
Figure 22. White Balance LUT Configuration
8.3.11.2 Adaptive Hi-FRC Dithering
The Adaptive FRC Dithering Feature delivers product-differentiating image quality. It reduces 24-bit RGB (8 bits
per sub-pixel) to 18-bit RGB (6 bits per sub-pixel), smoothing color gradients, and allowing the flexibility to use
lower cost 18-bit displays. FRC (Frame Rate Control) dithering is a method to emulate “missing” colors on a
lower color depth LCD display by changing the pixel color slightly with every frame. FRC is achieved by
controlling on and off pixels over multiple frames (Temporal). Static dithering regulates the number of on and off
pixels in a small defined pixel group (Spatial). The FRC module includes both Temporal and Spatial methods and
also Hi-FRC. Conventional FRC can display only 16,194,277 colors with 6-bit RGB source. “Hi-FRC” enables full
(16,777,216) color on an 18-bit LCD panel. The “adaptive” FRC module also includes input pixel detection to
apply specific Spatial dithering methods for smoother gray level transitions. When enabled, the lower LSBs of
each RGB output are not active; only 18 bit data (6 bits per R,G and B) are driven to the display. This feature is
enabled via serial control bus register. Two FRC functional blocks are available, and may be independently
enabled. FRC1 precedes the white balance LUT, and is intended to be used when 24-bit data is being driven to
an 18-bit display with a white balance LUT that is calibrated for an 18-bit data source. The second FRC block,
RC2, follows the white balance block and is intended to be used when fine adjustment of color temperature is
required on an 18-bit color display, or when a 24-bit source drives an 18-bit display with a white balance LUT
calibrated for 24-bit source data.
For proper operation of the FRC dithering feature, the user must provide a description of the display timing
control signals. The timing mode, “sync mode” (HS, VS) or “DE only” must be specified, along with the active
polarity of the timing control signals. All this information is entered to device control registers via the serial bus
interface.
Adaptive Hi-FRC dithering consists of several components. Initially, the incoming 8-bit data is expanded to 9-bit
data. This allows the effective dithered result to support a total of 16.7 million colors. The incoming 9-bit data is
evaluated, and one of four possible algorithms is selected. The majority of incoming data sequences are
supported by the default dithering algorithm. Certain incoming data patterns (black/white pixel, full on/off subpixel) require special algorithms designed to eliminate visual artifacts associated with these specific gray level
transitions. Three algorithms are defined to support these critical transitions.
An example of the default dithering algorithm is illustrated in Figure 23. The 1 or 0 value shown in the table
describes whether the 6-bit value is increased by 1 (“1”) or left unchanged (“0”). In this case, the 3 truncated
LSBs are “001”.
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Feature Description (continued)
Frame = 0, Line = 0
F0L0
Pixel Index
PD1
Pixel Data one
Cell Value 010
R[7:2]+0, G[7:2]+1, B[7:2]+0
LSB=001
three lsb of 9 bit data (8 to 9 for Hi-Frc)
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
F0L0
010
000
000
000
000
000
010
000
F0L1
101
000
000
000
101
000
000
000
R = 4/32
F0L2
000
000
010
000
010
000
000
000
G = 4/32
F0L3
000
000
101
000
000
000
101
000
B = 4/32
F1L0
000
000
000
000
000
000
000
000
F1L1
000
111
000
000
000
111
000
000
R = 4/32
F1L2
000
000
000
000
000
000
000
000
G = 4/32
F1L3
000
000
000
111
000
000
000
111
B = 4/32
F2L0
000
000
010
000
010
000
000
000
F2L1
000
000
101
000
000
000
101
000
R = 4/32
F2L2
010
000
000
000
000
000
010
000
G = 4/32
F2L3
101
000
000
000
101
000
000
000
B = 4/32
F3L0
000
000
000
000
000
000
000
000
F3L1
000
000
000
111
000
000
000
111
R = 4/32
F3L2
000
000
000
000
000
000
000
000
G = 4/32
F3L3
000
111
000
000
000
111
000
000
B = 4/32
LSB=001
LSB = 001
Figure 23. Default FRC Algorithm
8.3.12 Serial Link Fault Detect
The DS90UH928Q-Q1 can detect fault conditions in the FPD-Link III interconnect. If a fault condition occurs, the
Link Detect Status is 0 (cable is not detected) on bit 0 of address 0x1C (Table 8). The device will detect any of
the following conditions:
1. Cable open
2. RIN+ to - short
3. RIN+ to GND short
4. RIN- to GND short
5. RIN+ to battery short
6. RIN- to battery short
7. Cable is linked incorrectly (RIN+/RIN- connections reversed)
NOTE
The device will detect any of the above conditions, but does not report specifically which
one has occurred.
8.3.13 Oscillator Output
The deserializer provides an optional TxCLKOUT± output when the input clock (serial stream) has been lost.
This is based on an internal oscillator and may be controlled from register 0x02, bit 5 (OSC Clock Output Enable)
Table 8.
8.3.14 Interrupt Pin (INTB / INTB_IN)
1. Read ISR register 0xC7 (Table 8)
2. On the serializer, set register (HDCP_ICR) 0xC6[5] = 1 and 0xC6[0] = 1 (Table 8) to configure the interrupt.
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Feature Description (continued)
3. On the serializer, read from HDCP_ISR register 0xC7 to arm the interrupt for the first time.
4. When INTB_IN is set LOW, the INTB pin on the serializer also pulls low, indicating an interrupt condition.
5. The external controller detects INTB = LOW and reads the HDCP_ISR register (Table 8) to determine the
interrupt source. Reading this register also clears and resets the interrupt.
The INTB_IN signal is sampled and required approximately 8.6 µs of the minimum setup and hold time.
8.6 µs = 30 bit per back channel fram / ( 5 Mbps rate × ±30% Variation) = 30 / (5e6 × 0.7)
Note that -30% is the worst case.
8.3.15 General-Purpose I/O
8.3.15.1 GPIO[3:0]
In normal operation, GPIO[3:0] may be used as general purpose IOs in either forward channel (outputs) or back
channel (inputs) mode. GPIO modes may be configured from the registers (Table 8). GPIO[1:0] are dedicated
pins and GPIO[3:2] are shared with I2S_DC and I2S_DD respectively. Note: if the DS90UH928Q-Q1 is paired
with a DS90UH925Q-Q1 serializer, the devices must be configured into 18-bit mode to allow usage of GPIO pins
on the serializer. To enable 18-bit mode, set serializer register 0x12[2] = 1. 18-bit mode will be auto-loaded into
the deserializer from the serializer. See Table 2 for GPIO enable and configuration.
Table 1. DS90UH925Q-Q1 GPIO Enable and Configuration
DESCRIPTION
DEVICE
FORWARD CHANNEL
BACK CHANNEL
GPIO3
DS90UH925Q-Q1
0x0F = 0x03
0x0F = 0x05
DS90UH928Q-Q1
0x1F = 0x05
0x1F = 0x03
DS90UH925Q-Q1
0x0E = 0x30
0x0E = 0x50
DS90UH928Q-Q1
0x1E = 0x50
0x1E = 0x30
GPIO1/GPIO1
(SER/DES)
DS90UH925Q-Q1
N/A
0x0E = 0x05
DS90UH928Q-Q1
N/A
0x1E = 0x03
GPO_REG5/GPIO1
(SER/DES)
DS90UH925Q-Q1
0x10 = 0x03
N/A
DS90UH928Q-Q1
0x1E = 0x05
N/A
GPIO0/GPIO0
(SER/DES)
DS90UH925Q-Q1
N/A
0x0D = 0x05
DS90UH928Q-Q1
N/A
0x1D = 0x03
GPO_REG4/GPIO0
(SER/DES)
DS90UH925Q-Q1
0x0F = 0x30
N/A
DS90UH928Q-Q1
0x1D = 0x05
N/A
GPIO2
Table 2. DS90UH927Q-Q1 GPIO Enable and Configuration
DESCRIPTION
DEVICE
FORWARD CHANNEL
BACK CHANNEL
GPIO3
DS90UH927Q-Q1
0x0F = 0x03
0x0F = 0x05
DS90UH928Q-Q1
0x1F = 0x05
0x1F = 0x03
DS90UH927Q-Q1
0x0E = 0x30
0x0E = 0x50
DS90UH928Q-Q1
0x1E = 0x50
0x1E = 0x30
DS90UH927Q-Q1
0x0E = 0x03
0x0E = 0x05
DS90UH928Q-Q1
0x1E = 0x05
0x1E = 0x03
DS90UH927Q-Q1
0x0D = 0x03
0x0D = 0x05
DS90UH928Q-Q1
0x1D = 0x05
0x1D = 0x03
GPIO2
GPIO1
GPIO0
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The input value present on GPIO[3:0] may also be read from register, or configured to local output mode
(Table 8).
8.3.15.2 GPIO[8:5]
GPIO_REG[8:5] are register-only GPIOs and may be programmed as outputs or read as inputs through local
register bits only. Where applicable, these bits are shared with I2S pins and will override I2S input if enabled into
GPIO_REG mode. See Table 3 for GPIO enable and configuration.
Note: Local GPIO value may be configured and read either through local register access, or remote register
access through the Low-Speed Bidirectional Control Channel. Configuration and state of these pins are not
transported from serializer to deserializer as is the case for GPIO[3:0].
Table 3. GPIO_REG and GPIO Local Enable and Configuration
DESCRIPTION
REGISTER CONFIGURATION
GPIO_REG8
0x21 = 0x01
Output, L
0x21 = 0x09
Output, H
0x21 = 0x03
Input, Read: 0x6F[0]
GPIO_REG7
GPIO_REG6
GPIO_REG5
GPIO3
GPIO2
GPIO1
GPIO0
FUNCTION
0x21 = 0x01
Output, L
0x21 = 0x09
Output, H
0x21 = 0x03
Input, Read: 0x6E[7]
0x20 = 0x01
Output, L
0x20 = 0x09
Output, H
0x20 = 0x03
Input, Read: 0x6E[6]
0x20 = 0x01
Output, L
0x20 = 0x09
Output, H
0x20 = 0x03
Input, Read: 0x6E[5]
0x1F = 0x01
Output, L
0x1F = 0x09
Output, H
0x1F = 0x03
Input, Read: 0x6E[3]
0x1E = 0x01
Output, L
0x1E = 0x09
Output, H
0x1E = 0x03
Input, Read: 0x6E[2]
0x1E = 0x01
Output, L
0x1E = 0x09
Output, H
0x1E = 0x03
Input, Read: 0x6E[1]
0x1D = 0x01
Output, L
0x1D = 0x09
Output, H
0x1D = 0x03
Input, Read: 0x6E[0]
8.3.16 I2S Audio Interface
The DS90UH928Q-Q1 deserializer features six I2S output pins that, when paired with a DS90UH927QQ1serializer, supports surround-sound audio applications. The bit clock (I2S_CLK) supports frequencies between
1 MHz and the smaller of
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