Sample &
Buy
Product
Folder
Technical
Documents
Support &
Community
Tools &
Software
DS90UR903Q-Q1, DS90UR904Q-Q1
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
DS90UR903Q/DS90UR904Q 10 - 43MHz
18 Bit Color FPD-Link II Serializer and Deserializer
1 Features
3 Description
•
•
•
•
The DS90UR903Q/DS90UR904Q chipset offers a
FPD-Link II interface with a high-speed forward
channel for data transmission over a single
differential pair. The Serializer/ Deserializer pair is
targeted for direct connections between graphics host
controller and displays modules. This chipset is
ideally suited for driving video data to displays
requiring 18-bit color depth (RGB666 + HS, VS, and
DE). The serializer converts 21 bit data over a single
high-speed serial stream. This single serial stream
simplifies transferring a wide data bus over PCB
traces and cable by eliminating the skew problems
between parallel data and clock paths. This
significantly saves system cost by narrowing data
paths that in turn reduce PCB layers, cable width,
and connector size and pins.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
10 MHz to 43 MHz Input PCLK Support
210 Mbps to 903 Mbps Data Throughput
Single Differential Pair Interconnect
Embedded Clock with DC Balanced Coding to
Support AC-coupled Interconnects
Capable to Drive up to 10 meters Shielded
Twisted-Pair
I2C Compatible Serial Interface for Device
Configuration
Single Hardware Device Addressing Pin
LOCK Output Reporting Pin to Validate Link
Integrity
Integrated Termination Resistors
1.8V- or 3.3V-compatible Parallel Bus Interface
Single Power Supply at 1.8V
ISO 10605 ESD and IEC 61000-4-2 ESD
Compliant
Automotive Grade Product: AEC-Q100 Grade 2
Qualified
Temperature Range −40°C to +105°C
No Reference Clock Required on Deserializer
Programmable Receive Equalization
EMI/EMC Mitigation
– DES Programmable Spread Spectrum (SSCG)
outputs
– DES Receiver Staggered Outputs
The Deserializer inputs provide equalization control to
compensate for loss from the media over longer
distances. Internal DC balanced encoding/decoding is
used to support AC-Coupled interconnects.
The Serializer is offered in a 40-pin WQFN package
and the Deserializer is offered in a 48-pin WQFN
package.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS90UR903Q-Q1
WQFN RTA (40)
6.00 mm × 6.00 mm
DS90UR904Q-Q1
WQFN RHS (48)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
•
Automotive Display Systems
– Central Information Displays
– Navigation Displays
– Rear Seat Entertainment
Typical Eye Diagram
Simplified Schematic
DS90UR903Q
Serializer
FPD-Link II
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
PCLK
PLL
PDB
MODE
PDB
MODE
Config.
PC
SDA
SCL
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
PCLK
Timing
Controller
LCD
Display
Config.
SDA
SCL
Magnitude (80 mV/DIV)
Graphics
Controller
--Video
Processor
DS90UR904Q
Deserializer
PC
Time (200 ps/DIV)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90UR903Q-Q1, DS90UR904Q-Q1
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
6
6.1
6.2
6.3
6.4
6.5
Absolute Maximum Ratings ..................................... 6
Handling Ratings ...................................................... 6
Recommended Operating Conditions....................... 6
Thermal Information ................................................ 7
Electrical Characteristics
................................................................................... 7
6.6 Recommended Serializer Timing for PCLK ............. 9
6.7 Serial Control Bus AC Timing Specifications (SCL,
SDA) - I2C Compliant (See Figure 1)....................... 10
6.8 Serial Control Bus DC Characteristics (SCL, SDA) I2C Compliant........................................................... 11
6.9 Serializer Switching Characteristics........................ 15
6.10 Deserializer Switching Characteristics.................. 16
6.11 Typical Characteristics .......................................... 17
7
Detailed Description ............................................ 18
7.1
7.2
7.3
7.4
7.5
7.6
8
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming ..........................................................
Register Maps .........................................................
18
18
19
20
20
22
Application and Implementation ........................ 26
8.1 Application Information............................................ 26
8.2 Typical Applications ................................................ 26
9 Power Supply Recommendations...................... 31
10 Layout................................................................... 32
10.1 Layout Guidelines ................................................. 32
10.2 Layout Example .................................................... 32
11 Device and Documentation Support ................. 35
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
35
35
35
35
35
12 Mechanical, Packaging, and Orderable
Information ........................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2013) to Revision C
Page
•
Added data sheet flow and layout to conform with new TI standards. Added the following sections: Application and
Implementation; Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical,
Packaging, and Ordering Information .................................................................................................................................... 1
•
Added additional thermal charateristics.................................................................................................................................. 7
•
Changed test condition Vin to Vddio ........................................................................................................................................ 7
•
Added power up sequencing information and timing diagram. ............................................................................................ 29
•
Added application graphics of the serializer CML output. .................................................................................................... 30
Changes from Revision A (April 2013) to Revision B
•
2
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 30
Submit Documentation Feedback
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: DS90UR903Q-Q1 DS90UR904Q-Q1
DS90UR903Q-Q1, DS90UR904Q-Q1
www.ti.com
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
5 Pin Configuration and Functions
VDDIO
31
DIN[8]
32
DIN[9]
33
VDDD
34
DIN[7]
DIN[6]
DIN[5]
DIN[4]
DIN[3]
DIN[2]
DIN[1]
DIN[0]
NC
NC
30
29
28
27
26
25
24
23
22
21
40 Pin Serializer – DS90UR903Q
Package RTA
Top View
DAP = GND
DS90UR903Q
Serializer
40-Pin WQFN
(Top View)
20
NC
19
NC
18
VDDCML
17
DOUT+
16
DOUT-
15
VDDT
10
RES
RES
11
9
40
ID[x]
DIN[15]
8
MODE
SDA
12
7
39
SCL
DIN[14]
6
PDB
PCLK
13
5
38
DIN[20]
DIN[13]
4
VDDPLL
DIN[19]
14
3
37
DIN[18]
DIN[12]
2
36
DIN[17]
DIN[11]
1
35
DIN[16]
DIN[10]
DS90UR903Q Serializer Pin Functions
PIN
NAME
NUMBER
I/O, TYPE
DESCRIPTION
LVCMOS PARALLEL INTERFACE
DIN[20:0]
PCLK
5, 4, 3, 2, 1, 40,
39, 38, 37, 36, 35,
33, 32, 30, 29, 28,
27, 26, 25, 24, 23
Inputs, LVCMOS
w/ pull down
Parallel data inputs.
6
Input, LVCMOS
w/ pull down
Pixel Clock Input Pin. Strobe edge set by TRFB control register.
SERIAL CONTROL BUS - I2C COMPATIBLE
SCL
7
Input,
Open Drain
Clock line for the serial control bus communication
SCL requires an external pull-up resistor to VDDIO.
SDA
8
Input/Output,
Open Drain
Data line for the serial control bus communication
SDA requires an external pull-up resistor to VDDIO.
MODE
12
Input, LVCMOS
w/ pull down
ID[x]
9
Input, analog
I2C Mode select
MODE = H, -REQUIRED. The MODE pin must be set HIGH to allow I2C
configuration of the serializer.
Device ID Address Select
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 1
CONTROL AND CONFIGURATION
PDB
13
Input, LVCMOS
w/ pull down
Power down Mode Input Pin.
PDB = H, Serializer is enabled and is ON.
PDB = L, Serailizer is in Power Down mode. When the Serializer is in Power
Down, the PLL is shutdown, and IDD is minimized. Programmed control
register data are NOT retained and reset to default values
RES
10, 11
Input, LVCMOS
w/ pull down
Reserved.
This pin MUST be tied LOW.
NC
22, 21, 20, 19
No Connect
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DS90UR903Q-Q1 DS90UR904Q-Q1
3
DS90UR903Q-Q1, DS90UR904Q-Q1
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
www.ti.com
DS90UR903Q Serializer Pin Functions (continued)
PIN
NAME
I/O, TYPE
NUMBER
DESCRIPTION
FPD-LINK II INTERFACE
Output, CML
Non-inverting differential output. The interconnect must be AC Coupled with a
100 nF capacitor.
16
Output, CML
Inverting differential output. The interconnect must be AC Coupled with a 100
nF capacitor.
VDDPLL
14
Power, Analog
PLL Power, 1.8V ±5%
VDDT
15
Power, Analog
Tx Analog Power, 1.8V ±5%
VDDCML
18
Power, Analog
CML Power, 1.8V ±5%
VDDD
34
Power, Digital
Digital Power, 1.8V ±5%
VDDIO
31
Power, Digital
Power for I/O stage. The single-ended inputs and SDA, SCL are powered from
VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10%
Ground, DAP
DAP must be grounded. DAP is the large metal contact at the bottom side,
located at the center of the WQFN package. Connected to the ground plane
(GND) with at least 16 vias.
DOUT+
17
DOUTPOWER AND GROUND (1)
VSS
(1)
DAP
See Power Up Requirements and PDB PIN.
ROUT[2]
ROUT[3]
25
VDDIO1
29
26
NC
30
ROUT[0]
NC
31
ROUT[1]
NC
32
27
NC
33
28
PDB
LOCK
34
24
ROUT[4]
23
ROUT[5]
22
ROUT[6]
21
ROUT[7]
20
VDDIO2
19
ROUT[8]
18
ROUT[9]
17
VDDD
45
16
ROUT[10]
46
15
ROUT[11]
MODE
47
14
ROUT[12]
ID[x]
48
13
ROUT[13]
Submit Documentation Feedback
9
10
11
12
ROUT[17]
ROUT[16]
ROUT[15]
ROUT[14]
8
RES
7
VDDPLL
VDDIO3
44
ROUT[18]
43
RES
6
RES
DS90UR904Q
Deserializer
48-Pin WQFN
(Top View)
ROUT[19]
42
5
41
RIN-
4
RIN+
PCLK
40
ROUT[20]
VDDCML
DAP = GND
3
39
2
38
RES
SCL
RES
VDDSSCG
37
1
RES
SDA
4
35
VDDR
36
48 Pin Deserializer - DS90UR904Q
Package RHS
Top View
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: DS90UR903Q-Q1 DS90UR904Q-Q1
DS90UR903Q-Q1, DS90UR904Q-Q1
www.ti.com
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
DS90UR904Q Deserializer Pin Descriptions
PIN
NAME
NUMBER
I/O, TYPE
DESCRIPTION
LVCMOS PARALLEL INTERFACE
ROUT[20:0]
5, 6, 8, 9, 10,
11, 12, 13, 14,
15, 16, 18, 19,
21, 22, 23, 24,
25, 26, 27, 28
Outputs,
LVCMOS
Parallel data outputs.
4
Output,
LVCMOS
Pixel Clock Output Pin.
Strobe edge set by RRFB control register.
PCLK
SERIAL CONTROL BUS - I2C COMPATIBLE
SCL
2
Input,
Open Drain
Clock line for the serial control bus communication
SCL requires an external pull-up resistor to VDDIO.
SDA
1
Input/Output,
Open Drain
Data line for the serial control bus communication
SDA requires an external pull-up resistor to VDDIO.
MODE
47
ID[x]
9
I2C Mode select
Input, LVCMOS
MODE = H -REQUIRED. The MODE pin must be set HIGH to allow I2C configuration
w/ pull up
of the deserializer.
Input, analog
Device ID Address Select
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 2
CONTROL AND CONFIGURATION
PDB
35
LOCK
34
RES
37, 38, 39, 43,
44, 46
NC
30, 31, 32, 33
Power down Mode Input Pin.
PDB = H, Deserializer is enabled and is ON.
Input, LVCMOS
PDB = L, Deserializer is in Power Down mode. When the Deserializer is in Power
w/ pull down
Down. Programmed control register data are NOT retained and reset to default
values.
Output,
LVCMOS
-
LOCK Status Output Pin.
LOCK = H, PLL is Locked, outputs are active
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by
OSS_SEL control register. May be used as Link Status.
Reserved.
Pin 46: This pin MUST be tied LOW.
Pin 37, 43, 44: Leave pin open.
Pins 38, 39: Route to test point or leave open if unused.
No Connect
FPD-LINK II INTERFACE
RIN+
41
Input, CML
Noninverting differential input. The interconnect must be AC Coupled with a 100 nF
capacitor.
RIN-
42
Inputt, CML
Inverting differential input. The interconnect must be AC Coupled with a 100 nF
capacitor.
POWER AND GROUND
(1)
VDDSSCG
3
Power, Digital
SSCG Power, 1.8V ±5%
Power supply must be connected regardless if SSCG function is in operation.
VDDIO1/2/3
29, 20, 7
Power, Digital
LVCMOS I/O Buffer Power, The single-ended outputs and control input are powered
from VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10%
VDDD
17
Power, Digital
Digital Core Power, 1.8V ±5%
VDDR
36
Power, Analog
Rx Analog Power, 1.8V ±5%
VDDCML
40
Power, Analog
1.8V ±5%
VDDPLL
45
Power, Analog
PLL Power, 1.8V ±5%
DAP
Ground, DAP
DAP must be grounded. DAP is the large metal contact at the bottom side, located at
the center of the WQFN package. Connected to the ground plane (GND) with at least
16 vias.
VSS
(1)
See Power Up Requirements and PDB PIN.
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DS90UR903Q-Q1 DS90UR904Q-Q1
5
DS90UR903Q-Q1, DS90UR904Q-Q1
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
(1) (2)
MIN
MAX
UNIT
Supply Voltage – VDDn (1.8V)
PARAMETER
−0.3
+2.5
V
Supply Voltage – VDDIO
−0.3
+4.0V
V
LVCMOS Input Voltage I/O Voltage
−0.3
(VDDIO + 0.3V)
V
CML Driver I/O Voltage (VDD)
−0.3
(VDD + 0.3V)
V
CML Receiver I/O Voltage (VDD)
−0.3
(VDD + 0.3V)
V
+150
°C
1/θJA above +25°
°C/W
Junction Temperature
Maximum Package Power Dissipation Capacity
(1)
(2)
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional; the device should not be operated beyond such conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
6.2 Handling Ratings
Tstg
MIN
MAX
UNIT
–65
150
°C
-8
+8
-1
+1
Machine Model (MM)
-250
+250
Air Discharge
(DOUT+, DOUT-, RIN+, RIN-)
-25
+25
Contact Discharge
(DOUT+, DOUT-, RIN+, RIN-)
-10
+10
Air Discharge
(DOUT+, DOUT-, RIN+, RIN-)
-15
+15
Contact Discharge
(DOUT+, DOUT-, RIN+, RIN-)
-10
+10
Storage temperature range
Human body model (HBM), per AEC Q100-002
V(ESD)
Electrostatic discharge
ESD Rating (IEC 61000-4-2)
RD = 330Ω, CS = 150pF
ESD Rating (ISO10605)
RD = 330Ω, CS = 150/330pF
RD = 2KΩ, CS = 150/330pF
(1)
(1)
Charged device model (CDM), per AEC Q100-011
kV
V
kV
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
Supply Voltage (VDDn)
1.71
1.8
1.89
V
LVCMOS Supply Voltage (VDDIO) (1.8V)
1.71
1.8
1.89
V
3.0
3.3
LVCMOS Supply Voltage (VDDIO) (3.3V)
Supply Noise
3.6
V
VDDn (1.8V)
25
mVp-p
VDDIO (1.8V)
25
mVp-p
VDDIO (3.3V)
50
mVp-p
Operating Free Air Temperature (TA)
-40
PCLK Clock Frequency
10
6
Submit Documentation Feedback
+25
+105
°C
43
MHz
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: DS90UR903Q-Q1 DS90UR904Q-Q1
DS90UR903Q-Q1, DS90UR904Q-Q1
www.ti.com
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
Thermal Information (1)
6.4
THERMAL METRIC
(2)
DS90UR903Q
40L WQFN
DS90UR904Q
48L WQFN
RTA
RHS
40 PINS
48 PINS
RθJA
Junction-to-ambient thermal resistance
31.9
30.0
RθJC(top)
Junction-to-case (top) thermal resistance
18.5
11.1
RθJB
Junction-to-board thermal resistance
8.1
6.9
ψJT
Junction-to-top characterization parameter
0.3
0.1
ψJB
Junction-to-board characterization parameter
8.1
6.9
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.5
2.4
(1)
(2)
UNIT
°C/W
For soldering specifications, see SNOA549
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics (1)
(2) (3)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVCMOS DC SPECIFICATIONS 3.3V I/O (SER INPUTS, DES OUTPUTS, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input Voltage
VDDIO = 3.0V to 3.6V
2.0
VDDIO
V
VIL
Low Level Input Voltage
VDDIO = 3.0V to 3.6V
GND
0.8
V
IIN
Input Current
VIN = 0V or 3.6V
VDDIO = 3.0V to 3.6V
-20
+20
µA
VOH
High Level Output Voltage
VDDIO = 3.0V to 3.6V
IOH = -4 mA
2.4
VDDIO
V
VOL
Low Level Output Voltage
VDDIO = 3.0V to 3.6V
IOL = +4 mA
GND
0.4
V
IOS
Output Short Circuit Current
VOUT = 0V
TRI-STATE Output Current
PDB = 0V,
VOUT = 0V or VDD
IOZ
±1
-39
-20
±1
mA
+20
µA
LVCMOS DC SPECIFICATIONS 1.8V I/O (SER INPUTS, DES OUTPUTS, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input Voltage
VDDIO = 1.71V to 1.89V
0.65 VDDIO
VDDIO +0.3
V
VIL
Low Level Input Voltage
VDDIO = 1.71V to 1.89V
GND
0.35 VDDIO
V
IIN
Input Current
VIN = 0V or 1.89V
VDDIO = 1.71V to 1.89V
-20
+20
µA
VOH
High Level Output Voltage
VDDIO = 1.71V to 1.89V
IOH = −4 mA
VDDIO 0.45
VDDIO
V
VOL
Low Level Output Voltage
VDDIO = 1.71V to 1.89V
IOL = +4 mA
GND
0.45
V
IOS
Output Short Circuit Current
VOUT = 0V
IOZ
TRI-STATE Output Current
PDB = 0V,
VOUT = 0V or VDD
(1)
(2)
(3)
±1
-20
-20
±1
mA
+20
µA
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DS90UR903Q-Q1 DS90UR904Q-Q1
7
DS90UR903Q-Q1, DS90UR904Q-Q1
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
Electrical Characteristics(1) (2)
(continued)
www.ti.com
(3)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
268
340
412
mV
1
50
mV
VDD - VOD
VDD (MAX) VOD (MIN)
V
1
50
mV
CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-)
|VOD|
Output Differential Voltage
RT = 100Ω, Figure 5
ΔVOD
Output Differential Voltage Unbalance
RL = 100Ω
VOS
Output Differential Offset Voltage
RL = 100Ω
Figure 5
ΔVOS
Offset Voltage Unbalance
RL = 100Ω
IOS
Output Short Circuit Current
DOUT+/- = 0V
RT
Differential Internal Termination Resistance
Differential across DOUT+ and
DOUT-
VDD (MIN) VOD (MAX)
-27
80
100
mA
120
Ω
CML RECEIVER DC SPECIFICATIONS (RIN+, RIN-)
VTH
Differential Threshold High Voltage
VTL
Differential Threshold Low Voltage
VIN
Differential Input Voltage Range
RIN+ - RIN-
180
Input Current
VIN = VDD or 0V,
VDD = 1.89V
-20
±1
+20
µA
Differential Internal Termination Resistance
Differential across RIN+ and
RIN-
80
100
120
Ω
62
90
IIN
RT
Figure 7
+90
-90
mV
mV
SER/DES SUPPLY CURRENT *DIGITAL, PLL, AND ANALOG VDD
IDDT
Serializer (Tx)
VDDn Supply Current (includes load
current)
RT = 100Ω
WORST
CASE pattern
Figure 2
VDDn = 1.89V
PCLK = 43 MHz
Default
Registers
mA
RT = 100Ω
RANDOM
PRBS-7
pattern
IDDIOT
IDDTZ
Serializer (Tx)
VDDIO Supply Current (includes load
current)
Serializer (Tx) Supply Current Power-down
IDDIOTZ
8
Submit Documentation Feedback
RT = 100Ω
WORST
CASE pattern
Figure 2
PDB = 0V; All
other
LVCMOS
Inputs = 0V
55
VDDIO = 1.89V
PCLK = 43 MHz
Default
Registers
2
VDDIO = 3.6V
PCLK = 43 MHz
Default
Registers
7
15
VDDn = 1.89V
370
775
VDDIO = 1.89V
55
125
VDDIO = 3.6V
65
135
5
mA
µA
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: DS90UR903Q-Q1 DS90UR904Q-Q1
DS90UR903Q-Q1, DS90UR904Q-Q1
www.ti.com
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
Electrical Characteristics(1) (2)
(continued)
(3)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
IDDR
IDDIOR
IDDRZ
IDDIORZ
TEST CONDITIONS
Deserializer (Rx) VDDn Supply Current
(includes load current)
Deserializer (Rx) VDDIO Supply Current
(includes load current)
Deserializer (Rx) Supply Current Powerdown
VDDn = 1.89V
CL = 8 pF
WORST
CASE Pattern
Figure 2
PCLK = 43 MHz
SSCG[3:0] =
ON
Default
Registers
VDDn = 1.89V
CL = 8 pF
RANDOM
PRBS-7
Pattern
PCLK = 43 MHz
Default
Registers
VDDIO = 1.89V
CL = 8 pF
WORST
CASE Pattern
Figure 2
PCLK = 43 MHz
Default
Registers
VDDIO = 3.6V
CL = 8 pF
WORST
CASE Pattern
PCLK = 43 MHz
Default
Registers
PDB = 0V; All
other
LVCMOS
Inputs = 0V
VDDn = 1.89V
MIN
TYP
MAX
60
96
UNIT
53
mA
21
32
49
83
42
400
VDDIO = 1.89V
8
40
VDDIO = 3.6V
350
800
µA
6.6 Recommended Serializer Timing for PCLK (1)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
MIN
TYP
MAX
UNIT
23.3
T
100
ns
Transmit Clock Input High Time
0.4T
0.5T
0.6T
ns
tTCIL
Transmit Clock Input Low Time
0.4T
0.5T
0.6T
ns
tCLKT
PCLK Input Transition Time
Figure 8
0.5
3
ns
fOSC
Internal oscillator clock source
tTCP
Transmit Clock Period
tTCIH
(1)
TEST CONDITIONS
10 MHz – 43 MHz
25
MHz
Recommended Input Timing Requirements are input specifications and not tested in production.
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DS90UR903Q-Q1 DS90UR904Q-Q1
9
DS90UR903Q-Q1, DS90UR904Q-Q1
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
www.ti.com
Serial Control Bus AC Timing Specifications (SCL, SDA) - I2C Compliant (See Figure 1)
6.7
Over recommended supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
RECOMMENDED INPUT TIMING REQUIREMENTS
fSCL
SCL Clock Frequency
tLOW
SCL Low Period
tHIGH
MIN
TYP
MAX
UNIT
100
kHz
(1)
>0
fSCL = 100 kHz
4.7
µs
SCL High Period
4.0
µs
tHD:STA
Hold time for a start or a repeated start
condition
4.0
µs
tSU:STA
Set Up time for a start or a repeated
start condition
4.7
µs
tHD:DAT
Data Hold Time
tSU:DAT
Data Set Up Time
250
ns
tSU:STO
Set Up Time for STOP Condition
4.0
µs
tr
SCL & SDA Rise Time
1000
tf
SCL & SDA Fall Time
300
ns
Cb
Capacitive load for bus
400
pF
3.45
µs
0
3.45
µs
ns
SWITCHING CHARACTERISTICS (2)
tHD:DAT
Data Hold Time
tSU:DAT
Data Set Up Time
tf
SCL & SDA Fall Time
(1)
(2)
0
250
ns
300
ns
Recommended Input Timing Requirements are input specifications and not tested in production.
Specification is ensured by design.
SDA
tf
tHD;STA
tLOW
tr
tr
tBUF
tf
SCL
tSU;STA
tHD;STA
tHIGH
tHD;DAT
START
tSU;STO
tSU;DAT
STOP
REPEATED
START
START
Figure 1. Serial Control Bus Timing
10
Submit Documentation Feedback
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: DS90UR903Q-Q1 DS90UR904Q-Q1
DS90UR903Q-Q1, DS90UR904Q-Q1
www.ti.com
SNLS346C – AUGUST 2011 – REVISED JUNE 2014
6.8 Serial Control Bus DC Characteristics (SCL, SDA) - I2C Compliant
Over recommended supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.7 x
VDDIO
VDDIO
V
GND
0.3 x
VDDIO
V
VIH
Input High Level
SDA and SCL
VIL
Input Low Level Voltage
SDA and SCL
VHY
Input Hysteresis
SDA and SCL
IOZ
TRI-STATE Output Current
PDB = 0V
VOUT = 0V or VDD
-20
±1
+20
µA
IIN
Input Current
SDA or SCL,
Vin = VDDIO or GND
-20
±1
+20
µA
CIN
Input Pin Capacitance
VOL
Low Level Output Voltage
>50
mV
工商网监
湘ICP备2023018690号
