DS90UR907Q-EVK/NOPB

DS90UR907Q-EVK FPD-Link to FPD-Link II Converter Evaluation Kit Rev 0.1 April, 2010 General Description The DS90UR907Q-EVK converts FPD-link to FPD-Link II. It translates four LVDS data/control streams and one LVDS clock pair into a high-speed serialized interface over a single pair. It is backward compatible for operation with older generation deserializer devices. The DS90UR907Q-EVK board has a space saving 20-position wall header as the FPD-Link input, and a Rosenberger Automotive HSD Connector as the output. USB or SMA connectors can also be configured as the output, based on the type of the cable to be used. Features • • • • • • • • • • • • • • • 5 – 65 MHz support (140 Mbps to 1.82 Gbps Serial Link) 5-channel (4 data + 1 clock) FPD-Link receiver inputs AC Coupled STP Interconnect up to 10 meters in length Integrated output termination @ Speed link BIST Mode and reporting pin Optional I2C compatible Serial Control Bus RGB888 + VS, HS, DE serialized to 1 pair Power down Mode minimizes power dissipation Randomizer/Scrambler – DC-balanced data stream Low EMI FPD-Link input Selectable output VOD and adjustable de-emphasis 1.8V or 3.3V compatible control bus interface Automotive grade product: AEC-Q100 Grade 2 qualified >8 kV HBM and ISO 10605 ESD rating Backward compatible mode for operation with older generation devices Applications • • Automotive Displays for Navigation Automotive Display for Entertainment Ordering Information PART: DS90UR907QSQ Demo board: DS90UR907Q-EVK national.com © National Semiconductor Corporation 2010 1 Printed in U.S. Typical Configuration Quick Start Guide: 1. 2. 3. 4. Connect 3.3V DC power and ground of the board to the JP1 from the power supply. Connect 1.8V DC power and ground of the board to the J3 and J4 from the power supply. Attach an applicable cable (not supplied) to this TX board (DS90UR907Q) output to an RX board (DS90UR908Q) input. From the Video Decoder board, connect a flat cable (not supplied) to this TX board and connect another flat cable (not supplied) from the RX board to the panel. Jumpers and switches have been configured at the factory; they should not require any changes for immediate operation of the board. See text on Configuration Settings and datasheet for more details. national.com © National Semiconductor Corporation 2010 2 Printed in U.S. Configuration Settings Component Name Function Power Connections J3 1.8V DC 1.8V VDD Power. JP1 3.3V DC 3.3V VDD Power. J4 VSS Ground. JP2 VDDI Always connect to 3.3V. JP18 VDDL Always connect to 1.8V. JP23 VDDP Always connect to 1.8V. JP24 VDDHS Always connect to 1.8V. Input and Output Connections 20 position wall J1 header Automotive HSD P1 Connector J7 and J8 SMA Connectors P3 USB Connector Power Wire in USB cable through P3 JP25 and JP26 Connect to FPD-Link input. Connect to FPD-Link II output (default). Connect to FPD-Link II output. (When using these connectors, R8 and R9 should be placed with 0Ω resistors, the traces from R8 and R9 to the P1 should be cut). Connect to FPD-Link II output. (When using this connector, P1 should be removed, and R26 and R27 should be placed with 0Ω resistors). Connect to VSS is recommended. Control Connections JP4 MAPSEL JP5 TESTEN JP6 PDB JP7 BISTEN JP8 VODSEL JP21 and JP22 CONFIG JP17 and VR3 DEEMPH JP19 and VR4 ID[x] JP3 and J6 I2C Interface national.com © National Semiconductor Corporation 2010 Connect it to “L” or “H” for the FPD Link mapping select. See datasheet for detail information. NSC test mode. Always connect it to “L” or leave it unconnected. Connect it to “L” for the power down mode. Connect it to “H” for the enable mode. See datasheet for detail information. Connect it to “H” for the BIST enable mode. See datasheet for detail information. Connect it to “L” or “H” for the FPD-Link II VOD level select. See datasheet for detail information. Configuration select. See datasheet for detail information. Leave JP17 unconnected to disable the FPD-Link II output de-emphasis feature. Connect JP17, Adjust VR3 value to select de-emphasis level. Connect JP19 to VSS to have the default device PHY address (h’EC). Connect JP19 to VR4; then adjust VR4 value to select desired device PHY address. See datasheet for detail information. Connect JP3 if the I2C power is not supplied on J6. Otherwise, leave it unconnected. 3 Printed in U.S. Bill of Material Item Quantity Reference Comments Digi-key P/N Part number 1 2 C1,C13 CAPACITOR TANT 2.2UF 20V 10% SMD 399-3714-1-ND T491B225K020AT 2 2 C2,C14 CAP .10UF 50V CERAMIC X7R 1206 399-1249-1-ND C1206C104K5RACTU 3 4 C3,C4,C7,C8 CAP TANTALUM 10UF 16V 20% SMD. Optional. 493-2365-1-ND F931C106MBA_open 4 2 C5,C6 CAP CERAMIC .1UF25V X5R 0402 445-4964-1-ND C1005X5R1E104K 5 2 C9,C12 CAP TANTALUM 22UF 25V 20% SMD 493-2391-1-ND F931E226MNC 6 2 C10,C11 CAP CERAMIC 5.0PF 25V NP0 0201 PCC2107CT-ND ECJ-ZEC1E050C 7 7 C15,C20,C23,C24,C27,C30, CAP .1UF ±10% 25V CERAMIC X7R 0603 PCC2277CT-ND ECJ-1VB1E104K CAPACITOR TANT 22UF 16V 20% SMD 399-3835-1-ND T494B226M016AT C32 8 7 C16,C17,C18,C19,C28,C33, 9 6 C21,C22,C25,C26,C29,C31 CAP CERAMIC .01UF 100V X7R 0603 399-3189-1-ND C0603C103K1RACTU 10 3 JP1,JP3,JP17 CONN HEADER VERT .100 2POS 30AU A26542-ND 87220-2 11 14 JP2,JP4,JP5,JP6,JP7,JP8, CONN HEADER VERT .100 3POS 15AU A26545-ND 87224-3 N2520-6002RB C34 JP18,JP19,JP21,JP22,JP23, JP24,JP25,JP26 12 1 J1 CONN HEADER 20 POS STRGHT GOLD. MHC20K-ND 13 1 J2 CONN POWER JACK 2.1MM. Optional. CP-002A-ND_open PJ-002A_open 14 2 J3,J4 BANANA-female (non-insulated) J147-ND 108-0740-001 15 1 J5 CONN HDR DUAL 8POS .100 SRT AU. Optional. WM26808-ND 10-89-7082_open CONN HEADER 4POS .100 VERT GOLD End Launch Jack Receptacle - Tab Contact. Optional. WM2702-ND 22-11-2042 J658-ND_open 142-0701-851_open 16 1 J6 17 2 J7,J8 18 1 P1 Automotive HSD Conn - Right Angle Plug Optional. 19 1 P2 CONN RECEPT MINI USB2.0 5POS. Optional. H2959CT-ND UX60-MB-5ST_open D4S20B-40ML5-Y_open 292303-1 20 1 P3 CONN USB RECEPT R/A TYPE A 4POS. A31726-ND 21 1 R1 RES 1.50K OHM 1/16W 1% 0402 SMD P1.50KLCT-ND ERJ-2RKF1501X 22 2 R2,R12 RES ZERO OHM 1/16W 5% 0402 SMD. Optional. P0.0JTR-ND_open ERJ-2GEJ0R00X_open 23 5 R3,R4,R5,R6,R7 RES 100 OHM 0201 SMD. 1/20W .5% RR03P100DCT-ND RR0306P-101-D 24 2 R8,R9 RES 0 OHM 0201 SMD. Optional. ERJ-1GE0R00C 25 1 R10 RES 100K OHM 1/10W 1% 0603 SMD. Optional. P0.0AGCT-ND P100KHCTND_open 26 1 R11 RES 10.0K OHM 1/10W 1% 0603 SMD P10.0KHCT-ND ERJ-3EKF1002V 27 2 R13,R14 RES 4.7K OHM 1/10W 5% 0603 SMD P4.7KGCT-ND ERJ-3GEYJ472V 28 2 R15,R16 RES 82.5 OHM 1/10W 1% 0603 SMD. Optional. P82.5HCT-ND ERJ-3EKF82R5V_open 29 1 R17 RES 100 OHM 1/10W 1% 0603 SMD. Optional. P100HCT-ND ERJ-3EKF1000V_open 30 7 R18,R20,R21,R22,R23,R24, RES ZERO OHM 1/16W 5% 0402 SMD P0.0JTR-ND ERJ-2GEJ0R00X P0.0AGCT-ND ERJ-1GE0R00C ERJ-3EKF1003V_open R25 31 2 R26,R27 RES 0.0 OHM 1/20W 5% 0201 SMD 32 1 U1 DO NOT PURCHASE, National will supply. 33 2 U2,U3 IC REG ADJ 800MA LDO SOT-223. LM1117IMPADJ/NOPB DS90UR907 LM1117IMPADJ/NOPB_open 34 2 VR1,VR2 TRIMPOT 100 OHM 4MM TOP ADJ SMD. 3214W-101ETR-ND 3214W-1-101E_open 35 1 VR3 11-Turn Trimming Potentiometer; Top Adjust 3224W-1-203E 36 1 VR4 11-Turn Trimming Potentiometer; Top Adjust 3224W-203ECT-ND 3224W-1-104ECTND national.com © National Semiconductor Corporation 2010 3224W-1-104E 4 Printed in U.S. 1 RxIN0+ 3 5 RxIN1+ 7 9 RxIN2+ 11 13 RxCLKIN+15 17 19 RxIN3+ IDx VSS VSS VSS 2 R12 0 Ohm,0402_open RxIN3- RxCLKIN- RxIN2- RxIN1- RxIN0- VDDTX 2 4 6 8 10 12 14 16 18 20 JP19 1 2 3 J1 VSS VR4 3 2 1 3 2 1 R7 100 0201 R6 100 0201 R5 100 0201 R4 100 0201 R3 100 0201 JP3 1 2 0.1uF VSS C15 VDDIO VDD_I2C J6 100 ohm diff pair. +/5%. Resistors have to be placed close to the DUT. +/- 1 mil for all inter/intra pairs. 5pF 5pF VSS C11 C10 R14 4.7K 0603 VSS VDD_I2C VSS R13 4.7K 0603 DAP RxCh0RxCh0+ RxCh1RxCh1+ RxCh2RxCh2+ RxClkRxClk+ RxIN3RxIN3+ SDA SCL 37 28 29 30 31 32 33 34 35 1 2 U1 50 ohm single ended. 20mil +/-. place together 1 2 3 4 VDDRX 3 2 1 VDDL VD D R X JP8 JP7 JP6 3 2 1 JP5 3 2 1 MAPSEL TESTEN VSS DS90UR907 CONFIG[1] CONFIG[0] RES6 DOUT+ DOUT - VODSEL DeEmph VSS 10 9 3 + - 16 15 0402_orange_LED 2 1 LED2 INT 1 VSS R19 2 0 Ohm,0402_open JP10 SVR20K VSS VR3 CW 3 R1 1 1.50K 0402 JP17 R2 0 Ohm,0402_open C5 0.1uF R8 0201 DOUT+_SMA DOUT+ 1 2 0 ohm_open 0603_green_LED 2 1 LED1 RLD 1 JP9 2 VSS VODSEL R18 0 Ohm,0402 2 VSS 3 2 1 3 2 1 3 2 1 3-Pin Header JP20 JP25 VSS DOUT+_USB DOUT-_USB VDDIO USB A: solder side (BOTTOM) VSS VSS 5 Printed in U.S. 5 4 3 2 1 Document Number DS90UR907 Tx Demo Board Friday , August 07, 2009 Date: Sheet P3 2 P2 VSS mini USB 5pin_open of 3 Rev B mini B: component side (TOP) DS90UR907 Tx Demo Board - DS90UR907 Serializer Size B Title JP26 SMA_open J8 DOUT-_SMA 1 2 3 4 5 VSS 0.625" LAYOUT NOTE: Place J6, J7 0.625" center-to-center of pin #1s. Footprint on solder side (bottom). J7 DOUT+_SMA 1 2 3 L A YOU T N OT E: 4 100 oh m 5 d iff pair SMA_open R26 0201 1 DOUT+_USB 0 ohm 2USB A DOUT-_USB LA YOU T N OTE: 100 oh m d ifferential imp edance +/-5%. +/- 0 mil 3 DOUTR27 0201 4 0 ohm VSS VDDIO DOUT+ 50 ohm single ended. 20mil +/-. place together 3-Pin Header JP21 3-Pin Header JP22 VDDIO P1 HSD_2X2_open LA YOU T N OTE: 100 oh m d ifferential imp edance +/-5%. +/- 0 mil DOUT1 2 R9 0201 DOUT-_SMA C6 0.1uF 0 ohm_open DeEmph C16 22uF 20 19 + 50 ohm single ended. VSS 3-Pin Header3-Pin Header3-Pin Header3-Pin Header3-Pin Header3-Pin Header 3-Pin Header3-Pin Header3-Pin Header3-Pin Header3-Pin Header 3 2 1 VDDL VDDP VDDHS VDDTX VDDIO VDDRX VDDIO JP16 3 2 1 1 VDD VDDTX VDDHS VDDP VDDL VDDIO VSS JP4 JP14 JP15 3 2 1 JP13 3 2 1 2 VD D VD D TX VD D H S VD D P VD D L VD D IO VSS SVR100K 3 2 1 RES5 RES4 RES3 RES2 RES1 RES0 36 27 18 13 12 8 RES5 RES4 RES3 RES2 RES1 RES0 PDB BISTEN PDB BISTEN 26 25 5 11 14 17 22 24 2 1 3 2 1 VDDP VDDHS VDDTX 3 4 2 1 23 21 VDDIO VDDRX 6 7 5 8 1112 1013 9 MAPSEL TESTEN ID[x] SCL SDA 4 6 7 7 JP12 BLK R11 10K 100K_open R10 1 CW 3 1 RED 2 3 1 2 3 IDx SCL SDA RED BLK 5 6 6 © National Semiconductor Corporation 2010 8 national.com 9 JP11 Schematics 1 BANANA J4 1 C13 + 2.2uF 2 1 C12 + 22uF 2 1 3 5 7 OPTION AL 5V IN PUT POW ER C ON NEC TOR 1 2 3 CONN JACK PWR_open J2 2x4 pin Jumper_open VSS J5 2 4 6 8 0.1uF C14 + 1 C4 1 + C8 VSS VDD C7 2 + VSS VSS + C3 + 3.3V U2 OPTIONAL 5V to 3.3V IN PUT POW ER R EGU L ATOR VDD3.3V VR1 R17 1 100ohm_open U3 CW 3 SVR100_open VSS OPTIONAL 5V to 1.8V INPUT POWER REGULATOR SVR100_open VSS VR2 CW 3 1 2 + C2 + VD DH Sc VSS VDD3.3V 0.01uF 0.1uF C20 C32 + VSS R24 0 Ohm,0402 VDDHS=VDD (1.8V) VD D L + C28 22uF VDDHS VD DPc Place near pin 14 of U1 VDD H S C33 22uF Place near pin 5 of U1 C27 + VDDL 0.01uF 0.1uF C26 VD D IO C17 22uF Place near pin 22 of U1 VDDIO 0.01uF 0.1uF C31 VDDHS=3.3V (externa l) JP24 VSS R23 0 Ohm,0402 VDDL=VDD (1.8V) VDDL=3.3V (externa l ) JP18 VSS C21 VDDIO=VDD (1.8V) R20 0 Ohm,0402 VDD3.3V 1 VDDHSc 2 VDD 3 VSS VDDIO=3.3V (externa l ) JP2 VDD3.3V 1 VDDLc 2 VDD 3 VDD3.3V 1 VDDI 2 VDD 3 0.1uF C1 2.2uF + 22uF C9 VDD L c VD DI JP1 OPTIONAL Exte rnal 3.3V input. F EA T UR ES/OPT ION S ON T HE D EM O B OA RD : - R 33, R 34, R 37, R 38, R 39 series 0402 size p ad s 1) Pro vid ed fo r easy sep aratio n o f each VDD d o main (n o t a u ser requ iremen t). T h is will allo w in d ivid ual IDD cu rren t measu remen ts. (L o ad ed with 0 o h m resisto rs) 2) T h is also allo ws in sertio n o f series in d u cto r in each VDD d o main (n o t a u ser req u iremen t), fo r n o ise red u ctio n experimen tatio n . - C 13-C 27 d eco up lin g capacito rs 0603 an d B size p ad s 1) It is n o t a req u iremen t th at th e u ser mu st h ave all th ese cap acito rs an d p o wer sep aratio ns in th e u ser layo u t. T h e extra cap acito rs an d p ower sep aratio n s are p ro vid ed fo r ease o f exp erimen tatio n . It is easier to u n -p o p u late th an to ad d cap acitors an d p ad s after th e fact. 2) See "T yp ical C o n n ectio n D iag ram T x - U ser R eferen ce" fo r reco mmen d ed min imu m p o wer g ro u p in g an d deco u p ling . VSS 1.8V VD D 1 2 BANANA 1 1 2 R15 3 INPUT 82.5ohm_open 2 Tab/Vout OUTPUT 1 ADJ/GND 4 1 2 1 2 DIRECT 1.8V INPUT POWER CONNECTOR J3 1 2 2 10uF_open 1 2 10uF_open 1 2 2 10uF_open 1 2 10uF_open LM1117IMP-ADJ/SOT223_open LM1117IMP-ADJ/SOT223_open R16 3 INPUT 82.5ohm_open 2 Tab/Vout OUTPUT 1 ADJ/GND 4 1 2 !!!WARNING!!! Input power thru J2 OR J3 OR J4 ONLY!! Input power thru only one connector!! VSS 1 2 VDD3.3V 1 VDDPc 2 VDD 3 VSS R21 0 Ohm,0402 VSS R22 0 Ohm,0402 6 Printed in U.S. Date: Size Title VSS R25 0 Ohm,0402 VDDL=VDD (1.8V) C24 C23 0.01uF 0.1uF C29 C30 0.01uF 0.1uF C22 0.01uF 0.1uF C25 VDDIO=1.2V (externa l ) JP23 VDD VDD 1 2 1 2 1 © National Semiconductor Corporation 2010 + + + VDD T X VDD RX VDD P C34 22uF Place near pin 11 of U1 VDDP C18 22uF Place near pin 24 of U1 VDDRX C19 22uF Place near pin 17 of U1 VDDTX Wednesday , August 05, 2009 Document Number DS90UR907 Tx Demo Board Sheet 3 DS90UR907 Tx Demo Board - Power and Decoupling 2 national.com of 3 Rev B Reference Layout Top Layer national.com © National Semiconductor Corporation 2010 Bottom Layer 7 Printed in U.S. IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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