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DS90UR907Q-Q1
SNLS316G – SEPTEMBER 2009 – REVISED DECEMBER 2015
DS90UR907Q-Q1 5 to 65-MHz, 24-Bit Color FPD-Link to FPD-Link II Converter
1 Features
3 Description
•
The DS90UR907Q-Q1 converts FPD-Link to FPDLink II. It translates four LVDS data/control streams
and one LVDS clock pair (FPD-Link) into a highspeed serialized interface (FPD-Link II) over a single
pair. This serial bus scheme greatly eases system
design by eliminating skew problems between clock
and data, reduces the number of connector pins,
reduces the interconnect size, weight, and cost, and
overall eases PCB layout. In addition, internal DC
balanced encoding is used to support AC-coupled
interconnects.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
5-MHz to 65-MHz Support (140-Mbps to 1.82Gbps Serial Link)
5-Channel (4 data + 1 clock) FPD-Link Receiver
Inputs
AC-Coupled STP Interconnect up to 10 Meters in
Length
Integrated Output Termination
At Speed Link BIST Mode
Optional I2C Compatible Serial Control Bus
RGB888 + VS, HS, DE support
Power-Down Mode Minimizes Power Dissipation
Randomizer/Scrambler – DC-Balanced Data
Stream
Low EMI FPD-Link Input
Selectable Output VOD and Adjustable DeEmphasis
1.8-V or 3.3-V Compatible Control Bus Interface
Automotive Grade Product: AEC-Q100 Grade 2
Qualified
>8-kV HBM and ISO 10605 ESD Rating
Backward Compatible Mode for Operation With
Older Generation Devices
The DS90UR907Q-Q1 converts, balances and level
shifts four LVDS data/control streams, and embeds
one LVDS clock pair (FPD-Link) to a serial stream
(FPD-Link II). Up to 24 bits of RGB in the FPD-Link
are serialized along with the three video control
signals.
Serial transmission is optimized by a user selectable
de-emphasis and differential output level select
features. EMI is minimized by the use of low voltage
differential signaling and spread spectrum clocking
compatibility.
With fewer wires to the physical interface of the host,
FPD-Link input with LVDS technology is ideal for high
speed, low power and low EMI data transfer.
The device is offered in a 36-pin WQFN package and
is specified over the automotive AEC-Q100 Grade 2
temperature range of –40˚C to 105˚C.
2 Applications
•
•
Automotive Display for Navigation
Automotive Display for Entertainment
Device Information(1)
PART NUMBER
PACKAGE
DS90UR907Q-Q1
WQFN (36)
BODY SIZE (NOM)
6.00 mm × 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Applications Diagram
FPD-Link
FPD-Link II
HOST
Graphics
Processor
RGB Style Display Interface
VDDIO
(1.8V or 3.3V)
RxCLKIN+/-
PDB
MAPSEL
CONFIG[1:0]
Optional
SCL
SDA
ID[x]
TxOUT3+/-
High-Speed Serial Link
1 Pair/AC Coupled
RxIN2+/-
RxIN0+/-
VDDIO
1.8V 3.3V (1.8V or 3.3V)
1.8V
RxIN3+/-
RxIN1+/-
FPD-Link
TxOUT2+/-
DOUT+
RIN+
DOUT-
RIN100 ohm STP Cable
DS90UR907Q
Converter
CMF
BISTEN
VODSEL
De-Emph
SSC[2:0]
LFMODE
CONFIG[1:0]
MAPSEL
Optional
SCL
SDA
ID[x]
DS90UR908Q
Converter
TxOUT1+/TxOUT0+/-
RGB Display
QVGA to XGA
24-bit Color Depth
TxCLKOUT+/-
LOCK
PASS
PDB
BISTEN
OEN
OSSEL
VODSEL
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90UR907Q-Q1
SNLS316G – SEPTEMBER 2009 – REVISED DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
7
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings—JEDEC .............................................. 5
ESD Ratings—IEC and ISO...................................... 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
DC Electrical Characteristics .................................... 6
Recommended Timing for the Serial Control Bus .... 7
Switching Characteristics .......................................... 8
DC and AC Serial Control Bus Characteristics......... 8
Typical Characteristics .......................................... 12
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2
7.3
7.4
7.5
8
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
13
13
18
18
Application and Implementation ........................ 23
8.1 Application Information............................................ 23
8.2 Typical Application .................................................. 24
9 Power Supply Recommendations...................... 26
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Example .................................................... 27
11 Device and Documentation Support ................. 30
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
30
12 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (April 2013) to Revision G
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Deleted table note from Pin Functions .................................................................................................................................. 3
•
Deleted 36L WQFN Package row from Absolute Maximum Ratings .................................................................................... 5
Changes from Revision E (April 2013) to Revision F
•
2
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 27
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SNLS316G – SEPTEMBER 2009 – REVISED DECEMBER 2015
5 Pin Configuration and Functions
RxIN0-
28
RxIN0+
29
RxIN1-
30
RxIN1+
31
RES4
MAPSEL
RES7
VDDRX
PDB
VDDIO
BISTEN
VODSEL
De-Emph
27
26
25
24
23
22
21
20
19
NJK Package
36-Pin WQFN
Top View
DAP = GND
DS90UR907Q
(Top View)
18
RES3
17
VDDTX
16
DOUT+
15
DOUT-
14
VDDHS
9
CONFIG[1]
CONFIG[0]
10
8
36
RES0
RES5
7
VDDP
SDA
11
6
35
SCL
RxCLKIN+
5
RES1
VDDL
12
4
34
ID[x]
RxCLKIN-
3
RES2
RES6
13
2
33
RxIN3+
RxIN2+
1
32
RxIN3-
RxIN2-
Pin Functions
PIN
NAME
NO.
I/O, TYPE
DESCRIPTION
FPD-LINK INPUT INTERFACE
RxIN[3:0]+
2, 33, 31, 29
I, LVDS
True LVDS Data Input
This pair requires an external 100 Ω termination for standard LVDS levels.
RxIN[3:0]-
1, 34, 32, 30,
28
I, LVDS
Inverting LVDS Data Input
This pair requires an external 100 Ω termination for standard LVDS levels.
RxCLKIN+
35
I, LVDS
True LVDS Clock Input
This pair requires an external 100 Ω termination for standard LVDS levels.
RxCLKIN-
34
I, LVDS
Inverting LVDS Clock Input
This pair requires an external 100 Ω termination for standard LVDS levels.
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SNLS316G – SEPTEMBER 2009 – REVISED DECEMBER 2015
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Pin Functions (continued)
PIN
NAME
NO.
I/O, TYPE
DESCRIPTION
CONTROL AND CONFIGURATION
PDB
23
I, LVCMOS
w/ pulldown
Power-down Mode Input
PDB = 1, Device is enabled (normal operation).
Refer to Power-Up Requirements and PDB Pin in the Applications Information Section.
PDB = 0, Device is powered down
When the Device is in the power-down state, the driver outputs (DOUT+/-) are both logic
high, the PLL is shutdown, IDD is minimized. Control Registers are RESET.
VODSEL
20
I, LVCMOS
w/ pulldown
Differential Driver Output Voltage Select — Pin or Register Control
VODSEL = 1, LVDS VOD is ±450 mV, 900 mVp-p (typical) — Long Cable / De-E
Applications
VODSEL = 0, LVDS VOD is ±300 mV, 600 mVp-p (typical)
De-Emph
19
I, Analog
w/ pullup
MAPSEL
26
I, LVCMOS
w/ pulldown
FPD-Link Map Select — Pin or Register Control
MAPSEL = 1, MSB on RxIN3+/-. Figure 17
MAPSEL = 0, LSB on RxIN3+/-. Figure 16
10, 9
I, LVCMOS
w/ pulldown
Operating Modes
Determine the device operating mode and interfacing device. Table 1
CONFIG[1:0] = 00: Interfacing to DS90UR906 or DS90UR908, Control Signal Filter
DISABLED
CONFIG[1:0] = 01: Interfacing to DS90UR906 or DS90UR908, Control Signal Filter
ENABLED
CONFIG [1:0] = 10: Interfacing to DS90UR124, DS99R124
CONFIG [1:0] = 11: Interfacing to DS90C124
ID[x]
4
I, Analog
SCL
6
I, LVCMOS
SDA
7
BISTEN
21
I, LVCMOS
w/ pulldown
BIST Mode — Optional
BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
RES[7:0]
25, 3, 36, 27,
18, 13, 12, 8
I, LVCMOS
w/ pulldown
Reserved - tie LOW
CONFIG[1:0]
De-Emphasis Control — Pin or Register Control
De-Emph = open (float) - disabled
To enable De-emphasis, tie a resistor from this pin to GND or control through register.
See Table 3
Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10-kΩ pullup to 1.8-V rail. See Table 5.
Serial Control Bus Clock Input - Optional
SCL requires an external pullup resistor to VDDIO.
I/O, LVCMOS Serial Control Bus Data Input / Output - Optional
Open Drain SDA requires an external pullup resistor VDDIO.
FPD-LINK II SERIAL INTERFACE
DOUT+
16
O, LVDS
True Output.
The output must be AC Coupled with a 100 nF capacitor.
DOUT-
15
O, LVDS
Inverting Output.
The output must be AC Coupled with a 100 nF capacitor.
POWER AND GROUND
VDDL
5
Power
Logic Power, 1.8 V ±5%
VDDP
11
Power
PLL Power, 1.8 V ±5%
VDDHS
14
Power
TX High Speed Logic Power, 1.8 V ±5%
VDDTX
17
Power
Output Driver Power, 1.8 V ±5%
VDDRX
24
Power
RX Power, 1.8 V ±5%
VDDIO
22
Power
LVCMOS I/O Power and FPD-Link I/O Power 1.8 V ±5% OR 3.3 V ±10%
GND
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
4
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SNLS316G – SEPTEMBER 2009 – REVISED DECEMBER 2015
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
Supply voltage – VDDn (1.8 V)
–0.3
2.5
V
Supply voltage – VDDIO
−0.3
4
V
LVCMOS I/O voltage
−0.3
VDDIO + 0.3
V
LVDS input voltage
−0.3
VDDIO + 0.3
V
Driver output voltage
−0.3
VDDn + 0.3
V
150
°C
150
°C
Junction temperature
−65
Storage temperature
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
6.2 ESD Ratings—JEDEC
VALUE
Human-body model (HBM), per AEC Q100-002
(1)
V(ESD)
(1)
Electrostatic discharge
UNIT
±8000
Charged-device model (CDM), per AEC Q100-011
±1250
Machine model
±250
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 ESD Ratings—IEC and ISO
VALUE
RD = 330 Ω, CS = 150 pF
V(ESD)
Electrostatic discharge
RD = 330 Ω, CS = 150 and 330 pF
RD = 2 kΩ, CS = 150 and 330 pF
IEC, powered-up only contact discharge
(RIN+, RIN−)
≥±6000
IEC, powered-up only air-gap discharge
(RIN+, RIN−)
≥±30000
UNIT
V
ISO10605 contact discharge (RIN+, RIN−)
≥±8000
ISO10605 air-gap discharge (RIN+, RIN−)
≥±15000
ISO10605 contact discharge (RIN+, RIN−)
≥±8000
ISO10605 air-gap discharge (RIN+, RIN−)
≥±15000
V
V
6.4 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
Supply Voltage (VDDn)
1.71
1.8
1.89
V
LVCMOS Supply Voltage (VDDIO)
1.71
1.8
1.89
V
3
3.3
3.6
V
−40
25
105
°C
OR
LVCMOS Supply Voltage (VDDIO)
Operating Free Air Temperature (TA)
RxCLKIN Frequency
5
Supply Noise (1)
(1)
65
MHz
100
mVP-P
Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8 V) supply with
amplitude = 100 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter
cable shows no error when the noise frequency on the Ser is less than 750 kHz. The Des on the other hand shows no error when the
noise frequency is less than 400 kHz.
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6.5 Thermal Information
DS90UR907Q-Q1
THERMAL METRIC (1)
NJK (WQFN)
UNIT
36 PINS
RθJA
Junction-to-ambient thermal resistance
33.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
15.8
°C/W
RθJB
Junction-to-board thermal resistance
7.2
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
7.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.6 DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX
UNIT
LVCMOS INPUT DC SPECIFICATIONS
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
VDDIO = 3 to 3.6 V
VDDIO = 1.71 to 1.89 V
VDDIO = 3 to 3.6 V
IIN
Input Current
VDDIO = 1.71 to 1.89 V
VIN = 0 V or VDDIO
VDDIO = 3
to 3.6 V
PDB,
VODSEL,
MAPSEL,
CONFIG[1:0],
BISTEN
2.2
VDDIO
0.65* VDDIO
VDDIO
GND
0.8
GND
0.35*
VDDIO
–15
±1
15
–15
±1
15
V
V
μA
VDDIO = 1.7
to 1.89 V
FPD-LINK LVDS RECEIVER DC SPECIFICATIONS
VTH
Differential Threshold High
Voltage
VTL
Differential Threshold Low
Voltage
|VID|
Differential Input Voltage
Swing
VCM
Common Mode Voltage
IIN
Input Current
(1)
(2)
(3)
6
100
mV
VCM = 1.2 V, Figure 1
–100
RxIN[3:0]+/-,
RxCLKIN+/-,
200
600
VDDIO = 3.3 V
0
1.2
2.4
VDDIO = 1.8 V
0
1.2
1.55
−15
±1
15
mV
V
μA
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD = 3.3 V, Ta = 25°C, and at the Recommended Operation Conditions at the
time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
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DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX
±225
±300
±375
±350
±450
±550
UNIT
FPD-LINK II LVDS DRIVER DC SPECIFICATIONS
VOD
Differential Output Voltage
VODp-p
Differential Output Voltage
(DOUT+) – (DOUT-)
VODSEL = 0
RL = 100 Ω,
VODSEL = 1
De-Emph = disabled,
VODSEL = 0
Figure 3
VODSEL = 1
ΔVOD
Output Voltage Unbalance
RL = 100 Ω, De-Emph = disabled,
VODSEL = L
VOS
Offset Voltage – Singleended
At TP A and B, Figure 2
RL = 100 Ω,
De-Emph = disabled
ΔVOS
Offset Voltage Unbalance
Single-ended
At TP A and B, Figure 2
RL = 100 Ω, De-Emph = disabled
IOS
Output Short-Circuit Current
DOUT± = 0 V,
De-Emph = disabled
RT
Internal Termination
Resistor
VODSEL = 0
VODSEL = 1
600
mVp-p
900
mVp-p
1
DOUT+,
DOUT-
VODSEL = 0
mV
50
mV
1.65
V
1.575
V
1
mV
–35
mA
80
120
Ω
80
90
mA
3
5
mA
10
13
mA
75
85
mA
3
5
mA
10
13
mA
60
1000
µA
0.5
10
µA
1
30
µA
NOM
MAX
SUPPLY CURRENT
IDDT1
IDDIOT1
IDDT2
Supply Current
(includes load current)
RL = 100 Ω, f = 65 MHz
IDDIOT2
IDDZ
IDDIOZ
Supply Current Power
Down
Checker Board
Pattern,
De-Emph = 3 kΩ,
VODSEL = H,
Figure 10
VDD= 1.89 V
Checker Board
Pattern,
De-Emph = 6 kΩ,
VODSEL = L,
Figure 10
VDD= 1.89 V
PDB = 0 V , (All
other LVCMOS
Inputs = 0 V)
All VDD pins
VDDIO= 1.89 V
VDDIO = 3.6 V
VDDIO
All VDD pins
VDDIO= 1.89 V
VDDIO = 3.6 V
VDD= 1.89 V
VDDIO= 1.89 V
VDDIO = 3.6 V
VDDIO
All VDD pins
VDDIO
6.7 Recommended Timing for the Serial Control Bus
Over 3.3-V supply and temperature ranges unless otherwise specified.
MIN
fSCL
tLOW
tHIGH
tHD;STA
tSU:STA
tHD;DAT
tSU;DAT
SCL Clock Frequency
SCL Low Period
SCL High Period
Standard Mode
0
100
Fast Mode
0
400
Standard Mode
4.7
Fast Mode
1.3
Standard Mode
Fast Mode
4
us
0.6
Standard Mode
Fast Mode
0.6
Set Up time for a start or a
repeated start condition,
Figure 12
Standard Mode
4.7
Fast Mode
0.6
Data Hold Time,
Figure 12
Standard Mode
0
3.45
Fast Mode
0
0.9
Data Set Up Time,
Figure 12
Standard Mode
250
Fast Mode
100
4
us
us
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kHz
us
Hold time for a start or a
repeated start condition,
Figure 12
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Units
us
ns
7
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SNLS316G – SEPTEMBER 2009 – REVISED DECEMBER 2015
www.ti.com
Recommended Timing for the Serial Control Bus (continued)
Over 3.3-V supply and temperature ranges unless otherwise specified.
MIN
tSU;STO
tBUF
tr
tf
NOM
MAX
Set Up Time for STOP
Condition, Figure 12
Standard Mode
Fast Mode
0.6
4
Bus Free Time
Between STOP and START,
Figure 12
Standard Mode
4.7
Fast Mode
1.3
SCL and SDA Rise Time,
Figure 12
Standard Mode
Fast Mode
300
SCL and SDA Fall Time,
Figure 12
Standard Mode
300
Fast mode
300
Units
us
us
1000
ns
ns
6.8 Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FPD-LINK LVDS INPUT
tRSP0
Receiver Strobe Position-bit 0
0.66
1.1
1.54
ns
tRSP1
Receiver Strobe Position-bit 1
2.86
3.3
3.74
ns
tRSP2
Receiver Strobe Position-bit 2
5.05
5.5
5.93
ns
tRSP3
Receiver Strobe Position-bit 3
7.25
7.7
8.13
ns
tRSP4
Receiver Strobe Position-bit 4
9.45
9.90
10.33
ns
tRSP5
Receiver Strobe Position-bit 5
11.65
12.1
12.53
ns
tRSP6
Receiver Strobe Position-bit 6
13.85
14.30
14.73
ns
RxCLKIN = 65 MHz,
RxIN[3:0]
Figure 5
FPD-LINK II LVDS OUTPUT
tHLT
tHLT
tXZD
Output Low-to-High Transition
Time, Figure 4
RL = 100 Ω, De-Emphasis = disabled, VODSEL = 0
200
RL = 100 Ω, De-Emphasis = disabled, VODSEL = 1
200
Output High-to-Low Transition
Time, Figure 4
RL = 100 Ω, De-Emphasis = disabled, VODSEL = 0
200
RL = 100 Ω, De-Emphasis = disabled, VODSEL = 1
200
Ouput Active to OFF Delay,
Figure 7
(1)
tPLD
PLL Lock Time, Figure 6
RL = 100 Ω
tSD
Delay - Latency, Figure 8
RL = 100 Ω
tDJIT
Output Total Jitter,
Figure 9
RL = 100 Ω, De-Emphasis = disabled,
RANDOM pattern, RxCLKIN = 43 and 65 MHz (2)
λSTXBW
Jitter Transfer
Function –3-dB Bandwidth (3)
δSTX
(1)
(2)
(3)
(4)
(4)
Jitter Transfer
Function Peaking (3) (4)
ps
ps
5
15
ns
1.5
10
ms
140*T
145*T
ns
0.26
RxCLKIN = 43 MHz
2.2
RxCLKIN = 65 MHz
3
RxCLKIN = 43 MHz
1
RxCLKIN = 65 MHz
1
UI
MHz
dB
tPLD is the time required by the device to obtain lock when exiting power-down state with an active RxCLKIN.
UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 28*RxCLKIN). The UI scales with RxCLKIN frequency.
Specification is ensured by characterization and is not tested in production.
Specification is ensured by design and is not tested in production.
6.9 DC and AC Serial Control Bus Characteristics
Over 3.3-V supply and temperature ranges unless otherwise specified.
PARAMETER
VIH
Input High Level
TEST CONDITIONS
SDA and SCL
MIN
TYP
0.7*
VDDIO
VIL
Input Low Level Voltage
VHY
Input Hysteresis
8
SDA and SCL
GND
>50
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MAX
UNIT
VDDIO
V
0.3*
VDDIO
V
mV
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Product Folder Links: DS90UR907Q-Q1
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SNLS316G – SEPTEMBER 2009 – REVISED DECEMBER 2015
DC and AC Serial Control Bus Characteristics (continued)
Over 3.3-V supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
VOL
SDA, IOL = 1.25 mA
Iin
SDA or SCL, Vin = VDDIO or GND
MIN
TYP
MAX
UNIT
0
0.36
V
–10
10
µA
tR
SDA RiseTime – READ
tF
SDA Fall Time – READ
tSU;DAT
Set Up Time — READ
See Figure 12
tHD;DAT
Hold Up Time — READ
See Figure 12
615
ns
tSP
Input Filter
50
ns
Cin
Input Capacitance
10 PF
R = 10 k:
R1 (cable insertion loss specific)
RID (see ID[x] Resistor Value Table)
FB1-FB5: Impedance = 1 k:,
low DC resistance (10-μF capacitor to GND to delay the PDB input signal.
All inputs must not be driven until all supply voltages have reached their steady-state value.
26
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SNLS316G – SEPTEMBER 2009 – REVISED DECEMBER 2015
10 Layout
10.1 Layout Guidelines
10.1.1 PCB Layout and Power System Considerations
Design the circuit board layout and stack-up for the LVDS devices to provide low-noise power feed to the device.
Good layout practice will also separate high-frequency or high-level inputs and outputs to minimize unwanted
stray noise pickup, feedback, and interference. Power system performance may be greatly improved by using
thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance for the
PCB power system with low-inductance parasitics, which has proven especially effective at high frequencies, and
makes the value and placement of external bypass capacitors less critical. The capacitors may use values in the
range of 0.01 uF to 0.1 uF.
TI recommends surface mount capacitors due to their smaller parasitics. When using multiple capacitors per
supply pin, place the smaller value closer to the pin. TI recommends a large bulk capacitor at the point of power
entry. This is typically in the 50-uF to 100-uF range and will smooth low-frequency switching noise. TI
recommends connecting power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with the via on both ends of the capacitor. Connecting power or ground pins to an
external bypass capacitor will increase the inductance of the path.
TI recommends a small body size X7R chip capacitor, such as the 0603, for external bypass. The X7R chip
capacitor's small body size reduces the parasitic inductance of the capacitor. The user must pay attention to the
resonance frequency of these external bypass capacitors, usually in the range of 20 to 30 MHz. To provide
effective bypassing, use multiple capacitors to achieve low impedance between the supply rails over the
frequency of interest. At high frequency, it is also a common practice to use two vias from power and ground pins
to the planes, reducing the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. The table typically provides guidance on which circuit blocks are connected to which power pin pairs. In
some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs.
Use at least a four layer board with a power and ground plane. Place LVCMOS signals away from the LVDS
lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely-coupled differential lines of 100 Ω
are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled noise
will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiate
less.
10.1.2 LVDS Interconnect Guidelines
See SNLA008 and SNLA035 for full details.
• Use 100-Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500-megabits per second line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TI
website at: www.ti.com/lvds
10.2 Layout Example
Figure 28 and Figure 29 show the PCB layout example derived from the layout design of the DS90UR907Q-Q1
Evaluation Board. The graphic and layout description are used to determine both proper routing and proper
solder techniques for designing the board.
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27
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SNLS316G – SEPTEMBER 2009 – REVISED DECEMBER 2015
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Layout Example (continued)
AC Capacitors
Length-Matched
Differential Signals.
Length-Matched
Differential Signals.
High-Speed Traces
Figure 28. Top Layer
28
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SNLS316G – SEPTEMBER 2009 – REVISED DECEMBER 2015
Layout Example (continued)
Figure 29. Bottom Layer
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SNLS316G – SEPTEMBER 2009 – REVISED DECEMBER 2015
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Application Note 1108 Channel-Link PCB and Interconnect Design-In Guidelines, SNLA008
• Application Note AN-1187, Leadless Leadframe Package (LLP), SNOA401
• Application Note 905 Transmission Line RAPIDESIGNER Operation and Applications Guide, SNLA035
• LVDS Owner’s Manual Design Guide, 4th Edition, SNLA187
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
30
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Product Folder Links: DS90UR907Q-Q1
MECHANICAL DATA
NJK0036A
SQA36A (Rev A)
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DS90UR907QSQ/NOPB
ACTIVE
WQFN
NJK
36
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 105
UR907QSQ
DS90UR907QSQE/NOPB
ACTIVE
WQFN
NJK
36
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 105
UR907QSQ
DS90UR907QSQX/NOPB
ACTIVE
WQFN
NJK
36
2500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 105
UR907QSQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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