DS90UR908QSQ/NOPB

DS90UR908Q www.ti.com SNLS317H – SEPTEMBER 2009 – REVISED APRIL 2013 DS90UR908Q 5 - 65 MHz 24-bit Color FPD-Link II to FPD-Link Converter Check for Samples: DS90UR908Q FEATURES DESCRIPTION • The DS90UR908Q converts FPD-Link II to FPD Link. It translates a high-speed serialized interface with an embedded clock over a single pair (FPD-Link II) to four LVDS data/control streams and one LVDS clock pair (FPD-Link). This serial bus scheme greatly eases system design by eliminating skew problems between clock and data, reduces the number of connector pins, reduces the interconnect size, weight, and cost, and overall eases PCB layout. In addition, internal DC balanced decoding is used to support AC-coupled interconnects. 1 2 • • • • • • • • • • • • • • • • 5 – 65 MHz Support (140 Mbps to 1.82 Gbps Serial Link) 5-Channel (4 data + 1 clock) FPD-Link Driver Outputs AC Coupled STP Interconnect up to 10 Meters in Length Integrated Input Termination @ Speed link BIST Mode and Reporting Pin Optional I2C Compatible Serial Control Bus RGB888 + VS, HS, DE Support Power Down Mode Minimizes Power Dissipation FAST Random Data Lock; No Reference Clock Required Adjustable Input Receive Equalization LOCK (Real Time Link Status) Reporting Pin Low EMI FPD-Link Output SSCG Option for Lower EMI 1.8V or 3.3V Compatible I/O Interface Automotive Grade Product: AEC-Q100 Grade 2 Qualified >8kV HBM ESD Tolerance Backward Compatible Mode For Operation with Older Generation Devices APPLICATIONS • • Automotive Display for Navigation Automotive Display for Entertainment The DS90UR908Q converter recovers the data (RGB) and control signals and extracts the clock from a serial stream (FPD-Link II). It is able to lock to the incoming data stream without the use of a training sequence or special SYNC patterns and does not require a reference clock. A link status (LOCK) output signal is provided. Adjustable input equalization of the serial input stream provides compensation for transmission medium losses of the cable and reduces the mediuminduced deterministic jitter. EMI is minimized by the use of low voltage differential signaling, output voltage level select feature, and additional output spread spectrum generation. With fewer wires to the physical interface of the display, FPD-Link output with LVDS technology is ideal for high speed, low power and low EMI data transfer. The DS90UR908Q is offered in a 48-pin WQFN package and is specified over the automotive AECQ100 grade 2 temperature range of -40˚C to +105˚C. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2013, Texas Instruments Incorporated DS90UR908Q SNLS317H – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com Applications Diagram FPD-Link FPD-Link II HOST Graphics Processor RGB Style Display Interface VDDIO (1.8V or 3.3V) VDDIO 1.8V 3.3V (1.8V or 3.3V) 1.8V RxIN3+/- TxOUT3+/- High-Speed Serial Link 1 Pair/AC Coupled RxIN2+/- TxOUT2+/- DOUT+ RxIN1+/RxIN0+/- RIN+ DOUT- TxOUT1+/TxOUT0+/- RIN100 ohm STP Cable RxCLKIN+/- DS90UR907Q Converter PDB CMF BISTEN VODSEL De-Emph MAPSEL CONFIG[1:0] SCL SDA ID[x] Optional FPD-Link SSC[2:0] LFMODE CONFIG[1:0] MAPSEL DS90UR908Q Converter TxCLKOUT+/- LOCK PASS PDB BISTEN OEN OSSEL VODSEL SCL SDA ID[x] Optional RGB Display QVGA to XGA 24-bit Color Depth LFMODE OSS_SEL MAPSEL VODSEL GND VDDL OEN BISTEN PASS/EQ LOCK GND VDDIO 36 35 34 33 32 31 30 29 28 27 26 25 Pin Diagram RES 37 24 TxOUT0- VDDA 38 23 TxOUT0+ GND 39 22 TxOUT1- RIN+ 40 21 TxOUT1+ RIN- 41 20 TxOUT2- CMF 42 19 TxOUT2+ VDDA 43 18 TxCLKOUT- DS90UR908Q TOP VIEW DAP = GND 2 Submit Documentation Feedback 11 12 CONFIG[1] ID[x] 10 VDDTX CONFIG[0] 13 9 48 GND GND 8 GND VDDP 14 7 47 SSC[2] VDDSC 6 TxOUT3+ VDDL 15 5 46 SCL VDDSC 4 TxOUT3- SDA 16 3 45 SSC[1] GND 2 TxCLKOUT+ SSC[0] 17 1 44 PDB GND Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: DS90UR908Q DS90UR908Q www.ti.com SNLS317H – SEPTEMBER 2009 – REVISED APRIL 2013 PIN DESCRIPTIONS (1) Pin Name Pin # I/O, Type Description FPD-Link II Input Interface RIN+ 40 I, LVDS True input The input must be AC coupled with a 100 nF capacitor. Internal termination. RIN- 41 I, LVDS Inverting input The input must be AC coupled with a 100 nF capacitor. Internal termination. CMF 42 I, Analog Common-Mode Filter VCM center-tap is a virtual ground which maybe ac-coupled to ground to increase receiver common mode noise immunity. Recommended value is 4.7 μF or higher. FPD-Link Output Interface TxOUT[3:0]+ 15,19, 21, 23 O, LVDS True LVDS Data Output TxOUT[3:0]- 16,20, 22, 24 O, LVDS Inverting LVDS Data Output TxCLKOUT+ 17 O, LVDS True LVDS Clock Output TxCLKOUT- 18 O, LVDS Inverting LVDS Clock Output O, LVMOS LOCK Status Output LOCK = 1, PLL is locked, output states determined by OEN. LOCK = 0, PLL is unlocked, output states determined by OSS_SEL and OEN, Table 3 May be used as a Link Status or to flag when the Video Data is active (ON/OFF). LVCMOS Outputs LOCK 27 Control and Configuration PDB 1 I, LVCMOS w/ pull-down Power Down Mode Input PDB = 1, Device is enabled (normal operation) PDB = 0, Device is in power-down, the outputs are TRI-STATE. Control registers are RESET. VODSEL 33 I, LVCMOS w/ pull-down FPD-Link Output Voltage Select, Table 4 VODSEL = 1, LVDS VOD is ±400 mV, 800 mVp-p (typ) VODSEL = 0, LVDS VOD is ±250 mV, 500 mVp-p (typ) OEN 30 I, LVCMOS w/ pull-down Output Enable Input, Table 3 OSS_SEL 35 I, LVCMOS w/ pull-down Output Sleep State Select Input, Table 3 LFMODE 36 I, LVCMOS w/ pull-down Low Frequency Mode — Pin or Register Control LF_MODE = 1, low frequency mode (TxCLKOUT = 5-20 MHz) LF_MODE = 0, high frequency mode (TxCLKOUT = 20-65 MHz) MAPSEL 34 I, LVCMOS w/ pull-down FPD-Link Map Select — Pin or Register Control MAPSEL = 1, MSB on TxOUT3+/-, Figure 16 MAPSEL = 0, LSB on TxOUT3+/-, Figure 15 CONFIG[1:0] 11,10 I, LVCMOS w/ pull-down Operating Modes — Pin or Register Control Determine the device operating mode and interfacing device, Table 1 CONFIG[1:0] = 00: Interfacing to DS90UR905Q or DS90UR907Q, Control Signal Filter DISABLED CONFIG[1:0] = 01: Interfacing to DS90UR905Q or DS90UR907Q, Control Signal Filter ENABLED CONFIG[1:0] = 10: Interfacing to DS90UR241 or DS99R421 CONFIG[1:0] = 11: Interfacing to DS90C241 SSC[2:0] 7, 3, 2 I, LVCMOS w/ pull-down Spread Spectrum Clock Generation (SSCG) Range Select, See Table 5 and Table 6 RES 37 I, LVCMOS w/ pull-down Reserved Tie Low Control and Configuration — STRAP PIN For a High State, use a 10 kΩ pull up to VDDIO; for a Low State, the IO includes an internal pull down. The STRAP pin is read upon powerup and set device configuration. Pin number listed along with shared LVCMOS Output name in square bracket. EQ (1) 28 [PASS] STRAP I, LVCMOS w/ pull-down EQ Gain Control of FPD-Link II Input EQ = 1, EQ gain is enabled (~13 dB) EQ = 0, EQ gain is disabled (~1.625 dB) 1 = High, 0 = Low Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: DS90UR908Q 3 DS90UR908Q SNLS317H – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS(1) (continued) Pin Name Pin # I/O, Type Description Optional BIST Mode BISTEN 29 I, LVCMOS w/ pull-down BIST Enable Input – Optional BISTEN = 1, BIST Mode is enabled. BISTEN = 0, normal mode. PASS 28 O, LVCMOS PASS Output (BIST Mode) – Optional PASS = 1, no errors detected PASS = 0, errors detected Leave open if unused. Route to a test point (pad) recommended. Optional Serial Bus Control Interface SCL 5 I, LVCMOS Serial Control Bus Clock Input - Optional SCL requires an external pull-up resistor to VDDIO. SDA 4 I/O, LVCMOS Serial Control Bus Data Input / Output - Optional Open Drain SDA requires an external pull-up resistor to VDDIO. ID[x] 12 I, Analog Serial Control Bus Device ID Address Select — Optional Resistor to Ground and 10 kΩ pull-up to 1.8V rail, Table 7 Power and Ground VDDL 6, 31 Power Logic Power, 1.8 V ±5% VDDA 38, 43 Power Analog Power, 1.8 V ±5% VDDP 8 Power PLL Power, 1.8 V ±5% VDDSC 46, 47 Power SSC Generator Power, 1.8 V ±5% VDDTX 13 Power FPD-Link Power, 3.3 V ±10% VDDIO 25 Power LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10% GND 9, 14, 26, 32, 39, 44, 45, 48 Ground Ground DAP DAP Ground DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connect to the ground plane (GND) with at least 9 vias. Block Diagram DS90UR908Q ± CONVERTER SSCG RINEQ Serializer RIN+ TxOUT[3] DC Balance Decoder Serial to Parallel CMF SSC[2:0] OEN VODSEL TxOUT[2] TxOUT[1] TxOUT[0] TxCLKOUT Error Detector PDB SCL SCA ID[x] BISTEN OSS_SEL LFMODE Timing and Control PLL PASS LOCK Figure 1. FPD-Link II to FPD-Link Convertor 4 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: DS90UR908Q DS90UR908Q www.ti.com SNLS317H – SEPTEMBER 2009 – REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) Supply Voltage – VDDn (1.8V) −0.3V to +2.5V Supply Voltage – VDDTX (3.3V) −0.3V to +4.0V Supply Voltage – VDDIO −0.3V to +4.0V −0.3V to +(VDDIO + 0.3V) LVCMOS I/O Voltage −0.3V to (VDD + 0.3V) Receiver Input Voltage −0.3V to (VDDTX + 0.3V) LVDS Output Voltage Junction Temperature +150°C Storage Temperature −65°C to +150°C 48L WQFN Package Maximum Power Dissipation Capacity at 25°C 1/ θJA°C/W Derate about 25°C θJA 27.7 °C/W θJC 3.0 °C/W ESD Rating (IEC, powered-up only), RD = 330Ω, CS = 150pFs ≥±15 kV Air Discharge (RIN+, RIN−) ≥±8 kV Contact Discharge (RIN+, RIN−) ESD Rating (ISO10605), RD = 330Ω, CS = 150/330pF ESD Rating (ISO10605), RD = 2kΩ, CS = 150/330pF ≥±15 kV Air Discharge (RIN+, RIN−) Contact Discharge (RIN+, RIN−) ≥±8 kV ESD Rating (HBM) ≥±8 kV ESD Rating (HBM) ≥±8 kV ESD Rating (CDM) ≥±1.25 kV (1) (2) (3) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. For soldering specifications see product folder at www.ti.com and SNOA549 If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Recommended Operating Conditions Min Nom Max Units Supply Voltage (VDDn) 1.71 1.8 1.89 V LVCMOS Supply Voltage (VDDIO) OR 1.71 1.8 1.89 V LVCMOS Supply Voltage (VDDIO) 3.0 3.3 3.6 V Operating Free Air Temperature (TA) −40 +25 +105 °C TxCLKOUT Frequency 5 Supply Noise (1) (1) 65 MHz 100 mVP-P Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8V) supply with amplitude = 100 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 750 kHz. The Des on the other hand shows no error when the noise frequency is less than 400 kHz. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: DS90UR908Q 5 DS90UR908Q SNLS317H – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com DC Electrical Characteristics (1) (2) (3) (4) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units VODSEL = L 100 250 400 mV VODSEL = H 200 450 600 FPD-Link LVDS Output |VOD| Differential Output Voltage VODp-p Differential Output Voltage A-B ΔVOD Output Voltage Unbalance RL = 100Ω Figure 8 VOS Offset Voltage ΔVOS Offset Voltage Unbalance IOS Output Short Circuit Current Vout = GND IOZ Output TRI-STATE® Current OEN = GND, Vout =VDDTX, or GND VODSEL = L 500 VODSEL = H 900 VODSEL = H TxCLKOUT+, TxCLKOUT-, VODSEL = L TxOUT[3:0]+, VODSEL = H TxOUT[3:0]- 1.0 mV mVp-p mVp-p 4 50 mV 1.2 1.5 V 50 mV 1.2 1 V -5 mA -10 +10 µA 2.2 VDDIO V GND 0.8 V +15 μA 3.3 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 3.0 to 3.6V VIH High Level Input Voltage VIL Low Level Input Voltage IIN Input Current VIN = 0V or VDDIO VOH High Level Output Voltage IOH = −2 mA VOL Low Level Output Voltage IOL = +2 mA IOS Output Short Circuit Current VOUT = 0V IOZ TRI-STATE® Output Current PDB = 0V, OSS_SEL = 0V, VOUT = 0V or VDDIO PDB, VODSEL, OEN, OSS_SEL, MAPSEL, LFMODE, SSC[2:0], BISTEN -15 ±1 VDDIO0.25 VDDIO GND LOCK, PASS V 0.2 -45 V mA -10 +10 µA 0.7* VDDIO VDDIO V GND 0.3* VDDIO V +10 μA 1.8 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 1.71 to 1.89V VIH High Level Input Voltage VIL Low Level Input Voltage IIN Input Current VIN = 0V or VDDIO VOH High Level Output Voltage IOH = −2 mA VOL Low Level Output Voltage IOL = +2 mA IOS Output Short Circuit Current VOUT = 0V IOZ TRI-STATE® Output Current VOUT = 0V or VDDIO (1) (2) (3) (4) 6 PDB, VODSEL, OEN, OSS_SEL, MAPSEL, LFMODE, SSC[2:0], BISTEN LOCK, PASS -10 ±1 VDDIO - 0.2 VDDIO GND V 0.2 -13 -15 V mA +15 µA The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Typical values represent most likely parametric norms at VDD = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. When the Serializer output is at TRI-STATE the Deserializer will lose PLL lock. Resynchronization / Relock must occur before data transfer require tPLD Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD, VTH and VTL which are differential voltages. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: DS90UR908Q DS90UR908Q www.ti.com SNLS317H – SEPTEMBER 2009 – REVISED APRIL 2013 DC Electrical Characteristics(1)(2)(3)(4) (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units +50 mV FPD-Link II LVDS RECEIVER DC SPECIFICATIONS VTH Differential Input Threshold High Voltage VTL Differential Input Threshold Low Voltage VCM Common Mode Voltage, Internal VBIAS RT Input Termination VCM = +1.2V (Internal VBIAS) RIN+, RIN- -50 mV 1.2 80 V 100 120 Ω 85 95 mA SUPPLY CURRENT IDD1 IDDTX1 Supply Current (includes load current) 65 MHz Clock IDDIO1 IDD2 IDDTX2 Supply Current (includes load current) 65 MHz Clock IDDIO2 All VDD(1.8) VDDn= 1.89V pins Checker Board Pattern, VODSEL = H VDDTX = 3.6V VDDTX SSC{2:0] = 000 VDDIO=1.89V Figure 2 VDDIO VDDIO = 3.6V All VDD(1.8) VDDn= 1.89V pins Checker Board Pattern, VODSEL = H VDDTX = 3.6V VDDTX SSC[2:0] = 111 VDDIO=1.89V Figure 2 VDDIO VDDIO = 3.6V IDDZ IDDTXZ VDD= 1.89V Supply Current Power Down PDB = 0V, All other LVCMOS Inputs = 0V IDDIOZ All VDD(1.8) pins 40 50 mA 0.3 0.8 mA 0.8 1.5 mA 95 mA 40 mA 0.3 mA 0.8 mA 0.15 2.00 mA VDDTX = 3.6V VDDTX 0.01 0.10 mA VDDIO=1.89V 0.01 0.08 mA 0.01 0.08 mA VDDIO = 3.6V VDDIO Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: DS90UR908Q 7 DS90UR908Q SNLS317H – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units FPD-Link II tDDLT tIJIT Lock Time, Figure 7 (1) Input Jitter Tolerance, Figure 10 SSC[2:0] = 000 5 MHz 7 ms SSC[2:0] = 111 5 MHz 14 ms SSC[2:0] = 000 65 MHz 6 ms SSC[2:0] = 111 65 MHz EQ = Off SSC[2:0] = 000 TxCLKOUT± = 65 MHz 8 ms Input Jitter Frequency < 2 MHz >0.9 UI Input Jitter Frequency > 6 MHz > 0.5 UI FPD-Link Output tTLHT Low to High Transition Time tTHLT High to Low Transition Time tDCCJ Cycle-to-Cycle Output Jitter (2) (3) (4) RL = 100Ω 5 MHz 65 MHz 0.3 TxCLKOUT±, TxOUT[3:0]± TxCLKOUT± 0.6 ns 0.3 0.6 ns 900 2100 ps 75 125 ps tTTP1 Transmitter Pulse Position for bit 1 1 UI tTTP0 Transmitter Pulse Position for bit 0 2 UI tTPP6 Transmitter Pulse Position for bit 6 3 UI tTTP5 Transmitter Pulse Position for bit 5 4 UI tTTP4 Transmitter Pulse Position for bit 4 5 UI tTTP3 Transmitter Pulse Position for bit 3 6 UI tTTP2 Transmitter Pulse Position for bit 2 7 UI ΔtTTP Offset Transmitter Pulse Position (bit 6— bit 0) 65 MHz, Figure 9 < +0.1 UI tDD Delay-Latency SeeFigure 4 10*T T tTPDD Power Down Delay, active to OFF 65 MHz, Figure 5 7 12 ns tTXZR Enable Delay, OFF to active 65 MHz, Figure 6 40 55 ns 5 15 ns 5 - 65 MHz, Figure 9 TxOUT[3:0]± LVCMOS Outputs tCLH Low to High Transition Time tCHL High to Low Transition Time tPASS BIST PASS Valid Time, BISTEN = 1, Figure 11 CL = 8 pF, Figure 3 5 MHz 65 MHz LOCK, PASS PASS 5 15 ns 570 580 ns 50 65 ns SSCG Mode fDEV fMOD (1) (2) (3) (4) 8 Spread Spectrum Clocking Deviation Frequency See (4) TxCLKOUT = 5 to 65 MHz, SSC[2:0] = ON ±0.5 ±2 % Spread Spectrum Clocking Modulation Frequency See (4) TxCLKOUT = 5 to 65 MHz, SSC[2:0] = ON 8 100 kHz tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK. tDCCJ is the maximum amount of jitter between adjacent clock cycles. Specification is ensured by characterization and is not tested in production. Specification is ensured by design and is not tested in production. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: DS90UR908Q DS90UR908Q www.ti.com SNLS317H – SEPTEMBER 2009 – REVISED APRIL 2013 Recommended Timing for the Serial Control Bus Over 3.3V operating supply and temperature ranges unless otherwise specified. Symbol fSCL tLOW tHIGH tHD;STA tSU:STA tHD;DAT tSU;DAT Parameter SCL Clock Frequency SCL Low Period Conditions Min Typ Max Standard Mode 0 100 Fast Mode 0 400 Units kHz Standard Mode 4.7 us Fast Mode 1.3 us Standard Mode 4.0 us Fast Mode 0.6 us Hold time for a start or a repeated start condition, Figure 12 Standard Mode 4.0 us Fast Mode 0.6 us Set Up time for a start or a repeated start condition, Figure 12 Standard Mode 4.7 us Fast Mode 0.6 us Data Hold Time, Figure 12 Standard Mode 0 3.45 us Fast Mode 0 0.9 us SCL High Period Standard Mode 250 ns Fast Mode 100 ns Set Up Time for STOP Condition, Figure 12 Standard Mode 4.0 us Fast Mode 0.6 us Bus Free Time Between STOP and START, Figure 12 Standard Mode 4.7 us Fast Mode 1.3 tr SCL & SDA Rise Time, Figure 12 Standard Mode 1000 ns Fast Mode 300 ns tf SCL & SDA Fall Time, Figure 12 Standard Mode 300 ns Fast mode 300 ns tSU;STO tBUF Data Set Up Time, Figure 12 us DC and AC Serial Control Bus Characteristics Over 3.3V supply and temperature ranges unless otherwise specified. Symbol Parameter VIH Input High Level VIL Input Low Level Voltage VHY Input Hysteresis Conditions Max Units SDA and SCL 0.7* VDDIO VDDIO V SDA and SCL GND 0.3* VDDIO V SDA, IOL = 0.5mA Iin SDA or SCL, Vin = VDDIO or GND SDA RiseTime – READ tF SDA Fall Time – READ tSU;DAT Set Up Time — READ tHD;DAT Hold Up Time — READ tSP Input Filter Cin Input Capacitance Typ >50 VOL tR Min SDA, RPU = X, Cb ≤ 400pF, Figure 12 See Figure 12 SDA or SCL mV 0 0.36 V -10 +10 µA 800 ns 50 ns 540 ns 600 ns 50 ns