DS90UR916Q
www.ti.com
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
DS90UR916Q 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement
Check for Samples: DS90UR916Q
FEATURES
DESCRIPTION
•
The DS90UR916Q FPD-Link II deserializer operates
with the DS90UR905Q FPD-Link II serializer to
deliver 24-bit digital video data over a single
differential pair. The DS90UR916Q provides features
designed to enhance image quality at the display.
The high speed serial bus scheme of FPD-Link II
greatly eases system design by eliminating skew
problems between clock and data, reduces the
number of connector pins, reduces the interconnect
size, weight, and cost, and overall eases PCB layout.
In addition, internal DC balanced decoding is used to
support AC-coupled interconnects.
1
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
5 – 65 MHz PCLK support (140 Mbps – 1.82
Gbps)
RGB888 + VS, HS, DE Support
Image Enhancement - White Balance LUTs and
Adaptive Hi-FRC Dithering
AC Coupled STP Interconnect Cable up to 10
Meters
@ Speed Link BIST Mode and Reporting Pin
I2C Compatible Serial Control Bus
Power Down Mode Minimizes Power
Dissipation
1.8V or 3.3V Compatible LVCMOS I/O Interface
Automotive Grade Product: AEC-Q100 Grade 2
Qualified
>8 kV HBM and ISO 10605 ESD Rating
FAST Random Ddata Lock; No Reference
Clock Required
Adjustable Input Receiver Equalization
LOCK (Real Time Link Status) Reporting Pin
EMI Minimization on Output Parallel Bus
(SSCG)
Output Slew Control (OS)
Backward Compatible Mode for Operation with
Older Generation Devices
APPLICATIONS
•
•
Automotive Display for Navigation
Automotive Display for Entertainment
The DS90UR916Q Des (deserializer) recovers the
data (RGB) and control signals and extracts the clock
from the serial stream. The Des locks to the incoming
serial data stream without the use of a training
sequence or special SYNC patterns, and does not
require a reference clock. A link status (LOCK) output
signal is provided. The DS90UR916Q is ideally suited
for 24-bit color applications. White balance lookup
tables and adaptive Hi-FRC dithering provide the user
a cost-effective means to enhance display image
quality.
Serial transmission is optimized with user selectable
receiver equalization. EMI is minimized by the use of
low voltage differential signaling, output slew control,
and the Des may be configured to generate Spread
Spectrum Clock and Data on its parallel outputs.
The DS90UR916Qis offered in a 60-pin WQFN
package. It is specified over the automotive AECQ100 grade 2 temperature range of -40°C to +105°C.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
DS90UR916Q
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
www.ti.com
Applications Diagram
VDDn
HOST
Graphics
Processor
RGB Digital Display Interface
VDDn
VDDIO
(1.8V or 3.3V) 1.8V
FPD-Link II
1 Pair / AC Coupled
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
PDB
100 nF
100 nF
DOUT+
RIN+
DOUT-
RIN100 ohm STP Cable
DS90UR905Q
Serializer
DS90UR916Q
Deserializer
CMF
PDB
CONFIG [1:0]
BISTEN
RFB
VODSEL
SCL
DeEmph
SDA
Optional
ID[x]
BISTEN
Optional
VDDIO
1.8V (1.8V or 3.3V)
SCL
SDA
ID[x]
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
RGB Display
QVGA to XGA
24-bit or
18-bit dithered
color depth
LOCK
PASS
STRAP pins
not shown
DAP
DAP
Figure 1.
Block Diagrams
BISTEN
PDB
SCL
SCA
ID[x]
Timing and
Control
24
Output Latch
FRC Dithering 2
RIN-
White Balance LUT
RIN+
FRC Dithering 1
Serial to Parallel
CMF
DC Balance Decoder
SSCG
RGB [7:0]
HS
VS
DE
Error
Detector
PASS
Clock and
Data
Recovery
PCLK
LOCK
STRAP INPUT
CONFIG [1:0]
LF_MODE
OS_PCLK/DATA
OSS_SEL
RFB
EQ [3:0]
OSC_SEL [2:0]
SSC [3:0]
MAPSEL [1:0]
STRAP INPUT
OP_LOW
DS90UR916Q ± DESERIALIZER
Figure 2.
2
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: DS90UR916Q
DS90UR916Q
www.ti.com
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
NC
BISTEN
VDDR
PASS/OP_LOW
R[0]/MAP_SEL[0]
R[1]/MAP_SEL[1]
R[2]
VDDIO
R[3]/SSC[0]
R[4]/SSC[1]
R[5]/SSC[2]
R[6]/SSC[3]
R[7]
LOCK
NC
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
DS90UR916Q Pin Diagram
NC
46
30
NC
RES
47
29
VDDL
VDDIR
48
28
G[0]/OSC_SEL[0]
RIN+
49
27
G[1]/OSC_SEL[1]
RIN-
50
26
G[2]/OSC_SEL[2]
CMF
51
25
G[3]
CMLOUTP
52
24
VDDIO
CMLOUTN
53
TOP VIEW
23
G[4]/EQ[0]
VDDCMLO
54
DAP = GND
22
G[5]/EQ[1]
VDDR
55
21
G[6]/EQ[2]
ID[x]
56
20
G[7]/EQ[3]
VDDPR
57
19
B[0]
VDDSC
58
18
B[1]/RFB
PDB
59
17
B[2]/OSS_SEL
NC
60
16
NC
DS90UR916Q
4
5
6
7
8
9
10
11
12
13
14
VDDSC
PCLK
DE
VS
HS
B[7]/CONFIG[0]
B[6]/CONFIG[1]
B[5]/OS_PCLK
B[4]/LF_MODE
VDDIO
B[3]/OS_DATA
NC
15
3
2
SDA
SCL
1
NC
BOLD PIN NAME ± indicates I/O strap
pin associated with output pin
Figure 3. Deserializer - DS90UR916Q — Top View
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: DS90UR916Q
3
DS90UR916Q
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
www.ti.com
DS90UR916Q Deserializer Pin Descriptions (1)
Pin Name
Pin #
I/O, Type
Description
LVCMOS Parallel Interface
R[7:0]
33, 34, 35,
36, 37, 39,
40, 41
I, STRAP,
O, LVCMOS
RED Parallel Interface Data Output Pins (MSB = 7, LSB = 0)
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 5). These pins
are inputs during power-up (See STRAP Inputs).
G[7:0]
20, 21, 22,
23, 25, 26,
27, 28
I, STRAP,
O, LVCMOS
GREEN Parallel Interface Data Output Pins (MSB = 7, LSB = 0)
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 5). These pins
are inputs during power-up (See STRAP Inputs).
B[7:0]
9, 10, 11,
12, 14, 17,
18, 19
I, STRAP,
O, LVCMOS
BLUE Parallel Interface Data Output Pins (MSB = 7, LSB = 0)
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 5). These pins
are inputs during power-up (See STRAP Inputs).
HS
8
O, LVCMOS
Horizontal Sync Output
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 5). Video
control signal pulse width must be 3 PCLKs or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2
transitions per 130 PCLKs.
VS
7
O, LVCMOS
Vertical Sync Output
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 5). Video
control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width is 130
PCLKs.
DE
6
O, LVCMOS
Data Enable Output
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 5). Video
control signal pulse width must be 3 PCLKs or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2
transitions per 130 PCLKs.
PCLK
5
O, LVCMOS
Pixel Clock Output
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 5). Strobe
edge set by RFB function.
LOCK
32
O, LVCMOS
LOCK Status Output
LOCK = 1, PLL is Locked, outputs are active LOCK = 0, PLL is unlocked, RGB[7:0], HS, VS,
DE and PCLK output states are controlled by OSS_SEL (See Table 5). May be used as Link
Status or to flag when Video Data is active (ON/OFF).
PASS
42
O, LVCMOS
PASS Output (BIST Mode)
PASS = 1, error free transmission
PASS = 0, one or more errors were detected in the received payload
Route to test point for monitoring, or leave open if unused.
Control and Configuration — STRAP PINS
For a High State, use a 10 kΩ pull up to VDDIO; for a Low State, the IO includes an internal pull down. The STRAP pins are read upon
power-up and set device configuration. Pin Number listed along with shared RGB Output name in square brackets.
CONFIG[1:0]
10 [B6],
9 [B7]
STRAP
I, LVCMOS
w/ pull-down
Operating Modes — Pin or Register Control
These pins determine the DS90UR916’s operating mode and interfacing device.
CONFIG[1:0] = 00: Interfacing to DS90UR905, Control Signal Filter DISABLED
CONFIG[1:0] = 01: Interfacing to DS90UR905, Control Signal Filter ENABLED
CONFIG[1:0] = 10: Interfacing to DS90UR241
CONFIG[1:0] = 11: Interfacing to DS90C241
LF_MODE
12 [B4]
STRAP
I, LVCMOS
w/ pull-down
SSCG Low Frequency Mode — Pin or Register Control
Only required when SSCG is enabled, otherwise LF_MODE condition is a DON’T CARE (X).
LF_MODE = 1, SSCG in low frequency mode (PCLK = 5-20 MHz)
LF_MODE = 0, SSCG in high frequency mode (PCLK = 20-65 MHz)
OS_PCLK
11 [B5]
STRAP
I, LVCMOS
w/ pull-down
PCLK Output Slew Select — Pin or Register Control
OS_PCLK = 1, increased PCLK slew
OS_PCLK = 0, normal (default)
OS_DATA
14 [B3]
STRAP
I, LVCMOS
w/ pull-down
Data Output Slew Select — Pin or Register Control
OS_DATA = 1, increased DATA slew
OS_DATA = 0, normal (default)
(1)
4
1 = HIGH, 0 = LOW.
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: DS90UR916Q
DS90UR916Q
www.ti.com
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
DS90UR916Q Deserializer Pin Descriptions(1) (continued)
Pin Name
Pin #
I/O, Type
OP_LOW
42 PASS
STRAP
I, LVCMOS
w/ pull-down
Description
Outputs held Low when LOCK = 1 — Pin or Register Control
NOTE: IT IS NOT RECOMMENDED TO USE ANY OTHER STRAP OPTIONS WITH THIS
STRAP FUNCTION
OP_LOW = 1: all outputs are held LOW during power up until released by programming
OP_LOW release/set register HIGH
NOTE: Before the device is powered up, the outputs are in tri-state.
See Figure 23 and Figure 24.
OP_LOW = 0: all outputs toggle normally as soon as LOCK goes HIGH (default).
OSS_SEL
17 [B2]
STRAP
I, LVCMOS
w/ pull-down
Output Sleep State Select — Pin or Register Control
NOTE: OSS_SEL STRAP CANNOT BE USED IF OP_LOW =1
OSS_SEL is used in conjunction with PDB to determine the state of the outputs when
inactive. (See Table 5).
RFB
18 [B1]
STRAP
I, LVCMOS
w/ pull-down
Pixel Clock Output Strobe Edge Select — Pin or Register Control
RFB = 1, parallel interface data and control signals are strobed on the rising clock edge.
RFB = 0, parallel interface data and control signals are strobed on the falling clock edge.
EQ[3:0]
20 [G7],
21 [G6],
22 [G5],
23 [G4]
STRAP
I, LVCMOS
w/ pull-down
Receiver Input Equalization — Pin or Register Control
(See Table 2).
OSC_SEL[2:0]
26 [G2],
27 [G1],
28 [G0]
STRAP
I, LVCMOS
w/ pull-down
Oscillator Select — Pin or Register Control
(See Table 6 and Table 7).
SSC[3:0]
34 [R6],
35 [R5],
36 [R4],
37 R[3]
STRAP
I, LVCMOS
w/ pull-down
Spread Spectrum Clock Generation (SSCG) Range Select — Pin or Register Control
(See Table 3 and Table 4).
MAP_SEL[1:0]
40 [R1],
41 [R0]
STRAP
I, LVCMOS
w/ pull-down
Bit Mapping Backward Compatibility / DS90UR241 Options — Pin or Register Control
Normal setting to b'00. See (Table 8).
Power Down Mode Input
PDB = 1, Des is enabled (normal operation).
Refer to POWER UP REQUIREMENTS AND PDB PIN in the Applications Information
Section.
PDB = 0, Des is in power-down.
When the Des is in the power-down state, the LVCMOS output state is determined by
Table 5. Control Registers are RESET.
Control and Configuration
PDB
59
I, LVCMOS
w/ pull-down
ID[x]
56
I, Analog
SCL
3
I, LVCMOS
SDA
2
I/O, LVCMOS Serial Control Bus Data Input / Output - Optional
Open Drain SDA requires an external pull-up resistor to VDDIO.
BISTEN
44
I, LVCMOS
w/ pull-down
BIST Enable Input — Optional
BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
RES
47
I, LVCMOS
w/ pull-down
Reserved - tie LOW
NC
1, 15, 16,
30, 31, 45,
46, 60
Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. (See Table 9).
Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to VDDIO.
Not Connected
Leave pin open (float)
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: DS90UR916Q
5
DS90UR916Q
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
www.ti.com
DS90UR916Q Deserializer Pin Descriptions(1) (continued)
Pin Name
Pin #
I/O, Type
Description
FPD-Link II Serial Interface
RIN+
49
I, LVDS
True Input. The input must be AC Coupled with a 100 nF capacitor.
RIN-
50
I, LVDS
Inverting Input. The input must be AC Coupled with a 100 nF capacitor.
CMF
51
I, Analog
Common-Mode Filter
VCM center-tap is a virtual ground which may be ac-coupled to ground to increase receiver
common mode noise immunity. Recommended value is 4.7 μF or higher.
CMLOUTP
52
O, LVDS
Test Monitor Pin — EQ Waveform
NC or connect to test point. Requires Serial Bus Control to enable.
CMLOUTN
53
O, LVDS
Test Monitor Pin — EQ Waveform
NC or connect to test point. Requires Serial Bus Control to enable.
Power and Ground (2)
VDDL
29
Power
Logic Power, 1.8 V ±5%
VDDIR
48
Power
Input Power, 1.8 V ±5%
VDDR
43, 55
Power
RX High Speed Logic Power, 1.8 V ±5%
VDDSC
4, 58
Power
SSCG Power, 1.8 V ±5%
VDDPR
57
Power
PLL Power, 1.8 V ±5%
VDDCMLO
54
Power
RX High Speed Logic Power, 1.8 V ±5%
13, 24, 38
Power
LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10% (VDDIO)
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connected to the ground plane (GND) with at least 9 vias.
VDDIO
GND
(2)
6
The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on
the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: DS90UR916Q
DS90UR916Q
www.ti.com
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
−0.3V to +2.5V
Supply Voltage – VDDn (1.8V)
−0.3V to +4.0V
Supply Voltage – VDDIO
−0.3V to +(VDDIO + 0.3V)
LVCMOS I/O Voltage
−0.3V to (VDD + 0.3V)
Receiver Input Voltage
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
60L WQFN Package
Maximum Power Dissipation Capacity at
25°C 470mW
470mW
Derate above 25C
1/θJA mW / °C
θJA(based on 9 thermal vias)
24.6 °C/W
θJC(based on 9 thermal vias)
2.8 °C/W
ESD Rating (HBM)
≥±8 kV
ESD Rating (CDM)
≥±1 kV
≥±250 V
ESD Rating (MM)
ESD Rating (ISO10605), RD = 2kΩ, CS = 150pF or RD = 2kΩ, CS = 330pF or RD = 330Ω, CS = 150pF
Air Discharge (RIN+, RIN−)
≥±30 kV
Contact Discharge (RIN+, RIN−)
≥±10 kV
ESD Rating (ISO10605), RD = 330Ω, CS = 330pF
Air Discharge (RIN+, RIN−)
≥±15 kV
Contact Discharge (RIN+, RIN−)
≥±10 kV
ESD Rating (IEC 61000–4–2), RD = 330Ω, CS = 150pF
Air Discharge (RIN+, RIN−)
≥±25 kV
Contact Discharge (RIN+, RIN−)
≥±10 kV
For soldering specifications see product folder at www.ti.com and SNOA549
(1)
(2)
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Recommended Operating Conditions
Min
Nom
Max
Units
Supply Voltage (VDDn)
1.71
1.8
1.89
V
LVCMOS Supply Voltage (VDDIO)
1.71
1.8
1.89
V
LVCMOS Supply Voltage (VDDIO)
3.0
3.3
3.6
V
Operating Free Air Temperature (TA)
−40
+25
+105
°C
65
MHz
50
mVP-P
OR
PCLK Clock Frequency
5
Supply Noise (1)
(1)
Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8V) supply with
amplitude = 100 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter
cable shows no error when the noise frequency on the Ser is less than 750 kHz. The Des on the other hand shows no error when the
noise frequency is less than 400 kHz.
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: DS90UR916Q
7
DS90UR916Q
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
www.ti.com
Deserializer DC Electrical Characteristics (1) (2) (3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symb
ol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
3.3 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 3.0 to 3.6V
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IIN
Input Current
PDB, BISTEN
VIN = 0V or VDDIO
2.2
VDDIO
V
GND
0.8
V
+15
μA
−15
±1
2.4
VDDIO
GND
VOH
High Level Output
Voltage
IOH = −2 mA, OS_PCLK/DATA = L
R[7:0], G[7:0],
B[7:0], HS, VS,
DE, PCLK, LOCK,
PASS
VOL
Low Level Output
Voltage
IOL = +2 mA, OS_PCLK/DATA = L
R[7:0], G[7:0],
B[7:0], HS, VS,
DE, PCLK, LOCK,
PASS
Output Short Circuit
Current
VDDIO = 3.3V
VOUT = 0V, OS_PCLK/DATA = L/H
PCLK
36
mA
Output Short Circuit
Current
VDDIO = 3.3V
VOUT = 0V
OS_PCLK/DATA = L/H
Des Outputs
37
mA
TRI-STATE® Output
Current
PDB = 0V, OSS_SEL = 0V,
VOUT = 0V or VDDIO
Outputs
IOS
IOZ
V
0.4
V
−15
+15
µA
1.235
VDDIO
V
1.8 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 1.71 to 1.89V
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IIN
Input Current
VIN = 0V or VDDIO
VOH
High Level Output
Voltage
IOH = −2 mA, OS_PCLK/DATA = L
VOL
Low Level Output
Voltage
IOL = +2 mA, OS_PCLK/DATA = L
Output Short Circuit
Current
VDDIO = 1.8V
VOUT = 0V
OS_PCLK/DATA = L/H
PCLK
18
mA
Output Short Circuit
Current
VDDIO = 1.8V
VOUT = 0V
OS_PCLK/DATA = L/H
Des Outputs
18
mA
IOZ
TRI-STATE® Output
Current
PDB = 0V, OSS_SEL = 0V,
VOUT = 0V or VDDIO
Outputs
VTH
Differential Input
Threshold High Voltage
IOS
VTL
Differential Input
Threshold Low Voltage
VCM
Common Mode Voltage,
Internal VBIAS
IIN
Input Current
RT
Internal Termination
Resistor
(1)
(2)
(3)
8
PDB, BISTEN
GND
−15
VDDIO
R[7:0], G[7:0],
− 0.45
B[7:0], HS, VS,
DE, PCLK, LOCK,
GND
PASS
±1
0.595
V
+15
μA
VDDIO
V
0.45
-15
+15
V
µA
+50
mV
−50
mV
VCM = +1.2V (Internal VBIAS)
RIN+, RINVIN = 0V or VDDIO
1.2
-15
80
100
V
+15
µA
120
Ω
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
Typical values represent most likely parametric norms at VDD = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: DS90UR916Q
DS90UR916Q
www.ti.com
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
Deserializer DC Electrical Characteristics(1)(2)(3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symb
ol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
CML DRIVER OUTPUT DC SPECIFICATIONS – EQ TEST PORT
VOD
Differential Output
Voltage
RL = 100Ω
VOS
Offset Voltage
Single-ended
RL = 100Ω
RT
Internal Termination
Resistor
CMLOUTP,
CMLOUTN
80
542
mV
1.4
V
100
120
Ω
93
110
mA
33
45
mA
62
75
mA
40
3000
µA
5
50
µA
10
100
µA
SUPPLY CURRENT
IDD1
IDDIO1
Deserializer
Supply Current
(includes load current)
Checker Board Pattern,
OS_PCLK/DATA = H,
EQ = 001,
SSCG=ON,CMLOUTP/N
enabled
CL = 4pF, Figure 4
Deserializer Supply
Current Power Down
PDB = 0V, All other
LVCMOS Inputs = 0V
VDD= 1.89V
VDDIO = 3.6V
VDD= 1.89V
IDDZ
IDDIOZ
All VDD pins
VDDIO=1.89V
VDDIO=1.89V
VDDIO = 3.6V
VDDIO
All VDD pins
VDDIO
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
tRCP
PCLK Output Period
tRDC
PCLK Output Duty Cycle
tCLH
LVCMOS
Low-to-High
Transition Time, Figure 5
tCHL
LVCMOS
High-to-Low
Transition Time, Figure 5
tROS
tROH
Min
Typ
Max
Units
PCLK
Pin/Freq.
15.38
T
200
ns
PCLK
43
50
57
%
SSCG=ON, 5–20MHz
35
59
65
%
SSCG=ON, 20–65MHz
40
53
60
%
SSCG=OFF, 5–65MHz
VDDIO = 1.8V
CL = 4 pF (lumped load)
PCLK/RGB[7:0], HS, VS,
DE
VDDIO = 1.8V
CL = 4 pF (lumped load)
Data Valid after PCLK – Hold
Time, Figure 9
VDDIO = 1.71 to 1.89V or
3.0 to 3.6V
CL = 4 pF (lumped load)
RGB[7:0], HS, VS, DE
Deserializer Lock Time,
Figure 8
tDD
Des Delay - Latency, Figure 6
tDPJ (2)
Des Period Jitter
2.0
ns
1.6
ns
1.5
ns
0.27
0.45
T
0.4
0.55
T
VDDIO = 3.3V
CL = 4 pF (lumped load)
RGB[7:0], HS, VS, DE
Horizontal Blanking Time
ns
PCLK/RGB[7:0], HS, VS,
DE
VDDIO = 1.71 to 1.89V or
3.0 to 3.6V
CL = 4 pF (lumped load)
tDDLT
2.1
VDDIO = 3.3V
CL = 4 pF (lumped load)
Data Valid before PCLK – Set
Up Time, Figure 9
tHBLANK
(1)
(2)
(3)
(4)
Conditions
HS
SSC[3:0] = 0000 (OFF) (1)
SSC[3:0] = 0000 (OFF)
(1)
PCLK = 5 MHz
6
tRCP
3
ms
PCLK = 65MHz
4
ms
SSC[3:0] = ON (1)
PCLK = 5MHz
30
ms
SSC[3:0] = ON (1)
PCLK = 65MHz
6
ms
139*T
140*T
ns
SSC[3:0] = OFF (3) (4)
PCLK = 5 MHz
975
1700
ps
PCLK = 10 MHz
500
1000
ps
PCLK = 65 MHz
550
1250
ps
tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK.
Specification is ensured by design and is not tested in production.
tDPJ is the maximum amount the period is allowed to deviate over many samples.
Specification is ensured by characterization and is not tested in production.
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: DS90UR916Q
9
DS90UR916Q
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
www.ti.com
Deserializer Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tDCCJ
tRJIT
(2)
Parameter
Des Cycle-to-Cycle Jitter
Des Input Jitter Tolerance,
Figure 11
Conditions
SSC[3:0] = OFF
EQ = OFF,
SSCG = OFF,
PCLK = 65MHz
(4) (5)
Pin/Freq.
Min
Typ
Max
Units
PCLK = 5 MHz
675
1150
ps
PCLK = 10 MHz
375
900
ps
PCLK = 65 MHz
500
1150
for jitter freq < 2MHz
0.9
UI (6)
for jitter freq > 6MHz
0.5
UI
ps
BIST Mode
tPASS
BIST PASS Valid Time,
BISTEN = 1, Figure 12
1
10
ns
SSCG Mode
fDEV
Spread Spectrum Clocking
Deviation Frequency
PCLK = 5 to 65 MHz,
SSC[3:0] = ON
±0.5
±2
%
fMOD
Spread Spectrum Clocking
Modulation Frequency
PCLK = 5 to 65 MHz,
SSC[3:0] = ON
8
100
kHz
(5)
(6)
10
tDCCJ is the maximum amount of jitter between adjacent clock cycles.
UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 28*PCLK). The UI scales with PCLK frequency.
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: DS90UR916Q
DS90UR916Q
www.ti.com
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
Recommended Timing for the Serial Control Bus
Over +3.3V supply and temperature ranges unless otherwise specified.
Symbol
fSCL
tLOW
tHIGH
tHD;STA
tSU:STA
tHD;DAT
tSU;DAT
Parameter
SCL Clock Frequency
Conditions
Min
Typ
Max
Units
Standard Mode
>0
100
kHz
Fast Mode
>0
400
kHz
Standard Mode
4.7
us
Fast Mode
1.3
us
Standard Mode
4.0
us
Fast Mode
0.6
us
Hold time for a start or a
repeated start condition,
Figure 13
Standard Mode
4.0
us
Fast Mode
0.6
us
Set Up time for a start or a
repeated start condition,
Figure 13
Standard Mode
4.7
us
Fast Mode
0.6
us
Data Hold Time, Figure 13
Standard Mode
0
3.45
us
Fast Mode
0
0.9
us
SCL Low Period
SCL High Period
Standard Mode
250
ns
Fast Mode
100
ns
Set Up Time for STOP
Condition, Figure 13
Standard Mode
4.0
us
Fast Mode
0.6
us
Bus Free Time Between STOP
and START, Figure 13
Standard Mode
4.7
us
Fast Mode
1.3
tr
SCL & SDA Rise Time,
Figure 13
Standard Mode
1000
ns
Fast Mode
300
ns
tf
SCL & SDA Fall Time,
Figure 13
Standard Mode
300
ns
Fast mode
300
ns
tSU;STO
tBUF
Data Set Up Time, Figure 13
us
DC and AC Serial Control Bus Characteristics
Over 3.3V supply and temperature ranges unless otherwise specified.
Max
Units
VIH
Symbol
Input High Level
Parameter
SDA and SCL
Conditions
Min
2.2
Typ
VDDIO
V
VIL
Input Low Level Voltage
SDA and SCL
GND
0.8
V
VHY
Input Hysteresis
>50
VOL
SDA, IOL = 1.25mA
Iin
SDA or SCL, Vin = VDDIO or GND
SDA, RPU = X, Cb ≤ 400pF
mV
0
0.4
V
-15
+15
µA
tR
SDA RiseTime – READ
40
ns
tF
SDA Fall Time – READ
25
ns
tSU;DAT
Set Up Time — READ
520
ns
tHD;DAT
Hold Up Time — READ
55
ns
tSP
Input Filter
50
ns
Cin
Input Capacitance
工商网监
湘ICP备2023018690号
