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DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
DS92LV241x 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer
1 Features
3 Description
•
•
•
The DS92LV2411 (Serializer) and DS92LV2412
(Deserializer) chipset translates a parallel 24–bit
LVCMOS data interface into a single high-speed CML
serial interface with embedded clock information. This
single serial stream eliminates skew issues between
clock and data, reduces connector size and
interconnect cost for transferring a 24-bit, or less, bus
over FR-4 printed circuit board backplanes,
differential or coax cables.
1
•
•
•
•
•
•
•
•
24-Bit Data, 3–Bit Control, 5 to 50 MHz Clock
Application Payloads up to 1.2 Gbps
AC Coupled Interconnects: STP up to 10 m or
Coax 20+ m
1.8 V or 3.3 V Compatible LVCMOS I/O Interface
Integrated Terminations on Ser and Des
AT-SPEED BIST Mode and Reporting Pin
Configurable by Pins or I2C Compatible Serial
Control Bus
Power Down Mode Minimizes Power Dissipation
>8 kV HBM ESD Rating
SERIALIZER — DS92LV2411
– Supports Spread Spectrum Clocking (SSC) on
Inputs
– Data Scrambler for Reduced EMI
– DC-Balance Encoder for AC Coupling
– Selectable Output VOD and Adjustable Deemphasis
DESERIALIZER — DS92LV2412
– Random Data Lock; no Reference Clock
Required
– Adjustable Input Receiver Equalization
– LOCK (Real Time Link Status) Reporting Pin
– Selectable Spread Spectrum Clock Generation
(SSCG) and Output Slew Rate Control (OS) to
Reduce EMI
2 Applications
•
•
•
•
•
•
Embedded Video and Display
Medical Imaging
Factory Automation
Office Automation — Printer, Scanner
Security and Video Surveillance
General Purpose Data Communication
In addition to the 24-bit data bus interface, the
DS92LV2411/12 also features a 3-bit control bus for
slow speed signals. This allows implementing video
and display applications with up to 24–bits per pixel
(RGB888).
Programmable
transmit
de-emphasis,
receive
equalization, on-chip scrambling and DC balancing
enables long distance transmission over lossy cables
and backplanes. The DS92LV2412 automatically
locks to incoming data without an external reference
clock or special sync patterns, providing easy “plugand-go” or “hot plug” operation. EMI is minimized by
the use of low voltage differential signaling, receiver
drive strength control, and spread spectrum clocking
capability.
The DS92LV2411/12 chipset is programmable though
an I2C interface as well as through Pins. A built-in
AT-SPEED BIST feature validates link integrity and
may be used for system diagnostics.
The DS92LV2411 is offered in a 48-Pin WQFN and
the DS92LV2412 is offered in a 60-Pin WQFN
package. Both devices operate over the full industrial
temperature range of -40°C to +85°C.
Device Information
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS92LV2411
WQFN (48)
7.00 mm × 7.00 mm
DS92LV2412
WQFN (60)
9.00 mm × 9.00 mm
4 Typical Application Schematic
VDDIO
VDDn
(1.8V or 3.3V) 1.8V
DI[7:0]
DI[15:8]
DI[23:16]
CI1
CI2
CI3
CLKIN
Graphic
Processor
OR
Video
Imager
OR
ASIC/FPGA
PDB
Channel Link II
1 Pair / AC Coupled
0.1 PF
0.1 PF
DOUT+
RIN+
DOUT-
RIN100 ohm STP Cable
DS92LV2411
Serializer
BISTEN
Optional
VDDn
VDDIO
1.8V (1.8V or 3.3V)
CMF
RFB
VODSEL
DeEmph
SCL
SDA
ID[x]
Optional
DAP
DS92LV2412
Deserializer
PDB
BISTEN
DO[7:0]
DO[15:8]
DO[23:16]
CO1
CO2
CO3
CLKOUT
24-bit RGB
Display
OR
ASIC/FPGA
LOCK
PASS
STRAP pins
not shown
SCL
SDA
ID[x]
DAP
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features .................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Typical Application Schematic............................. 1
Revision History..................................................... 2
Pin Configuration and Functions ......................... 3
Specifications....................................................... 10
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
8
Absolute Maximum Ratings ....................................
ESD Ratings............................................................
Recommended Operating Conditions.....................
Thermal Information ................................................
Serializer DC Electrical Characteristics ..................
Deserializer DC Electrical Characteristics ..............
DC and AC Serial Control Bus Characteristics.......
Recommended Timing For The Serial Control Bus
Recommended Serializer Timing For CLKIN..........
Serializer Switching Characteristics......................
Deserializer Switching Characteristics..................
Typical Characteristics ..........................................
10
10
10
11
11
12
13
14
18
19
20
21
Detailed Description ............................................ 22
8.1
8.2
8.3
8.4
8.5
8.6
9
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
22
22
23
34
34
37
Applications and Implementation ...................... 40
9.1 Application Information............................................ 40
9.2 Typical Applications ................................................ 40
10 Power Supply Recommendations ..................... 44
11 Layout................................................................... 44
11.1 Layout Guidelines ................................................. 44
11.2 Layout Example .................................................... 44
12 Device and Documentation Support ................. 47
12.1
12.2
12.3
12.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
47
47
47
47
13 Mechanical, Packaging, and Orderable
Information ........................................................... 47
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (April 2014) to Revision E
Page
•
Changed "Terminal" terminology back to "Pin" ..................................................................................................................... 1
•
Added statement about checkerboard pattern from deserializer data output when in BIST mode ..................................... 32
•
Added note that BISTEN pin must be high and REG = 0 to use BIST mode. .................................................................... 32
•
Changed deserializer Reg 0x02[6] definition to match correct OSS_SEL behavior ............................................................ 38
Changes from Revision C (April 2013) to Revision D
Page
•
Added Handling Ratings and Thermal Characteristics and updated datasheet to new layout. ............................................ 1
•
Changed Serializer Supply current power down test condition from VDDIO from 13.6V to 3.6V .......................................... 12
•
Added DC to "Deserializer Electrical Characteristics" .......................................................................................................... 12
•
Changed typical value to 36mA instead of 37mA ............................................................................................................... 12
•
Changed Test condition of VOUT for determining IOZ ........................................................................................................... 12
•
Added max value for VIL when using 1.8V I/O LVCMOS .................................................................................................... 12
•
Changed IOL from 3mA to 1.25mA ..................................................................................................................................... 13
•
Changed parentheses location of UI equation for clarification ............................................................................................ 20
•
Added characteristic graphics for serializer CML driver output and deserializer LVCMOS clock output ............................ 21
•
Added applications graphics of the serializer output with and without de-emphasis .......................................................... 43
•
Added layout example and stencil diagram graphics ........................................................................................................... 44
Changes from Revision B (April 2013) to Revision C
•
2
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 43
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Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: DS92LV2411 DS92LV2412
DS92LV2411, DS92LV2412
www.ti.com
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
6 Pin Configuration and Functions
DI9
DI8
DI7
DI6
DI5
BISTEN
VDDIO
DI4
DI3
DI2
DI1
DI0
36
35
34
33
32
31
30
29
28
27
26
25
48-Pin WQFN
Package RHS
Top View
DI10
37
24
VODSEL
DI11
38
23
De-Emph
DI12
39
22
VDDTX
DI13
40
21
PDB
DI14
41
20
DOUT+
19
DOUT-
18
RES2
DI15
42
DI16
43
DS92LV2411
TOP VIEW
DAP = GND
DI17
44
17
VDDHS
DI18
45
16
RES1
DI19
46
15
RES0
DI20
47
14
VDDP
13
CONFIG[1]
5
6
7
8
9
10
CI1
ID[x]
VDDL
SCL
SDA
CLKIN
12
4
CI3
CONFIG[0]
3
CI2
11
2
DI23
RFB
1
48
DI22
DI21
Pin Functions, DS92LV2411 Serializer (1)
PIN
NAME
NO.
TYPE
DESCRIPTION
LVCMOS PARALLEL INTERFACE
CI1
5
I, LVCMOS
w/ pull-down
Control Signal Input
For Display/Video Application:
CI1 = Data Enable Input
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter
setting.
CI2
3
I, LVCMOS
w/ pull-down
Control Signal Input
For Display/Video Application:
CI2 = Horizontal Sync Input
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter
setting.
CI3
4
I, LVCMOS
w/ pull-down
Control Signal Input
For Display/Video Application:
CI3 = Vertical Sync Input
CI3 is limited to 1 transition per 130 clock cycles. Thus, the minimum pulse width allowed is
130 clock cycle wide.
(1)
NOTE: 1 = HIGH, 0 = LOW
The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on
the PDB Pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: DS92LV2411 DS92LV2412
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DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
www.ti.com
Pin Functions, DS92LV2411 Serializer(1) (continued)
PIN
NAME
NO.
TYPE
DESCRIPTION
CLKIN
10
I, LVCMOS
w/ pull-down
Clock Input
Latch/data strobe edge set by RFB Pin.
DI[7:0]
34, 33, 32, 29,
28, 27, 26, 25
I, LVCMOS
w/ pull-down
Parallel Interface Data Input Pins
For 8–bit RED Display: DI7 = R7 – MSB, DI0 = R0 – LSB.
DI[15:8]
42, 41, 40, 39,
38, 37, 36, 35
I, LVCMOS
w/ pull-down
Parallel Interface Data Input Pins
For 8–bit GREEN Display: DI15 = G7 – MSB, DI8 = G0 – LSB.
DI[23:16]
2, 1, 48, 47,
46, 45, 44, 43
I, LVCMOS
w/ pull-down
Parallel Interface Data Input Pins
For 8–bit BLUE Display: DI23 = B7 – MSB, DI16 = B0 – LSB.
CONTROL AND CONFIGURATION
BISTEN
31
I, LVCMOS
w/ pull-down
BIST Mode — Optional
BISTEN = 0, BIST is disabled (normal operation)
BISTEN = 1, BIST is enabled
13, 12
I, LVCMOS
w/ pull-down
00: Control Signal Filter DISABLED. Interfaces with DS92LV2412 or DS92LV0412
01: Control Signal Filter ENABLED. Interfaces with DS92LV2412 or DS92LV0412
10: Reverse compatibility mode to interface with the DS90UR124 or DS99R124Q
11: Reverse compatibility mode to interface with the DS90C124
De-Emph
23
I, Analog
w/ pull-up
De-Emphasis Control
De-Emph = open (float) - disabled
To enable De-emphasis, tie a resistor from this Pin to GND or control via register.
See Table 2.
This can also be controlled by I2C register access.
ID[x]
6
I, Analog
I2C Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 11.
PDB
21
I, LVCMOS
w/ pull-down
Power-down Mode Input
PDB = 1, Ser is enabled (normal operation).
Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = 0, Ser is powered down
When the Ser is in the power-down state, the driver outputs (DOUT+/-) are both logic high,
the PLL is shutdown, IDD is minimized. Control Registers are RESET.
18, 16, 15
I, LVCMOS
w/ pull-down
Reserved - tie LOW
RFB
11
I, LVCMOS
w/ pull-down
Clock Input Latch/Data Strobe Edge Select
RFB = 1, parallel interface data and control signals are latched on the rising clock edge.
RFB = 0, parallel interface data and control signals are latched on the falling clock edge.
This can also be controlled by I2C register access.
SCL
8
I, LVCMOS
Open Drain
I2C Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to 3.3V.
SDA
9
I/O, LVCMOS I2C Serial Control Bus Data Input / Output - Optional
Open Drain SDA requires an external pull-up resistor 3.3V.
VODSEL
24
I, LVCMOS
w/ pull-down
CONFIG[1:
0]
RES[2:0]
4
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Differential Driver Output Voltage Select
VODSEL = 1, CML VOD is ±420 mV, 840 mVp-p (typ) — long cable / De-Emph applications
VODSEL = 0, CML VOD is ±280 mV, 560 mVp-p (typ) — short cable (no De-emph), low
power mode.
This is can also be control by I2C register.
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: DS92LV2411 DS92LV2412
DS92LV2411, DS92LV2412
www.ti.com
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
Pin Functions, DS92LV2411 Serializer(1) (continued)
PIN
NAME
NO.
TYPE
DESCRIPTION
CHANNEL-LINK II — CML SERIAL INTERFACE
DOUT-
19
O, CML
Inverting Output.
The output must be AC Coupled with a 0.1 µF capacitor.
DOUT+
20
O, CML
Non–Inverting Output.
The output must be AC Coupled with a 0.1 µF capacitor.
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
VDDHS
17
Power
TX High Speed Logic Power, 1.8 V ±5%
VDDIO
30
Power
LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10%
VDDL
7
Power
Logic Power, 1.8 V ±5%
VDDP
14
Power
PLL Power, 1.8 V ±5%
VDDTX
22
Power
Output Driver Power, 1.8 V ±5%
POWER AND GROUND
GND
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: DS92LV2411 DS92LV2412
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DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
www.ti.com
NC
BISTEN
VDDR
PASS/OP_LOW
DO0/MAP_SEL[0]
DO1/MAP_SEL[1]
DO2
VDDIO
DO3/SSC0
DO4/SSC1
DO5/SSC2
DO6/SSC3
DO7
LOCK
NC
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
60-Pin WQFN
Package NKB
Top View
NC
46
30
NC
RES
47
29
VDDL
VDDIR
48
28
DO8/OSC_SEL0
RIN+
49
27
DO9/OSC_SEL1
RIN-
50
26
DO10/OSC_SEL2
CMF
51
25
DO11
ROUT+
52
DS92LV2412
ROUT-
53
TOP VIEW
VDDCMLO
54
DAP = GND
VDDR
55
ID[x]
56
BOLD PIN NAME ± indicates I/O strap
pin associated with output pin
VDDIO
23
DO12/EQ0
22
DO13/EQ1
21
DO14/EQ2
20
DO15/EQ3
19
DO16
PIN
NO.
9
10
11
12
13
14
DO23/CONFIG[0]
DO22/CONFIG[1]
DO21/OS_CLKOUT
DO20/LF_MODE
VDDIO
DO19/OS_DATA
15
8
CO2
TYPE
NC
7
NC
CO3
16
6
60
CO1
NC
5
DO18/OSS_SEL
CLKOUT
17
4
59
VDDSC
PDB
3
DO17/RFB
SCL
18
2
58
SDA
VDDSC
1
57
NC
VDDPR
Pin Functions, DS92LV2412 Deserializer
NAME
24
(1)
DESCRIPTION
LVCMOS PARALLEL INTERFACE
CLKOUT
5
O, LVCMOS
Pixel Clock Output
In power-down (PDB = 0), output is controlled by the OSS_SEL Pin (See Table 6). Data
strobe edge set by RFB.
CO1
6
O, LVCMOS
Control Signal Output
For Display/Video Application:
CO1 = Data Enable Output
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter
setting.
In power-down (PDB = 0), output is controlled by the OSS_SEL Pin (See Table 6).
(1)
6
NOTE: 1 = HIGH, 0 = LOW
The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on
the PDB Pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
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Product Folder Links: DS92LV2411 DS92LV2412
DS92LV2411, DS92LV2412
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SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
Pin Functions, DS92LV2412 Deserializer
PIN
NAME
NO.
(1)
(continued)
TYPE
DESCRIPTION
CO2
8
O, LVCMOS
Control Signal Output
For Display/Video Application:
CO2 = Horizontal Sync Output
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter
setting.
In power-down (PDB = 0), output is controlled by the OSS_SEL Pin (See Table 6).
CO3
7
O, LVCMOS
Control Signal Output
For Display/Video Application:
CO3 = Vertical Sync Output
CO3 is different than CO1 and CO2 because it is limited to 1 transition per 130 clock cycles.
Thus, the minimum pulse width allowed is 130 clock cycle wide.
The CONFIG[1:0] Pins have no affect on CO3 signal
In power-down (PDB = 0), output is controlled by the OSS_SEL Pin (See Table 6).
DO[7:0]
33, 34, 35,
36, 37, 39,
40, 41
I, STRAP,
O, LVCMOS
Parallel Interface Data Output Pins
For 8–bit RED Display: DO7 = R7 – MSB, DO0 = R0 – LSB.
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 6). These
Pins are inputs during power-up (See STRAP Inputs).
DO[15:8]
20, 21, 22,
23, 25, 26,
27, 28
I, STRAP,
O, LVCMOS
Parallel Interface Data Output Pins
For 8–bit GREEN Display: DO15 = G7 – MSB, DO8 = G0 – LSB.
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 6). These
Pins are inputs during power-up (See STRAP Inputs).
DO[23:16]
9, 10, 11,
12, 14, 17,
18, 19
I, STRAP,
O, LVCMOS
Parallel Interface Data Input Pins
For 8–bit BLUE Display: DO23 = B7 – MSB, DO16 = B0 – LSB.
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 6). These
Pins are inputs during power-up (See STRAP Inputs).
LOCK
32
O, LVCMOS
LOCK Status Output
LOCK = 1, PLL is Locked, outputs are active LOCK = 0, PLL is unlocked, DO[23:0], CO1,
CO2, CO3 and CLKOUT output states are controlled by OSS_SEL (See Table 6). May be
used as Link Status or to flag when Video Data is active (ON/OFF).
PASS
42
O, LVCMOS
PASS Output (BIST Mode)
PASS = 1, error free transmission
PASS = 0, one or more errors were detected in the received payload
Route to test point for monitoring, or leave open if unused.
CONTROL AND CONFIGURATION — STRAP PINS
(2)
CONFIG[1:0]
10 [DO22],
9 [DO23]
STRAP
I, LVCMOS
w/ pull-down
00: Control Signal Filter DISABLED. Interfaces with DS92LV2411 or DS92LV0411
01: Control Signal Filter ENABLED. Interfaces with DS92LV2411 or DS92LV0411
10: Reverse compatibility mode to interface with the DS90UR241 or DS99R241
11: Reverse compatibility mode to interface with the DS90C241
EQ[3:0]
20 [DO15],
21 [DO14],
22 [DO13],
23 [DO12]
STRAP
I, LVCMOS
w/ pull-down
Receiver Input Equalization
(See Table 3).
This can also be controlled by I2C register access.
LF_MODE
12 [DO20]
STRAP
I, LVCMOS
w/ pull-down
SSCG Low Frequency Mode
Only required when SSCG is enabled, otherwise LF_MODE condition is a DON’T CARE (X).
LF_MODE = 1, SSCG in low frequency mode (CLK = 5-20 MHz)
LF_MODE = 0, SSCG in high frequency mode (CLK = 20-50 MHz)
This can also be controlled by I2C register access.
40[D],
41 [D]
STRAP
I, LVCMOS
w/ pull-down
Bit mapping reverse compatibility / DS90UR241 Options
Pin or Register Control
Default setting is b'00.
MAP_SEL[1:0]
(2)
For a High State, use a 10 kΩ pull up to VDDIO; for a Low State, the IO includes an internal pull down. The STRAP Pins are read upon
power-up and set device configuration. Pin Number listed along with shared data output name in square brackets.
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: DS92LV2411 DS92LV2412
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DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
www.ti.com
Pin Functions, DS92LV2412 Deserializer
PIN
NAME
NO.
TYPE
(1)
(continued)
DESCRIPTION
OP_LOW
42 [PASS]
STRAP
I, LVCMOS
w/ pull-down
Outputs held LOW when LOCK = 1
NOTE: Do not use any other strap options with this strap function enabled
OP_LOW = 1: all outputs are held LOW during power up until released by programming
OP_LOW release/set register HIGH.
NOTE: Before the device is powered up, the outputs are in TRI-STATE
See Figure 26 and Figure 27
OP_LOW = 0: all outputs toggle normally as soon as LOCK goes HIGH (default)
This can also be controlled by I2C register access.
OS_CLKOUT
11 [DO21]
STRAP
I, LVCMOS
w/ pull-down
Output CLKOUT Slew Select
OS_CLKOUT = 1, Increased CLKOUT slew rate
OS_CLKOUT = 0, Normal CLKOUT slew rate (default)
This can also be controlled by I2C register access.
OS_DATA
14 [DO19]
STRAP
I, LVCMOS
w/ pull-down
Output DO[23:0], CO1, CO2, CO3 Slew Select
OS_DATA = 1, Increased DO slew rate
OS_DATA = 0, Normal DO slew rate (default)
This can also be controlled by I2C register access.
OSS_SEL
17 [DO18]
STRAP
I, LVCMOS
w/ pull-down
Output Sleep State Select
OSS_SEL is used in conjunction with PDB to determine the state of the outputs in Power
Down (Sleep). (See Table 6).
NOTE: OSS_SEL STRAP CANNOT BE USED IF OP_LOW = 1
This can also be controlled by I2C register access.
RFB
18 [DO17]
STRAP
I, LVCMOS
w/ pull-down
Clock Output Strobe Edge Select
RFB = 1, parallel interface data and control signals are strobed on the rising clock edge.
RFB = 0, parallel interface data and control signals are strobed on the falling clock edge.
This can also be controlled by I2C register access.
OSC_SEL[2:0]
26 [DO10],
27 [DO9],
28 [DO8]
STRAP
I, LVCMOS
w/ pull-down
Oscillator Selectl
(See Table 7 and Table 8).
This can also be controlled by I2C register access.
SSC[3:0]
34 [DO6],
35 [DO5],
36 [DO4],
37 [DO3]
STRAP
I, LVCMOS
w/ pull-down
Spread Spectrum Clock Generation (SSCG) Range Select
(See Table 4 and Table 5).
This can also be controlled by I2C register access.
CONTROL AND CONFIGURATION
BISTEN
44
I, LVCMOS
w/ pull-down
ID[x]
56
I, Analog
NC
1, 15, 16,
30, 31, 45,
46, 60
BIST Enable Input — Optional
BISTEN = 0, BIST is disabled (normal operation)
BISTEN = 1, BIST is enabled
I2C Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. (See Table 11).
Not Connected
Leave Pin open (float)
PDB
59
I, LVCMOS
w/ pull-down
Power Down Mode Input
PDB = 1, Des is enabled (normal operation).
Refer to “Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = 0, Des is in power-down.
When the Des is in the power-down state, the LVCMOS output state is determined by
Table 6. Control Registers are RESET.
RES
47
I, LVCMOS
w/ pull-down
Reserved - tie LOW
SCL
3
I, LVCMOS
Open Drain
I2C Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to 3.3V.
SDA
2
8
I/O, LVCMOS I2C Serial Control Bus Data Input / Output - Optional
Open Drain SDA requires an external pull-up resistor to 3.3V.
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SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
Pin Functions, DS92LV2412 Deserializer
PIN
NAME
NO.
TYPE
(1)
(continued)
DESCRIPTION
CHANNEL-LINK II — CML SERIAL INTERFACE
CMF
51
I, Analog
Common-Mode Filter
VCM center-tap is a virtual ground which may be AC coupled to ground to increase receiver
common mode noise immunity. Recommended value is 4.7 μF or higher.
RIN+
49
I, CML
True Input. The input must be AC Coupled with a 0.1 μF capacitor.
RIN-
50
I, CML
Inverting Input. The input must be AC Coupled with a 0.1 μF capacitor.
ROUT+
52
O, CML
True Output — Receive Signal after the Equalizer
NC if not used or connect to test point for monitor. Requires I2C control to enable.
ROUT-
53
O, CML
Inverting Output — Receive Signal after the Equalizer
NC if not used or connect to test point for monitor. Requires I2C control to enable.
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connected to the ground plane (GND) with at least 9 vias.
54
Power
RX High Speed Logic Power, 1.8 V ± 5%
VDDIO
13, 24, 38
Power
LVCMOS I/O Power, 1.8 V ± 5% OR 3.3 V ± 10% (VDDIO)
VDDIR
48
Power
Input Power, 1.8 V ±5%
VDDL
29
Power
Logic Power, 1.8 V ±5%
POWER AND GROUND (3)
GND
VDDCMLO
VDDPR
57
Power
PLL Power, 1.8 V ±5%
VDDR
43, 55
Power
RX High Speed Logic Power, 1.8 V ±5%
VDDSC
4, 58
Power
SSCG Power, 1.8 V ±5%
(3)
Power must be supplied to all power Pins for normal operation
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Product Folder Links: DS92LV2411 DS92LV2412
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7 Specifications
7.1 Absolute Maximum Ratings (1) (2) (3)
MIN
MAX
UNIT
Supply Voltage – VDDn (1.8 V)
−0.3
2.5
V
Supply Voltage – VDDIO
−0.3
4.0
V
LVCMOS I/O Voltage
−0.3
(VDDIO + 0.3)
V
Receiver Input Voltage
−0.3
(VDD + 0.3)
V
Driver Output Voltage
−0.3
(VDD + 0.3)
V
+150
°C
+150
°C
Junction Temperature
−65
Storage Temperature Range (Tstg)
(1)
(2)
(3)
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
For soldering specifications, see product folder at www.ti.com and http://www.ti.com/lit/SNOA549
7.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
Electrostatic discharge
(1)
UNIT
±8000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
Machine Model (MM)
±250
V
IEC61000–4–2), RD = 330Ω, CS = 150pF
V(ESD)
(1)
(2)
Electrostatic discharge
Air Discharge (DOUT+, DOUT-)
±2500
Contact Discharge (DOUT+, DOUT-)
±800
Air Discharge (RIN+, DIN-)
±2500
Contact Discharge (RIN+, RIN-)
±800
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible if necessary precautions are taken. Pins listed as DOUT+, DOUT- or RIN+, DIN- may actually have higher
performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible if necessary precautions are taken. Pins listed as DOUT+, DOUT- or RIN+, DIN- may actually have higher
performance.
7.3 Recommended Operating Conditions
MIN
TYP
MAX
UNIT
Supply Voltage (VDDn)
1.71
1.8
1.89
V
LVCMOS Supply Voltage (VDDIO)
1.71
1.8
1.89
V
OR
LVCMOS Supply Voltage (VDDIO)
Operating Free Air Temperature (TA)
Clock Frequency
3.0
3.3
3.6
V
−40
+25
+85
°C
5
Supply Noise (1)
(1)
10
50
MHz
50
mVP-P
Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8V) supply with
amplitude = 100 mVp-p measured at the device VDDn Pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter
cable shows no error when the noise frequency on the Ser is less than 750 kHz. The Des on the other hand shows no error when the
noise frequency is less than 400 kHz.
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SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
7.4 Thermal Information
THERMAL METRIC (1)
RHS (2)
NKB (3)
48 PINS
60 PINS
RθJA
Junction-to-ambient thermal resistance
27.1
24.6
RθJC(top)
Junction-to-case (top) thermal resistance
4.5
2.8
(1)
(2)
(3)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Ratings for maximum dissipation capacity (215 mW).
Ratings for maximum dissipation capacity (478 mW).
7.5 Serializer DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX
UNIT
LVCMOS INPUT DC SPECIFICATIONS
VIH
High Level Input
Voltage
VIL
Low Level Input
Voltage
IIN
Input Current
VDDIO = 3.0 to 3.6V
VDDIO = 1.71 to 1.89V
VDDIO = 3.0 to 3.6V
VDDIO = 1.71 to 1.89V
VIN = 0V or VDDIO
VDDIO = 3.0 to
3.6V
DI[23:0],
CI1,CI2,CI3, CLKIN,
PDB, VODSEL,
RFB, BISTEN,
CONFIG[1:0]
2.2
VDDIO
0.65*
VDDIO
VDDIO
GND
0.8
GND
0.35*
VDDIO
–15
±1
+15
–15
±1
+15
VODSEL = 0
±205
±280
±355
VODSEL = 1
±320
±420
±520
V
V
μA
VDDIO = 1.71 to
1.89V
CML DRIVER DC SPECIFICATIONS
VOD
Differential Output
Voltage
VODp-p
Differential Output
Voltage (DOUT+) –
(DOUT-)
RL = 100Ω, Deemph = disabled,
Figure 2
VODSEL = 0
560
mVp-p
VODSEL = 1
840
mVp-p
RL = 100Ω, Deemph = disabled,
VODSEL = L
ΔVOD
1
VOS
Offset Voltage –
Single-ended At TP A
and B, Figure 1
RL = 100Ω, Deemph = disabled
RL = 100Ω, De-emph = disabled
ΔVOS
Offset Voltage
Unbalance Singleended At TP A and B,
Figure 1
IOS
Output Short Circuit
Current
RTO
Internal Output
Termination Resistor
(1)
(2)
(3)
DOUT+/- = 0V,
De-emph =
disabled
mV
VODSEL = 0
VODSEL = 1
DOUT+, DOUT-
VODSEL = 0
80
50
mV
0.65
V
1.575
V
1
mV
–36
mA
100
120
Ω
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
Current into device Pins is defined as positive. Current out of a device Pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: DS92LV2411 DS92LV2412
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Serializer DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX
UNIT
75
85
mA
3
5
mA
11
15
mA
65
75
mA
3
5
mA
11
15
mA
40
1000
µA
5
10
µA
10
20
µA
TYP
MAX
UNIT
2.2
VDDIO
V
GND
0.8
V
+15
μA
SUPPLY CURRENT
IDDT1
IDDIOT1
Serializer Supply
Current (includes load
current) RL = 100 Ω,
CLKIN = 50 MHz
IDDT2
IDDIOT2
Serializer Supply
Current Power-down
IDDZ
Checker Board
VDD = 1.89V
Pattern, De-emph
VDDIO = 1.89V
= 3kΩ, VODSEL
VDDIO = 3.6V
= H, Figure 9
All VDD Pins
Checker Board
VDD33 = 1.89V
Pattern, De-emph
VDDIO = 1.89V
= 6kΩ, VODSEL
VDDIO = 3.6V
= L, Figure 9
All VDD Pins
PDB = 0V , (All
other LVCMOS
Inputs = 0V)
All VDD Pins
IDDIOZ
VDD33 = 1.89V
VDDIO = 1.89V
VDDIO = 3.6V
VDDIO
VDDIO
VDDIO
7.6 Deserializer DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
(2) (3)
MIN
3.3 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 3.0 to 3.6V
VIH
High Level Input
Voltage
VIL
Low Level Input
Voltage
IIN
Input Current
VIN = 0V or VDDIO
VOH
High Level Output
Voltage
IOH = −0.5 mA, RDS = L
VOL
Low Level Output
Voltage
IOL = +0.5 mA, RDS = L
IOS
Output Short Circuit
Current
IOZ
TRI-STATE Output
Current
PDB, BISTEN
DO[23:0], CO1,
CO2, CO3,
CLKOUT, LOCK,
PASS
VDDIO = 3.3V, VOUT = 0V,
OS_PCLK/DATA = L/H
CLKOUT
VDDIO = 3.3V, VOUT = 0V,
OS_PCLK/DATA = L/H
Outputs
–15
±1
2.4
VDDIO
GND
V
V
0.4
36
PDB = 0V, OSS_SEL = 0V, VOUT = H Outputs
V
mA
–15
+15
μA
1.235
VDDIO
V
GND
0.595
V
+15
µA
1.8 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 1.71 to 1.89V
VIH
High Level Input
Voltage
VIL
Low Level Input
Voltage
IIN
Input Current
VIN = 0V or VDDIO
VOH
High Level Output
Voltage
IOH = −0.5 mA, RDS = L
VOL
Low Level Output
Voltage
IOL = +0.5 mA, RDS = L
IOS
Output Short Circuit
Current
(1)
(2)
(3)
12
PDB, BISTEN
DO[23:0], CO1,
CO2, CO3,
CLKOUT, LOCK,
PASS
–15
±1
VDDIO –
0.45
VDDIO
GND
V
0.45
V
VDDIO = 1.8V, VOUT = 0V,
OS_PCLK/DATA = L/H
CLKOUT
18
mA
VDDIO = 1.8V, VOUT = 0V,
OS_PCLK/DATA = L/H
Outputs
18
mA
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
Current into device Pins is defined as positive. Current out of a device Pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
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Copyright © 2010–2015, Texas Instruments Incorporated
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DS92LV2411, DS92LV2412
www.ti.com
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
Deserializer DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3)
PARAMETER
TRI-STATE Output
Current
IOZ
TEST CONDITIONS
PIN/FREQ.
MIN
PDB = 0V, OSS_SEL = 0V, VOUT = H Outputs
TYP
–15
MAX
UNIT
+15
µA
CML RECEIVER DC SPECIFICATIONS
VTH
Differential Input
VCM = +1.2V (Internal VBIAS)
Threshold High Voltage
VTL
Differential Input
Threshold Low Voltage
VCM
Common Mode
Voltage, Internal VBIAS
IIN
Input Current
RTI
Internal Input
Termination Resistor
RIN+, RIN-
+50
mV
–50
mV
12
VIN = 0V or VDDIO
–15
RIN+, RIN-
80
100
V
+15
µA
120
Ω
LOOP THROUGH CML DRIVER OUTPUT DC SPECIFICATIONS – EQ TEST PORT
Differential Output
Voltage
RL = 100Ω
VOS
Offset Voltage Singleended
RL = 100Ω
RT
Internal Termination
Resistor
VOD
542
mV
1.4
V
ROUT+/-
ROUT+/-
80
100
120
Ω
93
110
mA
33
45
mA
62
75
mA
40
3000
µA
SUPPLY CURRENT
Checker Board
Pattern, RDS =
H, CL = 4pF,
Figure 9
VDD = 1.89V
IDDIO1
Deserializer
Supply Current
(includes load current)
CLKOUT = 50 MHz
IDDZ
Deserializer Supply
Current Power Down
PDB = 0V, All
other LVCMOS
Inputs = 0V
VDD = 1.89V
IDD1
IDDIOZ
VDDIO = 1.89V
VDDIO = 3.6V
VDDIO = 1.89V
VDDIO = 3.6V
All VDD Pins
VDDIO
All VDD Pins
VDDIO
5
50
µA
10
100
µA
TYP
MAX
UNIT
7.7 DC and AC Serial Control Bus Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
VIH
Input High Level
SDA and SCL
2.2
VDD 3.3V
VIL
Input Low Level Voltage
SDA and SCL
GND
0.8
VHY
Input Hysteresis
VOL
Output Low Voltage (1)
Iin
tR
SDA RiseTime – READ
tF
tSU;DAT
>50
V
V
mV
SDA, IOL = 1.25mA, VDDIO = 3.3V
0
0.4
V
SDA or SCL, Vin = VDDIO or GND
-15
+15
µA
SDA, RPU = X, Cb ≤ 400pF
40
ns
SDA Fall Time – READ
25
ns
Set Up Time — READ
520
ns
tHD;DAT
Hold Up Time — READ
55
ns
tSP
Input Filter
50
ns
Cin
Input Capacitance