DS92LV3241, DS92LV3242
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SNLS314D – SEPTEMBER 2009 – REVISED APRIL 2013
DS92LV3241/DS92LV3242 20-85 MHz 32-Bit Channel Link II Serializer / Deserializer
Check for Samples: DS92LV3241, DS92LV3242
FEATURES
APPLICATIONS
•
•
1
2
•
•
•
•
•
•
•
•
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Wide Operating Range Embedded Clock
SER/DES
– Up to 32-bit Parallel LVCMOS Data
– 20 to 85 MHz Parallel Clock
– Up to 2.72 Gbps Application Data Paylod
Selectable Serial LVDS Bus Width
– Dual Lane Mode (20 to 50 MHz)
– Quad Lane Mode (40 to 85 MHz)
Simplified Clocking Architecture
– No Separate Serial Clock Line
– No reference Clock Required
– Receiver Locks to Random Data
On-Chip Signal Conditioning for Robust Serial
Connectivity
– Transmit Pre-Emphasis
– Data Randomization
– DC-Balance Encoding
– Receive Channel Deskew
– Supports up to 10m CAT-5 at 2.7 Gbps
Integrated LVDS Terminations
Built-in AT-SPEED BIST for End-to-End
System Testing
AC-Coupled Interconnect for Isolation and
Fault Protection
> 4KV HBM ESD Protection
Space-Saving 64-pin TQFP Package
Full Industrial Temperature Range : -40° to
+85°C
•
•
•
Industrial Imaging (Machine-Vision) and
Control
Security & Surveillance Cameras and
Infrastructure
Medical imaging
Up to 30 bits per Pixel, VGA to HD Video
Transport and Display
DESCRIPTION
The DS92LV3241 (SER) serializes a 32-bit data bus
into 2 or 4 (selectable) embedded clock LVDS serial
channels for a data payload rate up to 2.72 Gbps
over cables such as CATx, or backplanes FR-4
traces. The companion DS92LV3242 (DES)
deserializes the 2 or 4 LVDS serial data channels,
de-skews channel-to-channel delay variations and
converts the LVDS data stream back into a 32-bit
LVCMOS parallel data bus.
On-chip data Randomization/Scrambling and DC
balance encoding and selectable serializer Preemphasis ensure a robust, low-EMI transmission over
longer, lossy cables and backplanes. The
Deserializer automatically locks to incoming data
without an external reference clock or special sync
patterns, providing an easy “plug-and-lock” operation.
By embedding the clock in the data payload and
including signal conditioning functions, the ChannelLink II SerDes devices reduce trace count, eliminate
skew issues, simplify design effort and lower
cable/connector cost for a wide variety of video,
control and imaging applications. A built-in ATSPEED BIST feature validates link integrity and may
be used for system diagnostics.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2013, Texas Instruments Incorporated
DS92LV3241, DS92LV3242
SNLS314D – SEPTEMBER 2009 – REVISED APRIL 2013
www.ti.com
Block Diagram
PLL
TxCLKIN
CDR/PLL
RxCLKOUT
High-Speed Serial Data
100: differential pairs
RxOUT0
LVCMOS
RxIN1 RxIN2+
Decoding, Alignment
TxOUT1 TxOUT2+
Serial-to-Parallel
RxIN0 RxIN1 +
TxOUT1+
Cable Deskew
TxOUT0 -
Parallel-to-Serial
LVCMOS
TxIN15
TxIN16
RxIN0+
TxOUT0+
DC Balance Encoder
TxIN0
RxOUT15
RxOUT16
RxOUT31
TxIN31
TxOUT2 -
RxIN2 RxIN3 +
TxOUT3+
BIST
PDB
R_FB
BISTEN
MODE
VSEL
PRE
BIST
TxOUT3 Control
LOCK
RxIN3 REN
R_FB
PDB
Pre-Emp
Control
Tx - SERIALIZER
Rx - DESERIALIZER
Mode Diagrams
DS92LV3242
TxOUT0N
RxIN0N
TxOUT1P
RxIN1P
R
R
D
RT = 100:
RT = 100:
R
D
RT = 100:
QUAD
RxIN1N
RT = 100:
TxIN
QUAD
TxOUT1N
32
RxIN0P
RT = 100:
TxOUT0P
RT = 100:
D
RT = 100:
D
RT = 100:
DS92LV3241
R
(LVCMOS Input)
MODE = L
(Dual Mode)
32
RxOUT
(LVCMOS Output)
RxCLKOUT
(20 MHz to 50 MHz)
TxCLKIN
(20 MHz to 50 MHz)
Tx - SERIALIZER
Rx - DESERIALIZER
Figure 1. 'Dual Mode
2
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SNLS314D – SEPTEMBER 2009 – REVISED APRIL 2013
DS92LV3242
RxIN0N
TxOUT1P
RxIN1P
(LVCMOS Input)
RT = 100:
D
MODE = H
(Quad Mode)
D
TxCLKIN
(40 MHz to 85 MHz)
R
RxIN1N
TxOUT2P
RxIN2P
TxOUT2N
RxIN2N
TxOUT3P
RxIN3P
TxOUT3N
QUAD
RT = 100:
TxIN
QUAD
TxOUT1N
32
RT = 100:
TxOUT0N
R
RT = 100:
D
RxIN0P
RT = 100:
RT = 100:
D
TxOUT0P
R
RT = 100:
RT = 100:
DS92LV3241
R
32
RxOUT
(LVCMOS Output)
RxCLKOUT
(40 MHz to 85 MHz)
RxIN3N
Rx - DESERIALIZER
Tx - SERIALIZER
Figure 2. Quad Mode
TxIN13
TxIN12
TxIN11
TxIN10
TxIN9
VSS
VDD
TxIN8
TxIN7
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN1
TxIN0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DS92LV3241 Pin Diagram
IOVDD
49
32
VDD
IOVSS
50
31
VSS
TxIN14
51
30
TxOUT0+
TxIN15
52
29
TxOUT0-
VDDPLL
53
28
TxOUT1+
VSSPLL
54
27
TxOUT1-
VSSPLL
55
26
VDDA
VDDPLL
56
25
VSSA
TxIN16
57
24
TxOUT2+
TxIN17
58
23
TxOUT2-
TxIN18
59
22
TxOUT3+
TxIN19
60
21
TxOUT3-
TxIN20
61
20
VSEL
TxIN21
62
19
PRE
TxIN22
63
18
VDD
TxIN23
64
17
VSS
8
9
10
11
12
13
14
15
16
TxIN29
TxIN30
TxIN31
TxCLKIN
PDB
BISTEN
R_FB
MODE
RSVD
5
TxIN28
7
4
TxIN27
6
3
TxIN26
VSS
2
TxIN25
VDD
1
TxIN24
DS92LV3241
Figure 3. DS92LV3241 Pin Diagram- Top View
64-Pin TQFP (PAG Package)
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: DS92LV3241 DS92LV3242
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DS92LV3241, DS92LV3242
SNLS314D – SEPTEMBER 2009 – REVISED APRIL 2013
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DS92LV3241 Serializer PIN DESCRIPTIONS
Pin #
Pin Name
I/O, Type
Description
LVCMOS PARALLEL INTERFACE PINS
10–8,
5–1,
64–57,
52–51,
48–44.
41–33
TxIN[31:29],
TxIN[28:24],
TxIN[23:16],
TxIN[15:14],
TxIN[13:9],
TxIN[8:0]
I, LVCMOS
Serializer Parallel Interface Data Input Pins.
11
TxCLKIN
I, LVCMOS
Serializer Parallel Interface Clock Input Pin. Strobe edge set by R_FB configuration pin.
CONTROL AND CONFIGURATION PINS
12
PDB
I, LVCMOS
Serializer Power Down Bar (ACTIVE LOW)
PDB = L; Device Disabled, Differential serial outputs are put into TRI-STATE stand-by mode,
PLL is shutdown
PDB = H; Device Enabled
15
MODE
I, LVCMOS
Dual or Quad mode select (ACTIVE H)
MODE = L (default); Dual Mode,
MODE = H; Quad Mode
19
PRE
I, LVCMOS
PRE-emphasis level select pin
PRE = (RPRE > 12kΩ); Imax = [(1.2/R) x 20 x 2], Rmin = 12kΩ.
PRE = H or floating; pre-emphasis is disabled.
14
R_FB
I, LVCMOS
Rising/Falling Bar Clock Edge Select
R_FB = H; Rising Edge,
R_FB = L; Falling Edge
20
VSEL
I, LVCMOS
VOD (Differential Output Voltage) Llevel Select
VSEL = L; Low Swing,
VSEL = H; High Swing
13
BISTEN
I, LVCMOS
BIST Enable
BISTEN = L; BIST OFF, (default), normal operating mode.
BISTEN = H; BIST Enabled (ACTIVE HIGH)
16
RSVD
I, LVCMOS
Reserved — MUST BE TIED LOW
LVDS SERIAL INTERFACE PINS
22, 24,
28, 30
TxOUT[3:0]+
O, LVDS
Serializer LVDS Non-Inverted Outputs(+)
21, 23,
27, 29
TxOUT[3:0]-
O, LVDS
Serializer LVDS Inverted Outputs(-)
7, 18, 32, VDD
42
VDD
Digital Voltage supply, 3.3V
6, 17, 31, VSS
43
GND
Digital ground
53, 56
VDDPLL
VDD
Analog Voltage supply, PLL POWER, 3.3V
54, 55
VSSPLL
GND
Analog ground, PLL GROUND
26
VDDA
VDD
Analog Voltage supply
25
VSSA
GND
Analog ground
49
IOVDD
VDD
Digital IO Voltage supply
Connect to 1.8V typ for 1.8V LVCMOS interface
Connect to 3.3V typ for 3.3V LVCMOS interface
50
IOVSS
GND
Digital IO ground
POWER / GROUND PINS
4
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SNLS314D – SEPTEMBER 2009 – REVISED APRIL 2013
DS92LV3242 Pin Diagram
R_FB
RSVD
RxOUT0
RxOUT1
RxOUT2
RxOUT3
RxOUT4
VSSPLL
VDDPLL
RxOUT5
RxOUT6
RxOUT7
RxOUT8
RxOUT9
RxOUT10
RxOUT11
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Top View
PDB
49
32
RxOUT12
REN
50
31
RxOUT13
RxIN0+
51
30
RxOUT14
RxIN0-
52
29
RxOUT15
RxIN1+
53
28
RxOUT16
RxIN1-
54
27
VSS
VDDA
55
26
VDD
DS92LV3242
VSSA
56
25
RxOUT17
RxIN2+
57
24
RxOUT18
RxIN2-
58
23
RxOUT19
RxIN3+
59
22
RxOUT20
RxIN3-
60
21
RxOUT21
VDD
61
20
RxOUT22
14
15
RxOUT24
VSS
16
13
RxOUT25
VDD
12
RxOUT26
9
VDD
11
8
VSS
10
7
RxOUT29
RxOUT27
6
RxOUT30
RxOUT28
5
RxOUT31
VDD
4
17
3
64
LOCK
VDDPLL
RxCLKOUT
VSS
2
RxOUT23
18
VSSPLL
19
63
1
62
VDDPLL
VSS
VSSPLL
Figure 4. DS92LV3242 Pin Diagram
64-Pin TQFP (PAG Package)
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DS92LV3241, DS92LV3242
SNLS314D – SEPTEMBER 2009 – REVISED APRIL 2013
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DS92LV3242 Deserializer PIN DESCRIPTIONS
Pin #
Pin Name
I/O, Type
Description
LVCMOS PARALLEL INTERFACE PINS
5–7,
10–14,
19–25,
28–32,
33–39,
42–46
RxOUT[31:29],
RxOUT[28:24],
RxOUT[23:17],
RxOUT[16:12],
RxOUT[11:5],
RxOUT[4:0]
O, LVCMOS
Deserializer Parallel Interface Data Output Pins.
4
RxCLKOUT
O, LVCMOS
Deserializer Recovered Clock Output. Parallel data rate clock recovered from the embedded
clock.
3
LOCK
O, LVCMOS
LOCK indicates the status of the receiver PLL LOCK = L; deserializer CDR/PLL is not locked,
RxOUT[31:0] and RCLK are TRI-STATED
LOCK = H; deserializer CDR/PLL is locked
CONTROL AND CONFIGURATION PINS
48
R_FB
I, LVCMOS
Rising/Falling Bar Clock Edge Select
R_FB = H; RxOUT clocked on rising edge
R_FB = L; RxOUT clocked on falling edge
50
REN
I, LVCMOS
Deserializer Enable, DES Output Enable Control Input (ACTIVE HIGH)
REN = L; disabled, RxOUT[31:0] and RxCLKOUT TRI-STATED, PLL still operational
REN = H; Enabled (ACTIVE HIGH)
49
PDB
I, LVCMOS
Power Down Bar, Control Input Signal (ACTIVE LOW)
PDB = L; disabled, RxOUT[31:0], RCLK, and LOCK are TRI-STATED in stand-by mode, PLL
is shutdown
PDB = H; Enabled
47
RSVD
I, LVCMOS
Reserved — MUST BE TIED LOW
LVDS SERIAL INTERFACE PINS
51, 53,
57, 59
RxIN[0:3]+
I, LVDS
Deserializer LVDS Non-Inverted Inputs(+)
52, 54,
58, 60
RxIN[0:3]-
I, LVDS
Deserializer LVDS Inverted Inputs(-)
POWER / GROUND PINS
9, 16,
17, 26,
61
VDD
VDD
Digital Voltage supply, 3.3V
8, 15,
18, 27,
62
VSS
GND
Digital Ground
55
VDDA
VDD
Analog LVDS Voltage supply, POWER, 3.3V
56
VSSA
GND
Analog LVDS GROUND
1, 40,
64
VDDPLL
VDD
Analog Voltage supply PLL VCO POWER, 3.3V
2, 41,
63
VSSPLL
GND
Analog ground, PLL VCO GROUND
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6
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SNLS314D – SEPTEMBER 2009 – REVISED APRIL 2013
Absolute Maximum Ratings (1) (2)
−0.3V to +4V
Supply Voltage (VDD)
LVCMOS Input Voltage
−0.3V to (VDD +0.3V)
LVCMOS Output Voltage
−0.3V to (VDD +0.3V)
LVDS Deserializer Input Voltage
−0.3V to +3.9V
LVDS Driver Output Voltage
−0.3V to +3.9V
Junction Temperature
+125°C
Storage Temperature
−65°C to +150°C
Lead Temperature (Soldering, 4 seconds)
+260°C
Maximum Package Power Dissipation Capacity Package Derating
1/θJA °C/W above +25°C
θJA
35.7 °C/W (3)
θJC
12.6 °C/W
ESD Rating (HBM)
(1)
(2)
(3)
>4 kV
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
4 Layer JEDEC
Recommended Operating Conditions
Min
Nom
Max
Units
3.135
3.3
3.465
V
3.3V I/O Interface
3.135
3.3
3.465
V
1.8V I/O Interface
1.71
1.8
1.89
V
−40
+25
Supply Voltage (VDD)
Supply Voltage(IOVDD)
(SER ONLY)
Operating Free Air Temperature (TA)
Input Clock Rate
+85
°C
Dual Mode
20
50
MHz
Quad Mode
40
85
MHz
100
mVP-P
Tolerable Supply Noise
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Electrical Characteristics (1) (2)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVCMOS DC SPECIFICATIONS
VIH
High Level Input Voltage
Tx: IOVDD = 1.71V to 1.89V
Rx
Low Level Input Voltage
IOVDD +
0.3
2.0
VDD
GND
0.35 x
IOVDD
GND
0.8
V
Tx: IOVDD = 3.135V to 3.465V
VIL
0.65 x
IOVDD
Tx: IOVDD = 1.71V to 1.89V
V
Tx: IOVDD = 3.135V to 3.465V
Rx
VCL
Input Clamp Voltage
ICL = −18 mA
IIN
Input Current
Tx: VIN = 0V or 3.465V(1.89V)
IOVDD = 3.465V(1.89V)
−10
+10
Rx: VIN = 0V or 3.465V
−10
+10
VOH
−0.8
IOH = −2mA (Dual)
High Level Output Voltage
VDD
V
GND
0.33
0.5
V
VOUT = 0V (Dual)
−22
−40
mA
VOUT = 0V (Quad)
−33
−70
mA
+10
μA
440
(850)
525
(1000)
mVP-P
1
50
mVP-P
1.25
1.50
V
4
50
mV
IOH = −2mA (Quad)
IOS
Output Short Circuit Current
IOZ
TRI-STATE Output Current
µA
3.0
IOH = −2mA (Dual)
Low Level Output Voltage
V
2.4
IOH = −2mA (Quad)
VOL
−1.5
PDB = 0V,
VOUT = 0V or VDD
−10
SERIALIZER LVDS DC SPECIFICATIONS
VOD
Output Differential Voltage
No pre-emphasis, VSEL = L
(VSEL = H)
ΔVOD
Output Differential Voltage Unbalance
VSEL = L, No pre-emphasis
VOS
Offset Voltage
VSEL = L, No pre-emphasis
ΔVOS
Offset Voltage Unbalance
VSEL = L, No pre-emphasis
IOS
Output Short Circuit Current
TxOUT[3:0] = 0V, PDB = VDD,
VSEL = L, No pre-emphasis
−2
−5
TxOUT[3:0] = 0V, PDB = VDD,
VSEL = H, No pre-emphasis
−6
−10
PDB = 0V,
TxOUT[3:0] = 0V OR VDD
−15
±1
+15
µA
PDB = VDD,
TxOUT[3:0] = 0V OR VDD
−15
±1
+15
µA
Internal differential output termination
between differential pairs
90
100
130
Ω
f = 85 MHz, CHECKER BOARD pattern
MODE = H, VSEL = H, PRE = OFF
150
200
f = 85 MHz, CHECKER BOARD pattern
MODE = H, VSEL = H, RPRE = 12 kΩ
150
200
f = 85 MHz, RANDOM pattern
MODE = H, VSEL = H, PRE = OFF
140
195
f = 85 MHz, RANDOM pattern
MODE = H, VSEL = H, RPRE = 12 kΩ
140
195
IOZ
TRI-STATE Output Current
RT
Output Termination
SERIALIZER SUPPLY CURRENT (DVDD, PVDD AND AVDD PINS)
IDDTQ
(1)
(2)
(3)
8
Serializer (Tx) Total Supply Current
Quad Mode
(includes load current)
350
(629)
1.00
mA
(3)
mA
Typical values represent most likely parametric norms at VDD = 3.3V, TA = +25°C, and at the Recommended Operating Conditions at
the time of product characterization and are not verified.
Current into a the device is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH, VTL which are differential voltages.
DIGITAL, PLL, AND ANALOG VDDS
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SNLS314D – SEPTEMBER 2009 – REVISED APRIL 2013
Electrical Characteristics(1)(2) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
IDDTD
IDDTZ
Parameter
Conditions
Serializer (Tx) Total Supply Current
Dual Mode
(includes load current)
Serializer Supply Current
Power-down
Min
Typ
Max
Units
f= 50 MHz, CHECKER BOARD pattern
MODE = L, VSEL = H, PRE = OFF
120
145
f= 50 MHz, CHECKER BOARD pattern
MODE = H, VSEL = H, RPRE = 12 kΩ
120
145
f= 50 MHz, RANDOM pattern
MODE = L, VSEL = H, PRE = OFF
115
135
f= 50 MHz, RANDOM pattern
MODE = L, VSEL = H, RPRE = 12 kΩ
115
135
2
50
µA
+50
mV
mA
TPWDNB = 0V
(All other LVCMOS Inputs = 0V)
DESERIALIZER LVDS DC SPECIFICATIONS
VTH
Differential Threshold High Voltage
VTL
Differential Threshold Low Voltage
VCM = +1.8V
RT
Input Termination
Internal differential output termination
between differential pairs
IIN
Input Current
−50
mV
100
130
Ω
VIN = +2.4V, VDD = 3.6V
±100
±250
µA
VIN = 0V, VDD = 3.6V
±100
±250
µA
f = 85 MHz, CL = 8 pF,
CHECKER BOARD pattern, Quad Mode
240
265
f = 85 MHz, CL = 8 pF,
RANDOM pattern, Quad Mode
190
210
f = 50 MHz, CL = 8 pF,
CHECKER BOARD pattern, Dual Mode
145
185
f = 50 MHz, CL = 8 pF,
RANDOM pattern, Dual Mode
122
140
90
DESERIALIZER SUPPLY CURRENT (DVDD, PVDD AND AVDD PINS) (4)
IDDR
IDDRZ
(4)
Deserializer Total Supply Current
(includes load current)
mA
mA
Deserializer Supply Current Power-down PDB = 0V
(All other LVCMOS Inputs = 0V,
RxIN[3:0](P/N) = 0V)
100
µA
Units
DIGITAL, PLL, AND ANALOG VDDS
Serializer Input Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tCIP
tCIH
tTCIL
tCIT
tJIT
Parameter
Conditions
TxCLKIN Period
TxCLKIN High Time
TxCLKIN Low Time
TxCLKIN Transition Time
Min
Typ
Max
MODE = L (Dual Mode)
20
tCIP
50
MODE = H (Quad Mode)
11.76
tCIP
25
20 MHz – 50 MHz
0.45 x
tCIP
0.5 x tCIP
0.55 x
tCIP
40 MHz – 85 MHz
0.45 x
tCIP
0.5 x tCIP
0.55 x
tCIP
20 MHz – 50 MHz
Figure 7
0.45 x
tCIP
0.5 x tCIP
0.55 x
tCIP
40 MHz – 85 MHz
0.45 x
tCIP
0.5 x tCIP
0.55 x
tCIP
20 MHz – 50 MHz
Figure 6
0.5
1.2
40 MHz – 85 MHz
0.5
1.2
TxCLKIN Jitter
±100
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ns
ns
ns
ns
psP-P
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Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
tLLHT
LVDS Low-to-High Transition Time
tLHLT
LVDS High-to-Low Transition Time
tSTC
TxIN[31:0] Setup to TxCLKIN
tHTC
TxIN[31:0] Hold from TxCLKIN
tPLD
Serializer PLL Lock Time
Min
No pre-emphasis
Figure 5
IOVDD = 1.71V to 1.89V
Figure 7
0
IOVDD = 3.135V to 3.465V
0
IOVDD = 1.71V to 1.89V
2.5
IOVDD = 3.135V to 3.465V
2.25
Figure 9
Typ
Data Output LOW to TRI-STATE
Delay
See
tHZD
Data Output TRI-STATE to HIGH
Delay
See (1)
tSD
Serializer Propagation Delay - Latency f = 50 MHz,
R_FB = H,
PRE = OFF,
MODE = L
Figure 8
350
ps
350
ps
ns
ns
4400 x
tCIP
5000 x
tCIP
ns
5
10
ns
5
10
ns
4.5 tCIP +
6.77
f = 50 MHz,
R_FB = L,
PRE = OFF,
MODE = L
4.5 tCIP + 4.5 tCIP + 4.5 tCIP +
5.63
7.09
9.29
f = 20 MHz,
R_FB = H,
PRE = OFF,
MODE = L
4.5 tCIP + 4.5 tCIP + 4.5 tCIP +
6.57
8.74
10.74
f = 85MHz,
R_FB = H,
PRE = OFF,
MODE = H
9.0 tCIP +
6.99
f = 85MHz,
R_FB = L,
PRE = OFF,
MODE = H
9.0 tCIP + 9.0 tCIP + 9.0 tCIP +
5.97
7.38
9.64
f = 40 MHz,
R_FB = HL,
PRE = OFF,
MODE = H
9.0 tCIP + 9.0 tCIP + 9.0 tCIP +
6.30
8.26
10.49
ns
tLVSKD
LVDS Output Skew
LVDS differential output channel-tochannel skew
30
ΛSTXBW
Jitter Transfer Function -3 dB
Bandwidth
Dual Mode
f = 50 MHz
Figure 15
2.8
Quad Mode
f = 85 MHz
2
Dual Mode
f = 50 MHz
0.3
Quad Mode
f = 85 MHz
0.9
(1)
10
Serializer Jitter Transfer Function
Peaking
Units
(1)
tLZD
δSTX
Max
500
ps
MHz
dB
When the Serializer output is at TRI-STATE the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
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Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tROCP
Parameter
Conditions
Receiver Output Clock Period
tRODC
RxCLKOUT Duty Cycle
tROTR
LVCMOS Low-to-High Transition
Time
tROTF
LVCMOS High-to-Low Transition
Time
tROTR
LVCMOS Low-to-High Transition
Time
tROTF
LVCMOS High-to-Low Transition
Time
tROSC
RxOUT[31:0] Setup to RxCLKOUT
tROHC
RxOUT[31:0] Hold to RxCLKOUT
tROSC
RxOUT[31:0] Setup to RxCLKOUT
tROHC
RxOUT[31:0] Hold to RxCLKOUT
tHZR
Data Output High to TRI-STATE
Delay
tLZR
Min
Typ
Max
tROCP = tCIP
(Dual Mode)
Figure 11
20
tROCP
50
tROCP = tCIP
(Quad Mode)
11.76
tROCP
25
45
50
55
ns
CL = 8pF (lumped load)
(Dual Mode)
Figure 10
CL = 8pF (lumped load)
(Quad Mode)
f = 85 MHz
(Quad Mode)
Figure 13
%
3.2
ns
3.5
ns
ns
2.4
ns
1.9
f = 50 MHz
(Dual Mode)
Units
5.6
0.5 x
tROCP
ns
7.4
0.5 x
tROCP
ns
3.4
0.5 x
tROCP
ns
3.4
0.5 x
tROCP
ns
5
10
ns
Data Output Low to TRI-STATE
Delay
5
10
ns
tZHR
Data Output TRI-STATE to High
Delay
5
10
ns
tZLR
Data Output TRI-STATE to Low
Delay
5
10
ns
tRD
Deserializer Propagation Delay –
Latency
tRPLLS (1)
Deserializer PLL Lock Time
TOLJIT
Deserializer Input Jitter Tolerance
tLVSKR
LVDS Differential Input Skew
Tolerance
(1)
f = 20 MHz
(Dual Mode)
Figure 12
5.5 x
tROCP +
3.35
ns
f = 50 MHz
(Dual Mode)
5.5 x
tROCP +
6.00
ns
f = 40 MHz
(Quad Mode)
12.0 x
tROCP +
7.4
ns
f = 85 MHz
(Quad Mode)
12.0 x
tROCP +
5.7
ns
20 MHz – 50 MHz
(Dual Mode)
Figure 13
128k x
tROCP
ns
40 MHz – 85 MHz
(Quad Mode)
Figure 13
256k x
tROCP
ns
0.25
20 MHz – 85 MHz
Figure 17
UI
0.4 x
tROCP
ns
tRPLLS is the time required by the Deserializer to obtain lock when exiting power-down mode.
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AC Timing Diagrams and Test Circuits
Differential
Signal
80%
80%
20%
Vdiff = 0V
20%
tLLHT
tLHLT
Figure 5. Serializer LVDS Transition Times
VDDIO
80%
80%
TxCLKIN
20%
20%
0V
tCIT
tCIT
Figure 6. Serializer Input Clock Transition Time
tCIP
TxCLKIN
tCIH + tCIL
tSTC
TxIN
tHTC
Setup
Hold
SYMBOL N +2
| |
SYMBOL N+1
| |
| |
SYMBOL N
SYMBOL N+3
|
SYMBOL N - 1
| |
TxIN
| |
Figure 7. Serializer Setup/Hold and High/Low Times
TxCLKIN
tSD
SYMBOL N
| |
SYMBOL N +1
| |
SYMBOL N-1
| |
SYMBOL N - 2
| |
TxOUT
| |
SYMBOL N - 3
Figure 8. Serializer Propagation Delay
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PDB
2.0V
0.8V
tHZD or
tLZD
TxCLKIN
tPLD
TxOUT
LVDS Output HIGH
TRI-STATE
LVDS Output Active
TRI-STATE
Figure 9. Serializer PLL Lock Time
VOH
80%
80%
20%
20%
VOL
tROTF
tROTR
Figure 10. Deserializer LVCMOS Output Transition Time
tROCP
tRODC
RxCLKOUT
tRODC
VDD/2
VDD/2
tROSC
RxOUT [31:0]
VDD/2
tROHC
Data Valid
Before
RxCLKOUT
Data Valid
After
RxCLKOUT
VDD/2
Figure 11. Deserializer Setup and Hold times
SYMBOL N + 3
| |
SYMBOL N + 2
| |
RxIN
SYMBOL N +1
| |
| |
SYMBOL N
| |
SYMBOL N - 1
|
t RD
SYMBOL N
| |
SYMBOL N - 1
| |
SYMBOL N - 2
| |
SYMBOL N - 3
| |
RxOUT
| |
RxCLKOUT
SYMBOL N +1
Figure 12. Deserializer Propagation Delay
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2.0V
PDB
0.8V
| |
tRPLLS
RxIN [1:0]+/-
LOCK
'RQ¶W &DUH
TRI-STATE
TRI-STATE
tHZR or tLZR
RxOUT [31:0]
TRI-STATE
TRI-STATE
RxCLKOUT
TRI-STATE
TRI-STATE
REN
Figure 13. Deserializer PLL Lock Time and PDB TRI-STATE Delay
500:
VREF
CL = 8 pF
VREF = VDD/2 for tZLR or tLZR
+
-
VREF = 0V for tZHR or tHZR
REN
VOH
VDD/2
REN
VDD/2
VOL
tLZR
tZLR
VOL + 0.5V
VOL + 0.5V
VOL
tHZR
RxOUT [31:0]
tZHR
VOH
VOH - 0.5V
VOH + 0.5V
Note: CL includes instrumentation and fixture capacitance within 6 cm of RxOUT [31:0].
Figure 14. Deserializer TRI_STATE Test Circuit and Timing
0
GAIN (dB)
Dual Mode 50 MHz
-3
Quad Mode 85 MHz
-6
-9
1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07
FREQUENCY (Hz)
Figure 15. Serializer Jitter Transfer
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32
TxIN
PARALLEL-TO-SERIAL
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TxOUT[3:0]+
RT
RL
TxOUT[3:0]-
TxCLKIN
Figure 16. Serializer VOD Test Circuit Diagram
CLK1
CLK1
CLK0
CLK1
CLK0
RxIN1
RxIN3
CLK0
CLK1
RxIN0
(Master)
RxIN2
CLK0
tLVSKR
1 RxCLKOUT Cycle
RxCLKOUT
Figure 17. LVDS Deserializer Input Skew
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FUNCTIONAL DESCRIPTION
The DS92LV3241 Serializer (SER) and DS92LV3242 Deserializer (DES) chipset is a flexible SER/DES chipset
that translates a 32-bit parallel LVCMOS data bus into a quad (4 pairs) or dual (2 pairs) LVDS serial links with
embedded clock. The DS92LV3241 serializes the 32-bit wide parallel LVCMOS word into four or two high-speed
LVDS serial data streams with embedded clock, scrambles and DC Balances the data to support AC coupling
and enhance signal quality. The DS92LV3242 receives the dual/quad LVDS serial data streams and converts it
back into a 32-bit wide parallel data with a recovered clock. The dual/quad LVDS serial data stream reduces
cable size, the number of connectors, and eases skew concerns.
Parallel clocks between 20 MHz to 85 MHz are supported by the dual or quad operating modes. The modes are
user selectable through a control pin on Serializer. In dual mode, the transmit clock frequency supports 20 MHz
to 50 MHz and in quad mode the transmit clock frequency supports 40 MHz to 85 MHz. In the dual mode
configuration, the embedded clock LVDS serial streams have an effective data payload of 640 Mbps (20MHz x
32-bit) to 1.6 Gbps (50MHz x 32- bit). In the quad mode configuration, the embedded clock LVDS serial streams
have an effective data payload of 1.28 Gbps (40MHz x 32-bit) to 2.72 Gbps (85MHz x 32-bit). The SER/DES
chipset is designed to transmit data over long distances through standard twisted pair (TWP) cables. The
differential inputs and outputs are internally terminated with 100 ohm resistors to provide source and load
termination, minimize stub length, to reduce component count and further minimize board space.
The DES can attain lock to a data stream without the use of a separate reference clock source; greatly
simplifying system complexity and reducing overall cost. The DES synchronizes to the SER regardless of data
pattern, delivering true automatic “plug-and-lock” performance. It will lock to the incoming serial stream without
the need of special training patterns or special sync characters. The DES recovers the clock and data by
extracting the embedded clock information, deskews the serial data channels and then deserializes the data. The
DES also monitors the incoming clock information, determines lock status, and asserts the LOCK output high
when lock occurs. In addition the DES also supports an optional AT-SPEED BIST (Built In Self Test) mode, BIST
error flag, and LOCK status reporting pin. The SER and the DES have a power down control signal to enable
efficient operation in various applications.
DESKEW AND CHANNEL ALIGNMENT
The DES automatically detects dual or quad serial channel mode and provides a clock alignment and deskew
function without the need for any special training patterns. During the locking phase, the embedded clock
information is recovered on all channels and the serial links are internally synchronized, de-skewed, and auto
aligned. The internal CDR circuitry will dynamically compensate for up to 0.4 times the parallel clock period of
per channel phase skew (channel-to-channel) between the recovered clocks of the serial links. This provides
skew phase tolerance from mismatches in interconnect wires such as PCB trace routing, cable pair-to-pair length
differences, and connector imbalances.
DATA TRANSFER
After SER lock is established (SER PLL to TxCLKIN), the inputs TxIN0–TxIN31 are latched into the encoder
block. Data is clocked into the SER by the TxCLKIN input. The edge of TxCLKIN used to strobe the data is
selectable via the R_FB (SER) pin. R_FB (SER) high selects the rising edge for clocking data and low selects
the falling edge. The SER outputs (TxOUT[3:0]+/-) are intended to drive a AC Coupled point-to-point
connections.
The SER latches 32-bit parallel data bus and performs several operations to it. The 32-bit parallel data is
internally encoded and sequentially transmitted over the two high-speed serial LVDS channels. For each serial
channel, the SER transmits 20 bits of information per payload to the DES. In the dual mode, the 32-bit parallel
data is scaled and bit-mapped across two 20-bit data payloads per channel, resulting in a per channel throughput
of 400 Mbps to 1.0 Gbps (20 bits x clock rate). Under quad mode, the internal PLL operates at ½ the input clock
frequency rate. The 32 bits are bit-mapped and sequenced per every 2 cycles at ½ the TxCLKIN frequency
across four channels, resutling in a per channel throughput of 400 Mbps to 850 Mbps (20 bits x clock rate/2). The
chipset supports frequency ranges of 20 MHz to 85 MHz.
16
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When all of the DES channels obtain lock , the LOCK pin is driven high and synchronously delivers valid data
and recovered clock on the output. The DES locks to the clock, uses it to generate multiple internal data strobes,
and then drives the recovered clock to the RxCLKOUT pin. The recovered clock (RxCLKOUT) is synchronous to
the data on the RxOUT[31:0] pins. While LOCK is high, data on RxOUT[31:0] is valid. Otherwise, RxOUT[31:0] is
invalid. The polarity of the RxCLKOUT edge is controlled by its R_FB (DES) input. RxOUT[31:0], LOCK and
RxCLKOUT outputs will each drive a maximum of 8 pF load. REN controls TRI-STATE for RxOUT0–RxOUT31
and the RxCLKOUT pin on the DES.
RESYNCHRONIZATION
In the absence of data transitions on one of the channels into the DES (e.g. a loss of the link), it will automatically
try to resynchronize and re-establish lock using the standard lock sequence on the master channel (Channel 0).
For example, if the embedded clock is not detected one time in succession on any of the serial links, the LOCK
pin is driven low. The DES then monitors the master channel for lock, once that is obtained, the second channel
is locked and aligned. The logic state of the LOCK signal indicates whether the data on RxOUT is valid; when it
is high, the data is valid. The system may monitor the LOCK pin to determine whether data on the RxOUT is
valid.
POWERDOWN
The Powerdown state is a low power sleep mode that the SER and DES may use to reduce power when no data
is being transferred. The respective PDB pins are used to set each device into power down mode, which reduces
supply current into the µA range. The SER enters Powerdown when the SER PDB pin is driven low. In
Powerdown, the PLL stops and the outputs go into TRI-STATE, disabling load current and reducing current
supply. To exit Powerdown, SER PDB must be driven high. When the SER exits Powerdown, its PLL must lock
to TxCLKIN before it is ready for sending data to the DES. The system must then allow time for the DES to lock
before data can be recovered.
The DES enters Powerdown mode when DES PDB is driven low. In Powerdown mode, the PLL’s stop and the
outputs enter TRI-STATE. To bring the DES block out of the Powerdown state, the system drives DES PDB high.
Both the SER and DES must relock before data can be transferred from Host and received by the Target. The
DES will startup and assert LOCK high when it is locked to the embedded clocks. See also Figure 13.
TRI-STATE
For the SER, TRI-STATE is entered when the SER PDB pin is driven low. This will TRI-STATE the driver output
pins on TxOUT[3:0]+/-. In addition, when MODE=0 (dual mode), the TxOUT[3:2]+/- outputs pins are in TRISTATE.
When you drive the REN or DES PDB pin low, the DES output pins (RxOUT[31:0]) and RxCLKOUT will enter
TRI-STATE. The LOCK output remains active, reflecting the state of the PLL. The DES input pins are high
impedance during receiver Powerdown (DES PDB low) and power-off (VDD = 0V). See also Figure 13.
TRANSMIT PARALLEL DATA AND CONTROL INPUTS
The DS92LV3241 operates on a core supply voltage of 3.3V with an optional digital supply voltage for 1.8V, lowswing, input support. The SER single-ended (32-bit parallel data and control inputs) pins are 1.8V and 3.3V
LVCMOS logic level compatible and is configured through the IOVDD input supply rail. If 1.8V is required, the
IOVDD pin must be connected to a 1.8V supply rail. Also when power is applied to the transmitter, IOVDD pin
must be applied before or simultaneously with other power supply pins (3.3V). If 1.8V input swing is not required,
this pin should be tied to the common 3.3V rail. During normal operation, the voltage level on the IOVDD pins
must not change.
PRE-EMPHASIS
The SER LVDS Line Driver features a Pre-Emphasis function used to compensate for extra long or lossy
transmission media. The same amount of Pre-Emphasis is applied on all of the enabled differential output
channels. Cable drive is enhanced with a user selectable Pre-Emphasis feature that provides additional output
current during transitions to counteract cable loading effects. The transmission distance will be limited by the loss
characteristics and quality of the media.
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To enable the Pre-Emphasis function, the “PRE” pin requires one external resistor (Rpre) to VSS (GND) in order
to set the pre-emphasized current level. Options include:
1. Normal Output (no Pre-emphasis) – Leave the PRE pin open, include an R pad, do not populate.
2. Enhanced Output (Pre-emphasis enabled) – connect a resistor on the PRE pin to Vss.
Values of the Rpre Resistor should be between 12K Ohm and 100K Ohm. Values less than 6K Ohm should not
be used. The amount of Pre-Emphasis for a given media will depend on the transmission distance and Fmax of
the application. In general, too much Pre-Emphasis can cause over or undershoot at the receiver input pins. This
can result in excessive noise, crosstalk, reduced Fmax, and increased power dissipation. For shorter cables or
distances, Pre-Emphasis is typically not be required. Signal quality measurements should be made at the end of
the application cable to confirm the proper amount of Pre-Emphasis for the specific application.
The Pre-Emphasis circuit increases the drive current to I = 48 / (RPRE). For example if RPRE = 15 kOhms, then
the current is increased by an additional 3.2 mA. To calculate the expected increase in VOD, multiply the increase
in current by 50 ohms. So for the case of RPRE = 15 kOhms, the boost to VOD would be 3.2 mA x 50 Ohms = 160
mV. The duration of the current is controlled to one bit by time. If more than one bit value is repeated in the next
cycle(s), the Pre-Emphasis current is turned off (back to the normal output current level) for the next bit(s). To
boost high frequency data and pre-equalize teh data patternreduce ISI (Inter-Symbol Interference) improving the
resulting eye pattern.
VOD SELECT
The SER Line Driver Differential Output Voltage (VOD) magnitude is selectable. Two levels are provided and are
selected by the VSEL pin. When this pin is LOW, normal output levels are obtained. For most application set the
VSEL pin LOW. When this pin is HIGH, the output current is increased to double the VOD level. Use this setting
only for extra long cables or high-loss interconnects.
Table 1. VOD Control
VSEL Pin Setting
Effect
LOW
Small VOD, typ 440 mVP-P
HIGH
Large VOD, typ 850 mVP-P
SERIAL INTERFACE
The serial links between the DS92LV3241 and the DS92LV3242 are intended for a balanced 100 Ohm
interconnects. The links must be configured as an AC coupled interface.
The SER and DES support AC-coupled interconnects through an integrated DC balanced encoding/decoding
scheme. An external AC coupling capacitors must be placed, in series, in the LVDS signal path. The DES input
stage is designed for AC-coupling by providing a built-in AC bias network which sets the internal common mode
voltage (VCM) to +1.8V.
For the high-speed LVDS transmission, small footprint packages should be used for the AC coupling capacitors.
This will help minimize degradation of signal quality due to package parasitics. NPO class 1 or X7R class 2 type
capacitors are recommended. 50 WVDC should be the minimum used for best system-level ESD performance.
The most common used capacitor value for the interface is 100 nF (0.1 uF) capacitor. One set of capacitors may
be used for isolation. Two sets (both ends) may also be used for maximum isolation of both the SER and DES
from cable faults.
The DS92LV3241 and the DS92LV3242 differential I/O’s are internally terminated with 100 Ohm resistance
between the inverting and non-inverting pins and do not require external termination. The internal resistance
value will be between 90 ohm and 130 ohm. The integrated terminations improve signal integrity, reduce stub
lengths, and decrease the external component count resulting in space savings.
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AT-SPEED BIST FEATURE
The DS92LV3241/ DS92LV3242 serial link is equipped with built-in self-test (BIST) capability to support both
system manufacturing and field diagnostics. BIST mode is intended to check the entire high-speed serial
interface at full link-speed without the use of specialized and expensive test equipment. This feature provides a
simple method for a system host to perform diagnostic testing of both SER and DES. The BIST function is easily
configured through the SER BISTEN pin. When the BIST mode is activated, the SER generates a PRBS
(pseudo-random bit sequence) pattern (2^7-1). This pattern traverses each lane to the DES input. The
DS92LV3242 includes an on-chip PRBS pattern verification circuit that checks the data pattern for bit errors and
reports any errors on the data output pins of the DES.
The AT-Speed BIST feature is enabled by setting the BISTEN to High on SER. The BISTEN input must be High
or Low for 4 or more TxCLKIN clock cycles in order to activate or deactivate the BIST mode. An input clock
signal for the Serializer TxCLKIN must also be applied during the entire BIST operation. Once BIST is enabled,
all the Serializer data inputs (TxIN[31:0]) are ignored and the DES outputs (RxOUT[31:0]) are not available. Next,
the internal test pattern generator for each channel starts transmission of the BIST pattern from SER to DES.
The DES BIST mode will be automatically activated by this sequence. A maximum of 128 consecutives clock
symbols on DS92LV3242 DES is needed to detect BIST enable function. The BIST is implemented with
independent transmit and receive paths for the four serial links. Each channel on the DES will be individually
compared against the expected bit sequence of the BIST pattern.
TxCLKIN
PDB (High)
BISTEN
2.0V
0.8V
BIST disabled
BIST enabled
4 x tCIP
BIST disabled
4 x tCIP
Figure 18. BIST Test Enabled/Disabled
Under the BIST mode, the DES parallel outputs on RxOUT[31:0] are multiplexed to represent BIST status
indicators. The pass/fail status of the BIST is represented by a Pass flag along with an Error counter. The Pass
flag output is designated on DES RxOUT0 for Channel 0, and RxOUT8 for Channel 1. The DES's PLL must first
be locked to ensure the Pass status is valid. The output Pass status pin will stay LOW and then transition to High
once 44*10^6 symbols are achieved across each of the respective transmission links. The total time duration of
the test is defined by the following: 44*10^6 x tCIP . After the Pass output flags reach a HIGH state, it will not
drop to LOW even if subsequent bit errors occurred after the BIST duration period. Errors will be reported if the
input test pattern comparison does not match. If an error (miss-compare) occurs, the status bit is latched on
RxOUT[7:1] for Channel 0, and RxOUT[15:9] for Channel 1; reflecting the number of errors detected. Whenever
a data bit contains an error, the Error counter bit output for that corresponding channel goes HIGH. Each counter
for the serial link utilizes a 7-bit counter to store the number of errors detected (0 to 127 max).
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Recovered Pixel Clock
Start
Pixel
BISTEN
Case 1: No bit errors
Recovered Pixel Data
Channel 0 - RxOUT0
Channel 1 - RxOUT8
Channel 2 ± RxOUT16
Channel 3 ± RxOUT24
Error counter
Channel 0 - RxOUT[7:1]
Channel 1 - RxOUT[15:9]
Channel 2 - RxOUT[23:17]
Channel 3 - RxOUT[31:25]
BIST PASS
0
0
0
Case 2: Bit error(s)
B
Recovered Pixel Data
B B
B
Channel 0 - RxOUT0
Channel 1 - RxOUT8
Channel 2 ± RxOUT16
Channel 3 ± RxOUT24
Error counter
Channel 0 - RxOUT[7:1]
Channel 1 - RxOUT[15:9]
Channel 2 - RxOUT[23:17]
Channel 3 - RxOUT[31:25]
BIST FAIL
0
1
2 3
4
4
Case 3: Bit error(s)
Recovered Pixel Data
Channel 0 - RxOUT0
Channel 1 - RxOUT8
Channel 2 ± RxOUT16
Channel 3 ± RxOUT24
Error counter
Channel 0 - RxOUT[7:1]
Channel 1 - RxOUT[15:9]
Channel 2 - RxOUT[23:17]
Channel 3 - RxOUT[31:25]
B
BIST PASS
0
B = Bad Bit
0
0
BIST Duration
44 x 106 x tCIP
Status
Region
Figure 19. BIST Diagram for Different Bit Error Cases
TYPICAL APPLICATION CONNECTION
Figure 20 shows a typical application of the DS92LV3241 Serializer (SER). The differential outputs utilize 100nF
coupling capacitors to the serial lines. Bypass capacitors are placed near the power supply pins. A system GPO
(General Purpose Output) controls the PDB and BISTEN pins. In this application the R_FB (SER) pin is tied Low
to latch data on the falling edge of the TxCLKIN. In this application the link is short, therefore the VSEL pin is tied
LOW for the standard output swing level. The Pre-emphasis input utilizes a resistor to ground to set the amount
of pre-emphasis desired by the application.
Configuration pins for the typical application are shown for SER:
• PDB – Power Down Control Input – Connect to host or tie HIGH (always ON)
• BISTEN – Mode Input - tie LOW if BIST mode is not used, or connect to host
• VSEL – tie LOW for normal VOD magnitude (application dependant)
• MODE – For clock rates between 20 MHz and 50 MHz tie LOW, for 40 MHz to 85 MHz tie HIGH
• PRE – Leave open if not required (have a R pad option on PCB)
• RSVD1 & RSVD2 – tie LOW
20
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There are eight power pins for the device. These may be bussed together on a common 3.3V plane (3.3V
LVCMOS I/O interface). If 1.8V input swing level for parallel data and control pins are required, connect the
IOVDD pin to 1.8V. At a minimum, eight 0.1uF capacitors should be used for local bypassing.
3.3V
VDDA
VDD
3.3V
VDDPLL
VDD
VDDPLL
VDD
IOVDD
VDD
TxCLKIN
VSS
1.8V or 3.3V
3.3V
VSS
TxIN31
VSS
TxIN30
VSS
TxIN29
TxIN28
VSSPLL
TxIN27
VSSPLL
TxIN26
TxIN25
VSSA
TxIN24
32-bit LVCMOS Data Bus + Clock
TxIN23
IOVSS
TxIN22
TxIN21
TxIN20
TxIN19
TxIN18
TxIN16
TxIN15
TxIN14
TxIN13
TxIN12
TxIN11
TxOUT0+
TxOUT0Serial LVDS
TxIN17
TxOUT1+
TxOUT1TxOUT2+
TxOUT2-
TxIN10
TxIN9
TxOUT3+
TxIN8
TxOUT3-
TxIN7
TxIN6
TxIN5
PRE
opt.
TxIN4
TxIN3
Control
TxIN2
TxIN1
R_FB
TxIN0
VSEL
PDB
BISTEN
MODE
RSVD
Notes:
Caps are 0.1 PF
except Bulk Supply (4.7 PF)
Figure 20. DS92LV3241 Typical Connection Diagram
Figure 21 shows a typical application of the DS92LV3242 Deserializer (DES). The differential inputs utilize 100nF
coupling capacitors in the serial lines. Bypass capacitors are placed near the power supply pins. A system GPO
(General Purpose Output) controls the PDB pin. In this application the R_FB (DES) pin is tied Low to strobe the
data on the falling edge of the RxCLKOUT. The REN signal is not used and is tied High also.
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Configuration pins for the typical application are shown for DES:
• PDB – Power Down Control Input – Connect to host or tie HIGH
• REN – tie HIGH if not used (used to MUX two DES to one target device)
• RSVD – tie LOW
3.3V
VDDA
VDD
3.3V
VDDPLL
VDD
VDDPLL
VDD
VDDPLL
VDD
3.3V
VDD
VSSPLL
VSSPLL
VSSPLL
VSSA
Serial LVDS
RxIN0+
RxIN0RxIN1+
RxIN1RxIN2+
RxIN2RxIN3+
RxIN3-
Tied ON
REN
R_FB
RSVD
Notes:
Caps are 0.1 PF
except Bulk Supply (4.7 PF)
RxOUT31
RxOUT30
RxOUT29
RxOUT28
RxOUT27
RxOUT26
RxOUT25
RxOUT24
RxOUT23
RxOUT22
RxOUT21
RxOUT20
RxOUT19
RxOUT18
RxOUT17
RxOUT16
RxOUT15
RxOUT14
RxOUT13
RxOUT12
RxOUT11
RxOUT10
RxOUT9
RxOUT8
RxOUT7
RxOUT6
RxOUT5
RxOUT4
RxOUT3
RxOUT2
RxOUT1
RxOUT0
32-bit LVCMOS Data Bus + Clock
VSS
RxCLKOUT
Control
VSS
VSS
VSS
VSS
PDB
LOCK
Figure 21. DS92LV3242 Typical Connection Diagram
22
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SNLS314D – SEPTEMBER 2009 – REVISED APRIL 2013
Applications Information
TRANSMISSION MEDIA
The SER and DES are used in AC-coupled point-to-point configurations, through a PCB trace, or through twisted
pair cables. Interconnect for LVDS typically has a differential impedance of 100 Ohms. Use cables and
connectors that have matched differential impedance to minimize impedance discontinuities. In most applications
that involve cables, the transmission distance will be determined on data rates involved, acceptable bit error rate
and transmission medium.
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the LVDS SER/DES devices should be designed to provide low-noise
power feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs
to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly
improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane
capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at
high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommended at the point of
power entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with vias on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz range. To provide effective bypassing,
multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of
interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the
planes, reducing the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS
lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely-coupled differential lines of 100
Ohms are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled
noise will appear as common mode and thus is rejected by the receivers. The tightly coupled lines will also
radiate less.
PLUG AND GO
The Serializer and Deserializer devices support hot plugging of the serial interconnect. The automatic receiver
lock to random data “plug & go” capability allows the DS92LV3242 to obtain lock to the active data stream during
a live insertion event.
LVDS INTERCONNECT GUIDELINES
For full details, see the Channel-Link PCB and Interconnect Design-In Guidelines (literature number SNLA008)
and the Transmission Line RAPIDESIGNER Operation and Applications Guide (literature number SNLA035).
• Use 100 Ohm coupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
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– 3S = space to LVCMOS signal
Minimize the number of vias
Use differential connectors when operating above 500 Mbps line speed
Maintain balance of the traces
Minimize skew within the pair
Terminate as close to the TX outputs and RX inputs as possible
•
•
•
•
•
Additional general guidance can be found in the LVDS Owner’s Manual (literature number SNLA187), which is
available in PDF format from the TI LVDS & CML Solutions web site.
Typical Performance Characteristics
The waveforms below illustrate the typical performance of the DS92LV3241. The SER was given a PCLK and configured as
described below each picture. In all of the pictures the SER was configured with BISTEN pin set to logic HIGH. Each
waveform was taken by using a high impedance low capacitance differential probe to probe across a 100 ohm differential
termination resistor within one inch of TxOUT0+/-.
24
Figure 22. Serial Output Quad Mode, 85 MHz, VSEL = H, No
Pre-Emphasis
Figure 23. Serial Output Quad Mode, 85 MHz, VSEL = L, No
Pre-Emphasis
Figure 24. Serial Output Dual Mode, 50 MHz, VSEL = H, No
Pre-Emphasis
Figure 25. Serial Output Dual Mode, 50 MHz, VSEL = L, No
Pre-Emphasis
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SNLS314D – SEPTEMBER 2009 – REVISED APRIL 2013
REVISION HISTORY
Changes from Revision C (April 2013) to Revision D
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 24
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25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
DS92LV3241TVS/NOPB
ACTIVE
TQFP
PAG
64
160
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
DS92LV3241
TVS
DS92LV3241TVSX/NOPB
ACTIVE
TQFP
PAG
64
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
DS92LV3241
TVS
DS92LV3242TVS/NOPB
ACTIVE
TQFP
PAG
64
160
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
DS92LV3242
TVS
DS92LV3242TVSX/NOPB
ACTIVE
TQFP
PAG
64
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
DS92LV3242
TVS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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