DS92LX2121, DS92LX2122
www.ti.com
SNLS330J – MAY 2010 – REVISED JANUARY 2014
DS92LX2121/DS92LX2122 10 - 50 MHz DC-Balanced Channel Link III Bi-Directional Control
Serializer and Deserializer
Check for Samples: DS92LX2121, DS92LX2122
FEATURES
APPLICATIONS
•
•
•
1
2
•
General
– Up to 1050 Mbits/sec Data Throughput
– 10 MHz to 50 MHz Input Clock Support
– Supports 18-bit Color Depth (RGB666 + HS,
VS, DE)
– Embedded Clock with DC Balanced Coding
to Support AC-Coupled Interconnects
– Capable to Drive up to 10 Meters Shielded
Twisted-Pair
– Bi-Directional Control Interface Channel
with I2C Support
– I2C Interface for Device Configuration.
Single-Pin ID Addressing
– Up to 4 GPI on DES and GPO on SER
– AT-SPEED BIST Diagnosis Feature to
Validate Link Integrity
– Individual Power-Down Controls for both
SER and DES
– User-Selectable Clock Edge for Parallel
Data on both SER and DES
– Integrated Termination Resistors
– 1.8V- or 3.3V-Compatible Parallel Bus
Interface
– Single Power Supply at 1.8V
– IEC 61000–4–2 ESD Compliant
– Temperature Range −40°C to +85°C
DESERIALIZER — DS92LX2122
– No Reference Clock Required on
Deserializer
– Programmable Receive Equalization
– LOCK Output Reporting Pin to Ensure
– EMI/EMC Mitigation
– Programmable Spread Spectrum (SSCG)
Outputs
– Receiver Output Drive Strength Control
(RDS)
– Receiver Staggered Outputs
Industrial Displays, Touch Screens
Medical Imaging
DESCRIPTION
The DS92LX2121/DS92LX2122 chipset offers a
Channel Link III interface with a high-speed forward
channel and a full-duplex control channel for data
transmission over a single differential pair. The
DS92LX2121/DS92LX2122 incorporates differential
signaling on both the high-speed and bi-directional
back channel control data paths. The Serializer/
Deserializer pair is targeted for direct connections
between graphics host controller and displays
modules. This chipset is ideally suited for driving
video data to displays requiring 18-bit color depth
(RGB666 + HS, VS, and DE) along with a bidirectional back channel control bus. The primary
transport converts 21 bit data over a single highspeed serial stream, along with a separate low
latency bi-directional back channel transport that
accepts control information from an I2C port. Using
TI’s embedded clock technology allows transparent
full-duplex communication over a single differential
pair, carrying asymmetrical bi-directional back
channel control information in both directions. This
single serial stream simplifies transferring a wide data
bus over PCB traces and cable by eliminating the
skew problems between parallel data and clock
paths. This significantly saves system cost by
narrowing data paths that in turn reduce cable width,
connector size and pins.
In addition, the Deserializer provides input
equalization to compensate for loss from the media
over longer distances. Internal DC balanced
encoding/decoding is used to support AC-Coupled
interconnects.
A sleep function provides a power-savings mode
when the high speed forward channel and embedded
bi-directional control channel are not needed.
The Serializer is offered in a 40-pin lead in WQFN
and Deserializer is offered in a 48-pin WQFN
packages.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2014, Texas Instruments Incorporated
DS92LX2121, DS92LX2122
SNLS330J – MAY 2010 – REVISED JANUARY 2014
www.ti.com
Typical Application Diagram
Channel Link III
Parallel
Data In
18+3
Graphics
Controller,
Camera
Parallel
Data Out
18+3
4
Display
Module, Frame
Grabber
4
DS92LX2121
DS92LX2122
GPO
GPI
Back Channel
2
Serial
Control Bus
2
Serializer
Deserializer
Serial
Control Bus
DOUT+
DOUT-
RIN+ RT
RT
Output Latch
RT
Decoder
Serializer
4
RT
Deserializer
GPO[3:0]
Encoder
Data [17:0], 21
Control [2:0]
Input Latch
Block Diagrams
21 Data [17:0],
Control [2:0]
4
GPI[3:0]
RINPCLK
PDB
BISTEN
M/S
LOCK
PASS
I2C Controller
Encoder
FIFO
Encoder
Decoder
Timing
and
Control
Decoder
CAD
I2C Controller
SCL
Clock
Gen
CDR
Timing
and
Control
PDB
M/S
SDA
Clock
Gen
PLL
FIFO
PCLK
SDA
SCL
CAD
DS92LX2122 - DESERIALIZER
DS92LX2121 - SERIALIZER
Figure 1. Block Diagram
DS92LX2121
Serializer
Graphics
Controller
--Video
Processor
-Camera
Channel Link III
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
PCLK
PDB
M/S
DS92LX2122
Deserializer
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
PCLK
PLL
Config.
Config.
PDB
M/S
BISTEN
GPI[3:0]
Timing
Controller
-Display
-Frame Grabber
GPO[3:0]
PC
SDA
SCL
2
I C
2
I C
SDA
SCL
PC
Figure 2. Application Block Diagram
2
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Product Folder Links: DS92LX2121 DS92LX2122
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SNLS330J – MAY 2010 – REVISED JANUARY 2014
DS92LX2121 Pin Diagram
DIN[7]
DIN[6]
DIN[5]
DIN[4]
DIN[3]
DIN[2]
DIN[1]
DIN[0]
GPO[3]
GPO[2]
30
29
28
27
26
25
24
23
22
21
Top View
20
GPO[1]
19
GPO[0]
33
18
VDDCML
VDDD
34
17
DOUT+
DIN[10]
35
16
DOUT-
DIN[11]
36
15
VDDT
DIN[12]
37
14
VDDPLL
DIN[13]
38
13
PDB
DIN[14]
39
12
M/S
DIN[15]
40
11
RES
3
4
5
6
7
8
9
10
DIN[19]
DIN[20]
PCLK
SCL
SDA
CAD
RES
DS92LX2121
(Top View)
DIN[18]
DIN[9]
DAP = GND
2
32
DIN[17]
DIN[8]
1
31
DIN[16]
VDDIO
Figure 3. Serializer - DS92LX2121
40-Pin WQFN (RTA Package)
DS92LX2121 Serializer PIN DESCRIPTIONS
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
DIN[20:0]
PCLK
5, 4, 3, 2, 1, 40,
39, 38, 37, 36,
35, 33, 32, 30,
29, 28, 27, 26,
25, 24, 23
Inputs, LVCMOS w/
pull down
Parallel data inputs.
6
Input, LVCMOS w/
pull down
Pixel Clock Input Pin. Strobe edge set by TRFB configuration.
GENERAL PURPOSE OUTPUT (GPO)
GPO[3:0]
22, 21, 20, 19
Output, LVCMOS
General-purpose pins individually configured as outputs; which are used to
control and respond to various commands.
SERIAL CONTROL BUS - I2C COMPATIBLE
SCL
7
Input/Output, Open
Drain
Clock line for the serial control bus communication
SCL requires an external pull-up resistor to VDDIO.
SDA
8
Input/Output, Open
Drain
Data line for the serial control bus communication
SDA requires an external pull-up resistor to VDDIO.
Input, LVCMOS w/
pull down
I2C Mode Select
M/S = L, Master mode (default); device generates and drives the SCL clock
line. Device is connected to a slave peripheral on the bus. (Serializer initially
starts up in Standby mode and is enabled through remote wakeup by the
Deserializer)
M/S = H, Slave; device accepts SCL clock input
M/S
CAD
12
9
Input, analog
Continuous Address Decoder
Input pin to select the Slave Device Address.
Input is connect to external resistor divider to programmable Device ID
address (see Serial Control Bus Connection).
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: DS92LX2121 DS92LX2122
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DS92LX2121, DS92LX2122
SNLS330J – MAY 2010 – REVISED JANUARY 2014
www.ti.com
DS92LX2121 Serializer PIN DESCRIPTIONS (continued)
Pin Name
Pin No.
I/O, Type
Description
CONTROL AND CONFIGURATION
PDB
13
Input, LVCMOS w/
pull down
Power down Mode Input Pin.
PDB = H, Transmitter is enabled and is ON.
PDB = L, Transmitter is in Sleep (Power Down). When the transmitter is in the
SLEEP state, the PLL is shutdown, and IDD is minimized.
RES
10, 11
Input, LVCMOS w/
pull down
Reserved. This pin MUST be tied LOW.
Channel Link III INTERFACE
DOUT+
17
Input/Output, CML
Non-inverting differential output, back-channel input.
DOUT-
16
Input/Output, CML
Inverting differential output, back-channel input.
VDDPLL
14
Power, Analog
PLL Power, 1.8V ±5%
VDDT
15
Power, Analog
Tx Analog Power, 1.8V ±5%
VDDCML
18
Power, Analog
LVDS & BC Dr Power, 1.8V ±5%
VDDD
34
Power, Digital
Digital Power, 1.8V ±5%
VDDIO
31
Power, Digital
Power for input stage, The single-ended inputs are powered from VDDIO.
DAP
Ground, DAP
DAP must be grounded. Connect to the ground plane (GND) with at least 16
vias.
Power and Ground
VSS
DS92LX2122 Pin Diagram
ROUT[0]
ROUT[1]
ROUT[2]
ROUT[3]
27
26
25
GPI[2]
31
28
GPI[1]
32
GPI[3]
GPI[0]
33
VDDOR1
LOCK
34
29
PDB
35
30
VDDR
36
Top View
24
ROUT[4]
23
ROUT[5]
PASS
37
RES
38
RES
39
22
ROUT[6]
VDDCML
40
21
ROUT[7]
RIN+
41
20
VDDOR2
19
ROUT[8]
18
ROUT[9]
DAP = GND
RIN-
42
RES
43
BISTEN
44
17
VDDD
VDDPLL
45
16
ROUT[10]
RES
46
15
ROUT[11]
M/S
47
14
ROUT[12]
CAD
48
13
ROUT[13]
9
10
11
12
ROUT[16]
ROUT[15]
ROUT[14]
8
ROUT[17]
7
6
ROUT[19]
VDDOR3
5
ROUT[18]
4
PCLK
3
ROUT[20]
2
SCL
VDDSSCG
SDA
1
DS92LX2122
(Top View)
Figure 4. Deserializer - DS92LX2122
48-Pin WQFN (RHS Package)
4
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Product Folder Links: DS92LX2121 DS92LX2122
DS92LX2121, DS92LX2122
www.ti.com
SNLS330J – MAY 2010 – REVISED JANUARY 2014
DS92LX2122 Deserializer PIN DESCRIPTIONS
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
ROUT[20:0]
PCLK
5, 6, 8, 9, 10,
11, 12, 13, 14,
15, 16, 18, 19,
21, 22, 23, 24,
25, 26, 27, 28
Outputs, LVCMOS
Parallel data outputs.
4
Output, LVCMOS
Pixel Clock Output Pin.
Strobe edge set by RFB configuration. In SLEEP, outputs are controlled by the
OSS_SEL.
General Purpose Input (GPI)
GPI[3:0]
30, 31, 32, 33
Input, Digital
General-purpose pins individually configured as inputs; which are used to
control and respond to various commands.
SERIAL CONTROL BUS - I2C COMPATIBLE
SCL
2
Input/Output, Open
Drain
Clock line for the serial control bus communication
SCL requires an external pull-up resistor to VDDIO.
SDA
1
Input/Output, Open
Drain
Data line for serial control bus communication
SDA requires an external pull-up resistor to VDDIO.
I2C Mode Select
M/S
47
Input, LVCMOS w/
pull up
M/S = L, Master; device generates and drives the SCL clock line. Device is
connected to slave peripheral on teh bus.
M/S = H, Slave (default); device accepts SCL clock input and is attached to an
I2C controller master on the bus. Slave mode does not generate the SCL clock,
but uses the clock generated by teh Master for teh data transfer.
Continuous Address Decoder
CAD
48
Input, analog
Input pin to select the Slave Device Address.
Input is connect to external resistor divider to programmable Device ID address
(see Serial Control Bus Connection)
CONTROL AND CONFIGURATION
Power down Mode Input Pin.
PDB
35
Input, LVCMOS w/
pull down
PDB = H, Receiver is enabled and is ON.
PDB = L, Receiver is in Sleep (Power down mode). When the Receiver is in the
SLEEP state, the LVCMOS Outputs are in TRI-STATE, the PLL is shutdown
and IDD is minimized.
LOCK Status Output Pin.
LOCK
34
Output, LVCMOS
LOCK = H, PLL is Locked, outputs are active
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by
OSS_SEL. May be used as Link Status.
Reserved.
RES
38, 39, 43, 46
-
Pin 43: Leave pin open.
Pin 46: This pin MUST be tied LOW.
Pins 38, 39: Route to test point as differential pair or leave open if unused.
BIST MODE
BIST Enable Pin.
BISTEN
44
Input, LVCMOS w/
pull down
BISTEN = H, BIST Mode is enabled.
BISTEN = L, BIST Mode is disabled.
PASS Output Pin for BIST mode.
PASS
37
Output, LVCMOS
PASS = H, ERROR FREE Transmission
PASS = L, one or more errors were detected in the received payload.
Leave Open if unused. Route to test point (pad) recommended.
Channel Link III INTERFACE
RIN+
41
Input/Output, CML
Non-inverting differential input, back channel output. The interconnect must be
AC coupled with a 0.1μF capacitor.
RIN-
42
Input/Output, CML
Inverting differential input, back channel output. The interconnect must be AC
coupled with a 0.1 μF capacitor.
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: DS92LX2121 DS92LX2122
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DS92LX2121, DS92LX2122
SNLS330J – MAY 2010 – REVISED JANUARY 2014
www.ti.com
DS92LX2122 Deserializer PIN DESCRIPTIONS (continued)
Pin Name
Pin No.
I/O, Type
Description
POWER AND GROUND
3
Digital Power
SSCG Power, 1.8V ±5%
Power supply must be connect regardless if SSCG function is in operation
29, 20, 7
Digital Power
TTL Output Buffer Power, The single-ended outputs and control input are
powered from VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10%
VDDSSCG
VDDOR1/2/3
VDDD
17
Digital Power
Digital Core Power, 1.8V ±5%
VDDR
36
Analog Power
Rx Analog Power, 1.8V ±5%
VDDCML
40
Analog Power
Bi-directional Channel Driver Power, 1.8V ±5%
VDDPLL
45
Analog Power
PLL Power, 1.8V ±5%
DAP
Ground, DAP
DAP must be grounded. Connect to the ground plane (GND) with at least 16
vias.
VSS
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
Supply Voltage ( VDD1V8)
−0.3V to +2.5V
Supply Voltage (VDD3V3)
−0.3V to +4.0V
LVCMOS Input Voltage (VDD1V8)
−0.3V to +(VDD1V8 + 0.3V)
LVCMOS Input Voltage (VDD3V3)
−0.3V to +(VDD3V3 + 0.3V)
−0.3V to +(VDD + 0.3V)
LVCMOS Output Voltage (VDD)
CML Receiver Input Voltage (VDD1V8)
−0.3V to (VDD1V8 + 0.3V)
CML Driver Output Voltage (VDD1V8)
−0.3V to (VDD1V8 + 0.3V)
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
Maximum Package Power Dissipation Capacity
1/θJA °C/W above +25°
Package Derating:
DS92LX2121 40L WQFN
θJA(based on 16 thermal vias)
30.7 °C/W
θJC(based on 16 thermal vias)
6.8 °C/W
DS92LX2122 48L WQFN
θJA(based on 16 thermal vias)
26.9 °C/W
θJC(based on 16 thermal vias)
4.4 °C/W
ESD Rating (IEC61000–4–2)
RD = 330Ω, CS = 150 pF
Air Discharge (DOUT+, DOUT-, RIN+, RIN-)
≥±25 kV
Contact Discharge (DOUT+, DOUT-, RIN+, RIN-)
≥±10 kV
≥±8 kV
ESD Rating (HBM)
For soldering specifications, see the Absolute Maximum Ratings for Soldering Application Report (literature number SNOA549).
(1)
(2)
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional; the device should not be operated beyond such conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Recommended Operating Conditions
Min
Nom
Max
Units
VDD (1.8V)
1.71
1.8
1.89
V
VDDIO (1.8V Mode)
1.71
1.8
1.89
V
VDDIO (3.3V Mode)
3
3.3
3.6
V
6
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SNLS330J – MAY 2010 – REVISED JANUARY 2014
Recommended Operating Conditions (continued)
Min
Nom
Max
Units
VDDn (1.8 V)
25
mVP-P
VDDIO (1.8 V)
25
mVP-P
50
mVP-P
Supply Noise (1)
VDDIO (3.3 V)
Operating Free Air
Temperature (TA)
-40
Input Clock Rate
(1)
25
10
85
°C
50
MHz
Supply noise testing was done with minimum capacitors (as shown on Figures 35, 36) on the PCB. A sinusoidal signal is AC coupled to
the VDDn (1.8V) supply with amplitude = 25 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the Ser and output
of the Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 1 MHz. The Des on the other hand
shows no error when the noise frequency is less than 750 kHz.
Serializer Electrical Characteristics (1) (2) (3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVCMOS DC SPECIFICATIONS 3.3V I/O (TX INPUTS, RX OUTPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input Voltage
VIN = 3.0V to 3.6V
2.0
VIN
V
VIL
Low Level Input Voltage
VIN = 3.0V to 3.6V
GND
0.8
V
IIN
Input Current
VIN = 0V or 3.6V
VIN = 3.0V to 3.6V
-20
+20
µA
VOH
High Level Output Voltage
VDDIO = 3.0V to
3.6V
2.4
VDDIO
VOL
Low Level Output Voltage
VDDIO = 3.0V to
3.6V
IOH = +4mA
GND
0.4
IOS
IOZ
Output Short Circuit Current
VOUT = 0V
RPWDNB = 0V,
VOUT = 0V or VDD
TRI-STATE Output Current
±1
V
V
Serializer
GPO Outputs
-24
Deserializer
LVCMOS
Outputs
-39
mA
Register
Address
(OSS_SEL =
0)
-20
±1
+20
µA
LVCMOS DC SPECIFICATIONS 1.8V I/O (TX INPUTS, RX OUTPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input Voltage
VIN = 1.71V to
1.89V
0.65 VIN
VIN + 0.3
VIL
Low Level Input Voltage
VIN = 1.71V to
1.89V
GND
0.35 VIN
IIN
Input Current
VIN = 0V or 1.89V
VIN = 1.71V to
1.89V
-20
VOH
High Level Output Voltage
VDDIO = 1.71V to
1.89V
IOH = −4mA
VOL
Low Level Output Voltage
VDDIO = 1.71V to
1.89V
IOL = +4 mA
(1)
(2)
(3)
V
±1
+20
µA
VDDIO - 0.45
VDDIO
V
GND
0.45
V
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not guaranteed.
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Serializer Electrical Characteristics(1)(2)(3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
IOS
Parameter
Conditions
Output Short Circuit Current
IOZ
VOUT = 0V
(4)
RPWDNB = 0V,
VOUT = 0V or VDD
TRI-STATE Output Current
Min
Typ
Serializer
GPO Outputs
-11
Deserializer
LVCMOS
Outputs
-20
Max
Units
mA
Register
Address
(OSS_SEL =
0)
-20
±1
+20
µA
268
340
412
mV
1
50
mV
VDD (MIN) - VOD
VDD - VOD
VDD (MAX) VOD (MIN)
V
1
50
mV
CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-)
RT = 100Ω
(SeeFigure 9)
|VOD|
Output Differential Voltage
ΔVOD
Output Differential Voltage Unbalance RL = 100Ω
RL = 100Ω (See
Figure 9)
VOS
Output Differential Offset Voltage
ΔVOS
Offset Voltage Unbalance
RL = 100Ω
IOS
Output Short Circuit Current
DOUT+/- = 0V,
PDB = L or H (4)
RT
Differential Internal Termination
Resistance
Differential across
DOUT+ and
DOUT-
(MAX)
-27
80
100
mA
120
Ω
CML RECEIVER DC SPECIFICATIONS (RIN+, RIN-)
VTH
Differential Threshold High Voltage
VTL
Differential Threshold Low Voltage
+90
VIN
Differential Input Voltage Range
RIN+ - RIN-
180
IIN
Input Current
VIN = VDD or 0 V,
VDD = 1.89 V
-20
±1
+20
µA
RT
Differential Internal Termination
Resistance
Differential across
RIN+ and RIN-
80
100
120
Ω
62
90
VCM = 1.2V
-90
mV
mV
SER/DES SUPPLY CURRENT *DIGITAL, PLL,
AND ANALOG VDDS
Serializer (Tx)
Total Supply Current Mode (includes
load current)
IDDT
IDDIOT
RT = 100Ω
WORST CASE
pattern (See
Figure 6)
RT = 100Ω
RANDOM pattern
RT = 100Ω
Serializer (Tx)
WORST CASE
VDDIO Supply Current (includes load
pattern (See
current)
Figure 6)
IDDTZ
IDDIOTZ
(4)
8
Serializer (Tx)
Supply Current Power-down
PDB = 0V; All
other LVCMOS
Inputs = 0V
VDDn = 1.89
V
f = 50 MHz
Default
Registers
mA
55
VDDIO = 1.89
V
PCLK = 50
MHz
Default
Registers
2
VDDIO = 3.6 V
PCLK = 50
MHz
Default
Registers
7
15
VDD = 1.89 V
370
775
VDDIO = 1.89
V
55
125
VDDIO = 3.6 V
65
135
5
mA
µA
Specification is ensured by characterization and is not tested in production.
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Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: DS92LX2121 DS92LX2122
DS92LX2121, DS92LX2122
www.ti.com
SNLS330J – MAY 2010 – REVISED JANUARY 2014
Serializer Electrical Characteristics(1)(2)(3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Deserializer (Rx)
VDDn Supply Current (includes load
current)
IDDR
IDDIOR
IDDRZ
Typ
Max
96
VDDn = 1.89V
CL = 8pF
WORST CASE
Pattern
(See Figure 6)
PCLK = 50
MHz
SSCG[3:0] =
ON
Default
Registers
60
VDDn = 1.89V
CL = 8pF
RANDOM Pattern
PCLK = 50
MHz
Default
Registers
53
VDDIO = 1.89 V
CL = 8pF
WORST CASE
Pattern
(See Figure 6)
PCLK = 50
MHz
Default
Registers
Deserializer (Rx)
VDDIO Supply Current (includes load
VDDIO = 3.6 V
current)
CL = 8pF
WORST CASE
Pattern
(See Figure 6)
PDB = 0V; All
other LVCMOS
Inputs = 0V
Deserializer (Rx)
Supply Current Power-down
Min
IDDIORZ
Units
mA
21
32
mA
PCLK = 50
MHz
Default
Registers
49
83
VDDn = 1.89
V
42
400
VDDIO = 1.89
V
8
40
VDDIO = 3.6 V
350
800
µA
Serializer Electrical Characteristics Recommended Serializer Timing for PCLK (1) (2) (3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
tTCP
Transmit Clock Period
tTCIH
Transmit Clock Input High
Time
Conditions
10 MHz – 50 MHz
Transmit Clock Input Low
Time
tCLKT
PCLK Input Transition Time
tOSC
Internal oscillator clock
source
(2)
(3)
(4)
Typ
Max
Units
20
T
100
ns
0.4T
0.5T
0.6T
ns
0.4T
0.5T
0.6T
ns
3
ns
(4)
tTCIL
(1)
Min
0.5
25
MHz
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not guaranteed.
Specification is ensured by characterization and is not tested in production.
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: DS92LX2121 DS92LX2122
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SNLS330J – MAY 2010 – REVISED JANUARY 2014
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Serializer Electrical Characteristics Serializer Switching Characteristics (1) (2) (3)
Symbol
Typ
Max
Units
tLHT
CML Low-to-High Transition
Time
RL = 100Ω (Figure 7)
150
330
ps
tHLT
CML High-to-Low Transition
Time
RL = 100Ω
(Figure 7)
150
330
ps
tDIS
Data Input Setup to PCLK
tDIH
Data Input Hold from PCLK
tPLD
Serializer PLL Lock Time
RL = 100Ω
tSD
Serializer Delay
RT = 100Ω
f = 10-50 MHz
Reg Address 0x03h b[0] (TRFB = 1)
(Figure 15)
tJIND
Serializer Output
Deterministic Jitter
Serializer output intrinsic deterministic
jitter . Measured (cycle-cycle) with
PRBS-7 test pattern PCLK = 50 MHz
0.13
UI
tJINR
Serializer Output Random
Jitter
Serializer output intrinsic random jitter
(cycle-cycle). Alternating-1,0 pattern.
PCLK = 50 MHz
0.04
UI
tJINT
Peak-to-peak Serializer
Output Jitter
Serializer output peak-to-peak jitter
includes deterministic jitter, random
jitter, and jitter transfer from serializer
input. Measured (cycle-cycle) with
PRBS-7 test pattern.
PCLK = 50MHz
0.396
UI
λSTXBW
Serializer Jitter Transfer
Function -3 dB Bandwidth
PCLK = 50 MHz Default Registers
1.90
MHz
δSTX
Serializer Jitter Transfer
Function (Peaking
PCLK = 50 MHz Default Registers
0.944
dB
δSTXf
Serializer Jitter Transfer
Function (Peaking
Frequency)
PCLK = 50 MHz Default Registers
500
kHz
(1)
(2)
(3)
Parameter
Conditions
Min
Serializer Data Inputs (Figure 13)
2.0
ns
2.0
ns
6.386T + 5
1
2
ms
6.386T +
12
6.386T +
19.7
ns
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not guaranteed.
Serializer Electrical Characteristics Deserializer Switching Characteristics (1) (2) (3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
tRCP
Receiver Output Clock Period
tPDC
PCLK Duty Cycle
tCLH
LVCMOS Low-to-High Transition
Time
tCHL
(1)
(2)
(3)
(4)
10
LVCMOS High-to-Low Transition
Time
Conditions
tRCP = tTCP
VDDIO: 1.71 V to 1.89 V
or 3.0 V to 3.6 V,
CL = 8pF (lumped load)
Default Registers
(Figure 16 ) (4)
Min
Typ
Max
Units
PCLK
Pin/Freq.
20
T
100
ns
PCLK
45
50
55
%
1.3
2.0
2.8
1.3
2.0
2.8
Deserializer PCLK
Output
ns
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not guaranteed.
Specification is ensured by design and is not tested in production.
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: DS92LX2121 DS92LX2122
DS92LX2121, DS92LX2122
www.ti.com
SNLS330J – MAY 2010 – REVISED JANUARY 2014
Serializer Electrical Characteristics Deserializer Switching Characteristics(1)(2)(3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
LVCMOS Low-to-High Transition
Time
tCLH
tCHL
LVCMOS High-to-Low Transition
Time
tROS
ROUT Setup Data to PCLK
tROH
ROUT Hold Data to PCLK
tDD
Deserializer Delay
tDDLT
Deserializer Data Lock Time
tRJIT
Receiver Input Jitter Tolerance
tDCJ
Deserializer Clock Jitter
tDPJ
Deserializer Period Jitter
tDCCJ
Deserializer Cycle-to-Cycle Clock
Jitter
fDEV
Spread Spectrum Clocking
Deviation Frequency
fMOD
Spread Spectrum Clocking
Modulation Frequency
(5)
(6)
(7)
(8)
(9)
(10)
(11)
Conditions
Pin/Freq.
VDDIO: 1.71 V to 1.89 V
or 3.0 V to 3.6 V,
CL = 8pF (lumped load)
Default Registers
(Figure 17) (4)
Deserializer Data
Outputs
VDDIO: 1.71 V to 1.89 V
or 3.0 V to 3.6 V, CL =
8pF (lumped load)
Default Registers
Deserializer Data
Outputs
Default Registers
Register 0x03h b[0]
(RRFB = 1)
Figure 18
10 MHz - 50 MHz
(5)
Min
Typ
Max
1.6
2.4
3.3
1.6
2.4
3.3
0.38
0.5
0.38T
0.5T
4.571T +
8
4.571T +
12
Units
ns
10 MHz - 50 MHz
T
4.571T
+ 16
ns
10
ms
(6) (7)
0.53
PCLK
SSCG[3:0] = OFF
10 MHz
300
550
50 MHz
120
250
PCLK
SSCG[3:0] = OFF
10 MHz
425
600
(10) (9)
50 MHz
320
480
PCLK
SSCG[3:0] = OFF
10 MHz
320
500
(11) (9)
50 MHz
300
500
LVCMOS Output Bus
SSC[3:0] = ON
Figure 20
20 MHz - 50 MHz
±0.5% to
±2.0%
%
20 MHz - 50 MHz
9 kHz to
66 kHz
kHz
50 MHz
(8) (9)
UI
ps
ps
ps
tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK.
UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
tRJIT max (0.61UI) is limited by instrumentation and actual tRJIT of in-band jitter at low frequency (0
0
3.45
µs
ns
Recommended Input Timing Requirements are input specifications and not tested in production.
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: DS92LX2121 DS92LX2122
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DS92LX2121, DS92LX2122
SNLS330J – MAY 2010 – REVISED JANUARY 2014
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Bi-Directional Control Bus AC Timing Specifications (SCL, SDA) - I2C Compliant
(Figure 5) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SWITCHING CHARACTERISTICS ()
fSCL
SCL Clock Frequency
tLOW
Serializer MODE = 0 – R/W Register
0x05 = 0x40'h
100
Deserializer MODE = 0 – READ
Register 0x06 b[6:4] = 0x00'h
100
kHz
Serializer MODE = 0 – R/W Register
0x05 = 0x40'h
SCL Low Period
Deserializer MODE = 0 – READ
Register 0x06 b[6:4] = 0x00'h
Serializer MODE = 0 – R/W Register
0x05 = 0x40'h
4.7
μs
4.0
μs
tHIGH
SCL High Period
tHD:STA
Hold time for a start or a repeated start
condition
Serializer MODE = 0 Register 0x05
= 0x40'h
4.0
μs
tSU:STA
Set Up time for a start or a repeated
start condition
Serializer MODE = 0 Register 0x05
= 0x40'h
4.7
μs
tHD:DAT
Data Hold Time
tSU:DAT
Data Set Up Time
tSU:STO
Set Up Time for STOP Condition
tf
SCL & SDA Fall Time
tBUF
Bus free time between a stop and start
condition
tTIMEOUT
NACK Time out
Deserializer MODE = 0 – READ
Register 0x06 b[6:4] = 0x00'h
0
3.45
Serializer M/S = 0
μs
4.0
300
Serializer M/S = 0
μs
μs
250
4.7
μs
µs
Serializer
1
Deserializer
25
ms
SDA
tLOW
tf
tHD;STA
tr
tf
tBUF
tr
tSP
SCL
tSU;STA
tHD;STA
tHIGH
tSU;STO
tSU;DAT
tHD;DAT
START
STOP
REPEATED
START
START
Figure 5. Serial Control Bus Timing
Bi-Directional Control Bus DC Characteristics (SCL, SDA) - I2C Compliant
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VDDIO
V
0.3 x
VDDIO
V
VIH
Input High Level
SDA and SCL
0.7 x
VDDIO
VIL
Input Low Level Voltage
SDA and SCL
GND
VHY
Input Hysteresis
IOZ
TRI-STATE Output Current
PDB = 0V VOUT = 0V or VDD
-20
±1
+20
µA
IIN
Input Current
SDA or SCL, Vin = VDDIO or GND
-20
±1
+20
µA
CIN
Input Pin Capacitance
12
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>50
100 pF
RPU = 1 k: to 4.7 k:
RID (see ID[x] Resistor Value Table)
FB1 - FB7: Impedance = 1 k: (@ 100 MHz)
low DC resistance (100 pF
RPU = 1 k: to 4.7 k:
RID (see ID[x] Resistor Value Table)
FB1 - FB8: Impedance = 1 k: (@ 100 MHz)
low DC resistance (
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