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ESD122
ZHCSGB3A – JUNE 2017 – REVISED AUGUST 2018
适用于 USB Type-C 和 HDMI 2.0 的 ESD122 2 通道 ESD 保护二极管
1 特性
•
1
•
•
•
•
•
•
•
•
•
•
•
•
IEC 61000-4-2 4 级静电放电 (ESD) 保护
– ±17kV 接触放电
– ±17kV 气隙放电
可承受超过 1 万次 ESD 冲击而不出现任何性能下
降的情况，符合 IEC 61000-4-2 4 级（接触）标准
IEC 61000-4-4 瞬态放电 (EFT) 保护
– 80A (5/50ns)
IEC 61000-4-5 浪涌保护
– 2.5A (8/20µs)
低 IO 电容
– IO 之间 0.1pF（典型）
– IO 接地 0.2pF（典型）
直流击穿电压：5.1V（最小值）
超低泄漏电流：10nA（最大值）
低 ESD 钳位电压：在 5A TLP 下为 8.4V
支持超过 10Gbps 的高速接口
工业温度范围：-40°C 至 +125°C
Type-C 友好型双通道直通布线封装
引脚适合对称差分高速信号路由
两种不同的封装选项
– 0402 封装，0.6mm × 1mm，0.34mm 间距
– 0502 封装，0.6mm × 1.32mm，0.5mm 间距
2 应用
•
•
终端设备
– 手机和平板电脑
– 便携式计算机和台式机
– 机顶盒
– 电视和监视器
– 服务器
接口
– USB Type-C
– HDMI 2.0/1.4
– USB 3.1 第 2 代/第 1 代，USB 3.0 和 USB 2.0
– Thunderbolt-1 和 Thunderbolt-2
– 显示端口 1.3
– PCI Express 3.0总线接口
– 串口硬盘（SATA）
3 说明
ESD122 是一种双向 TVS ESD 保护二极管阵列，用于
USB Type-C 和 HDMI 2.0 电路保护。ESD122 的额定
消散接触 ESD 冲击能力达到了 IEC 61000-4-2 国际标
准所规定的最高水平（17kV 接触放电，17kV 气隙放
电）。
该器件 具有 每通道和引脚一个低 IO 电容，以适应对
称差分高速信号路由，使其成为保护高达 10Gbps 的
高速接口（如 USB 3.1 第 2 代和 HDMI 2.0）的理想
选择。低动态电阻和低钳位电压确保系统级抗瞬变事件
保护。
此外，ESD122 是面向 USB Type-C Tx/Rx 线路的理
想 ESD 解决方案。由于 USB Type-C 连接器有两层，
所以使用 4 通道 ESD 器件需要 VIA 来降级信号完整
性。使用 4 个 ESD122（2 通道）器件可最大限度减
少 VIA 的数量并简化电路板布局。
在两个简便的直通布线封装中提供了 ESD122。
器件信息(1)
器件型号
ESD122
封装
X2SON (3)
封装尺寸（标称值）
(DMX)
0.60mm x 1.00mm
(DMY)
0.60mm × 1.32mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
USB Type-C 应用示例
ESD122
USB Type-C
Connector
SSRX1P
ESD122
SSRX1N
SSTX1P
SSTX1N
VBUS
C_SBU2
SBU2
CC1
DPT
DMT
DMB
TPD8S300
CC1
C_DPT
DPT
C_DMT
ESD and OVP
Protection
C_DMB
DPB
C_DPB
SBU1
C_SBU1
CC2
SBU2
C_CC1
C_CC2
DMT
DMB
DPB
SBU1
CC2
VBUS
SSRX2N
ESD122
SSRX2P
SSTX2N
SSTX2P
ESD122
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSDP5
ESD122
ZHCSGB3A – JUNE 2017 – REVISED AUGUST 2018
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性 ..........................................................................
应用 ..........................................................................
说明 ..........................................................................
修订历史记录 ...........................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings—JEDEC Specification.........................
ESD Ratings—IEC Specification ..............................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
7.4 Device Functional Modes.......................................... 9
8
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Applications ............................................... 10
9 Power Supply Recommendations...................... 14
10 Layout................................................................... 14
10.1 Layout Guidelines ................................................. 14
10.2 Layout Examples................................................... 14
11 器件和文档支持 ..................................................... 16
11.1
11.2
11.3
11.4
11.5
11.6
文档支持................................................................
接收文档更新通知 .................................................
社区资源................................................................
商标 .......................................................................
静电放电警告.........................................................
术语表 ...................................................................
16
16
16
16
16
16
12 机械、封装和可订购信息 ....................................... 16
4 修订历史记录
Changes from Original (June 2017) to Revision A
Page
•
Changed VBRF From: MIN = 5.1, MAX = 7 To: MIN = 5 and MAX = 7.9 ............................................................................... 5
•
Changed VBRR From: MIN = –7, MAX = –5.1 To: MIN = –7.9 and MAX = –5 ....................................................................... 5
2
Copyright © 2017–2018, Texas Instruments Incorporated
ESD122
www.ti.com.cn
ZHCSGB3A – JUNE 2017 – REVISED AUGUST 2018
5 Pin Configuration and Functions
DMX Package
3-Pin X2SON
Top View
IO2
IO1
3
2
DMY Package
3-Pin X2SON
Top View
IO2
IO1
3
2
1
GND
1
GND
Pin Functions
PIN
DMX
NO.
DMY
NO.
I/O
GND
1
1
—
IO1
2
2
I
ESD protected channel
IO2
3
3
I
ESD protected channel
NAME
Copyright © 2017–2018, Texas Instruments Incorporated
DESCRIPTION
Ground
3
ESD122
ZHCSGB3A – JUNE 2017 – REVISED AUGUST 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Electrical fast transient
Peak pulse
MAX
UNIT
80
A
IEC 61000-4-5 Power (tp - 8/20 µs) at 25°C
20
W
IEC 61000-4-5 Current (tp - 8/20 µs) at 25°C
2.5
A
IEC 61000-4-4 (5/50 ns) at 25°C
TA
Operating free-air temperature
–40
125
°C
Tstg
DMD storage temperature
–65
155
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings—JEDEC Specification
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS001 (1)
±2500
Charged-device model (CDM), per JEDEC specification
JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings—IEC Specification
VALUE
V(ESD)
Electrostatic discharge
IEC 61000-4-2 contact discharge
±17000
IEC 61000-4-2 air-gap discharge
±17000
UNIT
V
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VIO
Input pin voltage
–3.6
3.6
UNIT
V
TA
Operating free-air temperature
–40
125
°C
6.5 Thermal Information
ESD122
THERMAL METRIC (1)
DMX (X2SON)
DMY (X2SON)
3 PINS
3 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
617.8
717.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
286.2
300.2
°C/W
RθJB
Junction-to-board thermal resistance
455.1
526
°C/W
ψJT
Junction-to-top characterization parameter
99.3
113.9
°C/W
ψJB
Junction-to-board characterization parameter
453.4
523.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2017–2018, Texas Instruments Incorporated
ESD122
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ZHCSGB3A – JUNE 2017 – REVISED AUGUST 2018
6.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VRWM
Reverse stand-off voltage
IIO < 10 nA
VBRF
Breakdown voltage, any IO pin to
GND (1)
VBRR
VHOLD
VCLAMP
ILEAK
MAX
UNIT
3.6
V
IIO = 1 mA, TA = 25°C
5
7.9
V
Breakdown voltage, GND to any IO
pin (1)
IIO = 1 mA, TA = 25°C
–7.9
–5
V
Holding voltage (2)
IIO = 1 mA
5.9
IPP = 1 A, TLP, from IO to GND, TA =
25°C
6.4
IPP = 5 A, TLP, from IO to GND, TA =
25°C
8.4
IPP = 1 A, TLP, from GND to IO, TA =
25°C
6.4
IPP = 5 A, TLP, from GND to IO, TA =
25°C
8.4
Clamping voltage
Leakage current, any IO to GND
0.5
GND to IO, Measured between TLP IPP of
10 A and 20 A, TA = 25°C
0.5
Line capacitance
VIO = 0 V, f = 1 MHz, IO to GND, TA =
25°C
Variation of line capacitance
Difference between the capacitance of
the two IO pins measured with respect to
ground, VIO = 0 V, f = 1 MHz, TA = 25°C,
GND = 0 V
Channel to channel capacitance
Capacitance from one IO to another IO,
VIO = 0 V, f = 1 MHz, TA = 25°C,
GND = 0 V
ΔCL
CCROSS
10
IO to GND, Measured between TLP IPP of
10 A and 20 A, TA = 25°C
CL
V
V
VIO = ±2.5 V
Dynamic resistance
(2)
TYP
–3.6
RDYN
(1)
MIN
0.2
0.1
nA
Ω
0.27
pF
0.01
pF
0.14
pF
VBRF and VBRR are defined as the voltage obtained at 1 mA when sweeping the voltage up, before the device latches into the snapback
state.
VHOLD is defined as the voltage when 1 mA is applied, after the device has successfully latched into the snapback state.
Copyright © 2017–2018, Texas Instruments Incorporated
5
ESD122
ZHCSGB3A – JUNE 2017 – REVISED AUGUST 2018
www.ti.com.cn
32
32
28
28
24
24
20
20
Current (A)
Current (A)
6.7 Typical Characteristics
16
12
16
12
8
8
4
4
0
0
-4
-4
0
2
4
6
8
10 12 14
Voltage (V)
16
18
20
22
0
2
4
6
8
D002
Figure 1. Positive TLP Curve, IO Pin to GND
10 12 14
Voltage (V)
16
18
20
22
24
D003
Figure 2. Negative TLP Curve, IO Pin to GND (Plotted as
Positive TLP Curve GND to IO)
120
0
110
-10
100
-20
90
-30
Voltage (V)
Voltage (V)
80
70
60
50
40
-40
-50
-60
-70
30
-80
20
-90
10
0
-15
0
15
30
45
60
Time (ns)
75
90
105
-100
-15
120
Figure 3. 8-kV IEC 61000-4-2 Waveform, IO Pin to GND
Power
Voltage
Current
20
45
60
Time (ns)
75
90
105
120
D005
-40qC
25qC
85qC
125qC
0.35
Capacitance (pF)
Voltage (V) / Current (A) / Power (W)
30
0.4
15
10
5
0
0.3
0.25
0.2
0.15
0.1
0
25
50
75
Time (Ps)
100
125
150
D006
Figure 5. IEC 61000-4-5 Surge Curve (tp = 8/20µs), IO Pin to
GND
6
15
Figure 4. –8-kV IEC 61000-4-2 Waveform, IO Pin to GND
25
-5
-25
0
D004
0
0.5
1
1.5
2
Bias (V)
2.5
3
3.5
D008
Figure 6. Capacitance vs Bias Voltage at Multiple
Temperatures, IO Pin to GND
Copyright © 2017–2018, Texas Instruments Incorporated
ESD122
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ZHCSGB3A – JUNE 2017 – REVISED AUGUST 2018
Typical Characteristics (continued)
0.001
1
0.9
0.8
0.0005
Leakage (nA)
Current (A)
0.7
0
0.6
0.5
0.4
0.3
-0.0005
0.2
0.1
-0.001
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2
Voltage (V)
3
4
5
6
7
0
-60
8
-40
-20
0
20
40
60
80
Temperature (qC)
D001
Figure 7. DC Voltage Sweep I-V Curve, IO Pin to GND
100
120
140
D009
Figure 8. Leakage Current vs Temperature, IO Pin to GND,
at 2.5 V Bias
0.8
0.35
0
0.3
-1.6
Capacitance (pF)
Insertion Loss (dB)
-0.8
-2.4
-3.2
-4
-4.8
-5.6
-6.4
0.25
0.2
0.15
0.1
0.05
-7.2
-8
0.0001
0
0.001
0.01
0.1
1
Frequency (GHz)
10
100
2
3
4
5
6
D010
Figure 9. Insertion Loss
7
8
9 10 11 12 13 14 15
Frequency (GHz)
D011
Figure 10. Capacitance vs Frequency
0.001
Pre-Stress
Post-Stress
Current (A)
0.0005
0
-0.0005
-0.001
-7
-6
-5
-4
-3
-2
-1 0 1
Voltage (V)
2
3
4
5
6
7
D012
Figure 11. DC Voltage Sweep I-V Curve, IO Pin to GND,
Pre and Post 10,000 Repetitive ESD Strikes per IEC 61000-4-2 Level 4 (Contact)
Copyright © 2017–2018, Texas Instruments Incorporated
7
ESD122
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7 Detailed Description
7.1 Overview
The ESD122 is a bidirectional ESD Protection Diode with ultra-low capacitance. This device can dissipate ESD
strikes above the maximum level specified by the IEC 61000-4-2 International Standard. The ultra-low
capacitance makes this device ideal for protecting any super high-speed signal pins. Additionally, the ESD122
has two identical protection channels with a symmetrical pin-out that is suited for the differential high-speed
signal lines.
7.2 Functional Block Diagram
IO1
IO2
GND
7.3 Feature Description
7.3.1 IEC 61000-4-2 ESD Protection
The I/O pins can withstand ESD events up to ±17-kV contact and air gap. An ESD-surge clamp diverts the
current to ground.
7.3.2 IEC 61000-4-4 EFT Protection
The I/O pins can withstand an electrical fast transient burst of up to 80 A (5/50-ns waveform, 4 kV with 50-Ω
impedance). An ESD-surge clamp diverts the current to ground.
7.3.3 IEC 61000-4-5 Surge Protection
The I/O pins can withstand surge events up to 2.5 A and 20 W (8/20-µs waveform). An ESD-surge clamp diverts
this current to ground.
7.3.4 IO Capacitance
The capacitance between each I/O pin to ground is very small and supports data rates up to 10 Gbps.
7.3.5 DC Breakdown Voltage
The DC breakdown voltage of each I/O pin is a minimum of ±5.1 V. This ensures that sensitive equipment is
protected from surges above the reverse standoff voltage of ±3.6 V.
7.3.6 Ultra Low Leakage Current
The I/O pins feature an ultra-low leakage current of 10 nA (maximum) with a bias of ±2.5 V.
7.3.7 Low ESD Clamping Voltage
The I/O pins feature an ESD clamp that is capable of clamping the voltage to 8.4 V (IPP-TLP = 5 A).
7.3.8 Supports High Speed Interfaces
This device is capable of supporting high speed interfaces up to 10 Gbps such as USB 3.1 Gen2 and Gen1,
USB 3.0, USB 2.0, Thunderbolt-1, Thunderbolt-2, PCI express 3.0, Display Port 1.3, HDMI 2.0, and HDMI 1.4,
because of the extremely low IO capacitance.
7.3.9 Industrial Temperature Range
This device features an industrial operating range of –40°C to +125°C.
8
Copyright © 2017–2018, Texas Instruments Incorporated
ESD122
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ZHCSGB3A – JUNE 2017 – REVISED AUGUST 2018
Feature Description (continued)
7.3.10 Easy Flow-Through Routing Package
The layout of this device makes it simple and easy to add protection to an existing layout. 2-channel setup
provides easy, flexible routing and good matching between the channels.
7.4 Device Functional Modes
The ESD122 is a passive circuit that triggers when voltages are above VBRF or below VBRR. During ESD events,
voltages as high as ±17 kV (contact) can be directed to ground via the internal diode network. When the voltages
on the protected line fall below the trigger levels of ESD122 (usually within 10s of nano-seconds) the device
reverts to passive.
Figure 12 shows typical TLP behavior of bi-directional ESD device.
+ ve
Ipp
RDYN+
-Vclamp-Ipp
- ve
-VBR-TLP
-Vhold-TLP
-Vrwm
+ ve
Vrwm
RDYN-
Vhold-TLP
VBR-TLP
Vclamp-Ipp
Note 1: VBR-TLP and Vhold-TLP shown here are from the TLP
measurements and not to be confused with the DC
measurements of VBRF,VBRR, and VHOLD in Table 6.6
Note 2: Vrwm is not measured from the TLP curve. ,W¶V
shown here only to show that Vrwm < VBR-TLP
-Ipp
- ve
Figure 12. Generic TLP I-V Curve for a Bi-Directional ESD Device
for the Illustration of Vrwm, VBR, Vhold and Vclamp
Copyright © 2017–2018, Texas Instruments Incorporated
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The ESD122 is a diode type TVS which is used to provide a path to ground for dissipating ESD events on highspeed signal lines between a human interface connector and a system. As the current from ESD passes through
the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC.
The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC.
8.2 Typical Applications
8.2.1 USB 3.1 Gen 2 Application
ESD122
USB Type-C
Connector
SSRX1P
ESD122
SSRX1N
SSTX1P
SSTX1N
TPD4E05U06
VBUS
SBU2
CC1
DPT
TPD4E05U06
DMT
DMB
DPB
SBU1
CC2
VBUS
SSRX2N
ESD122
SSRX2P
SSTX2N
SSTX2P
ESD122
Figure 13. Typical Application
8.2.1.1 Design Requirements
For this design example, four ESD122 devices and two TPD4E05U06 devices are being used in a USB 3.1 Gen
2 Type-C application. This provides a complete ESD protection scheme.
Given the application, the parameters listed in Table 1 are known.
10
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ESD122
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ZHCSGB3A – JUNE 2017 – REVISED AUGUST 2018
Typical Applications (continued)
Table 1. Design Parameters
DESIGN PARAMETER
VALUE
Signal range on Type C SuperSpeed+ lines
0 V to 3.6 V
Operating frequency on Type C USB 3.1 Gen 2 SuperSpeed+ lines
5 GHz
Signal range on CC, SBU, and DP/DM lines
0 V to 5 V
Operating frequency on CC, SBU, and DP/DM lines
up to 480 MHz
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Signal Range
The ESD122 supports signal ranges between –3.6 V and 3.6 V, which supports the SuperSpeed+ pairs on the
USB Type-C application. The TPD4E05U06 supports signal ranges between 0 V and 5.5 V, which supports the
CC, SBU, and DP/DM lines.
8.2.1.2.2 Operating Frequency
The ESD122 has a 0.27 pF (maximum) capacitance, which supports the USB 3.1 Gen 2 Type-C rate of 10 Gbps
with sufficient capacitance margin. The TPD4E05U06 has a 0.5 pF (typical) capacitance, which easily supports
the CC, SBU, and DP/DM data rates. The ESD122 has 2 identical protection channels for the differential HDMI
high-speed signal lines. The symmetrical pin out of the device with a ground pin between the two differential
signal pins makes it suitable for this application.
8.2.1.3 Application Curves
Figure 14. USB3.1 Gen2 10-Gbps Eye Diagram Without
ESD122
Copyright © 2017–2018, Texas Instruments Incorporated
Figure 15. : USB3.1 Gen2 10-Gbps Eye Diagram With
ESD122
11
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www.ti.com.cn
8.2.2 HDMI 2.0 Application
TMDS D2+
ESD122
TMDS_GND
TMDS D2+
TMDS D1+
ESD122
TMDS_GND
TMDS D1-
TMDS_GND
TMDS D0TMDS CLK+
ESD122
TMDS_GND
TMDS CLK-
TPD1E05U06
TPD1E05U06
CEC
HDMI 2.0 Connector
TMDS D0+
ESD122
UTILITY
DDC_CLK
TPD1E05U06
TPD1E05U06
DDC_DAT
GND
P 5V0
HOTPLUG
TPD1E05U06
Copyright © 2017, Texas Instruments Incorporated
Figure 16. HDMI 2.0 Schematic
8.2.2.1 Design Requirements
For this design example, the four ESD122 devices for the HDMI 2.0 high-speed lines, and four TPD1E05U06
devices on the control lines HDMI 2.0 control lines. This provides a complete port protection scheme.
Given the HDMI 2.0 application, the parameters listed in Table 2 are known.
Table 2. Design Parameters
12
DESIGN PARAMETER
VALUE
Signal voltage range on the high-speed pins
0 V to 3.3 V
Signal voltage range on the control pins
0 V to 5 V
Max operating frequency of high-speed lines
3 GHz
Copyright © 2017–2018, Texas Instruments Incorporated
ESD122
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ZHCSGB3A – JUNE 2017 – REVISED AUGUST 2018
8.2.2.2 Detailed Design Procedure
8.2.2.2.1 Signal Range
The ESD122 supports signal ranges between –3.6 V and 3.6 V, which supports the high-speed lines on the
HDMI 2.0 application. The TPD1E05U06 supports signal ranges between 0 V and 5.5 V, which supports the
HDMI control lines.
8.2.2.2.2 Operating Frequency
The ESD122 has a 0.27 pF (maximum) capacitance, which supports the HDMI 2.0 rate of 6 Gbps with sufficient
capacitance margin. The TPD1E05U06 has a 0.42 pF (typical) capacitance, which easily supports the control
lines. The ESD122 has 2 identical protection channels for the differential HDMI high-speed signal lines. The
symmetrical pin out of the device with a ground pin between the two differential signal pins makes it suitable for
this application.
8.2.2.3 Application Curves
Figure 17. HDMI 2.0 6-Gbps Eye Diagram Without ESD122
Copyright © 2017–2018, Texas Instruments Incorporated
Figure 18. HDMI 2.0 6-Gbps Eye Diagram With ESD122
13
ESD122
ZHCSGB3A – JUNE 2017 – REVISED AUGUST 2018
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9 Power Supply Recommendations
This device is a passive ESD device so there is no need to power it. Take care not to violate the recommended
I/O specification (–3.6 V to 3.6 V) to ensure the device functions properly.
10 Layout
10.1 Layout Guidelines
•
•
•
The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
Route the protected traces as straight as possible. Use as few vias as possible for 10-Gbps application.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
SSTX2P
ESD122
SSTX2N
SSRX2P
SSRX2N
ESD122
CC2
SBU1
DM_bot
DP_bot
CC1
DP_top
DM_top
TPD4E05U06
TPD4E05U06
SBU2
SSTX1P
SSTX1N
ESD122
ESD122
SSRX1P
SSRX1N
10.2 Layout Examples
Legend
Top Layer
Bottom Layer
Pin to GND
VIA to VBUS Plane
VIA to Other Layer
VIA to GND Plane
Figure 19. USB 3.1 Gen 2 SuperSpeed Lines Protected by ESD122
14
Copyright © 2017–2018, Texas Instruments Incorporated
ESD122
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ZHCSGB3A – JUNE 2017 – REVISED AUGUST 2018
Layout Examples (continued)
Legend
ESD122 (x4)
Top Layer
VIA to GND Plane
GND
TMDS_D2+
TMDS_D2+
GND
TMDS_D2GND
TMDS_D1+
TMDS_D2TMDS_D1+
GND
TMDS_D1GND
TMDS_D0+
TMDS_D1TMDS_D0+
GND
TMDS_D0GND
TMDS_CK+
TMDS_D0TMDS_CK+
GND
TMDS_CK-
TMDS_CKGND
CEC
CEC
UTILITY
UTILITY
DDC_CLK
GND
DDC_CLK
DDC_DAT
GND
DDC_DAT
5V_OUT
GND
HOTPLUG_DET
5V_SUPPLY
HOTPLUG_DET
GND
TPD1E05U06 (x5)
Figure 20. HDMI2_Layout
版权 © 2017–2018, Texas Instruments Incorporated
15
ESD122
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11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
ESD122 评估模块
11.2 接收文档更新通知
如需接收文档更新通知，请访问 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
串口硬盘（SATA） is a trademark of others.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。
16
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重要声明和免责声明
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Copyright © 2018 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ESD122DMXR
ACTIVE
X2SON
DMX
3
10000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
6U
ESD122DMYR
ACTIVE
X2SON
DMY
3
10000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
6V
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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