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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
MSP430F673x, MSP430F672x Mixed-Signal Microcontrollers
1 Device Overview
1.1
Features
1
• Low Supply Voltage Range:
3.6 V Down to 1.8 V
• Ultra-Low Power Consumption
– Active Mode (AM):
All System Clocks Active
265 µA/MHz at 8 MHz, 3.0 V, Flash Program
Execution (Typical)
140 µA/MHz at 8 MHz, 3.0 V, RAM Program
Execution (Typical)
– Standby Mode (LPM3):
Real-Time Clock (RTC) With Crystal, Watchdog,
and Supply Supervisor Operational, Full RAM
Retention, Fast Wakeup:
1.7 µA at 2.2 V, 2.5 µA at 3.0 V (Typical)
– Off Mode (LPM4):
Full RAM Retention, Supply Supervisor
Operational, Fast Wakeup:
1.6 µA at 3.0 V (Typical)
– Shutdown RTC Mode (LPM3.5):
Shutdown Mode, Active Real-Time Clock (RTC)
With Crystal:
1.24 µA at 3.0 V (Typical)
– Shutdown Mode (LPM4.5):
0.78 µA at 3.0 V (Typical)
• Wake up From Standby Mode in 3 µs (Typical)
• 16-Bit RISC Architecture, Extended Memory, up to
25-MHz System Clock
• Flexible Power Management System
– Fully Integrated LDO With Programmable
Regulated Core Supply Voltage
– Supply Voltage Supervision, Monitoring, and
Brownout
– System Operation From up to Two Auxiliary
Power Supplies
• Unified Clock System
– FLL Control Loop for Frequency Stabilization
– Low-Power Low-Frequency Internal Clock
Source (VLO)
– Low-Frequency Trimmed Internal Reference
Source (REFO)
– 32-kHz Crystals (XT1)
• One 16-Bit Timer With Three Capture/Compare
Registers
• Three 16-Bit Timers With Two Capture/Compare
Registers Each
• Enhanced Universal Serial Communication
Interfaces
– eUSCI_A0, eUSCI_A1, and eUSCI_A2
– Enhanced UART Supports Automatic BaudRate Detection
– IrDA Encoder and Decoder
– Synchronous SPI
– eUSCI_B0
– I2C With Multiple Slave Addressing
– Synchronous SPI
• Password-Protected RTC With Crystal Offset
Calibration and Temperature Compensation
• Separate Voltage Supply for Backup Subsystem
– 32-kHz Low-Frequency Oscillator (XT1)
– Real-Time Clock
– Backup Memory (4 × 16 Bits)
• Three 24-Bit Sigma-Delta Analog-to-Digital
Converters (ADCs) With Differential PGA Inputs
• Integrated LCD Driver With Contrast Control for up
to 320 Segments in 8-Mux Mode
• Hardware Multiplier Supports 32-Bit Operations
• 10-Bit 200-ksps ADC
– Internal Reference
– Sample-and-Hold, Autoscan Feature
– Up to Six External Channels and Two Internal
Channels, Including Temperature Sensor
• 3-Channel Internal DMA
• Serial Onboard Programming, No External
Programming Voltage Needed
• Single-Phase Electronic Watt-Hour Meter
Development Tool (Also See Tools and Software)
– EVM430-F6736 - MSP430F6736 EVM for
Metering
– Energy Measurement Design Center for
MSP430™ MCUs
• Device Comparison Summarizes the Available
Family Members
• Available in 100-Pin and 80-Pin LQFP Packages
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
1.2
•
•
Applications
2-Wire Single-Phase Metering
3-Wire Single-Phase Metering
1.3
www.ti.com
•
Tamper-Resistant Meters
Description
The TI MSP family of ultra-low-power microcontrollers consists of several devices featuring different sets
of peripherals targeted for various applications. The architecture, combined with extensive low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device
features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to
maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from lowpower modes to active mode in 3 µs (typical).
The MSP430F673x and MSP430F672x microcontrollers feature up to three high-performance 24-bit
sigma-delta ADCs, a 10-bit ADC, four enhanced universal serial communication interfaces (three
eUSCI_A modules and one eUSCI_B module), four 16-bit timers, a hardware multiplier, a DMA module,
an RTC module with alarm capabilities, an LCD driver with integrated contrast control, an auxiliary supply
system, and up to 72 I/O pins in the 100-pin devices and 52 I/O pins in the 80-pin devices.
For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's Guide.
Device Information (1)
PACKAGE
BODY SIZE (2)
MSP430F6736IPZ
LQFP (100)
14 mm × 14 mm
MSP430F6736IPN
LQFP (80)
12 mm × 12 mm
PART NUMBER
(1)
(2)
2
For the most current part, package, and ordering information, see the Package Option Addendum in
Section 8, or see the TI website at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 8.
Device Overview
Copyright © 2011–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F6736 MSP430F6735 MSP430F6734 MSP430F6733 MSP430F6731 MSP430F6730
MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.ti.com
1.4
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Functional Block Diagrams
DVCC DVSS
AVCC AVSS
AUXVCC3
XOUT
AUXVCC2
XIN
AUXVCC1
Figure 1-1 shows the functional block diagram for all device variants in the PZ package.
RST/NMI
PA
P1.x P2.x
PB
P3.x P4.x
PC
P5.x P6.x
PD
P7.x P8.x
PE
P9.x
I/O Ports
P1, P2
2×8 I/Os
Interrupt and
Wakeup
I/O Ports
P3, P4
2×8 I/Os
I/O Ports
P5, P6
2×8 I/Os
I/O Ports
P7, P8
2×8 I/Os
I/O Ports
P9
1×4 I/O
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
PD
1×16 I/Os
PE
1×4 I/O
(32kHz)
ACLK
Unified
Clock
System
SMCLK
SYS
128KB
96KB
64KB
32KB
16KB
8KB
4KB
2KB
1KB
Flash
RAM
MCLK
Watchdog
MPY32
CRC16
Port
Mapping
Controller
CPUXV2
and
Working
Registers
(25 MHz)
EEM
(S: 3+1)
PMM
Auxiliary
Supplies
JTAG,
SBW
Interface
LDO
SVM, SVS
BOR
Port PJ
SD24_B
ADC10_A
LCD_C
REF
3 channel
2 channel
10 bit
200 ksps
8-mux
Up to 320
Segments
Reference
1.5 V, 2.0 V,
2.5 V
RTC_C
(UART,
IrDA,SPI)
Timer_A
2 CC
Registers
Timer_A
3 CC
Registers
PJ.x
eUSCI_A0
eUSCI_A1
eUSCI_A2
TA1
TA2
TA3
TA0
eUSCI_B0
2
(SPI, I C)
DMA
3 channel
Copyright © 2018, Texas Instruments Incorporated
Figure 1-1. Functional Block Diagram - MSP430F673xIPZ and MSP430F672xIPZ
DVCC DVSS
AVCC AVSS
AUXVCC3
XOUT
AUXVCC2
XIN
AUXVCC1
Figure 1-2 shows the functional block diagram for all device variants in the PN package.
RST/NMI
PA
P1.x P2.x
PB
P3.x P4.x
PC
P5.x P6.x
I/O Ports
P1, P2
2×8 I/Os
Interrupt and
Wakeup
I/O Ports
P3, P4
2×8 I/Os
I/O Ports
P5, P6
2×8 I/Os
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
TA0
TA1
TA2
TA3
eUSCI_A0
eUSCI_A1
eUSCI_A2
Timer_A
3 CC
Registers
Timer_A
2 CC
Registers
(UART,
IrDA, SPI)
(32 kHz)
ACLK
Unified
Clock
System
SMCLK
MCLK
128KB
96KB
64KB
32KB
16KB
8KB
4KB
2KB
1KB
Flash
RAM
SYS
DMA
Watchdog
3 Channel
Port
Mapping
Controller
CRC16
MPY32
CPUXV2
and
Working
Registers
(25 MHz)
EEM
(S: 3+1)
JTAG,
SBW
Interface
Port PJ
PMM
Auxiliary
Supplies
LDO
SVM, SVS
BOR
SD24_B
ADC10_A
LCD_C
REF
3 channel
2 channel
10 bit
200 ksps
8-mux
Up to 320
segments
Reference
1.5 V, 2.0 V,
2.5 V
RTC_C
eUSCI_B0
(SPI, I2C)
PJ.x
Copyright © 2018, Texas Instruments Incorporated
Figure 1-2. Functional Block Diagram - MSP430F673xIPN and MSP430F672xIPN
Device Overview
Submit Documentation Feedback
Product Folder Links: MSP430F6736 MSP430F6735 MSP430F6734 MSP430F6733 MSP430F6731 MSP430F6730
MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
Copyright © 2011–2018, Texas Instruments Incorporated
3
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
www.ti.com
Table of Contents
1
2
3
Device Overview ......................................... 1
5.17
REF.................................................. 61
1.1
Features .............................................. 1
5.18
Flash Memory ....................................... 62
1.2
Applications ........................................... 2
5.19
Emulation and Debug ............................... 62
1.3
Description ............................................ 2
1.4
5
Functional Block Diagrams ........................... 3
6.1
CPU
6.2
Instruction Set ....................................... 64
6.3
Operating Modes .................................... 65
Related Products ..................................... 7
6.4
Interrupt Vector Addresses.......................... 66
Terminal Configuration and Functions .............. 8
6.5
Memory Organization ............................... 67
4.1
Pin Diagrams ......................................... 8
6.6
Bootloader (BSL) .................................... 69
.................................................
4.2
63
Signal Descriptions .................................. 12
6.7
JTAG Operation ..................................... 69
Specifications ........................................... 24
6.8
Flash Memory ....................................... 70
5.1
Absolute Maximum Ratings ......................... 24
6.9
RAM ................................................. 70
5.2
ESD Ratings
24
6.10
Backup RAM ........................................ 70
5.3
5.4
........................................
Recommended Operating Conditions ...............
24
Active Mode Supply Current Into VCC Excluding
External Current ..................................... 26
Low-Power Mode Supply Currents (Into VCC)
Excluding External Current.......................... 27
Low-Power Mode With LCD Supply Currents (Into
VCC) Excluding External Current .................... 28
6.11
Peripherals
6.12
Input/Output Diagrams .............................. 95
6.13
Device Descriptors (TLV) .......................... 127
5.5
5.6
7
..........................................
71
Device and Documentation Support .............. 129
...................
7.1
Getting Started and Next Steps
7.2
Device Nomenclature .............................. 129
129
5.7
Thermal Resistance Characteristics ................ 29
7.3
Tools and Software ................................ 131
5.8
.....................................
Clock Specifications .................................
Power-Management Module (PMM) ................
Auxiliary Supplies ...................................
Timer_A .............................................
eUSCI ...............................................
LCD Controller ......................................
SD24_B .............................................
ADC10_A ............................................
30
7.4
Documentation Support ............................ 133
35
7.5
Related Links
38
7.6
Community Resources............................. 134
41
7.7
Trademarks ........................................ 134
44
7.8
Electrostatic Discharge Caution
44
7.9
Export Control Notice .............................. 135
7.10
Glossary............................................ 135
Digital I/O Ports
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.16
4
Detailed Description ................................... 63
Revision History ......................................... 5
Device Comparison ..................................... 6
3.1
4
6
Table of Contents
50
52
59
8
......................................
...................
134
135
Mechanical, Packaging, and Orderable
Information ............................................. 136
Copyright © 2011–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F6736 MSP430F6735 MSP430F6734 MSP430F6733 MSP430F6731 MSP430F6730
MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.ti.com
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from February 28, 2013 to September 28, 2018
•
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•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
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•
•
Page
Document format and organization changes throughout, including addition of section numbering ....................... 1
Added links to development tool and design center in , Features ............................................................. 1
Added Device Information table .................................................................................................... 2
Corrected the names of the AUXVCC1, AUXVCC2, and AUXVCC3 pins in Section 1.4, Functional Block Diagrams . 3
Added Section 3 and moved Table 3-1 to it ....................................................................................... 6
Added Section 3.1, Related Products ............................................................................................. 7
Added note to RST/NMI/SBWTDIO pin in Table 4-3, Terminal Functions, PZ Package .................................. 17
Added note to RST/NMI/SBWTDIO pin in Table 4-4, Terminal Functions, PN Package .................................. 22
Added typical conditions statements at the beginning of Section 5, Specifications ........................................ 24
Moved all electrical specifications to Section 5, Specifications ............................................................... 24
Added SD24_B input pins and AUXVCCx pins to exception list on "Voltage applied to pins" parameter, and
added SD24_B input pin limits in "Diode current at pins" parameter in Section 5.1, Absolute Maximum Ratings ..... 24
Added Section 5.2, ESD Ratings.................................................................................................. 24
Added note on CVCORE in Section 5.3, Recommended Operating Conditions ............................................... 24
Added Section 5.7, Thermal Resistance Characteristics ...................................................................... 29
Added note to RPull in Table 5-1, Schmitt-Trigger Inputs – General-Purpose I/O ........................................... 30
Changed TYP value of CL,eff with Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to 1 pF in Table 5-7,
Crystal Oscillator, XT1, Low-Frequency Mode .................................................................................. 35
Corrected the formula in note (1) [added "/ (85ºC – (–40ºC)"] in Table 5-8, Internal Very-Low-Power LowFrequency Oscillator (VLO) ........................................................................................................ 36
Corrected the formula in note (1) [added "/ (85ºC – (–40ºC)"] in Table 5-9, Internal Reference, Low-Frequency
Oscillator (REFO) ................................................................................................................... 36
Changed the MIN value of the V(DVCC_BOR_hys) parameter from 60 mV to 50 mV in Table 5-11, PMM, Brownout
Reset (BOR) ........................................................................................................................ 38
Updated notes (1) and (2) and added note (3) in Table 5-17, Wake-up Times From Low-Power Modes and
Reset ................................................................................................................................. 40
Corrected the names of the AUXVCC1, AUXVCC2, and AUXVCC3 pins in Auxiliary Supplies section ................ 41
Corrected the name of the AUXCHCx bit in the Test Conditions of Table 5-25, Auxiliary Supplies, Charge
Limiting Resistor ..................................................................................................................... 43
Replaced fFrame parameter with fLCD, fFRAME,4mux, and fFRAME,8mux parameters in Table 5-33, LCD_C
Recommended Operating Conditions ............................................................................................ 50
Removed ADC10DIV from the formula for the TYP value in the second row of the tCONVERT parameter in Table 544, 10-Bit ADC, Timing Parameters, because ADC10CLK is after division ................................................. 59
Updated Test Conditions for all parameters in Table 5-45, 10-Bit ADC, Linearity Parameters: Changed from
"CVREF+ = 20 pF" to "CVeREF+ = 20 pF"; Changed from "(VeREF+ – VeREF–)min ≤ (VeREF+ – VeREF–)" to
"1.4 V ≤ (VeREF+ – VeREF–)"; Added "CVeREF+ = 20 pF" to EI Test Conditions ................................................. 60
Added "ADC10SREFx = 11b" to Test Conditions for EG and ET in Table 5-45 ............................................. 60
Throughout document, changed all instances of "bootstrap loader" to "bootloader" ....................................... 69
Corrected spelling of NMIIFG in Table 6-11, System Module Interrupt Vector Registers ................................. 75
Removed mention of real-time clock mode (also called counter mode) in Section 6.11.21, Real-Time Clock
(RTC_C) (feature is not supported in this device) .............................................................................. 80
Removed SD24BTRGCTL, SD24BTRGOSR, and SD24BTRGPRE registers (not supported) in Table 6-55,
SD24_B Registers................................................................................................................... 93
Added Section 7, Device and Documentation Support, and moved Device and Development Tool Nomenclature
and Trademarks sections to it .................................................................................................... 129
Replaced former section Development Tools Support with Section 7.3, Tools and Software .......................... 131
Added Section 8, Mechanical, Packaging, and Orderable Information ..................................................... 136
Revision History
Submit Documentation Feedback
Product Folder Links: MSP430F6736 MSP430F6735 MSP430F6734 MSP430F6733 MSP430F6731 MSP430F6730
MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
Copyright © 2011–2018, Texas Instruments Incorporated
5
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
www.ti.com
3 Device Comparison
Table 3-1 summarizes the available family members.
Table 3-1. Family Members (1) (2)
DEVICE
FLASH
(KB)
SRAM
(KB)
SD24_B
CONVERTERS
ADC10_A
CHANNELS
Timer_A (3)
eUSCI_A:
UART, IrDA,
SPI
eUSCI_B:
SPI, I2C
I/Os
PACKAGE
MSP430F6736IPZ
128
8
3
6 ext, 2 int
3, 2, 2, 2
3
1
72
100 PZ
MSP430F6735IPZ
128
4
3
6 ext, 2 int
3, 2, 2, 2
3
1
72
100 PZ
MSP430F6734IPZ
96
4
3
6 ext, 2 int
3, 2, 2, 2
3
1
72
100 PZ
MSP430F6733IPZ
64
4
3
6 ext, 2 int
3, 2, 2, 2
3
1
72
100 PZ
MSP430F6731IPZ
32
2
3
6 ext, 2 int
3, 2, 2, 2
3
1
72
100 PZ
MSP430F6730IPZ
16
1
3
6 ext, 2 int
3, 2, 2, 2
3
1
72
100 PZ
MSP430F6726IPZ
128
8
2
6 ext, 2 int
3, 2, 2, 2
3
1
72
100 PZ
MSP430F6725IPZ
128
4
2
6 ext, 2 int
3, 2, 2, 2
3
1
72
100 PZ
MSP430F6724IPZ
96
4
2
6 ext, 2 int
3, 2, 2, 2
3
1
72
100 PZ
MSP430F6723IPZ
64
4
2
6 ext, 2 int
3, 2, 2, 2
3
1
72
100 PZ
MSP430F6721IPZ
32
2
2
6 ext, 2 int
3, 2, 2, 2
3
1
72
100 PZ
MSP430F6720IPZ
16
1
2
6 ext, 2 int
3, 2, 2, 2
3
1
72
100 PZ
MSP430F6736IPN
128
8
3
3 ext, 2 int
3, 2, 2, 2
3
1
52
80 PN
MSP430F6735IPN
128
4
3
3 ext, 2 int
3, 2, 2, 2
3
1
52
80 PN
MSP430F6734IPN
96
4
3
3 ext, 2 int
3, 2, 2, 2
3
1
52
80 PN
MSP430F6733IPN
64
4
3
3 ext, 2 int
3, 2, 2, 2
3
1
52
80 PN
MSP430F6731IPN
32
2
3
3 ext, 2 int
3, 2, 2, 2
3
1
52
80 PN
MSP430F6730IPN
16
1
3
3 ext, 2 int
3, 2, 2, 2
3
1
52
80 PN
MSP430F6726IPN
128
8
2
3 ext, 2 int
3, 2, 2, 2
3
1
52
80 PN
MSP430F6725IPN
128
4
2
3 ext, 2 int
3, 2, 2, 2
3
1
52
80 PN
MSP430F6724IPN
96
4
2
3 ext, 2 int
3, 2, 2, 2
3
1
52
80 PN
MSP430F6723IPN
64
4
2
3 ext, 2 int
3, 2, 2, 2
3
1
52
80 PN
MSP430F6721IPN
32
2
2
3 ext, 2 int
3, 2, 2, 2
3
1
52
80 PN
MSP430F6720IPN
16
1
2
3 ext, 2 int
3, 2, 2, 2
3
1
52
80 PN
(1)
(2)
(3)
6
For the most current package and ordering information, see the Package Option Addendum in Section 8, or see the TI website at
www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
Device Comparison
Copyright © 2011–2018, Texas Instruments Incorporated
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Product Folder Links: MSP430F6736 MSP430F6735 MSP430F6734 MSP430F6733 MSP430F6731 MSP430F6730
MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.ti.com
3.1
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Related Products
For information about other devices in this family of products or related products, see the following links.
Products for TI Microcontrollers TI's low-power and high-performance MCUs, with wired and wireless
connectivity options, are optimized for a broad range of applications.
Products for MSP430 Ultra-Low-Power Microcontrollers One platform. One ecosystem. Endless
possibilities. Enabling the connected world with innovations in ultra-low-power
microcontrollers with advanced peripherals for precise sensing and measurement.
Companion Products for MSP430F6736 Review products that are frequently purchased or used with
this product.
Reference Designs for MSP430F6736 The TI Designs Reference Design Library is a robust reference
design library that spans analog, embedded processor, and connectivity. Created by TI
experts to help you jump start your system design, all TI Designs include schematic or block
diagrams, BOMs, and design files to speed your time to market. Search and download
designs at ti.com/tidesigns.
Device Comparison
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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4 Terminal Configuration and Functions
4.1
Pin Diagrams
P6.1/S18
P6.2/S17
P6.3/S16
P6.4/S15
P6.5/S14
P6.6/S13
P6.7/S12
P7.0/S11
P7.1/S10
P7.2/S9
P7.3/S8
P7.4/S7
P7.5/S6
P7.6/S5
P7.7/S4
P8.0/S3
P8.1/S2
P8.2/S1
P8.3/S0
TEST/SBWTCK
PJ.0/SMCLK/TDO
PJ.1/MCLK/TDI/TCLK
PJ.2/ADC10CLK/TMS
PJ.3/ACLK/TCK
RST/NMI/SBWTDIO
Figure 4-1 shows the pinout for the 100-pin PZ package. See Table 4-1 for differences between the
MSP430F673x and MSP430F672x devices in this package.
SD0P0
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
DVSS
SD0N0
2
74
DVSYS
SD1P0
3
73
P6.0/S19
SD1N0
4
72
P5.7/S20
SD2P0
5
71
P5.6/S21
SD2N0
6
70
P5.5/S22
VREF
7
69
P5.4/S23
AVSS
8
68
P5.3/S24
AVCC
9
67
P5.2/S25
VASYS
10
66
P5.1/S26
P9.1/A5
11
65
P5.0/S27
P9.2/A4
12
64
P4.7/S28
P9.3/A3
13
63
P4.6/S29
P1.0/PM_TA0.0/VeREF-/A2
14
62
P4.5/S30
P1.1/PM_TA0.1/VeREF+/A1
15
61
P4.4/S31
P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0
16
60
P4.3/S32
P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03
17
59
P4.2/S33
AUXVCC2
18
58
P4.1/S34
AUXVCC1
19
57
P4.0/S35
VDSYS
20
56
P3.7/PM_SD2DIO/S36
DVCC
21
55
P3.6/PM_SD1DIO/S37
DVSS
22
54
P3.5/PM_SD0DIO/S38
VCORE
23
53
P3.4/PM_SDCLK/S39
XIN
24
52
P3.3/PM_TA0.2
P3.2/PM_TACLK/PM_RTCCLK
P3.1/PM_TA2.1/BSL_RX
P3.0/PM_TA2.0/BSL_TX
P2.7/PM_TA1.1
P2.6/PM_TA1.0
P2.5/PM_UCA2CLK
P2.4/PM_UCA1CLK
P2.3/PM_UCA2TXD/PM_UCA2SIMO
P2.2/PM_UCA2RXD/PM_UCA2SOMI
P9.0/TACLK/RTCCLK
P8.7/TA2.1
P8.6/TA2.0
P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7
P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6
P1.7/PM_UCB0CLK/COM5
P1.6/PM_UCA0CLK/COM4
COM3
COM2
COM1
COM0
P8.5/TA1.1
P8.4/TA1.0
LCDCAP/R33
P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23
AUXVCC3
25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13
XOUT
NOTE: The secondary digital functions on Ports P1, P2, and P3 are fully mappable. This pinout shows the default mapping.
See Table 6-9 for details.
NOTE: The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
CAUTION: The LCDCAP/R33 pin must be connected to DVSS if not used.
Figure 4-1. 100-Pin PZ Package (Top View)
8
Terminal Configuration and Functions
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 4-1. Pinout Differences Between MSP430F673xIPZ and MSP430F672xIPZ (1)
PIN NUMBER
(1)
PIN NAME
MSP430F673xIPZ
MSP430F672xIPZ
1
SD0P0
SD0P0
2
SD0N0
SD0N0
3
SD1P0
SD1P0
4
SD1N0
SD1N0
5
SD2P0
NC
6
SD2N0
NC
7
VREF
VREF
53
P3.4/PM_SDCLK/S39
P3.4/PM_SDCLK/S39
54
P3.5/PM_SD0DIO/S38
P3.5/PM_SD0DIO/S38
55
P3.6/PM_SD1DIO/S37
P3.6/PM_SD1DIO/S37
56
P3.7/PM_SD2DIO/S36
P3.7/PM_NONE/S36
Signal names that differ between devices are indicated by italic typeface.
Terminal Configuration and Functions
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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P5.2/S13
P5.3/S12
P5.4/S11
P5.5/S10
P5.6/S9
P5.7/S8
P6.0/S7
P6.1/S6
P6.2/S5
P6.3/S4
P6.4/S3
P6.5/S2
P6.6/S1
P6.7/S0
TEST/SBWTCK
PJ.0/SMCLK/TDO
PJ.1/MCLK/TDI/TCLK
PJ.2/ADC10CLK/TMS
PJ.3/ACLK/TCK
RST/NMI/SBWTDIO
Figure 4-2 shows the pinout for the 80-pin PN package. See Table 4-2 for differences between the
MSP430F673x and MSP430F672x devices in this package.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
54
P4.5/S18
AVSS
8
53
P4.4/S19
AVCC
9
52
P4.3/S20
VASYS
10
51
P4.2/S21
P1.0/PM_TA0.0/VeREF-/A2
11
50
P4.1/S22
P1.1/PM_TA0.1/VeREF+/A1
12
49
P4.0/S23
P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0
13
48
P3.7/PM_SD2DIO/S24
P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03
14
47
P3.6/PM_SD1DIO/S25
AUXVCC2
15
46
P3.5/PM_SD0DIO/S26
AUXVCC1
16
45
P3.4/PM_SDCLK/S27
VDSYS
17
44
P3.3/PM_TA0.2/S28
DVCC
18
43
P3.2/PM_TACLK/PM_RTCCLK/S29
DVSS
19
42
P3.1/PM_TA2.1/S30/BSL_RX
41
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P3.0/PM_TA2.0/S31/BSL_TX
XIN
VCORE
P2.7/PM_TA1.1/S32
7
P2.6/PM_TA1.0/S33
P4.6/S17
VREF
P2.5/PM_UCA2CLK/S34
55
P2.4/PM_UCA1CLK/S35
6
P2.3/PM_UCA2TXD/PM_UCA2SIMO/S36
P4.7/S16
SD2N0
P2.2/PM_UCA2RXD/PM_UCA2SOMI/S37
56
P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7/S38
5
P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6/S39
P5.0/S15
SD2P0
P1.7/PM_UCB0CLK/COM5
57
P1.6/PM_UCA0CLK/COM4
4
COM3
P5.1/S14
SD1N0
COM2
58
COM1
3
COM0
DVSYS
SD1P0
LCDCAP/R33
59
P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23
DVSS
2
P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13
60
SD0N0
AUXVCC3
1
XOUT
SD0P0
NOTE: The secondary digital functions on Ports P1, P2, and P3 are fully mappable. This pinout shows the default mapping.
See Table 6-9 for details.
NOTE: The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
CAUTION: The LCDCAP/R33 pin must be connected to DVSS if not used.
Figure 4-2. 80-Pin PN Package (Top View)
10
Terminal Configuration and Functions
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 4-2. Pinout Differences Between MSP430F673xIPN and
MSP430F672xIPN (1)
PIN NUMBER
(1)
PIN NAME
MSP430F673xIPN
MSP430F672xIPN
1
SD0P0
SD0P0
2
SD0N0
SD0N0
3
SD1P0
SD1P0
4
SD1N0
SD1N0
5
SD2P0
NC
6
SD2N0
NC
7
VREF
VREF
45
P3.4/PM_SDCLK/S27
P3.4/PM_SDCLK/S27
46
P3.5/PM_SD0DIO/S26
P3.5/PM_SD0DIO/S26
47
P3.6/PM_SD1DIO/S25
P3.6/PM_SD1DIO/S25
48
P3.7/PM_SD2DIO/S24
P3.7/PM_NONE/S24
Signal names that differ between devices are indicated by italic typeface.
Terminal Configuration and Functions
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Copyright © 2011–2018, Texas Instruments Incorporated
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
4.2
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Signal Descriptions
Table 4-3 describes the signals for all device variants in the PZ package. See Table 4-4 for signal
descriptions in the PN package.
Table 4-3. Terminal Functions, PZ Package
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
PZ
SD0P0
1
I
SD24_B positive analog input for converter 0 (2)
SD0N0
2
I
SD24_B negative analog input for converter 0 (2)
SD1P0
3
I
SD24_B positive analog input for converter 1 (2)
SD1N0
4
I
SD24_B negative analog input for converter 1 (2)
SD2P0
5
I
SD24_B positive analog input for converter 2 (2) (not available on F672x devices)
SD2N0
6
I
SD24_B negative analog input for converter 2 (2) (not available on F672x devices)
VREF
7
I
SD24_B external reference voltage
AVSS
8
Analog ground supply
AVCC
9
Analog power supply
VASYS
10
Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect
recommended capacitor value of CVSYS (see Table 5-18).
P9.1/A5
11
I/O
General-purpose digital I/O
Analog input A5 for 10-bit ADC
P9.2/A4
12
I/O
General-purpose digital I/O
Analog input A4 for 10-bit ADC
P9.3/A3
13
I/O
General-purpose digital I/O
Analog input A3 for 10-bit ADC
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output
P1.0/PM_TA0.0/VeREF-/A2
14
I/O
Negative terminal for the ADC reference voltage for an external applied reference
voltage
Analog input A2 for 10-bit ADC
General-purpose digital I/O with port interrupt and mappable secondary function
P1.1/PM_TA0.1/VeREF+/A1
15
I/O
Default mapping: Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output
Positive terminal for the ADC reference voltage for an external applied reference voltage
Analog input A1 for 10-bit ADC
General-purpose digital I/O with port interrupt and mappable secondary function
P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A0
16
I/O
Default mapping: eUSCI_A0 UART receive data; eUSCI_A0 SPI slave out/master in
Analog input A0 for 10-bit ADC
General-purpose digital I/O with port interrupt and mappable secondary function
P1.3/PM_UCA0TXD/
PM_UCA0SIMO/R03
17
AUXVCC2
18
Auxiliary power supply AUXVCC2
AUXVCC1
19
Auxiliary power supply AUXVCC1
I/O
Default mapping: eUSCI_A0 UART transmit data; eUSCI_A0 SPI slave in/master out
Input/output port of lowest analog LCD voltage (V5)
(1)
(2)
12
I = input, O = output
Short unused analog input pairs and connect them to analog ground.
Terminal Configuration and Functions
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 4-3. Terminal Functions, PZ Package (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
PZ
20
Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect
recommended capacitor value of CVSYS (see Table 5-18).
DVCC
21
Digital power supply
DVSS
22
Digital ground supply
VCORE (4)
23
XIN
24
I
Input terminal for crystal oscillator
XOUT
25
O
Output terminal for crystal oscillator
AUXVCC3
26
VDSYS
(3)
Regulated core power supply (internal use only, no external current loading)
Auxiliary power supply AUXVCC3 for back up subsystem
General-purpose digital I/O with port interrupt and mappable secondary function
P1.4/PM_UCA1RXD/
PM_UCA1SOMI/LCDREF/R13
27
I/O
Default mapping: eUSCI_A1 UART receive data; eUSCI_A1 SPI slave out/master in
External reference voltage input for regulated LCD voltage
Input/output port of third most positive analog LCD voltage (V3 or V4)
General-purpose digital I/O with port interrupt and mappable secondary function
P1.5/PM_UCA1TXD/
PM_UCA1SIMO/R23
28
I/O
Default mapping: eUSCI_A1 UART transmit data; eUSCI_A1 SPI slave in/master out
Input/output port of second most positive analog LCD voltage (V2)
LCD capacitor connection
LCDCAP/R33
29
I/O
Input/output port of most positive analog LCD voltage (V1)
CAUTION: This pin must be connected to DVSS if not used.
P8.4/TA1.0
30
I/O
General-purpose digital I/O
Timer TA1 CCR0 capture: CCI0A input, compare: Out0 output
General-purpose digital I/O
P8.5/TA1.1
31
I/O
COM0
32
O
LCD common output COM0 for LCD backplane
COM1
33
O
LCD common output COM1 for LCD backplane
COM2
34
O
LCD common output COM2 for LCD backplane
COM3
35
O
LCD common output COM3 for LCD backplane
P1.6/PM_UCA0CLK/COM4
36
I/O
Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A0 clock input/output
LCD common output COM4 for LCD backplane
General-purpose digital I/O with port interrupt and mappable secondary function
P1.7/PM_UCB0CLK/COM5
37
I/O
Default mapping: eUSCI_B0 clock input/output
LCD common output COM5 for LCD backplane
General-purpose digital I/O with port interrupt and mappable secondary function
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6
38
I/O
Default mapping: eUSCI_B0 SPI slave out/master in; eUSCI_B0 I2C clock
LCD common output COM6 for LCD backplane
(3)
(4)
The pins VDSYS and DVSYS must be connected externally on the board for proper device operation.
VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE.
Terminal Configuration and Functions
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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Table 4-3. Terminal Functions, PZ Package (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
PZ
General-purpose digital I/O with port interrupt and mappable secondary function
P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7
39
I/O
Default mapping: eUSCI_B0 SPI slave in/master out; eUSCI_B0 I2C data
LCD common output COM7 for LCD backplane
P8.6/TA2.0
40
I/O
General-purpose digital I/O
Timer TA2 CCR0 capture: CCI0A input, compare: Out0 output
P8.7/TA2.1
41
I/O
General-purpose digital I/O
Timer TA2 CCR1 capture: CCI1A input, compare: Out1 output
General-purpose digital I/O
P9.0/TACLK/RTCCLK
42
I/O
Timer clock input TACLK for TA0, TA1, TA2, TA3
RTCCLK clock output
P2.2/PM_UCA2RXD/
PM_UCA2SOMI
43
P2.3/PM_UCA2TXD/
PM_UCA2SIMO
44
P2.4/PM_UCA1CLK
45
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A2 UART receive data; eUSCI_A2 SPI slave out/master in
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A2 UART transmit data; eUSCI_A2 SPI slave in/master out
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A1 clock input/output
P2.5/PM_UCA2CLK
46
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A2 clock input/output
P2.6/PM_TA1.0
47
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Timer TA1 capture CCR0: CCI0A input, compare: Out0 output
P2.7/PM_TA1.1
48
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Timer TA1 capture CCR1: CCI1A input, compare: Out1 output
General-purpose digital I/O with mappable secondary function
P3.0/PM_TA2.0/BSL_TX
49
I/O
Default mapping: Timer TA2 capture CCR0: CCI0A input, compare: Out0 output
Bootloader: Data transmit
General-purpose digital I/O with mappable secondary function
P3.1/PM_TA2.1/BSL_RX
50
I/O
Default mapping: Timer TA2 capture CCR1: CCI1A input, compare: Out1 output
Bootloader: Data receive
General-purpose digital I/O with mappable secondary function
P3.2/PM_TACLK/PM_RTCCLK
51
I/O
P3.3/PM_TA0.2
52
I/O
Default mapping: Timer clock input TACLK for TA0, TA1, TA2, TA3; RTCCLK clock
output
General-purpose digital I/O with mappable secondary function
Default mapping: Timer TA0 capture CCR2: CCI2A input, compare: Out2 output
General-purpose digital I/O with mappable secondary function
P3.4/PM_SDCLK/S39
53
I/O
Default mapping: SD24_B bitstream clock input/output
LCD segment output S39
14
Terminal Configuration and Functions
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 4-3. Terminal Functions, PZ Package (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
PZ
General-purpose digital I/O with mappable secondary function
P3.5/PM_SD0DIO/S38
54
I/O
Default mapping: SD24_B converter-0 bitstream data input/output
LCD segment output S38
General-purpose digital I/O with mappable secondary function
P3.6/PM_SD1DIO/S37
55
I/O
Default mapping: SD24_B converter-1 bitstream data input/output
LCD segment output S37
General-purpose digital I/O with mappable secondary function
P3.7/PM_SD2DIO/S36
56
I/O
Default mapping: SD24_B converter-2 bitstream data input/output (not available on
F672x devices)
LCD segment output S36
P4.0/S35
57
I/O
General-purpose digital I/O
LCD segment output S35
P4.1/S34
58
I/O
General-purpose digital I/O
LCD segment output S34
P4.2/S33
59
I/O
General-purpose digital I/O
LCD segment output S33
P4.3/S32
60
I/O
General-purpose digital I/O
LCD segment output S32
P4.4/S31
61
I/O
General-purpose digital I/O
LCD segment output S31
P4.5/S30
62
I/O
General-purpose digital I/O
LCD segment output S30
P4.6/S29
63
I/O
General-purpose digital I/O
LCD segment output S29
P4.7/S28
64
I/O
General-purpose digital I/O
LCD segment output S28
P5.0/S27
65
I/O
General-purpose digital I/O
LCD segment output S27
P5.1/S26
66
I/O
General-purpose digital I/O
LCD segment output S26
P5.2/S25
67
I/O
General-purpose digital I/O
LCD segment output S25
P5.3/S24
68
I/O
General-purpose digital I/O
LCD segment output S24
P5.4/S23
69
I/O
General-purpose digital I/O
LCD segment output S23
Terminal Configuration and Functions
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Copyright © 2011–2018, Texas Instruments Incorporated
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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Table 4-3. Terminal Functions, PZ Package (continued)
TERMINAL
NAME
P5.5/S22
NO.
I/O (1)
DESCRIPTION
PZ
70
I/O
General-purpose digital I/O
LCD segment output S22
P5.6/S21
71
I/O
General-purpose digital I/O
LCD segment output S21
P5.7/S20
72
I/O
General-purpose digital I/O
LCD segment output S20
I/O
General-purpose digital I/O
P6.0/S19
73
DVSYS (3)
74
Digital power supply for I/Os
DVSS
75
Digital ground supply
P6.1/S18
76
LCD segment output S19
I/O
General-purpose digital I/O
LCD segment output S18
P6.2/S17
77
I/O
General-purpose digital I/O
LCD segment output S17
P6.3/S16
78
I/O
General-purpose digital I/O
LCD segment output S16
P6.4/S15
79
I/O
General-purpose digital I/O
LCD segment output S15
P6.5/S14
80
I/O
General-purpose digital I/O
LCD segment output S14
P6.6/S13
81
I/O
General-purpose digital I/O
LCD segment output S13
P6.7/S12
82
I/O
General-purpose digital I/O
LCD segment output S12
P7.0/S11
83
I/O
General-purpose digital I/O
LCD segment output S11
P7.1/S10
84
I/O
General-purpose digital I/O
LCD segment output S10
P7.2/S9
85
I/O
General-purpose digital I/O
LCD segment output S9
P7.3/S8
86
I/O
General-purpose digital I/O
LCD segment output S8
P7.4/S7
87
I/O
General-purpose digital I/O
LCD segment output S7
16
Terminal Configuration and Functions
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 4-3. Terminal Functions, PZ Package (continued)
TERMINAL
NAME
P7.5/S6
NO.
I/O (1)
DESCRIPTION
PZ
88
I/O
General-purpose digital I/O
LCD segment output S6
P7.6/S5
89
I/O
General-purpose digital I/O
LCD segment output S5
P7.7/S4
90
I/O
General-purpose digital I/O
LCD segment output S4
P8.0/S3
91
I/O
General-purpose digital I/O
LCD segment output S3
P8.1/S2
92
I/O
General-purpose digital I/O
LCD segment output S2
P8.2/S1
93
I/O
General-purpose digital I/O
LCD segment output S1
P8.3/S0
94
I/O
General-purpose digital I/O
LCD segment output S0
TEST/SBWTCK
95
I
Test mode pin – select digital I/O on JTAG pins
Spy-Bi-Wire input clock
General-purpose digital I/O
PJ.0/SMCLK/TDO
96
I/O
SMCLK clock output
Test data output
General-purpose digital I/O
PJ.1/MCLK/TDI/TCLK
97
I/O
MCLK clock output
Test data input or Test clock input
General-purpose digital I/O
PJ.2/ADC10CLK/TMS
98
I/O
ADC10_A clock output
Test mode select
General-purpose digital I/O
PJ.3/ACLK/TCK
99
I/O
ACLK clock output
Test clock
Reset input active low (5)
RST/NMI/SBWTDIO
100
I/O
Nonmaskable interrupt input
Spy-Bi-Wire data input/output
(5)
When this pin is configured as reset, the internal pullup resistor is enabled by default.
Terminal Configuration and Functions
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Copyright © 2011–2018, Texas Instruments Incorporated
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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Table 4-4 describes the signals for all device variants in the PN package. See Table 4-3 for signal
descriptions in the PZ package.
Table 4-4. Terminal Functions, PN Package
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
PN
SD0P0
1
I
SD24_B positive analog input for converter 0 (2)
SD0N0
2
I
SD24_B negative analog input for converter 0 (2)
SD1P0
3
I
SD24_B positive analog input for converter 1 (2)
SD1N0
4
I
SD24_B negative analog input for converter 1 (2)
SD2P0
5
I
SD24_B positive analog input for converter 2 (2) (not available on F672x devices)
SD2N0
6
I
SD24_B negative analog input for converter 2 (2) (not available on F672x devices)
VREF
7
I
SD24_B external reference voltage
AVSS
8
Analog ground supply
AVCC
9
Analog power supply
VASYS
10
Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect
recommended capacitor value of CVSYS (see Table 5-18).
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output
P1.0/PM_TA0.0/VeREF-/A2
11
I/O
Negative terminal for the ADC reference voltage for an external applied reference
voltage
Analog input A2 for 10-bit ADC
General-purpose digital I/O with port interrupt and mappable secondary function
P1.1/PM_TA0.1/VeREF+/A1
12
I/O
Default mapping: Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output
Positive terminal for the ADC reference voltage for an external applied reference voltage
Analog input A1 for 10-bit ADC
General-purpose digital I/O with port interrupt and mappable secondary function
P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A0
13
I/O
Default mapping: eUSCI_A0 UART receive data; eUSCI_A0 SPI slave out/master in
Analog input A0 for 10-bit ADC
General-purpose digital I/O with port interrupt and mappable secondary function
P1.3/PM_UCA0TXD/
PM_UCA0SIMO/R03
14
AUXVCC2
15
Auxiliary power supply AUXVCC2
AUXVCC1
16
Auxiliary power supply AUXVCC1
VDSYS (3)
17
Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect
recommended capacitor value of CVSYS (see Table 5-18).
DVCC
18
Digital power supply
DVSS
19
Digital ground supply
I/O
Default mapping: eUSCI_A0 UART transmit data; eUSCI_A0 SPI slave in/master out
Input/output port of lowest analog LCD voltage (V5)
VCORE
(4)
20
Regulated core power supply (internal use only, no external current loading)
XIN
21
I
Input terminal for crystal oscillator
XOUT
22
O
Output terminal for crystal oscillator
AUXVCC3
23
(1)
(2)
(3)
(4)
18
Auxiliary power supply AUXVCC3 for back up subsystem
I = input, O = output
Short unused analog input pairs and connect them to analog ground.
The pins VDSYS and DVSYS must be connected externally on the board for proper device operation.
VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE.
Terminal Configuration and Functions
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 4-4. Terminal Functions, PN Package (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
PN
General-purpose digital I/O with port interrupt and mappable secondary function
P1.4/PM_UCA1RXD/
PM_UCA1SOMI/LCDREF/R13
24
I/O
Default mapping: eUSCI_A1 UART receive data; eUSCI_A1 SPI slave out/master in
External reference voltage input for regulated LCD voltage
Input/output port of third most positive analog LCD voltage (V3 or V4)
General-purpose digital I/O with port interrupt and mappable secondary function
P1.5/PM_UCA1TXD/
PM_UCA1SIMO/R23
25
I/O
Default mapping: eUSCI_A1 UART transmit data; eUSCI_A1 SPI slave in/master out
Input/output port of second most positive analog LCD voltage (V2)
LCD capacitor connection
LCDCAP/R33
26
I/O
Input/output port of most positive analog LCD voltage (V1)
CAUTION: This pin must be connected to DVSS if not used.
COM0
27
O
LCD common output COM0 for LCD backplane
COM1
28
O
LCD common output COM1 for LCD backplane
COM2
29
O
LCD common output COM2 for LCD backplane
COM3
30
O
LCD common output COM3 for LCD backplane
P1.6/PM_UCA0CLK/COM4
31
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A0 clock input/output
LCD common output COM4 for LCD backplane
General-purpose digital I/O with port interrupt and mappable secondary function
P1.7/PM_UCB0CLK/COM5
32
I/O
Default mapping: eUSCI_B0 clock input/output
LCD common output COM5 for LCD backplane
General-purpose digital I/O with port interrupt and mappable secondary function
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6/S39
33
I/O
Default mapping: eUSCI_B0 SPI slave out/master in; eUSCI_B0 I2C clock
LCD common output COM6 for LCD backplane
LCD segment output S39
General-purpose digital I/O with port interrupt and mappable secondary function
P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7/S38
34
I/O
Default mapping: eUSCI_B0 SPI slave in/master out; eUSCI_B0 I2C data
LCD common output COM7 for LCD backplane
LCD segment output S38
General-purpose digital I/O with port interrupt and mappable secondary function
P2.2/PM_UCA2RXD/
PM_UCA2SOMI/S37
35
I/O
Default mapping: eUSCI_A2 UART receive data; eUSCI_A2 SPI slave out/master in
LCD segment output S37
General-purpose digital I/O with port interrupt and mappable secondary function
P2.3/PM_UCA2TXD/
PM_UCA2SIMO/S36
36
I/O
Default mapping: eUSCI_A2 UART transmit data; eUSCI_A2 SPI slave in/master out
LCD segment output S36
General-purpose digital I/O with port interrupt and mappable secondary function
P2.4/PM_UCA1CLK/S35
37
I/O
Default mapping: eUSCI_A1 clock input/output
LCD segment output S35
Terminal Configuration and Functions
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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Table 4-4. Terminal Functions, PN Package (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
PN
General-purpose digital I/O with port interrupt and mappable secondary function
P2.5/PM_UCA2CLK/S34
38
I/O
Default mapping: eUSCI_A2 clock input/output
LCD segment output S34
General-purpose digital I/O with port interrupt and mappable secondary function
P2.6/PM_TA1.0/S33
39
I/O
Default mapping: Timer TA1 capture CCR0: CCI0A input, compare: Out0 output
LCD segment output S33
General-purpose digital I/O with port interrupt and mappable secondary function
P2.7/PM_TA1.1/S32
40
I/O
Default mapping: Timer TA1 capture CCR1: CCI1A input, compare: Out1 output
LCD segment output S32
General-purpose digital I/O with mappable secondary function
P3.0/PM_TA2.0/S31/BSL_TX
41
I/O
Default mapping: Timer TA2 capture CCR0: CCI0A input, compare: Out0 output
LCD segment output S31
Bootloader: Data transmit
General-purpose digital I/O with mappable secondary function
P3.1/PM_TA2.1/S30/BSL_RX
42
I/O
Default mapping: Timer TA2 capture CCR1: CCI1A input, compare: Out1 output
LCD segment output S30
Bootloader: Data receive
General-purpose digital I/O with mappable secondary function
P3.2/PM_TACLK/PM_RTCCLK/
S29
43
I/O
Default mapping: Timer clock input TACLK for TA0, TA1, TA2, TA3; RTCCLK clock
output
LCD segment output S29
General-purpose digital I/O with mappable secondary function
P3.3/PM_TA0.2/S28
44
I/O
Default mapping: Timer TA0 capture CCR2: CCI2A input, compare: Out2 output
LCD segment output S28
General-purpose digital I/O with mappable secondary function
P3.4/PM_SDCLK/S27
45
I/O
Default mapping: SD24_B bitstream clock input/output
LCD segment output S27
General-purpose digital I/O with mappable secondary function
P3.5/PM_SD0DIO/S26
46
I/O
Default mapping: SD24_B converter-0 bitstream data input/output
LCD segment output S26
General-purpose digital I/O with mappable secondary function
P3.6/PM_SD1DIO/S25
47
I/O
Default mapping: SD24_B converter-1 bitstream data input/output
LCD segment output S25
General-purpose digital I/O with mappable secondary function
P3.7/PM_SD2DIO/S24
48
I/O
Default mapping: SD24_B converter-2 bitstream data input/output (not available on
F672x devices)
LCD segment output S24
20
Terminal Configuration and Functions
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 4-4. Terminal Functions, PN Package (continued)
TERMINAL
NAME
P4.0/S23
NO.
I/O (1)
DESCRIPTION
PN
49
I/O
General-purpose digital I/O
LCD segment output S23
P4.1/S22
50
I/O
General-purpose digital I/O
LCD segment output S22
P4.2/S21
51
I/O
General-purpose digital I/O
LCD segment output S21
P4.3/S20
52
I/O
General-purpose digital I/O
LCD segment output S20
P4.4/S19
53
I/O
General-purpose digital I/O
LCD segment output S19
P4.5/S18
54
I/O
General-purpose digital I/O
LCD segment output S18
P4.6/S17
55
I/O
General-purpose digital I/O
LCD segment output S17
P4.7/S16
56
I/O
General-purpose digital I/O
LCD segment output S16
P5.0/S15
57
I/O
General-purpose digital I/O
LCD segment output S15
P5.1/S14
58
I/O
General-purpose digital I/O
LCD segment output S14
DVSYS
(3)
59
Digital power supply for I/Os
DVSS
60
Digital ground supply
P5.2/S13
61
I/O
General-purpose digital I/O
LCD segment output S13
P5.3/S12
62
I/O
General-purpose digital I/O
LCD segment output S12
P5.4/S11
63
I/O
General-purpose digital I/O
LCD segment output S11
P5.5/S10
64
I/O
General-purpose digital I/O
LCD segment output S10
P5.6/S9
65
I/O
General-purpose digital I/O
LCD segment output S9
P5.7/S8
66
I/O
General-purpose digital I/O
LCD segment output S8
Terminal Configuration and Functions
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Copyright © 2011–2018, Texas Instruments Incorporated
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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Table 4-4. Terminal Functions, PN Package (continued)
TERMINAL
NAME
P6.0/S7
NO.
I/O (1)
DESCRIPTION
PN
67
I/O
General-purpose digital I/O
LCD segment output S7
P6.1/S6
68
I/O
General-purpose digital I/O
LCD segment output S6
P6.2/S5
69
I/O
General-purpose digital I/O
LCD segment output S5
P6.3/S4
70
I/O
General-purpose digital I/O
LCD segment output S4
P6.4/S3
71
I/O
General-purpose digital I/O
LCD segment output S3
P6.5/S2
72
I/O
General-purpose digital I/O
LCD segment output S2
P6.6/S1
73
I/O
General-purpose digital I/O
LCD segment output S1
P6.7/S0
74
I/O
General-purpose digital I/O
LCD segment output S0
TEST/SBWTCK
75
I
Test mode pin – select digital I/O on JTAG pins
Spy-Bi-Wire input clock
General-purpose digital I/O
PJ.0/SMCLK/TDO
76
I/O
SMCLK clock output
Test data output
General-purpose digital I/O
PJ.1/MCLK/TDI/TCLK
77
I/O
MCLK clock output
Test data input or Test clock input
General-purpose digital I/O
PJ.2/ADC10CLK/TMS
78
I/O
ADC10_A clock output
Test mode select
General-purpose digital I/O
PJ.3/ACLK/TCK
79
I/O
ACLK clock output
Test clock
Reset input active low (5)
RST/NMI/SBWTDIO
80
I/O
Nonmaskable interrupt input
Spy-Bi-Wire data input/output
(5)
22
When this pin is configured as reset, the internal pullup resistor is enabled by default.
Terminal Configuration and Functions
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Terminal Configuration and Functions
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Copyright © 2011–2018, Texas Instruments Incorporated
23
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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5 Specifications
All graphs in this section are for typical conditions, unless otherwise noted.
Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted.
5.1
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Voltage applied at DVCC to DVSS
MIN
MAX
–0.3
4.1
UNIT
V
–0.3
VCC + 0.3
V
(3)
All pins except VCORE , SD24_B input pins (SD0N0, SD0P0,
SD1N0, SD1P0, SD2N0, SD2P0) (4), AUXVCC1, AUXVCC2, and
AUXVCC3 (5)
Voltage applied to pins (2)
All pins except SD24_B input pins (SD0N0, SD0P0, SD1N0,
SD1P0, SD2N0, SD2P0)
Diode current at pins
±2
SD0N0, SD0P0, SD1N0, SD1P0, SD2N0, SD2P0 (6)
Maximum junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
(3)
(4)
(5)
(6)
(7)
mA
2
(7)
–55
95
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS = V(DVSS) = V(AVSS).
VCORE is for internal device use only. Do not apply external DC loading or voltage.
See Table 5-35 for SD24_B specifications.
See Table 5-18 for AUX specifications.
A protection diode is connected to VCC for the SD24_B input pins. No protection diode is connected to VSS.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2
ESD Ratings
VALUE
V(ESD)
(1)
(2)
5.3
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±250
Recommended Operating Conditions
Supply voltage during program execution and flash
programming, V(AVCC) = V(DVCC) = VCC (1) (2)
VCC
VSS
Supply voltage V(AVSS) = V(DVSS) = VSS
TA
Operating free-air temperature
TJ
Operating junction temperature
CVCORE
Recommended capacitor at VCORE
CDVCC/CVCORE
Capacitor ratio of DVCC to VCORE
(2)
(3)
24
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
MIN
(1)
UNIT
NOM
MAX
PMMCOREVx = 0
1.8
3.6
PMMCOREVx = 0, 1
2.0
3.6
PMMCOREVx = 0, 1, 2
2.2
3.6
PMMCOREVx = 0, 1, 2, 3
2.4
3.6
0
UNIT
V
V
–40
85
°C
–40
85
°C
(3)
470
nF
10
TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between V(AVCC) and V(DVCC) can be
tolerated during power up and operation.
The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Table 5-13 threshold parameters for
the exact values and further details.
A capacitor tolerance of ±20% or better is required.
Specifications
Copyright © 2011–2018, Texas Instruments Incorporated
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Recommended Operating Conditions (continued)
MIN
PMMCOREVx = 0,
1.8 V ≤ VCC ≤ 3.6 V
(default condition)
PMMCOREVx = 1,
Processor frequency (maximum MCLK frequency) (4) (5) 2.0 V ≤ VCC ≤ 3.6 V
(see Figure 5-1)
PMMCOREVx = 2,
2.2 V ≤ VCC ≤ 3.6 V
fSYSTEM
PMMCOREVx = 3,
2.4 V ≤ VCC ≤ 3.6 V
NOM
MAX
0
8.0
0
12.0
0
20.0
0
25.0
UNIT
MHz
ILOAD,
DVCCD
Maximum load current that can be drawn from DVCC for core and IO
(ILOAD = ICORE + IIO)
20
mA
ILOAD,
AUX1D
Maximum load current that can be drawn from AUXVCC1 for core and IO
(ILOAD = ICORE + IIO)
20
mA
ILOAD,
AUX2D
Maximum load current that can be drawn from AUXVCC2 for core and IO
(ILOAD = ICORE + IIO)
20
mA
ILOAD,
AVCCA
Maximum load current that can be drawn from AVCC for analog modules
(ILOAD = IModules)
10
mA
ILOAD,
AUX1A
Maximum load current that can be drawn from AUXVCC1 for analog modules
(ILOAD = IModules)
5
mA
ILOAD,
AUX2A
Maximum load current that can be drawn from AUXVCC2 for analog modules
(ILOAD = IModules)
5
mA
(4)
(5)
The MSP430 CPU is clocked directly with MCLK. Both the high and low phases of MCLK must not exceed the pulse duration of the
specified maximum frequency.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
25
System Frequency - MHz
3
20
2
2, 3
1
1, 2
1, 2, 3
0, 1
0, 1, 2
0, 1, 2, 3
12
8
0
0
1.8
2.0
2.2
2.4
3.6
Supply Voltage - V
The numbers within the fields denote the supported PMMCOREVx settings.
Figure 5-1. Maximum System Frequency
Specifications
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Copyright © 2011–2018, Texas Instruments Incorporated
25
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
5.4
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Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted) (1)
(2) (3)
FREQUENCY (fDCO = fMCLK = fSMCLK)
PARAMETER
IAM,
IAM,
(1)
(2)
(3)
(4)
(5)
26
Flash
RAM
(4)
(5)
EXECUTION
MEMORY
Flash
RAM
VCC
3.0 V
3.0 V
PMMCOREVx
1 MHz
8 MHz
12 MHz
20 MHz
TYP
MAX
TYP
MAX
TYP
MAX
0
0.32
0.36
2.10
2.30
1
0.36
2.39
2
0.39
3.54
3.90
2.65
3
0.42
0
0.20
1
0.22
1.30
1.90
2
0.24
1.45
2.15
3.55
3
0.26
1.55
2.30
3.80
2.82
0.22
1.10
25 MHz
TYP
MAX
3.94
6.54
7.23
4.20
6.96
TYP
UNIT
MAX
mA
8.65
9.54
1.22
2.10
mA
4.0
4.70
5.30
All inputs are tied to 0 or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
Characterized with program executing typical data processing.
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.
Active mode supply current when program executes in flash at a nominal supply voltage of 3 V.
Active mode supply current when program executes in RAM at a nominal supply voltage of 3 V.
Specifications
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
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5.5
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
TEMPERATURE (TA)
PARAMETER
VCC
PMMCOREVx
–40°C
TYP
ILPM0,1MHz
Low-power mode 0 (3) (4)
ILPM2
Low-power mode 2 (5) (4)
ILPM3,XT1LF
Low-power mode 3, crystal
mode (6) (4)
ILPM3,XT1LF
ILPM3,VLO
ILPM4
Low-power mode 3, crystal
mode (6) (4)
Low-power mode 3,
VLO mode (7) (4)
ILPM4.5
MAX
MAX
TYP
TYP
UNIT
MAX
0
75
78
87
81
84
96
3
85
89
99
93
98
110
2.2 V
0
5.9
6.2
9
6.9
9.4
17
3.0 V
3
6.9
7.4
10
8.4
11
19
0
1.4
1.7
2.5
4.9
1
1.5
1.9
2.7
5.2
2
1.7
2.0
2.9
5.5
0
2.2
2.5
3.3
5.5
1
2.3
2.7
3.5
5.8
2
2.5
2.9
3.7
6.1
3
2.5
2.9
3.5
3.7
6.1
14.0
0
1.4
1.7
2.2
2.4
4.5
11.5
1
1.5
1.8
2.5
4.7
2
1.6
1.9
2.7
4.9
3
1.6
1.9
2.4
2.7
5.0
12.7
0
1.3
1.6
2.0
2.3
4.4
11.1
1
1.4
1.6
2.4
4.5
2
1.4
1.7
2.5
4.8
2.2 V
3.0 V
Low-power mode 4 (8) (4)
3.0 V
1.4
1.7
Low-power mode 3.5, RTC
active on AUXVCC3 (9)
2.2 V
0.65
0.80
3.0 V
1.16
1.24
3.0 V
0.70
0.78
Low-power mode 4.5
85°C
MAX
3.0 V
3.0 V
(10)
60°C
TYP
2.2 V
3
ILPM3.5
25°C
3.1
2.2
µA
µA
µA
12.7
µA
µA
µA
2.5
4.8
0.90
1.30
12.2
2.05
1.43
1.87
2.71
1.05
0.90
1.20
1.85
µA
µA
(1)
(2)
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
(4) Current for brownout, high-side supervisor (SVSH) normal mode included. Low-side supervisor (SVSL) and low-side monitor (SVML)
disabled. High-side monitor (SVMH) disabled. RAM retention enabled.
(5) Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. ACLK = low-frequency crystal operation (XTS = 0,
XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz, DCO setting
= 1-MHz operation, DCO bias generator enabled.
(6) Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. ACLK = low-frequency crystal operation (XTS = 0,
XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
(7) Current for watchdog timer clocked by ACLK included. RTC is disabled (RTCHOLD = 1). ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz
(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
(9) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC active on AUXVCC3 supply
(10) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 0 Hz, PMMREGOFF = 1
Specifications
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5.6
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Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
TEMPERATURE (TA)
PARAMETER
VCC
PMMCOREVx
–40°C
TYP
ILPM3
LCD,
int. bias
Low-power mode 3
(LPM3) current, LCD 4mux mode, internal
biasing, charge pump
disabled (3) (4)
ILPM3
LCD,
int. bias
Low-power mode 3
(LPM3) current, LCD 4mux mode, internal
biasing, charge pump
disabled (3) (4)
2.2 V
3.0 V
2.2 V
ILPM3
LCD,CP
(1)
(2)
(3)
(4)
(5)
28
Low-power mode 3
(LPM3) current, LCD 4mux mode, internal
biasing, charge pump
enabled (3) (5)
3.0 V
MAX
25°C
60°C
TYP
MAX
TYP
3.6
85°C
MAX
UNIT
TYP
MAX
3.8
5.8
12.2
4.0
6.0
0
2.4
2.9
1
2.5
3.1
2
2.6
3.3
3.9
4.2
6.3
13.4
0
2.8
3.2
3.9
4.1
6.4
13.3
1
2.9
3.4
4.3
6.7
2
3.1
3.6
4.5
7.0
3
3.1
3.6
4.5
7.0
0
3.8
1
3.9
2
4.0
0
4.0
1
4.1
2
4.2
3
4.2
4.5
µA
µA
14.7
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. ACLK = low-frequency crystal operation (XTS = 0,
XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
Current for brownout, high-side supervisor (SVSH) normal mode included. Low-side supervisor (SVSL) and low-side monitor (SVML)
disabled. High-side monitor (SVMH) disabled. RAM retention enabled.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2, ... = 0 and odd segments S1, S3, ... = 1. No LCD panel load.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump
enabled), VLCDx = 1000 (VLCD = 3 V, typical), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2, ... = 0 and odd segments S1, S3, ... = 1. No LCD panel load.
Specifications
Copyright © 2011–2018, Texas Instruments Incorporated
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
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5.7
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Thermal Resistance Characteristics
THERMAL METRIC (1)
(2)
RθJA
Junction-to-ambient thermal resistance, still air
RθJC(TOP)
Junction-to-case (top) thermal resistance
RθJC(BOTTOM)
Junction-to-case (bottom) thermal resistance
RθJB
Junction-to-board thermal resistance
ΨJT
Junction-to-package-top thermal characterization parameter
ΨJB
Junction-to-board thermal characterization parameter
(1)
(2)
(3)
VALUE
LQFP 80 (PN)
46.3
LQFP 100 (PZ)
45.6
LQFP 80 (PN)
11.5
LQFP 100 (PZ)
11.0
LQFP 80 (PN)
N/A (3)
LQFP 100 (PZ)
N/A
LQFP 80 (PN)
21.9
LQFP 100 (PZ)
23.4
LQFP 80 (PN)
0.5
LQFP 100 (PZ)
0.4
LQFP 80 (PN)
21.6
LQFP 100 (PZ)
23.0
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
N/A = not applicable
Specifications
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
5.8
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Digital I/O Ports
Table 5-1 lists the characteristics of the schmitt-trigger Inputs.
Table 5-1. Schmitt-Trigger Inputs – General-Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup or pulldown resistor (1)
For pullup: VIN = VSS
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
(1)
VCC
MIN
TYP
1.8 V
0.80
1.40
3V
1.50
2.10
1.8 V
0.45
1.00
3V
0.75
1.65
1.8 V
0.3
0.85
3V
0.4
1.0
20
35
MAX
UNIT
V
V
V
50
kΩ
5
pF
Also applies to RST pin when pullup or pulldown resistor is enabled.
Table 5-2 lists the characteristics of the P1 and P2 inputs.
Table 5-2. Inputs – Ports P1 and P2 (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
t(int)
(1)
(2)
PARAMETER
TEST CONDITIONS
VCC
External interrupt timing (2)
Port P1, P2: P1.x to P2.x, External trigger pulse duration
to set interrupt flag
2.2 V, 3 V
MIN
MAX
UNIT
20
ns
Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It might be set by trigger signals
shorter than t(int).
Table 5-3 lists the characteristics of the GPIO leakage current.
Table 5-3. Leakage Current – General-Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.y)
(1)
(2)
TEST CONDITIONS
High-impedance leakage current
See
VCC
(1) (2)
MIN
1.8 V, 3 V
MAX
UNIT
±50
nA
The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
Table 5-4 lists the characteristics of the full drive strength GPIO output.
Table 5-4. Outputs – General-Purpose I/O (Full Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –3 mA (1)
VOH
High-level output voltage
I(OHmax) = –10 mA (1)
I(OHmax) = –5 mA (1)
I(OHmax) = –15 mA (1)
I(OLmax) = 3 mA (2)
VOL
Low-level output voltage
I(OLmax) = 10 mA (3)
I(OLmax) = 5 mA
(2)
(3)
30
1.8 V
3V
1.8 V
(2)
I(OLmax) = 15 mA (3)
(1)
VCC
3V
MIN
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
VSS
VSS + 0.25
VSS
VSS + 0.60
VSS
VSS + 0.25
VSS
VSS + 0.60
UNIT
V
V
The maximum total current, I(OHmax), for all outputs combined should not exceed ±20 mA to hold the maximum voltage drop specified.
See Section 5.3 for more details.
The maximum total current, I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified.
The maximum total current, I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage drop specified.
Specifications
Copyright © 2011–2018, Texas Instruments Incorporated
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
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5.8.1
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Typical Characteristics – General-Purpose I/O (Full Drive Strength)
0
-10
-5
IOH – High-Level Output Current – mA
IOH – High-Level Output Current – mA
0
-10
-15
TA = 85°C
-20
-20
-30
-40
TA = 85°C
-50
TA = 25°C
TA = 25°C
-60
-25
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
0
1.8
0.5
VCC = 1.8 V
Full Drive Strength
Figure 5-2. High-Level Output Current vs High-Level Output
Voltage
1.5
2
VCC = 3 V
2.5
3
Full Drive Strength
Figure 5-3. High-Level Output Current vs High-Level Output
Voltage
60
25
50
20
IOL – Low-Level Output Current – mA
IOL – Low-Level Output Current – mA
1
VOH – High-Level Output Voltage – V
VOH – High-Level Output Voltage – V
TA = 25°C
TA = 85°C
15
10
5
TA = 25°C
TA = 85°C
40
30
20
10
0
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
0
0.5
VCC = 1.8 V
Full Drive Strength
Figure 5-4. Low-Level Output Current vs Low-Level Output
Voltage
1
1.5
2
2.5
VCC = 3 V
Full Drive Strength
Figure 5-5. Low-Level Output Current vs Low-Level Output
Voltage
Specifications
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VOL – Low-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
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Table 5-5 lists the characteristics of the reduced drive strength GPIO output.
Table 5-5. Outputs – General-Purpose I/O (Reduced Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA (2)
VOH
High-level output voltage
I(OHmax) = –3 mA (2)
I(OHmax) = –2 mA (2)
I(OHmax) = –6 mA (2)
I(OLmax) = 1 mA (3)
VOL
Low-level output voltage
I(OLmax) = 3 mA (4)
I(OLmax) = 2 mA (3)
I(OLmax) = 6 mA (4)
(1)
(2)
(3)
(4)
32
VCC
1.8 V
3.0 V
1.8 V
3.0 V
MIN
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
VSS
VSS + 0.25
VSS
VSS + 0.60
VSS
VSS + 0.25
VSS
VSS + 0.60
UNIT
V
V
Selecting reduced drive strength may reduce EMI.
The maximum total current, I(OHmax), for all outputs combined should not exceed ±20 mA to hold the maximum voltage drop specified.
See Section 5.3 for more details.
The maximum total current, I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified.
The maximum total current, I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage drop specified.
Specifications
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5.8.2
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Typical Characteristics – General-Purpose I/O (Reduced Drive Strength)
0
0
IOH – High-Level Output Current – mA
IOH – High-Level Output Current – mA
-1
-2
-3
-4
-5
TA = 85°C
-6
-5
-10
-15
TA = 85°C
-20
TA = 25°C
-7
TA = 25°C
-8
-25
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
0
0.5
VOH – High-Level Output Voltage – V
VCC = 1.8 V
Reduced Drive Strength
Figure 5-6. High-Level Output Current vs High-Level Output
Voltage
1.5
VCC = 3 V
2
2.5
3
Reduced Drive Strength
Figure 5-7. High-Level Output Current vs High-Level Output
Voltage
8
20
18
7
TA = 25°C
TA = 25°C
IOL – Low-Level Output Current – mA
IOL – Low-Level Output Current – mA
1
VOH – High-Level Output Voltage – V
6
TA = 85°C
5
4
3
2
1
16
TA = 85°C
14
12
10
8
6
4
2
0
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
0
0.5
VCC = 1.8 V
Reduced Drive Strength
Figure 5-8. Low-Level Output Current vs Low-Level Output
Voltage
1
1.5
2
2.5
VCC = 3 V
Reduced Drive Strength
Figure 5-9. Low-Level Output Current vs Low-Level Output
Voltage
Specifications
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VOL – Low-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
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Table 5-6 lists the characteristics of the GPIO output frequency.
Table 5-6. Output Frequency – General-Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fPx.y
Port output frequency (with load)
fPort_CLK
(1)
(2)
34
Clock output frequency
TEST CONDITIONS
See
(1) (2)
ACLK, SMCLK, MCLK,
CL = 20 pF (2)
MIN
MAX
VCC = 1.8 V,
PMMCOREVx = 0
16
VCC = 3 V,
PMMCOREVx = 3
25
VCC = 1.8 V,
PMMCOREVx = 0
16
VCC = 3 V,
PMMCOREVx = 3
25
UNIT
MHz
MHz
A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
Specifications
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5.9
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Clock Specifications
Table 5-7 lists the characteristics of the XT1 oscillator in low-frequency mode.
Table 5-7. Crystal Oscillator, XT1, Low-Frequency Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ΔIDVCC.LF
Differential XT1 oscillator
crystal current consumption
from lowest drive setting, LF
mode
TEST CONDITIONS
VCC
MIN
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 1, TA = 25°C
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 2, TA = 25°C
3.0 V
0.170
0.290
XTS = 0, XT1BYPASS = 0
32768
XT1 oscillator crystal
frequency, LF mode
fXT1,LF,SW
XT1 oscillator logic-level
square-wave input frequency, XTS = 0, XT1BYPASS = 1 (2)
LF mode
OALF
Oscillation allowance for
LF crystals (4)
(3)
10
fFault,LF
tSTART,LF
210
XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF
300
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
12.0
Oscillator fault frequency,
LF mode (7)
XTS = 0 (8)
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 0, TA = 25°C, CL,eff = 6 pF
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 3, TA = 25°C, CL,eff = 12 pF
µA
Hz
50
kHz
1
5.5
Duty cycle, LF mode
UNIT
kΩ
XTS = 0, XCAPx = 1
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
Start-up time, LF mode
32.768
XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF
XTS = 0, XCAPx = 0 (6)
CL,eff
MAX
0.075
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 3, TA = 25°C
fXT1,LF0
Integrated effective load
capacitance, LF mode (5)
TYP
pF
30%
70%
10
10000
Hz
1000
3.0 V
ms
500
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger inputs section of this data sheet.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
• For XT1DRIVEx = 0, CL,eff ≤ 6 pF.
• For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF.
• For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF.
• For XT1DRIVEx = 3, CL,eff ≥ 6 pF.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specifications might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Specifications
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Table 5-8 lists the characteristics of the VLO.
Table 5-8. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fVLO
VLO frequency
dfVLO/dT
VLO frequency temperature drift
dfVLO/dVCC VLO frequency supply voltage drift
Duty cycle
(1)
(2)
TEST CONDITIONS
Measured at ACLK
VCC
MIN
TYP
MAX
6
9.4
15
1.8 V to 3.6 V
(1)
1.8 V to 3.6 V
0.5
Measured at ACLK (2)
1.8 V to 3.6 V
4
Measured at ACLK
1.8 V to 3.6 V
Measured at ACLK
30%
UNIT
kHz
%/°C
%/V
70%
Calculated using the box method: (MAX(–40°C to 85ºC) – MIN(–40°C to 85ºC)) / MIN(–40°C to 85ºC) / (85ºC – (–40ºC))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Table 5-9 lists the characteristics of the REFO.
Table 5-9. Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IREFO
fREFO
TEST CONDITIONS
VCC
MIN
TYP
TA = 25°C
1.8 V to 3.6 V
3
REFO frequency calibrated
Measured at ACLK
1.8 V to 3.6 V
32768
Full temperature range
1.8 V to 3.6 V
±3.5%
3V
±1.5%
REFO absolute tolerance calibrated
TA = 25°C
dfREFO/dT
REFO frequency temperature drift
(1)
1.8 V to 3.6 V
0.01
dfREFO/dVCC
REFO frequency supply voltage drift Measured at ACLK (2)
1.8 V to 3.6 V
1.0
Duty cycle
Measured at ACLK
1.8 V to 3.6 V
REFO start-up time
40%/60% duty cycle
1.8 V to 3.6 V
tSTART
(1)
(2)
36
MAX
REFO oscillator current
consumption
Measured at ACLK
40%
50%
UNIT
µA
Hz
%/°C
%/V
60%
25
µs
Calculated using the box method: (MAX(–40°C to 85ºC) – MIN(–40°C to 85ºC)) / MIN(–40°C to 85ºC) / (85ºC – (–40ºC))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Specifications
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 5-10 lists the frequency characteristics of the DCO.
Table 5-10. DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DCO frequency (0, 0) (1)
fDCO(0,0)
(1)
MAX
UNIT
DCORSELx = 0, DCOx = 0, MODx = 0
0.07
MIN
TYP
0.20
MHz
fDCO(0,31)
DCO frequency (0, 31)
DCORSELx = 0, DCOx = 31, MODx = 0
0.70
1.70
MHz
fDCO(1,0)
DCO frequency (1, 0) (1)
DCORSELx = 1, DCOx = 0, MODx = 0
0.15
0.36
MHz
fDCO(1,31)
DCO frequency (1, 31) (1)
DCORSELx = 1, DCOx = 31, MODx = 0
1.47
3.45
MHz
fDCO(2,0)
DCO frequency (2, 0) (1)
DCORSELx = 2, DCOx = 0, MODx = 0
0.32
0.75
MHz
(1)
fDCO(2,31)
DCO frequency (2, 31)
DCORSELx = 2, DCOx = 31, MODx = 0
3.17
7.38
MHz
fDCO(3,0)
DCO frequency (3, 0) (1)
DCORSELx = 3, DCOx = 0, MODx = 0
0.64
1.51
MHz
fDCO(3,31)
DCO frequency (3, 31) (1)
DCORSELx = 3, DCOx = 31, MODx = 0
6.07
14.0
MHz
(1)
fDCO(4,0)
DCO frequency (4, 0)
DCORSELx = 4, DCOx = 0, MODx = 0
1.3
3.2
MHz
fDCO(4,31)
DCO frequency (4, 31) (1)
DCORSELx = 4, DCOx = 31, MODx = 0
12.3
28.2
MHz
fDCO(5,0)
DCO frequency (5, 0) (1)
DCORSELx = 5, DCOx = 0, MODx = 0
2.5
6.0
MHz
(1)
fDCO(5,31)
DCO frequency (5, 31)
DCORSELx = 5, DCOx = 31, MODx = 0
23.7
54.1
MHz
fDCO(6,0)
DCO frequency (6, 0) (1)
DCORSELx = 6, DCOx = 0, MODx = 0
4.6
10.7
MHz
fDCO(6,31)
DCO frequency (6, 31) (1)
DCORSELx = 6, DCOx = 31, MODx = 0
39.0
88.0
MHz
fDCO(7,0)
DCO frequency (7, 0) (1)
DCORSELx = 7, DCOx = 0, MODx = 0
8.5
19.6
MHz
(1)
fDCO(7,31)
DCO frequency (7, 31)
DCORSELx = 7, DCOx = 31, MODx = 0
60
135
MHz
SDCORSEL
Frequency step between range
DCORSEL and DCORSEL + 1
SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)
1.2
2.3
ratio
SDCO
Frequency step between tap
DCO and DCO + 1
SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)
1.02
1.12
ratio
40%
Duty cycle
Measured at SMCLK
dfDCO/dT
DCO frequency temperature drift
fDCO = 1 MHz
0.1
%/°C
dfDCO/dVCORE
DCO frequency voltage drift
fDCO = 1 MHz
1.9
%/V
(1)
50%
60%
When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the
range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency,
range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap 31
(DCOx = 31). This ensures that the target DCO frequency resides within the range selected. If the actual fDCO frequency for the selected
range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the selected range is at its minimum
or maximum tap setting.
100
VCC = 3.0 V
TA = 25°C
fDCO – MHz
10
DCOx = 31
1
0.1
DCOx = 0
0
1
2
3
4
5
6
7
DCORSEL
Figure 5-10. Typical DCO Frequency
Specifications
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5.10 Power-Management Module (PMM)
Table 5-11 lists the brownout characteristics of the PMM.
Table 5-11. PMM, Brownout Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V(DVCC_BOR_IT–)
BORH on voltage, DVCC falling level
| dDVCC/dt | < 3 V/s
V(DVCC_BOR_IT+)
BORH off voltage, DVCC rising level
| dDVCC/dt | < 3 V/s
V(DVCC_BOR_hys)
BORH hysteresis
tRESET (1)
Pulse duration required at RST/NMI pin to accept
a reset
(1)
MIN
TYP
0.80
1.30
50
MAX
UNIT
1.45
V
1.50
V
250
mV
2
µs
Pulse much shorter than 2 µs might trigger reset.
Table 5-12 lists the core voltage characteristics of the PMM.
Table 5-12. PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCORE3(AM)
Core voltage, active mode, PMMCOREV = 3
2.4 V ≤ DVCC ≤ 3.6 V
1.93
V
VCORE2(AM)
Core voltage, active mode, PMMCOREV = 2
2.2 V ≤ DVCC ≤ 3.6 V
1.83
V
VCORE1(AM)
Core voltage, active mode, PMMCOREV = 1
2.0 V ≤ DVCC ≤ 3.6 V
1.62
V
VCORE0(AM)
Core voltage, active mode, PMMCOREV = 0
1.8 V ≤ DVCC ≤ 3.6 V
1.42
V
VCORE3(LPM)
Core voltage, low-current mode, PMMCOREV = 3
2.4 V ≤ DVCC ≤ 3.6 V
1.96
V
VCORE2(LPM)
Core voltage, low-current mode, PMMCOREV = 2
2.2 V ≤ DVCC ≤ 3.6 V
1.94
V
VCORE1(LPM)
Core voltage, low-current mode, PMMCOREV = 1
2.0 V ≤ DVCC ≤ 3.6 V
1.74
V
VCORE0(LPM)
Core voltage, low-current mode, PMMCOREV = 0
1.8 V ≤ DVCC ≤ 3.6 V
1.54
V
38
Specifications
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 5-13 lists the characteristics of the high-side SVS.
Table 5-13. PMM, SVS High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVSHE = 0, DVCC = 3.6 V
I(SVSH)
SVS current consumption
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0
SVSH on voltage level (1)
V(SVSH_IT+)
SVSH off voltage level (1)
tpd(SVSH)
SVSH propagation delay
t(SVSH)
SVSH on or off delay time
dVDVCC/dt
DVCC rise time
(1)
MAX
UNIT
0
nA
200
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1
V(SVSH_IT–)
TYP
1.5
µA
SVSHE = 1, SVSHRVL = 0
1.60
1.65
1.70
SVSHE = 1, SVSHRVL = 1
1.77
1.84
1.90
SVSHE = 1, SVSHRVL = 2
1.97
2.04
2.10
SVSHE = 1, SVSHRVL = 3
2.09
2.16
2.23
SVSHE = 1, SVSMHRRL = 0
1.68
1.74
1.80
SVSHE = 1, SVSMHRRL = 1
1.89
1.95
2.01
SVSHE = 1, SVSMHRRL = 2
2.08
2.14
2.21
SVSHE = 1, SVSMHRRL = 3
2.21
2.27
2.34
SVSHE = 1, SVSMHRRL = 4
2.35
2.41
2.49
SVSHE = 1, SVSMHRRL = 5
2.65
2.72
2.80
SVSHE = 1, SVSMHRRL = 6
2.96
3.04
3.13
SVSHE = 1, SVSMHRRL = 7
2.96
3.04
3.13
SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1
2.5
SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0
20
SVSHE = 0 → 1, SVSHFP = 1
12.5
SVSHE = 0 → 1, SVSHFP = 0
100
0
V
V
µs
µs
1000
V/s
The SVSH settings available depend on the VCORE (PMMCOREVx) setting. Refer to the Power Management Module and Supply
Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide on recommended settings and usage.
Table 5-14 lists the characteristics of the high-side SVM.
Table 5-14. PMM, SVM High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVMHE = 0, DVCC = 3.6 V
I(SVMH)
SVMH current consumption
SVMH on or off voltage level (1)
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0
SVMH propagation delay
t(SVMH)
SVMH on or off delay time
(1)
UNIT
nA
200
1.5
µA
SVMHE = 1, SVSMHRRL = 0
1.68
1.74
1.80
SVMHE = 1, SVSMHRRL = 1
1.89
1.95
2.01
SVMHE = 1, SVSMHRRL = 2
2.08
2.14
2.21
SVMHE = 1, SVSMHRRL = 3
2.21
2.27
2.34
SVMHE = 1, SVSMHRRL = 4
2.35
2.41
2.49
SVMHE = 1, SVSMHRRL = 5
2.65
2.72
2.80
SVMHE = 1, SVSMHRRL = 6
2.96
3.04
3.13
SVMHE = 1, SVSMHRRL = 7
2.96
3.04
3.13
SVMHE = 1, SVMHOVPE = 1
tpd(SVMH)
MAX
0
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1
V(SVMH)
TYP
V
3.79
SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1
2.5
SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0
20
SVMHE = 0 → 1, SVMHFP = 1
12.5
SVMHE = 0 → 1, SVMHFP = 0
100
µs
µs
The SVMH settings available depend on the VCORE (PMMCOREVx) setting. Refer to the Power Management Module and Supply
Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide on recommended settings and usage.
Specifications
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Table 5-15 lists the characteristics of the low-side SVS.
Table 5-15. PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVSLE = 0, PMMCOREV = 2
I(SVSL)
SVSL current consumption
tpd(SVSL)
SVSL propagation delay
t(SVSL)
SVSL on or off delay time
TYP
MAX
0
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
200
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
1.5
SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1
2.5
SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0
20
SVSLE = 0 → 1, SVSLFP = 1
12.5
SVSLE = 0 → 1, SVSLFP = 0
100
UNIT
nA
µA
µs
µs
Table 5-16 lists the characteristics of the low-side SVM.
Table 5-16. PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVMLE = 0, PMMCOREV = 2
I(SVML)
SVML current consumption
tpd(SVML)
SVML propagation delay
t(SVML)
SVML on or off delay time
TYP
MAX
0
SVMLE = 1, PMMCOREV = 2, SVMLFP = 0
200
SVMLE = 1, PMMCOREV = 2, SVMLFP = 1
1.5
SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1
2.5
SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0
20
SVMLE = 0 → 1, SVMLFP = 1
12.5
SVMLE = 0 → 1, SVMLFP = 0
100
UNIT
nA
µA
µs
µs
Table 5-17 lists the wake-up times.
Table 5-17. Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
fMCLK ≥ 4 MHz
3
5
1 MHz < fMCLK <
4 MHz
4
6
150
160
µs
tWAKE-UP-FAST
Wake-up time from LPM2,
LPM3, or LPM4 to active
mode (1)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 1
tWAKE-UP-SLOW
Wake-up time from LPM2,
LPM3, or LPM4 to active
mode (2) (3)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 0
tWAKE-UP-LPM4.5
Wake-up time from LPM4.5 to
active mode (4)
2
3
ms
tWAKE-UP-RESET
Wake-up time from RST or BOR
event to active mode (4)
2
3
ms
(1)
(2)
(3)
(4)
40
µs
This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance
mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-FAST is possible with SVSL and SVML in full performance
mode or disabled. For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in
the Power Management Module and Supply Voltage Supervisor chapter of the MSP430x5xx and MSP430x6xx Family User's Guide.
This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance
mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-SLOW is set with SVSL and SVML in normal mode (low
current mode). For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in the
Power Management Module and Supply Voltage Supervisor chapter of the MSP430x5xx and MSP430x6xx Family User's Guide.
The wake-up times from LPM0 and LPM1 to AM are not specified. They are proportional to MCLK cycle time but are not affected by the
performance mode settings as for LPM2, LPM3, and LPM4.
This value represents the time from the wake-up event to the reset vector execution.
Specifications
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
5.11 Auxiliary Supplies
Table 5-18 lists the operating conditions of the auxiliary supplies.
Table 5-18. Auxiliary Supplies, Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage range for all supplies at pins DVCC, AVCC, AUXVCC1, AUXVCC2,
AUXVCC3
VCC
Digital system supply voltage range,
VDSYS = VCC – RON × ILOAD
VDSYS
NOM
MAX
1.8
3.6
PMMCOREVx = 0
1.8
3.6
PMMCOREVx = 1
2.0
3.6
PMMCOREVx = 2
2.2
3.6
PMMCOREVx = 3
2.4
3.6
See module
specifications
UNIT
V
V
VASYS
Analog system supply voltage range, VASYS = VCC – RON × ILOAD
V
CVCC,
CAUX1/2
Recommended capacitor at pins DVCC, AVCC, AUXVCC1, AUXVCC2
4.7
µF
CVSYS
Recommended capacitor at pins VDSYS and VASYS
4.7
µF
CVCORE
Recommended capacitance at VCORE pin
0.47
µF
CAUX3
Recommended capacitor at pin AUXVCC3
0.47
µF
Table 5-19 lists the current consumption of AUX3.
Table 5-19. Auxiliary Supplies, AUXVCC3 (Backup Subsystem) Currents
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IAUX3,RTCon
AUXVCC3 current with
RTC enabled
RTC and 32-kHz oscillator in
backup subsystem enabled
3V
IAUX3,RTCoff
AUXVCC3 current with
RTC disabled
RTC and 32-kHz oscillator in
backup subsystem disabled
3V
TA
MIN
TYP
MAX
25°C
0.83
85°C
0.95
25°C
110
85°C
165
UNIT
µA
nA
Table 5-20 lists the characteristics of the auxiliary supply monitor.
Table 5-20. Auxiliary Supplies, Auxiliary Supply Monitor
over operating free-air temperature range (unless otherwise noted)
PARAMETER
ICC,Monitor
Average supply current for
monitoring circuitry drawn from
VDSYS
Average current drawn from
IMeas,Monitor monitored supply during
measurement cycle
VMonitor
Auxiliary supply threshold level
TEST CONDITIONS
LOCKAUX = 0, AUXMRx = 0,
AUX0MD = 0, AUX1MD = 0, AUX2MD = 1,
VDSYS = DVCC, VASYS = AVCC,
Current measured at VDSYS pin (also see
Figure 5-11)
VCC
MIN
TYP
3V
LOCKAUX = 0, AUXMRx = 0,
AUX0MD = 0, AUX1MD = 0, AUX2MD = 1,
VDSYS = DVCC, VASYS = AVCC,
AUXVCC1 = 3 V,
Current measured at AUXVCC1 pin (also see
Figure 5-12)
MAX
UNIT
0.70
µA
0.11
µA
AUXLVLx = 0
1.67
1.74
1.80
AUXLVLx = 1
1.87
1.95
2.01
AUXLVLx = 2
2.06
2.14
2.21
AUXLVLx = 3
2.19
2.27
2.33
AUXLVLx = 4
2.33
2.41
2.48
AUXLVLx = 5
2.63
2.72
2.79
AUXLVLx = 6
2.91
3.02
3.10
AUXLVLx = 7
2.91
3.02
3.10
Specifications
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V
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
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0.7
0.6
ICC, monitor – µA
0.5
0.4
0.3
0.2
0.1
0
1.8
2
2.2
2.4
2.6
2.8
VDSYS Voltage – V
3
3.2
3.4
3.6
3.2
3.4
3.6
Figure 5-11. VDSYS Voltage vs ICC,Monitor
120
Imeas, monitor – nA
100
80
60
40
20
0
1.8
2.0
2.2
2.4
2.6
2.8
AUXVCC1 Voltage – V
3.0
Figure 5-12. AUXVCC1 Voltage vs IMeas,Monitor
Table 5-21 lists the ON-resistance characteristics of the auxiliary supplies.
Table 5-21. Auxiliary Supplies, Switch ON-Resistance
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RON,DVCC
ON-resistance of switch
between DVCC and VDSYS
ILOAD = ICORE + IIO = 10 mA + 10 mA = 20 mA
5
Ω
RON,DAUX1
ON-resistance of switch
between AUXVCC1 and
VDSYS
ILOAD = ICORE + IIO = 10 mA + 10 mA = 20 mA
5
Ω
RON,DAUX2
ON-resistance of switch
between AUXVCC2 and
VDSYS
ILOAD = ICORE + IIO = 10 mA + 10 mA = 20 mA
5
Ω
RON,AVCC
ON-resistance of switch
between AVCC and VASYS
ILOAD = IModules = 10 mA
5
Ω
RON,AAUX1
ON-resistance of switch
between AUXVCC1 and VASYS
ILOAD = IModules = 5 mA
20
Ω
RON,AAUX2
ON-resistance of switch
between AUXVCC2 and VASYS
ILOAD = IModules = 5 mA
20
Ω
42
Specifications
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 5-22 lists the switching times of the auxiliary supplies.
Table 5-22. Auxiliary Supplies, Switching Time
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
tSwitch
Time from occurence of trigger (SVM or software) to "new" supply connected to system supplies
tRecover
"Recovery time" after a switch over took place; during this time, no further switching takes place
MAX
UNIT
100
ns
200
450
µs
TYP
MAX
UNIT
50
100
nA
450
730
nA
UNIT
Table 5-23 lists the switch leakage of the auxiliary supplies.
Table 5-23. Auxiliary Supplies, Switch Leakage
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ISW,Lkg
Current into DVCC, AVCC, AUXVCC1, or
AUXVCC2 if not selected
IVmax
Current drawn from highest supply
MIN
Per supply (but not the highest supply)
Table 5-24 lists the characteristics of the auxiliary supplies to ADC10_A.
Table 5-24. Auxiliary Supplies, Auxiliary Supplies to ADC10_A
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Supply voltage divider
V3 = VSupply/3
V3
RV3
Load resistance
tSample,V3
Sampling time required if
V3 selected
VCC
MIN
TYP
MAX
1.8 V
0.58
0.60
0.62
3.0 V
0.98
1.00
1.02
3.6 V
1.18
1.20
1.22
AUXADCRx = 0
18
AUXADCRx = 1
1.5
AUXADCRx = 2
0.6
AUXADC = 1, ADC10ON = 1,
INCH = 0Ch,
Error of conversion result
≤ 1 LSB
AUXADCRx = 0
1000
AUXADCRx = 1
1000
AUXADCRx = 2
1000
V
kΩ
ns
Table 5-25 lists the charge limiting resistor characteristics of the auxiliary supplies.
Table 5-25. Auxiliary Supplies, Charge Limiting Resistor
over operating free-air temperature range (unless otherwise noted)
PARAMETER
RCHARGE
Charge limiting resistor
TEST CONDITIONS
VCC
MIN
TYP
MAX
AUXCHCx = 1
3V
5
AUXCHCx = 2
3V
10
AUXCHCx = 3
3V
20
Specifications
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UNIT
kΩ
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5.12 Timer_A
Table 5-26 lists the characteristics of the Timer_A.
Table 5-26. Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
fTA
Timer_A input clock frequency
Internal: SMCLK or ACLK,
External: TACLK,
Duty cycle = 50% ±10%
1.8 V, 3 V
tTA,cap
Timer_A capture timing
All capture inputs, minimum pulse duration
required for capture
1.8 V, 3 V
MAX
UNIT
25
MHz
20
ns
5.13 eUSCI
Table 5-27. eUSCI (UART Mode) Clock Frequency
PARAMETER
CONDITIONS
feUSCI
eUSCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
VCC
MIN
Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%
MAX
UNIT
fSYSTEM
MHz
5
MHz
UNIT
Table 5-28 lists the switching characteristics of the eUSCI in UART mode.
Table 5-28. eUSCI (UART Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tt
UART receive deglitch time (1)
TEST CONDITIONS
MIN
TYP
MAX
UCGLITx = 0
10
15
25
UCGLITx = 1
30
50
85
50
80
150
70
120
200
UCGLITx = 2
UCGLITx = 3
(1)
44
VCC
2 V, 3 V
ns
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their duration should exceed the maximum specification of the deglitch time.
Specifications
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Table 5-29 lists the supported clock frequencies of the eUSCI in SPI master mode.
Table 5-29. eUSCI (SPI Master Mode) Clock Frequency
PARAMETER
feUSCI
eUSCI input clock frequency
CONDITIONS
VCC
MIN
Internal: SMCLK or ACLK,
Duty cycle = 50% ±10%
MAX
UNIT
fSYSTEM
MHz
Table 5-30 lists the switching characteristics of the eUSCI in SPI master mode.
Table 5-30. eUSCI (SPI Master Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
tSTE,LEAD
STE lead time, STE active to clock
tSTE,LAG
STE lag time, Last clock to STE
inactive
TEST CONDITIONS
VCC
MIN
UCSTEM = 0, UCMODEx = 01 or 10
2 V, 3 V
150
UCSTEM = 1, UCMODEx = 01 or 10
2 V, 3 V
150
UCSTEM = 0, UCMODEx = 01 or 10
2 V, 3 V
200
UCSTEM = 1, UCMODEx = 01 or 10
2 V, 3 V
200
UCSTEM = 0, UCMODEx = 01 or 10
tSTE,ACC
STE access time, STE active to SIMO
data out
UCSTEM = 1, UCMODEx = 01 or 10
UCSTEM = 0, UCMODEx = 01 or 10
tSTE,DIS
STE disable time, STE inactive to
SIMO high impedance
UCSTEM = 1, UCMODEx = 01 or 10
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time (2)
UCLK edge to SIMO valid, CL = 20 pF
tHD,MO
SIMO output data hold time (3)
CL = 20 pF
(1)
(2)
(3)
MAX
ns
ns
2V
50
3V
30
2V
50
3V
30
2V
40
3V
25
2V
40
3V
UNIT
ns
ns
25
2V
50
3V
30
2V
0
3V
0
ns
ns
2V
9
3V
5
2V
0
3V
0
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave))
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-13 and Figure 5-14.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 513 and Figure 5-14.
Specifications
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1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 5-13. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,MI
tSU,MI
SOMI
tVALID,MO
SIMO
Figure 5-14. SPI Master Mode, CKPH = 1
46
Specifications
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 5-31 lists the switching characteristics of the eUSCI in SPI slave mode.
Table 5-31. eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
tSTE,LEAD
STE lead time, STE active to clock
tSTE,LAG
STE lag time, Last clock to STE inactive
tSTE,ACC
STE access time, STE active to SOMI data out
tSTE,DIS
STE disable time, STE inactive to SOMI high
impedance
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time (2)
UCLK edge to SOMI valid,
CL = 20 pF
tHD,SO
SOMI output data hold time (3)
CL = 20 pF
(1)
(2)
(3)
VCC
MIN
2.0 V
4
3.0 V
3
2.0 V
0
3.0 V
0
TYP
MAX
ns
ns
2.0 V
46
3.0 V
24
2.0 V
38
3.0 V
25
2.0 V
2
3.0 V
1
2.0 V
2
3.0 V
2
55
32
3.0 V
16
ns
ns
3.0 V
24
ns
ns
2.0 V
2.0 V
UNIT
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI))
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-15 and Figure 5-16.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams inFigure 5-15
and Figure 5-16.
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tSU,SIMO
tLOW/HIGH
tHD,SIMO
SIMO
tACC
tVALID,SOMI
tDIS
SOMI
Figure 5-15. SPI Slave Mode, CKPH = 0
Specifications
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tSTE,LAG
tSTE,LEAD
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tACC
tDIS
tVALID,SO
SOMI
Figure 5-16. SPI Slave Mode, CKPH = 1
48
Specifications
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 5-32 lists the switching characteristics of the eUSCI in I2C mode.
Table 5-32. eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-17)
PARAMETER
TEST CONDITIONS
feUSCI
eUSCI input clock frequency
fSCL
SCL clock frequency
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
Data setup time
tSU,STO
Setup time for STOP
fSCL = 100 kHz
2 V, 3 V
fSCL > 100 kHz
fSCL = 100 kHz
2 V, 3 V
fSCL > 100 kHz
TYP
0
400
kHz
µs
µs
5.0
fSCL > 100 kHz
2 V, 3 V
1.3
µs
µs
5.2
µs
1.7
UCGLITx = 0
75
220
UCGLITx = 1
35
120
30
60
2 V, 3 V
UCGLITx = 2
20
30
UCCLTOx = 2
2 V, 3 V
33
UCCLTOx = 3
tSU,STA
tHD,STA
ns
35
UCCLTOx = 1
Clock low time-out
MHz
1.4
0.4
UCGLITx = 3
tTIMEOUT
fSYSTEM
5.1
2 V, 3 V
fSCL > 100 kHz
UNIT
1.5
2 V, 3 V
2 V, 3 V
MAX
5.1
fSCL = 100 kHz
fSCL = 100 kHz
Pulse duration of spikes suppressed by
input filter
tSP
MIN
2 V, 3 V
tHD,STA
tSU,DAT
VCC
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ±10%
ms
37
tHD,STA
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-17. I2C Mode Timing
Specifications
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5.14 LCD Controller
Table 5-33 lists the recommended operating conditions of the LCD_C.
Table 5-33. LCD_C Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VCC,LCD_C,CP en,3.6
Supply voltage range, charge
pump enabled, VLCD ≤ 3.6 V
LCDCPEN = 1, 0000 < VLCDx ≤ 1111
(charge pump enabled, VLCD ≤ 3.6 V)
2.2
3.6
V
VCC,LCD_C,CP en,3.3
Supply voltage range, charge
pump enabled, VLCD ≤ 3.3 V
LCDCPEN = 1, 0000 < VLCDx ≤ 1100
(charge pump enabled, VLCD ≤ 3.3 V)
2.0
3.6
V
VCC,LCD_C,int.
bias
Supply voltage range, internal
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 0
2.4
3.6
V
VCC,LCD_C,ext.
bias
Supply voltage range, external
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 0
2.4
3.6
V
VCC,LCD_C,VLCDEXT
Supply voltage range, external
LCD voltage, internal or external
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 1
2.0
3.6
V
VLCDCAP/R33
External LCD voltage at
LCDCAP/R33, internal or external
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 1
2.4
3.6
V
CLCDCAP
Capacitor on LCDCAP when
charge pump enabled
LCDCPEN = 1, VLCDx > 0000
(charge pump enabled)
10
µF
fLCD
LCD frequency range
fFRAME = 1/(2 × mux) × fLCD
with mux = 1 (static) to 8
1024
Hz
fFRAME,4mux
LCD frame frequency range
fFRAME,4mux(MAX) = 1/(2 × 4) ×
fLCD(MAX) = 1/(2 × 4) × 1024 Hz
128
Hz
fFRAME,8mux
LCD frame frequency range
fFRAME,8mux(MAX) = 1/(2 × 4) ×
fLCD(MAX) = 1/(2 × 8) × 1024 Hz
64
Hz
fACLK,in
ACLK input frequency range
40
kHz
CPanel
Panel capacitance
10000
pF
VCC
+ 0.2
V
4.7
0
30
32
100-Hz frame frequency
VR33
Analog input voltage at R33
LCDCPEN = 0, VLCDEXT = 1
VR23,1/3bias
Analog input voltage at R23
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR13
VR03 + 2/3 ×
(VR33-VR03)
VR33
V
VR13,1/3bias
Analog input voltage at R13 with
1/3 biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR03
VR03 + 1/3 ×
(VR33-VR03)
VR23
V
VR13,1/2bias
Analog input voltage at R13 with
1/2 biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 1
VR03
VR03 + 1/2 ×
(VR33-VR03)
VR33
V
VR03
Analog input voltage at R03
R0EXT = 1
VSS
VLCD–VR03
Voltage difference between VLCD
and R03
LCDCPEN = 0, R0EXT = 1
2.4
VLCDREF/R13
External LCD reference voltage
applied at LCDREF/R13
VLCDREFx = 01
0.8
50
Specifications
2.4
V
1.2
VCC
+ 0.2
V
1.5
V
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 5-34 lists the characteristics of the LCD_C.
Table 5-34. LCD_C Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VLCD
LCD voltage
TEST CONDITIONS
VCC
MIN
TYP
VLCDx = 0000, VLCDEXT = 0
2.4 V to 3.6 V
VCC
LCDCPEN = 1, VLCDx = 0001
2 V to 3.6 V
2.58
LCDCPEN = 1, VLCDx = 0010
2 V to 3.6 V
2.64
LCDCPEN = 1, VLCDx = 0011
2 V to 3.6 V
2.71
LCDCPEN = 1, VLCDx = 0100
2 V to 3.6 V
2.78
LCDCPEN = 1, VLCDx = 0101
2 V to 3.6 V
2.83
LCDCPEN = 1, VLCDx = 0110
2 V to 3.6 V
2.90
LCDCPEN = 1, VLCDx = 0111
2 V to 3.6 V
2.96
LCDCPEN = 1, VLCDx = 1000
2 V to 3.6 V
3.02
LCDCPEN = 1, VLCDx = 1001
2 V to 3.6 V
3.07
LCDCPEN = 1, VLCDx = 1010
2 V to 3.6 V
3.14
LCDCPEN = 1, VLCDx = 1011
2 V to 3.6 V
3.21
LCDCPEN = 1, VLCDx = 1100
2 V to 3.6 V
3.27
LCDCPEN = 1, VLCDx = 1101
2.2 V to 3.6 V
3.32
LCDCPEN = 1, VLCDx = 1110
2.2 V to 3.6 V
3.38
MAX
UNIT
V
LCDCPEN = 1, VLCDx = 1111
2.2 V to 3.6 V
3.44
ICC,Peak,CP
Peak supply currents due to
charge pump activities
3.6
LCDCPEN = 1, VLCDx = 1111
2.2 V
400
tLCD,CP,on
Time to charge CLCD when
discharged
CLCD = 4.7µF, LCDCPEN = 0→1,
VLCDx = 1111
2.2 V
150
ICP,Load
Maximum charge pump load
current
LCDCPEN = 1, VLCDx = 1111
2.2 V
RLCD,Seg
LCD driver output impedance,
segment lines
LCDCPEN = 1, VLCDx = 1000,
ILOAD = ±10 µA
2.2 V
10
kΩ
RLCD,COM
LCD driver output impedance,
common lines
LCDCPEN = 1, VLCDx = 1000,
ILOAD = ±10 µA
2.2 V
10
kΩ
µA
500
50
µA
Specifications
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5.15 SD24_B
Table 5-35 lists the power supply and recommended operating conditions of the SD24_B.
Table 5-35. SD24_B Power Supply and Recommended Operating Conditions
MIN
AVCC
Analog supply voltage
AVCC = DVCC, AVSS = DVSS = 0 V
TYP
MAX
2.4
UNIT
3.6
V
MHz
fSD
Modulator clock frequency
(1)
0.03
2.3
VI
Absolute input voltage range
AVSS – 1
AVCC
V
VIC
Common-mode input voltage range
AVSS – 1
AVCC
V
VID,FS
Differential full-scale input voltage
Differential input voltage for specified
performance (2)
VID
CREF
(1)
(2)
(3)
VID = VI,A+ – VI,A–
SD24REFS = 1
VREF load capacitance (3)
–VREF/GAIN
+VREF/GAIN
SD24GAINx = 1
±910
±920
SD24GAINx = 2
±455
±460
SD24GAINx = 4
±227
±230
SD24GAINx = 8
±113
±115
SD24GAINx = 16
±57
±58
SD24GAINx = 32
±28
±29
SD24GAINx = 64
±14
±14.5
SD24GAINx = 128
±7
±7.2
SD24REFS = 1
mV
100
nF
Modulator clock frequency: MIN = 32.768 kHz – 10% ≈ 30 kHz. MAX = 32.768 kHz × 64 + 10% ≈ 2.3 MHz
The full-scale range (FSR) is defined by VFS+ = +VREF/GAIN and VFS– = –VREF/GAIN: FSR = VFS+ – VFS– = 2 × VREF / GAIN. If VREF is
sourced externally, the analog input range should not exceed 80% of VFS+ or VFS–; that is, VID = 0.8 VFS– to 0.8 VFS+. If VREF is sourced
internally, the given VID ranges apply.
There is no capacitance required on VREF. However, a capacitance of 100 nF is recommended to reduce any reference voltage noise.
Table 5-36 lists the analog input characteristics of the SD24_B.
Table 5-36. SD24_B Analog Input
PARAMETER
CI
Input capacitance
TEST CONDITIONS
(1)
VCC
MIN
5
SD24GAINx = 2
5
SD24GAINx = 4
5
SD24GAINx = 8
5
SD24GAINx = 16
5
SD24GAINx = 32, 64, 128
ZI
ZID
(1)
52
Input impedance
(Pin A+ or A- to AVSS)
Differential input impedance
(Pin A+ to pin A-)
TYP
SD24GAINx = 1
fSD24 = 1 MHz
fSD24 = 1 MHz
MAX
UNIT
pF
5
SD24GAINx = 1
3V
200
SD24GAINx = 8
3V
200
SD24GAINx = 32
3V
SD24GAINx = 1
3V
SD24GAINx = 8
3V
SD24GAINx = 32
3V
kΩ
200
300
400
400
300
kΩ
400
All parameters pertain to each SD24_B converter.
Specifications
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
1600
Input Leakage Current – nA
1400
1200
1000
800
600
400
200
0
-200
-1
-0.5
0
0.5
1
Input Voltage – V
1.5
2
2.5
3
Figure 5-18. Input Leakage Current vs Input Voltage
(Modulator OFF)
Table 5-37 lists the supply current of the SD24_B.
Table 5-37. SD24_B Supply Currents
PARAMETER
ISD,256
ISD,512
TEST CONDITIONS
Analog plus digital supply current per
converter (reference not included)
fSD24 = 1 MHz,
SD24OSR = 256
Analog plus digital supply current per
converter (reference not included)
fSD24 = 2 MHz,
SD24OSR = 512
VCC
MIN
TYP
MAX
SD24GAIN: 1
3V
600
675
SD24GAIN: 2
3V
600
675
SD24GAIN: 4
3V
600
675
SD24GAIN: 8
3V
700
750
SD24GAIN: 16
3V
700
750
SD24GAIN: 32
3V
775
850
SD24GAIN: 64
3V
775
850
SD24GAIN: 128
3V
775
850
SD24GAIN: 1
3V
750
800
SD24GAIN: 8
3V
825
900
SD24GAIN: 32
3V
900
1000
TYP
MAX
UNIT
µA
µA
Table 5-38 lists the performance characteristics of the SD24_B.
Table 5-38. SD24_B Performance
fSD24 = 1 MHz, SD24OSRx = 256, SD24REFS = 1
PARAMETER
INL
Gnom
Integral nonlinearity, endpoint fit
Nominal gain
VCC
MIN
SD24GAIN: 1
TEST CONDITIONS
3V
–0.01
0.01
SD24GAIN: 8
3V
–0.01
0.01
SD24GAIN: 32
3V
–0.01
0.01
SD24GAIN: 1
3V
1
SD24GAIN: 2
3V
2
SD24GAIN: 4
3V
4
SD24GAIN: 8
3V
8
SD24GAIN: 16
3V
16
SD24GAIN: 32
3V
31.7
SD24GAIN: 64
3V
63.4
SD24GAIN: 128
3V
126.8
Specifications
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UNIT
% of
FSR
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Table 5-38. SD24_B Performance (continued)
fSD24 = 1 MHz, SD24OSRx = 256, SD24REFS = 1
PARAMETER
TEST CONDITIONS
EG
Gain error (1)
ΔEG/ΔT
Gain error temperature
coefficient (2), internal
reference
ΔEG/ΔVCC
Gain error vs VCC
Offset error (4)
EOS[V]
Offset error (4)
EOS[FS]
Offset error temperature
coefficient (5)
ΔEOS/ΔT
ΔEOS/ΔVCC
CMRR,DC
(1)
(2)
(3)
(4)
(5)
(6)
(7)
54
(3)
Offset error vs VCC
(6)
Common-mode rejection at
DC (7)
VCC
MIN
SD24GAIN: 1, with external reference (1.2 V)
3V
–1%
TYP
MAX
+1%
SD24GAIN: 8, with external reference (1.2 V)
3V
–2%
+2%
SD24GAIN: 32, with external reference (1.2 V)
3V
–2%
+2%
SD24GAIN: 1, 8, or 32 (with internal reference)
3V
50
SD24GAIN: 1
0.15
SD24GAIN: 8
0.15
SD24GAIN: 32
0.4
3V
2.3
SD24GAIN: 8
3V
0.73
SD24GAIN: 32
3V
0.18
SD24GAIN: 1 (with Vdiff = 0 V)
3V
–0.2
0.2
SD24GAIN: 8
3V
–0.5
0.5
SD24GAIN: 32
3V
–0.5
0.5
SD24GAIN: 1
3V
1
SD24GAIN: 8
3V
0.15
SD24GAIN: 32
3V
0.1
600
SD24GAIN: 8
100
SD24GAIN: 32
50
SD24GAIN: 1
3V
–110
SD24GAIN: 8
3V
–110
SD24GAIN: 32
3V
–110
ppm/
°C
%/V
SD24GAIN: 1 (with Vdiff = 0 V)
SD24GAIN: 1
UNIT
mV
% FS
µV/°C
µV/V
dB
The gain error EG specifies the deviation of the actual gain Gact from the nominal gain Gnom: EG = (Gact – Gnom)/Gnom. It covers process,
temperature and supply voltage variations.
The gain error temperature coefficient ΔEG / ΔT specifies the variation of the gain error EG over temperature (EG(T) = (Gact(T) –
Gnom)/Gnom) using the box method (that is, MIN and MAX values):
ΔEG/ ΔT = (MAX(EG(T)) – MIN(EG(T) ) / (MAX(T) – MIN(T)) = (MAX(Gact(T)) – MIN(Gact(T)) / Gnom / (MAX(T) – MIN(T))
with T ranging from –40°C to +85°C.
The gain error vs VCC coefficient ΔEG/ ΔVCC specifies the variation of the gain error EG over supply voltage (EG(VCC) = (Gact(VCC) –
Gnom)/Gnom) using the box method (that is, MIN and MAX values):
ΔEG/ ΔVCC = (MAX(EG(VCC)) – MIN(EG(VCC) ) / (MAX(VCC) – MIN(VCC)) = (MAX(Gact(VCC)) – MIN(Gact(VCC)) / Gnom / (MAX(VCC) –
MIN(VCC))
with VCC ranging from 2.4 V to 3.6 V.
The offset error EOS is measured with shorted inputs in 2s-complement mode with +100% FS = VREF / G and –100% FS = –VREF / G.
Conversion between EOS [FS] and EOS [V] is as follows: EOS [FS] = EOS [V]×G/VREF; EOS [V] = EOS [FS]×VREF/G.
The offset error temperature coefficient ΔEOS / ΔT specifies the variation of the offset error EOS over temperature using the box method
(that is, MIN and MAX values):
ΔEOS / ΔT = (MAX(EOS(T)) – MIN(EOS(T) ) / (MAX(T) – MIN(T))
with T ranging from –40°C to +85°C.
The offset error vs VCC ΔEOS / ΔVCC specifies the variation of the offset error EOS over supply voltage using the box method (that is,
MIN and MAX values):
ΔEOS / ΔVCC = (MAX(EOS(VCC)) – MIN(EOS(VCC) ) / (MAX(VCC) – MIN(VCC))
with VCC ranging from 2.4 V to 3.6 V.
The DC CMRR specifies the change in the measured differential input voltage value when the common-mode voltage varies:
DC CMRR = –20log(ΔMAX/FSR) with ΔMAX being the difference between the minium value and the maximum value measured when
sweeping the common-mode voltage (for example, calculating with 16-bit FSR = 65536, a maximum change by 1 LSB results in
–20log(1/65536) ≈ –96 dB) .
The DC CMRR is measured with both inputs connected to the common-mode voltage (that is, no differential input signal is applied), and
the common-mode voltage is swept from –1 V to VCC.
Specifications
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 5-38. SD24_B Performance (continued)
fSD24 = 1 MHz, SD24OSRx = 256, SD24REFS = 1
PARAMETER
CMRR,50Hz
AC PSRR,ext
AC PSRR,int
XT
Common-mode rejection at
50 Hz (8)
AC power supply rejection
ratio, external reference (9)
AC power supply rejection
ratio, internal reference (9)
Crosstalk between
converters (10)
TEST CONDITIONS
VCC
MIN
TYP
SD24GAIN: 1, fCM = 50 Hz, VCM = 930 mV
3V
–110
SD24GAIN: 8, fCM = 50 Hz, VCM = 120 mV
3V
–110
SD24GAIN: 32, fCM = 50 Hz, VCM = 30 mV
3V
–110
SD24GAIN: 1,
VCC = 3 V + 50 mV × sin(2π × fVcc × t),
fVcc = 50 Hz
–61
SD24GAIN: 8,
VCC = 3 V + 50 mV × sin(2π × fVcc × t),
fVcc = 50 Hz
–77
SD24GAIN: 32,
VCC = 3 V + 50 mV × sin(2π × fVcc × t),
fVcc = 50 Hz
–79
SD24GAIN: 1,
VCC = 3 V + 50 mV × sin(2π × fVcc × t),
fVcc = 50 Hz
–61
SD24GAIN: 8,
VCC = 3 V + 50 mV × sin(2π × fVcc × t),
fVcc = 50 Hz
–77
SD24GAIN: 32,
VCC = 3 V + 50 mV × sin(2π × fVcc × t),
fVcc = 50 Hz
–79
Crosstalk source: SD24GAIN: 1,
Sine wave with maximum possible Vpp,
fIN = 50 Hz or 100 Hz,
Converter under test: SD24GAIN: 1
3V
–120
Crosstalk source: SD24GAIN: 1,
Sine wave with maximum possible Vpp,
fIN = 50 Hz or 100 Hz,
Converter under test: SD24GAIN: 8
3V
–115
Crosstalk source: SD24GAIN: 1,
Sine wave with maximum possible Vpp,
fIN = 50 Hz or 100 Hz,
Converter under test: SD24GAIN: 32
3V
–100
MAX
UNIT
dB
dB
dB
dB
(8)
The AC CMRR is the difference between a hypothetical signal with the amplitude and frequency of the applied common-mode ripple
applied to the inputs of the ADC and the actual common-mode signal spur visible in the FFT spectrum:
AC CMRR = Error Spur [dBFS] – 20log(VCM / 1.2 V / G) [dBFS] with a common-mode signal of VCM × sin(2π × fCM × t) applied to the
analog inputs.
The AC CMRR is measured with the both inputs connected to the common-mode signal (that is, no differential input signal is applied).
With the specified typical values the error spur is within the noise floor (as specified by the SINAD values).
(9) The AC PSRR is the difference between a hypothetical signal with the amplitude and frequency of the applied supply voltage ripple
applied to the inputs of the ADC and the actual supply ripple spur visible in the FFT spectrum:
AC PSRR = Error Spur [dBFS] – 20log(50 mV / 1.2 V / G) [dBFS] with a signal of 50 mV × sin(2π × fVcc × t) added to VCC.
The AC PSRR is measured with the inputs grounded (that is, no analog input signal is applied).
With the specified typical values the error spur is within the noise floor (as specified by the SINAD values).
SD24GAIN: 1 → Hypothetical signal: 20log(50 mV / 1.2 V / 1) = –27.6 dBFS
SD24GAIN: 8 → Hypothetical signal: 20log(50 mV / 1.2 V / 8) = –9.5 dBFS
SD24GAIN: 32 → Hypothetical signal: 20log(50 mV / 1.2 V / 32) = 2.5 dBFS
(10) The crosstalk (XT) is specified as the tone level of the signal applied to the crosstalk source seen in the spectrum of the converter under
test. It is measured with the inputs of the converter under test being grounded.
Specifications
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Table 5-39 lists the AC performance characteristics of the SD24_B.
Table 5-39. SD24_B AC Performance
fSD24 = 1 MHz, SD24OSRx = 256, SD24REFS = 1
PARAMETER
SINAD
Signal-to-noise + distortion ratio
VCC
MIN
TYP
SD24GAIN: 1
TEST CONDITIONS
3V
85
87
SD24GAIN: 2
3V
SD24GAIN: 4
3V
SD24GAIN: 8
3V
SD24GAIN: 16
fIN = 50 Hz (1)
Total harmonic distortion
84
3V
3V
68
SD24GAIN: 128
3V
62
3V
100
3V
90
3V
80
fIN = 50 Hz (1)
dB
80
SD24GAIN: 64
SD24GAIN: 32
(1)
85
82
SD24GAIN: 32
SD24GAIN: 8
UNIT
86
3V
SD24GAIN: 1
THD
MAX
73
74
dB
The following voltages were applied to the SD24_B inputs:
VI,A+(t) = 0 V + VPP / 2 × sin(2π × fIN × t)
VI,A-(t) = 0 V – VPP / 2 × sin(2π × fIN × t)
resulting in a differential voltage of VID = VI,A+(t) – VI,A–(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value
allowed for a given range (according to SD24_B recommended operating conditions).
Table 5-40 lists the AC performance characteristics of the SD24_B.
Table 5-40. SD24_B AC Performance
fSD24 = 2 MHz, SD24OSRx = 512, SD24REFS = 1
PARAMETER
SINAD
(1)
56
Signal-to-noise + distortion ratio
TEST CONDITIONS
VCC
MIN
TYP
SD24GAIN: 1
3V
87
SD24GAIN: 2
3V
86
SD24GAIN: 4
3V
85
SD24GAIN: 8
3V
84
3V
81
SD24GAIN: 32
3V
76
SD24GAIN: 64
3V
71
SD24GAIN: 128
3V
65
SD24GAIN: 16
fIN = 50 Hz (1)
MAX
UNIT
dB
The following voltages were applied to the SD24_B inputs:
VI,A+(t) = 0 V + VPP / 2 × sin(2π × fIN × t)
VI,A-(t) = 0 V – VPP / 2 × sin(2π × fIN × t)
resulting in a differential voltage of VID = VI,A+(t) – VI,A–(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value
allowed for a given range (according to SD24_B recommended operating conditions).
Specifications
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 5-41 lists the AC performance characteristics of the SD24_B.
Table 5-41. SD24_B AC Performance
fSD24 = 32 kHz, SD24OSRx = 512, SD24REFS = 1
PARAMETER
SINAD
(1)
TEST CONDITIONS
Signal-to-noise + distortion ratio
VCC
MIN
TYP
SD24GAIN: 1
3V
89
SD24GAIN: 2
3V
85
SD24GAIN: 4
3V
84
SD24GAIN: 8
3V
86
3V
80
SD24GAIN: 32
3V
76
SD24GAIN: 64
3V
67
SD24GAIN: 128
3V
61
SD24GAIN: 16
fIN = 12 Hz (1)
MAX
UNIT
dB
The following voltages were applied to the SD24_B inputs:
VI,A+(t) = 0 V + VPP / 2 × sin(2π × fIN × t)
VI,A-(t) = 0 V – VPP / 2 × sin(2π × fIN × t)
resulting in a differential voltage of VID = VI,A+(t) – VI,A–(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value
allowed for a given range (according to SD24_B recommended operating conditions).
95
90
SINAD – dB
85
80
75
70
65
60
55
32
64
128
256
512
1024
SD24OSRx
Figure 5-19. SINAD vs OSR
(fSD24 = 1 MHz, SD24REFS = 1, SD24GAIN = 1)
Specifications
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90
85
SINAD – dB
80
75
70
65
60
0.1
0.2
0.3
0.4
0.5
0.6
Vpp/Vref/Gain
0.7
0.8
0.9
1
Figure 5-20. SINAD vs VPP
Table 5-42 lists the external reference input requirements of the SD24_B.
Table 5-42. SD24_B External Reference Input
ensure correct input voltage range according to VREF
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
1.0
1.20
1.5
V
50
nA
VREF(I)
Input voltage
SD24REFS = 0
3V
IREF(I)
Input current
SD24REFS = 0
3V
58
Specifications
UNIT
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
5.16 ADC10_A
Table 5-43 lists the power supply and input range conditions of the ADC10_A.
Table 5-43. 10-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
VCC
AVCC
Analog supply voltage
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
V(Ax)
Analog input voltage range (1)
All ADC10_A pins
Operating supply current into
AVCC terminal, REF module
and reference buffer off
fADC10CLK = 5 MHz, ADC10ON =1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
ADC10SREF = 00
Operating supply current into
AVCC terminal, REF module
on, reference buffer on
fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 1,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
ADC10SREF = 01
Operating supply current into
AVCC terminal, REF module
off, reference buffer on
MIN
TYP
MAX
1.8
3.6
V
0
AVCC
V
2.2 V
70
105
3V
80
115
3V
130
185
fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
ADC10SREF = 10, VEREF = 2.5 V
3V
108
160
Operating supply current into
AVCC terminal, REF module
off, reference buffer off
fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
ADC10SREF = 11, VEREF = 2.5 V
3V
74
105
CI
Input capacitance
Only one terminal Ax can be selected at one time
from the pad to the ADC10_A capacitor array
including wiring and pad.
2.2 V
3.5
RI
Input MUX ON resistance
IADC10_A
(1)
UNIT
µA
pF
AVCC > 2 V, 0 V ≤ VAx ≤ AVCC
36
1.8 V < AVCC < 2 V, 0 V ≤ VAx ≤ AVCC
96
kΩ
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. The external
reference voltage requires decoupling capacitors. Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to
decouple the dynamic current required for an external reference source if it is used for the ADC10_A. Also see the MSP430x5xx and
MSP430x6xx Family User's Guide.
Table 5-44 lists the timing parameters of the ADC10_A.
Table 5-44. 10-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX
UNIT
For specified performance of ADC10_A
linearity parameters
2.2 V, 3 V
0.45
5
5.5
MHz
Internal ADC10_A
oscillator (1)
ADC10DIV = 0, fADC10CLK = fADC10OSC
2.2 V, 3 V
4.4
5.0
5.6
MHz
2.2 V, 3 V
2.4
Conversion time
REFON = 0, Internal oscillator,
12 ADC10CLK cycles, 10-bit mode
fADC10OSC = 4 MHz to 5 MHz
fADC10CLK
fADC10OSC
tCONVERT
TEST CONDITIONS
µs
External fADC10CLK from ACLK, MCLK or
SMCLK, ADC10SSEL ≠ 0
tADC10ON
Turnon settling time of
the ADC
tSample
Sampling time
(1)
(2)
(3)
See
3.0
12 ×
1 / fADC10CLK
(2)
100
RS = 1000 Ω, RI = 96 kΩ, CI = 3.5 pF (3)
1.8 V
3
RS = 1000 Ω, RI = 36 kΩ, CI = 3.5 pF (3)
3V
1
ns
µs
The ADC10OSC is sourced directly from MODOSC inside the UCS.
The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
Approximately ei8ght Tau (t) are needed to get an error of less than ±0.5 LSB
Specifications
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Table 5-45. 10-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.4 V ≤ (VeREF+ – VeREF–) ≤ 1.6 V, CVeREF+ = 20 pF
MIN
TYP
MAX
±1.0
UNIT
EI
Integral
linearity error
ED
Differential
linearity error
1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF
2.2 V, 3 V
±1.0
LSB
EO
Offset error
1.4 V ≤ (VeREF+ – VeREF–), CVREF+ = 20 pF,
Internal impedance of source RS < 100 Ω
2.2 V, 3 V
±1.0
LSB
EG
Gain error
1.4 V ≤ (VeREF+ – VeREF–),
CVeREF+ = 20 pF, ADC10SREFx = 11b
2.2 V, 3 V
±1.0
LSB
ET
Total unadjusted
error
1.4 V ≤ (VeREF+ – VeREF–),
CVeREF+ = 20 pF, ADC10SREFx = 11b
2.2 V, 3 V
±2.0
LSB
MAX
UNIT
2.2 V, 3 V
1.6 V < (VeREF+ – VeREF–) ≤ VAVCC, CVeREF+ = 20 pF
±1.0
±1.0
LSB
Table 5-46 lists the external reference requirements of the ADC10_A.
Table 5-46. 10-Bit ADC, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
VeREF+
Positive external reference
VeREF+ > VeREF–
voltage input
(2)
1.4
AVCC
V
VeREF–
Negative external
reference voltage input
VeREF+ > VeREF–
(3)
0
1.2
V
(VeREF+ –
VeREF–)
Differential external
reference voltage input
VeREF+ > VeREF–
(4)
1.4
AVCC
V
±26
µA
±1
µA
IVeREF+,
IVeREF–
CVeREF+/(1)
(2)
(3)
(4)
(5)
60
Static input current
Capacitance at VeREF+
or VeREF- terminal
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V,
fADC10CLK = 5 MHz, ADC10SHTx = 0x0001,
Conversion rate 200 ksps
2.2 V, 3 V
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V,
fADC10CLK = 5 MHz, ADC10SHTX = 0x1000,
Conversion rate 20 ksps
2.2 V, 3 V
See
(5)
±8.5
10
µF
The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
Two decoupling capacitors, 10 µF and 100 nF, should be connected to VeREF to decouple the dynamic current required for an external
reference source if it is used for the ADC10_A. Also see the MSP430x5xx and MSP430x6xx Family User's Guide.
Specifications
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5.17 REF
Table 5-47 lists the characteristics of the REF.
Table 5-47. REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Positive built-in reference
voltage
VREF+
AVCC minimum voltage,
Positive built-in reference
active
AVCC(min)
Operating supply current
into AVCC terminal (1)
IREF+
TEST CONDITIONS
VCC
MIN
TYP
MAX
REFVSEL = {2} for 2.5 V, REFON = 1
3V
2.47
2.51
2.55
REFVSEL = {1} for 2.0 V, REFON = 1
3V
1.95
1.99
2.03
REFVSEL = {0} for 1.5 V, REFON = 1
2.2 V, 3 V
1.46
1.50
1.54
REFVSEL = {0} for 1.5 V
1.8
REFVSEL = {1} for 2.0 V
2.2
REFVSEL = {2} for 2.5 V
2.7
UNIT
V
V
fADC10CLK = 5 MHz,
REFON = 1, REFBURST = 0,
REFVSEL = {2} for 2.5 V
3V
23
30
fADC10CLK = 5 MHz,
REFON = 1, REFBURST = 0,
REFVSEL = {1} for 2.0 V
3V
21
27
fADC10CLK = 5 MHz,
REFON = 1, REFBURST = 0,
REFVSEL = {0} for 1.5 V
3V
19
25
10
50
µA
TCREF+
Temperature coefficient of
built-in reference (2)
REFVSEL = {0, 1, 2}, REFON = 1
ISENSOR
Operating supply current
into AVCC terminal
REFON = 1, ADC10ON = 1,
INCH = 0Ah, TA = 30°C
2.2 V
145
220
3V
170
245
VSENSOR
See
REFON = 1, ADC10ON = 1,
INCH = 0Ah, TA = 30°C
2.2 V
780
3V
780
VMID
AVCC divider at channel 11
ADC10ON = 1, INCH = 0Bh,
VMID is ~0.5 × VAVCC
2.2 V
1.08
1.1
1.12
3V
1.48
1.5
1.52
tSENSOR(sample)
Sample time required if
channel 10 is selected (4)
REFON = 1, ADC10ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
tVMID(sample)
Sample time required if
channel 11 is selected (5)
ADC10ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
PSRR_DC
Power supply rejection ratio
(DC)
AVCC = AVCC (min) to AVCC(max),
TA = 25°C,
REFVSEL = {0, 1, 2}, REFON = 1
120
PSRR_AC
Power supply rejection ratio
(AC)
AVCC = AVCC (min) to AVCC(max),
TA = 25°C,
f = 1 kHz, ΔVpp = 100 mV
REFVSEL = {0, 1, 2}, REFON = 1
1
mV/V
tSETTLE
Settling time of reference
voltage (6)
AVCC = AVCC (min) to AVCC(max),
REFVSEL = {0, 1, 2}, REFON = 0→1
75
µs
VSD24REF
SD24_B internal reference
voltage
SD24REFS = 1
3V
tON
SD24_B internal reference
turnon time (7)
SD24REFS = 0→1, CREF = 100 nF
3V
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(3)
ppm/
°C
µA
mV
V
30
µs
1
µs
1.137
1.151
300
1.165
200
µV/V
V
µs
The internal reference current is supplied through the AVCC terminal. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).
The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor.
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
The condition is that the error in a conversion started after tREFON is ≤ 1 LSB.
The condition is that SD24_B conversion started after tON should guarantee specified SINAD values for the selected Gain, OSR and
fSD24.
Specifications
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5.18 Flash Memory
Table 5-48 lists the characteristics of the flash memory.
Table 5-48. Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TJ
MIN
TYP
Program and erase supply voltage
IPGM
Average supply current from DVCC during program
3
5
mA
IERASE
Average supply current from DVCC during erase
6
11
mA
IMERASE, IBANK
Average supply current from DVCC during mass erase or bank erase
6
11
mA
Cumulative program time
(1)
16
104
Program and erase endurance
tRetention
Data retention duration
tWord
3.6
UNIT
DVCC(PGM/ERASE)
tCPT
1.8
MAX
ms
cycles
100
years
64
85
µs
0
Block program time for first byte or word (2)
49
65
µs
tBlock,
1–(N–1)
Block program time for each additional byte or word, except for last
byte or word (2)
37
49
µs
tBlock,
N
Block program time for last byte or word (2)
55
73
µs
tErase
Erase time for segment erase, mass erase, and bank erase when
available (2)
23
32
ms
fMCLK,MGR
MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)
0
1
MHz
tBlock,
(1)
(2)
Word or byte program time
25°C
(2)
105
V
The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word- or byte-write and block-write modes.
These values are hardwired into the state machine of the flash controller.
5.19 Emulation and Debug
Table 5-49 lists the characteristics of the JTAG and Spy-Bi-Wire interface.
Table 5-49. JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V, 3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2.2 V, 3 V
0.025
15
µs
tSBW, En
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge) (1)
2.2 V, 3 V
1
µs
tSBW,Rst
Spy-Bi-Wire return to normal operation time
100
µs
fTCK
TCK input frequency for 4-wire JTAG (2)
Rinternal
Internal pulldown resistance on TEST
(1)
(2)
62
15
2.2 V
0
5
3V
0
10
2.2 V, 3 V
45
60
80
MHz
kΩ
Tools that access the Spy-Bi-Wire interface must wait for the minimum tSBW,En time after pulling the TEST/SBWTCK pin high before
applying the first SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
Specifications
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
6 Detailed Description
6.1
CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are
dedicated as program counter, stack pointer, status register, and constant generator, respectively. The
remaining registers are general-purpose registers (see Figure 6-1).
Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be
managed with all instructions.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
Constant Generator
SR/CG1/R2
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Figure 6-1. Integrated CPU Registers
Detailed Description
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6.2
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Instruction Set
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data. Table 6-1 lists examples of the three types of instruction formats. Table 6-2 lists the address
modes.
Table 6-1. Instruction Word Formats
INSTRUCTION WORD FORMAT
EXAMPLE
OPERATION
Dual operands, source and destination
ADD R4,R5
R4 + R5 → R5
Single operands, destination only
CALL R8
PC → (TOS), R8 → PC
Relative jump, unconditional or conditional
JNE
Jump-on-equal bit = 0
Table 6-2. Address Mode Descriptions
ADDRESS MODE
S (1)
D (1)
SYNTAX
EXAMPLE
Register
+
+
MOV Rs,Rd
MOV R10,R11
R10 → R11
Indexed
+
+
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) → M(6+R6)
Symbolic (PC relative)
+
+
MOV EDE,TONI
Absolute
+
+
MOV & MEM, & TCDAT
Indirect
+
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) → M(Tab+R6)
Indirect autoincrement
+
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) → R11
R10 + 2 → R10
Immediate
+
MOV #X,TONI
MOV #45,TONI
#45 → M(TONI)
(1)
S = source, D = destination
64
Detailed Description
OPERATION
M(EDE) → M(TONI)
M(MEM) → M(TCDAT)
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6.3
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Operating Modes
These microcontrollers have one active mode and seven software-selectable low-power modes of
operation. An interrupt event can wake up the device from any of the low-power modes, service the
request, and restore back to the low-power mode on return from the interrupt program.
Software can configure the following operating modes:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active
• Low-power mode 1 (LPM1)
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK and FLL loop control and DCOCLK are disabled
– DC generator of the DCO remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– Crystal oscillator is stopped
– Complete data retention
• Low-power mode 3.5 (LPM3.5)
– Internal regulator disabled
– No RAM retention, Backup RAM retained
– I/O pad state retention
– RTC clocked by low-frequency oscillator
– Wake-up input from RST/NMI, RTC_C events, Ports P1 and P2
• Low-power mode 4.5 (LPM4.5)
– Internal regulator disabled
– No RAM retention, Backup RAM retained
– RTC is disabled
– I/O pad state retention
– Wake-up input from RST/NMI, Ports P1 and P2
Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
6.4
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Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see
Table 6-3). The vector contains the 16-bit address of the appropriate interrupt-handler instruction
sequence.
Table 6-3. Interrupt Sources, Flags, and Vectors of MSP430F67xx Configurations
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
System Reset
Power up
External reset
Watchdog time-out, key violation
Flash memory key violation
WDTIFG, KEYV (SYSRSTIV) (1) (2)
Reset
0FFFEh
63, highest
System NMI
PMM
Vacant memory access
JTAG mailbox
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,
JMBOUTIFG (SYSSNIV) (1) (3)
(Non)maskable
0FFFCh
62
User NMI
NMI
Oscillator fault
Flash memory access violation
Supply switch
NMIIFG, OFIFG, ACCVIFG, AUXSWNMIFG
(SYSUNIV) (1) (3)
(Non)maskable
0FFFAh
61
Watchdog Timer_A interval timer
mode
WDTIFG
Maskable
0FFF8h
60
eUSCI_A0 receive or transmit
UCA0RXIFG, UCA0TXIFG (UCA0IV) (1) (4)
Maskable
0FFF6h
59
eUSCI_B0 receive or transmit
UCB0RXIFG, UCB0TXIFG (UCB0IV) (1) (4)
Maskable
0FFF4h
58
ADC10_A
ADC10IFG0, ADC10INIFG, ADC10LOIFG,
ADC10HIIFG, ADC10TOVIFG, ADC10OVIFG
(ADC10IV) (1) (4)
Maskable
0FFF2h
57
SD24_B
SD24_B Interrupt Flags (SD24IV) (1) (4)
Maskable
0FFF0h
56
Timer TA0
TA0CCR0 CCIFG0 (4)
Maskable
0FFEEh
55
Timer TA0
TA0CCR1 CCIFG1, TA0CCR2 CCIFG2,
TA0IFG (TA0IV) (1) (4)
Maskable
0FFECh
54
eUSCI_A1 receive or transmit
UCA1RXIFG, UCA1TXIFG (UCA1IV)
(1) (4)
Maskable
0FFEAh
53
eUSCI_A2 receive or transmit
UCA2RXIFG, UCA2TXIFG (UCA2IV) (1) (4)
Maskable
0FFE8h
52
(1) (4)
Maskable
0FFE6h
51
DMA
DMA0IFG, DMA1IFG, DMA2IFG (DMAIV) (1) (4)
Maskable
0FFE4h
50
Timer TA1
TA1CCR0 CCIFG0 (4)
Maskable
0FFE2h
49
Timer TA1
TA1CCR1 CCIFG1,
TA1IFG (TA1IV) (1) (4)
Maskable
0FFE0h
48
Maskable
0FFDEh
47
Maskable
0FFDCh
46
Maskable
0FFDAh
45
Auxiliary supplies
I/O port P1
P1IFG.0 to P1IFG.7 (P1IV)
Timer TA2
TA2CCR0 CCIFG0 (4)
Timer TA2
TA2CCR1 CCIFG1,
TA2IFG (TA2IV) (1) (4)
I/O port P2
(1)
(2)
(3)
(4)
66
Auxiliary Supplies Interrupt Flags (AUXIV)
P2IFG.0 to P2IFG.7 (P2IV)
(1) (4)
(1) (4)
Maskable
0FFD8h
44
Timer TA3
TA3CCR0 CCIFG0
(4)
Maskable
0FFD6h
43
Timer TA3
TA3CCR1 CCIFG1,
TA3IFG (TA3IV) (1) (4)
Maskable
0FFD4h
42
LCD_C
LCD_C Interrupt Flags (LCDCIV) (1) (4)
Maskable
0FFD2h
41
RTC_C
RTCOFIFG, RTCRDYIFG, RTCTEVIFG,
RTCAIFG, RT0PSIFG, RT1PSIFG (RTCIV) (1) (4)
Maskable
0FFD0h
40
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot disable it.
Interrupt flags are in the module.
Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 6-3. Interrupt Sources, Flags, and Vectors of MSP430F67xx Configurations (continued)
(5)
INTERRUPT SOURCE
INTERRUPT FLAG
Reserved
Reserved (5)
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
0FFCEh
39
⋮
⋮
0FF80h
0, lowest
Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, TI recommends reserving these locations.
6.5
Memory Organization
Table 6-4 and Table 6-5 summarize the memory map for the devices.
Table 6-4. Memory Organization
Main Memory
(flash)
MSP430F6730
MSP430F6720
MSP430F6731
MSP430F6721
MSP430F6733
MSP430F6723
16KB
32KB
64KB
00FFFFh to 00FF80h
00FFFFh to 00FF80h
00FFFFh to 00FF80h
Bank 3
not available
not available
not available
Bank 2
not available
not available
not available
Bank 1
not available
16KB
00FFFFh to 00C000h
32KB
013FFFh to 00C000h
Bank 0
16KB
00FFFFh to 00C000h
16KB
00BFFFh to 008000h
32KB
00BFFFh to 004000h
Total Size
Main: Interrupt
vector
Main: code
memory
Total Size
1KB
2KB
4KB
Sector 3
not available
not available
not available
Sector 2
not available
not available
not available
Sector 1
not available
not available
2KB
002BFFh to 002400h
Sector 0
1KB
001FFFh to 001C00h
2KB
0023FFh to 001C00h
2KB
0023FFh to 001C00h
Info A
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
Info B
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
Info C
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
Info D
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
BSL 3
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
BSL 2
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
BSL 1
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
BSL 0
512 B
0011FFh to 001000h
512 B
0011FFh to 001000h
512 B
0011FFh to 001000h
4KB
000FFFh to 0h
4KB
000FFFh to 0h
4KB
000FFFh to 0h
RAM
Information
memory (flash)
Bootloader (BSL)
memory (flash)
Peripherals
Detailed Description
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Table 6-5. Memory Organization
MSP430F6734
MSP430F6724
MSP430F6735
MSP430F6725
MSP430F6736
MSP430F6726
96KB
128KB
128KB
00FFFFh to 00FF80h
00FFFFh to 00FF80h
00FFFFh to 00FF80h
Bank 3
not available
32KB
023FFFh to 01C000h
32KB
023FFFh to 01C000h
Bank 2
32KB
01BFFFh to 014000h
32KB
01BFFFh to 014000h
32KB
01BFFFh to 014000h
Bank 1
32KB
013FFFh to 00C000h
32KB
013FFFh to 00C000h
32KB
013FFFh to 00C000h
Bank 0
32KB
00BFFFh to 004000h
32KB
00BFFFh to 004000h
32KB
00BFFFh to 004000h
4KB
4KB
8KB
Sector 3
not available
not available
2KB
003BFFh to 003400h
Sector 2
not available
not available
2KB
0033FFh to 002C00h
Sector 1
2KB
002BFFh to 002400h
2KB
002BFFh to 002400h
2KB
002BFFh to 002400h
Sector 0
2KB
0023FFh to 001C00h
2KB
0023FFh to 001C00h
2KB
0023FFh to 001C00h
Info A
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
Info B
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
Info C
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
Info D
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
BSL 3
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
BSL 2
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
BSL 1
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
BSL 0
512 B
0011FFh to 001000h
512 B
0011FFh to 001000h
512 B
0011FFh to 001000h
4KB
000FFFh to 0h
4KB
000FFFh to 0h
4KB
000FFFh to 0h
Total
Size
Main Memory (flash)
Main: Interrupt vector
Main: code memory
Total
Size
RAM
Information memory
(flash)
Bootloader (BSL)
memory (flash)
Peripherals
68
Detailed Description
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6.6
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Bootloader (BSL)
The BSL enables users to program the flash memory or RAM using various serial interfaces. Access to
the device memory through the BSL is protected by an user-defined password. BSL entry requires a
specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For complete description of
the features of the BSL and its implementation, see MSP430™ Flash Device Bootloader (BSL) User's
Guide. Table 6-6 lists the BSL pin requirements.
Table 6-6. UART BSL Pin Requirements and Functions
6.7
6.7.1
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P3.0
Data transmit
P3.1
Data receive
DVCC
Power supply
DVSS
Ground supply
JTAG Operation
JTAG Standard Interface
The MSP430 family supports the standard JTAG interface, which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to
enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with
MSP430 development tools and device programmers. Table 6-7 lists the JTAG pin requirements. For
further details on interfacing to development tools and device programmers, see the MSP430 Hardware
Tools User's Guide and MSP430 Programming With the JTAG Interface.
Table 6-7. JTAG Pin Requirements and Functions
DEVICE SIGNAL
DIRECTION
FUNCTION
PJ.3/ACLK/TCK
IN
JTAG clock input
PJ.2/ADC10CLK/TMS
IN
JTAG state control
PJ.1/MCLK/TDI/TCLK
IN
JTAG data input and TCLK input
PJ.0/SMCLK/TDO
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
DVCC
Power supply
DVSS
Ground supply
Detailed Description
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
6.7.2
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Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the 2-wire Spy-Bi-Wire interface.
Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. Table 6-8
lists the Spy-Bi-Wire interface pin requirements. For further details on interfacing to development tools and
device programmers, see the MSP430 Hardware Tools User's Guide and MSP430 Programming With the
JTAG Interface.
Table 6-8. Spy-Bi-Wire Pin Requirements and Functions
6.8
DEVICE SIGNAL
DIRECTION
FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input and output
DVCC
Power supply
DVSS
Ground supply
Flash Memory
The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system
by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory.
Features of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are
also called information memory.
• Segment A can be locked separately.
6.9
RAM
The RAM is made up of n sectors. Each sector can be completely powered down to save leakage;
however, all data are lost. Features of the RAM include:
• RAM has n sectors of 2KB each.
• Each sector 0 to n can be complete disabled; however, data retention is lost.
• Each sector 0 to n automatically enters low-power retention mode when possible.
6.10 Backup RAM
The backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5. This
backup RAM is part of the Backup subsystem in MSP430F67xx that operates on dedicated power supply
AUXVCC3. There are 8 bytes of backup RAM available in this device. The backup RAM can be word-wise
accessed through the registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3. The backup RAM
registers cannot be accessed by the CPU when the high-side SVS is disabled by the user.
70
Detailed Description
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
6.11 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be
managed using all instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx
Family User's Guide.
6.11.1 Oscillator and System Clock
The Unified Clock System (UCS) module includes support for a 32768-Hz watch crystal oscillator, an
internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator
(REFO), and an integrated internal digitally controlled oscillator (DCO). The UCS module is designed to
meet the requirements of both low system cost and low power consumption. The UCS module features
digital frequency-locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the
DCO frequency to a programmable multiple of the selected FLL reference frequency. The internal DCO
provides a fast turnon clock source and stabilizes in 3 µs (typical). The UCS module provides the following
clock signals:
• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, the internal low-frequency oscillator
(VLO), or the trimmed low-frequency oscillator (REFO).
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be
sourced by same sources made available to ACLK.
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
6.11.2 Power Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and
contains programmable output levels to provide for power optimization. The PMM also includes supply
voltage supervisor (SVS) and supply voltage monitor (SVM) circuitry, as well as brownout protection. The
brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The SVS and SVM circuitry detects if the supply voltage drops below a user-selectable
level and supports both supply voltage supervision (the device is automatically reset) and supply voltage
monitoring (the device is not automatically reset). SVS and SVM circuitry is available on the primary
supply and core supply.
6.11.3 Auxiliary Supply System
The auxiliary supply system provides the possibility to operate the device from auxiliary supplies when the
primary supply fails.There are two auxililary supplies AUXVCC1 and AUXVCC2 supported in
MSP430F67xx. This module supports automatic and manual switching from primary supply to auxiliary
suppllies while maintaining full functionality. It allows threshold based monitoring of primary and auxiliary
supplies. The device can be started from primary supply or from AUXVCC1, whichever is higher. The
auxiliary supply system enables internal monitoring of voltage levels on the primary and auxiliary supplies
using ADC10_A. This module also implements a simple charger for the backup supplies.
6.11.4 Backup Subsystem
The backup subsystem operates on a dedicated power supply, AUXVCC3. This subsystem includes lowfrequency oscillator (XT1), RTC module, and backup RAM. The functionality of backup subsystem is
retained during LPM3.5. The backup subsystem module registers cannot be accessed by CPU when the
high-side SVS is disabled by the user. Keep the high-side SVS enabled (SVSHMD = 1 and SVSMHACE =
0) to turn off the low-frequency oscillator (XT1) in LPM4.
Detailed Description
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6.11.5 Digital I/O
Up to nine 8-bit I/O ports are implemented. For 100-pin options, Ports P1 to P8 are complete, and P9 is
reduced to 4-bit I/O. For 80-pin options, Ports P1 to P6 are complete, and P7, P8, and P9 are completely
removed. Port PJ contains four individual I/O pins, common to all devices. All I/O bits are individually
programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Pullup or pulldown on all ports is programmable.
• Programmable drive strength on all ports.
• Edge-selectable interrupt and LPM3.5 or LPM4.5 wake-up input are available for all bits of ports P1
and P2.
• Read and write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise (P1 through P9) or word-wise in pairs (PA through PE).
6.11.6 Port Mapping Controller
The port mapping controller allows flexible and reconfigurable mapping of digital functions to P1, P2, and
P3 (see Table 6-9). Table 6-10 lists the default settings for all pins that support port mapping.
Table 6-9. Port Mapping Mnemonics and Functions
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
0
PM_NONE
None
DVSS
1
2
3
4
5
6
eUSCI_A0 UART RXD (direction controlled by eUSCI – Input)
PM_UCA0SOMI
eUSCI_A0 SPI slave out master in (direction controlled by eUSCI)
PM_UCA0TXD
eUSCI_A0 UART TXD (direction controlled by eUSCI – Output)
PM_UCA0SIMO
eUSCI_A0 SPI slave in master out (direction controlled by eUSCI)
PM_UCA0CLK
eUSCI_A0 clock input/output (direction controlled by eUSCI)
PM_UCA0STE
eUSCI_A0 SPI slave transmit enable (direction controlled by eUSCI)
PM_UCA1RXD
eUSCI_A1 UART RXD (direction controlled by eUSCI – Input)
PM_UCA1SOMI
eUSCI_A1 SPI slave out master in (direction controlled by eUSCI)
PM_UCA1TXD
eUSCI_A1 UART TXD (direction controlled by eUSCI – Output)
PM_UCA1SIMO
eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)
7
PM_UCA1CLK
eUSCI_A1 clock input/output (direction controlled by eUSCI)
8
PM_UCA1STE
eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI)
9
10
PM_UCA2RXD
eUSCI_A2 UART RXD (direction controlled by eUSCI – Input)
PM_UCA2SOMI
eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)
PM_UCA2TXD
eUSCI_A2 UART TXD (direction controlled by eUSCI – Output)
PM_ UCA2SIMO
eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)
11
PM_UCA2CLK
eUSCI_A2 clock input/output (direction controlled by eUSCI)
12
PM_UCA2STE
eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI)
13
14
72
PM_UCA0RXD
PM_UCB0SIMO
eUSCI_B0 SPI slave in master out (direction controlled by eUSCI)
PM_UCB0SDA
eUSCI_B0 I2C data (open drain and direction controlled by eUSCI)
PM_UCB0SOMI
eUSCI_B0 SPI slave out master in (direction controlled by eUSCI)
PM_UCB0SCL
eUSCI_B0 I2C clock (open drain and direction controlled by eUSCI)
15
PM_UCB0CLK
eUSCI_B0 clock input/output (direction controlled by eUSCI)
16
PM_UCB0STE
eUSCI_B0 SPI slave transmit enable (direction controlled by eUSCI)
17
PM_TA0.0
TA0 CCR0 capture input CCI0A
TA0 CCR0 compare output Out0
18
PM_TA0.1
TA0 CCR1 capture input CCI1A
TA0 CCR1 compare output Out1
19
PM_TA0.2
TA0 CCR2 capture input CCI2A
TA0 CCR2 compare output Out2
20
PM_TA1.0
TA1 CCR0 capture input CCI0A
TA1 CCR0 compare output Out0
21
PM_TA1.1
TA1 CCR1 capture input CCI1A
TA1 CCR1 compare output Out1
Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 6-9. Port Mapping Mnemonics and Functions (continued)
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
22
PM_TA2.0
TA2 CCR0 capture input CCI0A
TA2 CCR0 compare output Out0
23
PM_TA2.1
TA2 CCR1 capture input CCI1A
TA2 CCR1 compare output Out1
24
PM_TA3.0
TA3 CCR0 capture input CCI0A
TA3 CCR0 compare output Out0
25
PM_TA3.1
TA3 CCR1 capture input CCI1A
TA3 CCR1 compare output Out1
PM_TACLK
Timer_A clock input to
TA0, TA1, TA2, TA3
None
None
RTC_C clock output
26
PM_RTCCLK
(1)
27
PM_SDCLK
SD24_B bitstream clock input/output (direction controlled by SD24_B)
28
PM_SD0DIO
SD24_B converter-0 bitstream data input/output (direction controlled by SD24_B)
29
PM_SD1DIO
SD24_B converter-1 bitstream data input/output (direction controlled by SD24_B)
30
PM_SD2DIO
SD24_B converter-2 bitstream data input/output (direction controlled by SD24_B)
31 (0FFh) (1)
PM_ANALOG
Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents
when applying analog signals.
The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide, and the upper bits are
ignored, which results in a read value of 31.
Table 6-10. Default Mapping
PIN NAME
PZ
PN
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
P1.0/PM_TA0.0/
VeREF-/A2
P1.0/PM_TA0.0/
VeREF-/A2
PM_TA0.0
TA0 CCR0 capture input CCI0A
TA0 CCR0 compare output Out0
P1.1/PM_TA0.1/
VeREF+/A1
P1.1/PM_TA0.1/
VeREF+/A1
PM_TA0.1
TA0 CCR1 capture input CCI1A
TA0 CCR1 compare output Out1
P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A0
P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A0
PM_UCA0RXD,
PM_UCA0SOMI
eUSCI_A0 UART RXD
(direction controlled by eUSCI – input),
eUSCI_A0 SPI slave out master in
(direction controlled by eUSCI)
P1.3/PM_UCA0TXD/
PM_UCA0SIMO/R03
P1.3/PM_UCA0TXD/
PM_UCA0SIMO/R03
PM_UCA0TXD,
PM_UCA0SIMO
eUSCI_A0 UART TXD
(direction controlled by eUSCI – output),
eUSCI_A0 SPI slave in master out
(direction controlled by eUSCI)
P1.4/PM_UCA1RXD/
PM_UCA1SOMI/
LCDREF/R13
P1.4/PM_UCA1RXD/
PM_UCA1SOMI/
LCDREF/R13
PM_UCA1RXD,
PM_UCA1SOMI
eUSCI_A1 UART RXD
(direction controlled by eUSCI – input),
eUSCI_A1 SPI slave out master in
(direction controlled by eUSCI)
P1.5/PM_UCA1TXD/
PM_UCA1SIMO/R23
P1.5/PM_UCA1TXD/
PM_UCA1SIMO/R23
PM_UCA1TXD,
PM_UCA1SIMO
eUSCI_A1 UART TXD
(direction controlled by eUSCI – output),
eUSCI_A1 SPI slave in master out
(direction controlled by eUSCI)
P1.6/PM_UCA0CLK/
COM4
P1.6/PM_UCA0CLK/
COM4
PM_UCA0CLK
eUSCI_A0 clock input/output (direction controlled by eUSCI)
P1.7/PM_UCB0CLK/
COM5
P1.7/PM_UCB0CLK/
COM5
PM_UCB0CLK
eUSCI_B0 clock input/output (direction controlled by eUSCI)
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6/S39
PM_UCB0SOMI,
PM_UCB0SCL
eUSCI_B0 SPI slave out master in
(direction controlled by eUSCI),
eUSCI_B0 I2C clock
(open drain and direction controlled by eUSCI)
P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7
P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7/S38
PM_UCB0SIMO,
PM_UCB0SDA
eUSCI_B0 SPI slave in master out
(direction controlled by eUSCI),
eUSCI_B0 I2C data
(open drain and direction controlled by eUSCI)
P2.2/PM_UCA2RXD/
PM_UCA2SOMI
P2.2/PM_UCA2RXD/
PM_UCA2SOMI/S37
PM_UCA2RXD,
PM_UCA2SOMI
eUSCI_A2 UART RXD
(direction controlled by eUSCI – input),
eUSCI_A2 SPI slave out master in
(direction controlled by eUSCI)
P2.3/PM_UCA2TXD/
PM_UCA2SIMO
P2.3/PM_UCA2TXD/
PM_UCA2SIMO/S36
PM_UCA2TXD,
PM_UCA2SIMO
eUSCI_A2 UART TXD
(direction controlled by eUSCI – output),
eUSCI_A2 SPI slave in master out
(direction controlled by eUSCI)
P2.4/PM_UCA1CLK
P2.4/PM_UCA1CLK/S35
PM_UCA1CLK
eUSCI_A1 clock input/output (direction controlled by eUSCI)
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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Table 6-10. Default Mapping (continued)
PIN NAME
PZ
PN
PxMAPy MNEMONIC
INPUT PIN FUNCTION
PM_UCA2CLK
OUTPUT PIN FUNCTION
P2.5/PM_UCA2CLK
P2.5/PM_UCA2CLK/S34
P2.6/PM_TA1.0
P2.6/PM_TA1.0/S33
PM_TA1.0
TA1 CCR0 capture input CCI0A
eUSCI_A2 clock input/output (direction controlled by eUSCI)
TA1 CCR0 compare output Out0
P2.7/PM_TA1.1
P2.7/PM_TA1.1/S32
PM_TA1.1
TA1 CCR1 capture input CCI1A
TA1 CCR1 compare output Out1
P3.0/PM_TA2.0
P3.0/PM_TA2.0/S31
PM_TA2.0
TA2 CCR0 capture input CCI0A
TA2 CCR0 compare output Out0
P3.1/PM_TA2.1
P3.1/PM_TA2.1/S30
PM_TA2.1
TA2 CCR1 capture input CCI1A
TA2 CCR1 compare output Out1
P3.2/PM_TACLK/
PM_RTCCLK
P3.2/PM_TACLK/
PM_RTCCLK/S29
PM_TACLK,
PM_RTCCLK
Timer_A clock input to
TA0, TA1, TA2, TA3
RTC_C clock output
P3.3/PM_TA0.2
P3.3/PM_TA0.2/S28
PM_TA0.2
TA0 CCR2 capture input CCI2A
TA0 CCR2 compare output Out2
P3.4/PM_SDCLK/S39
P3.4/PM_SDCLK/S27
PM_SDCLK
SD24_B bitstream clock input/output
(direction controlled by SD24_B)
P3.5/PM_SD0DIO/S38
P3.5/PM_SD0DIO/S26
PM_SD0DIO
SD24_B converter-0 bitstream data input/output
(direction controlled by SD24_B)
P3.6/PM_SD1DIO/S37
P3.6/PM_SD1DIO/S25
PM_SD1DIO
SD24_B converter-1 bitstream data input/output
(direction controlled by SD24_B)
P3.7/PM_SD2DIO/S36
P3.7/PM_SD2DIO/S24
PM_SD2DIO
SD24_B converter-2 bitstream data input/output
(direction controlled by SD24_B)
6.11.7 System Module (SYS)
The SYS module handles many of the system functions within the device. These include power-on reset
(POR) and power-up clear (PUC) handling, NMI source selection and management, reset interrupt vector
generators, bootloader entry mechanisms, as well as, configuration management (device descriptors). It
also includes a data exchange mechanism through JTAG called a JTAG mailbox that can be used in the
application. Table 6-11 lists the SYS module interrupt vector registers.
Table 6-11. System Module Interrupt Vector Registers
INTERRUPT VECTOR REGISTER
SYSRSTIV, System Reset
74
Detailed Description
INTERRUPT EVENT
WORD
ADDRESS
OFFSET
No interrupt pending
00h
Brownout (BOR)
02h
RST/NMI (POR)
04h
DoBOR (BOR)
06h
Wakeup from LPMx.5 (BOR)
08h
Security violation (BOR)
0Ah
SVSL (POR)
0Ch
SVSH (POR)
0Eh
SVML_OVP (POR)
SVMH_OVP (POR)
019Eh
PRIORITY
Highest
10h
12h
DoPOR (POR)
14h
WDT time-out (PUC)
16h
WDT key violation (PUC)
18h
KEYV flash key violation (PUC)
1Ah
Reserved
1Ch
Peripheral area fetch (PUC)
1Eh
PMM key violation (PUC)
20h
Reserved
22h to 3Eh
Lowest
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 6-11. System Module Interrupt Vector Registers (continued)
INTERRUPT VECTOR REGISTER
INTERRUPT EVENT
WORD
ADDRESS
OFFSET
No interrupt pending
00h
SVMLIFG
02h
SVMHIFG
04h
DLYLIFG
06h
DLYHIFG
SYSSNIV, System NMI
Highest
08h
VMAIFG
019Ch
0Ah
JMBINIFG
0Ch
JMBOUTIFG
0Eh
VLRLIFG
10h
VLRHIFG
12h
Reserved
14h to 1Eh
No interrupt pending
00h
NMIIFG
02h
OFIFG
SYSUNIV, User NMI
PRIORITY
019Ah
ACCVIFG
Lowest
Highest
04h
06h
AUXSWNMIFG
08h
Reserved
0Ah to 1Eh
Lowest
6.11.8 Watchdog Timer (WDT_A)
The primary function of the WDT_A module is to perform a controlled system restart after a software
problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function
is not needed in an application, the timer can be configured as an interval timer and can generate
interrupts at selected time intervals.
6.11.9 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC10_A conversion
memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode, without
having to awaken to move data to or from a peripheral. Table 6-12 lists the triggers that are available to
start DMA transfer.
Table 6-12. DMA Trigger Assignments (1)
TRIGGER
(1)
CHANNEL
0
1
0
DMAREQ
1
TA0CCR0 CCIFG
2
TA0CCR2 CCIFG
3
TA1CCR0 CCIFG
4
Reserved
5
TA2CCR0 CCIFG
6
Reserved
7
TA3CCR0 CCIFG
8
Reserved
2
Reserved DMA triggers may be used by other devices in the family.
Reserved DMA triggers do not cause a DMA trigger event when
selected.
Detailed Description
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Table 6-12. DMA Trigger Assignments(1) (continued)
TRIGGER
CHANNEL
0
1
9
Reserved
10
Reserved
11
Reserved
12
Reserved
13
SD24IFG
14
Reserved
15
Reserved
16
UCA0RXIFG
17
UCA0TXIFG
18
UCA1RXIFG
19
UCA1TXIFG
20
UCA2RXIFG
21
UCA2TXIFG
22
UCB0RXIFG0
23
UCB0TXIFG0
24
ADC10IFG0
25
Reserved
26
Reserved
27
Reserved
28
Reserved
29
30
31
2
MPY ready
DMA2IFG
DMA0IFG
DMA1IFG
Reserved
6.11.10 CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
6.11.11 Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs
operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication
as well as signed and unsigned multiply-and-accumulate operations.
6.11.12 Enhanced Universal Serial Communication Interface (eUSCI)
The eUSCI module is used for serial data communication. The eUSCI module supports synchronous
communication protocols such as SPI (3- or 4-pin) and I2C, and asynchronous communication protocols
such as UART, enhanced UART with automatic baudrate detection, and IrDA.
The eUSCI_An module supports for SPI (3- or 4-pin), UART, enhanced UART, or IrDA.
The eUSCI_Bn module supports for SPI (3- or 4-pin) or I2C.
Three eUSCI_A and one eUSCI_B modules are implemented in MSP430F67xx devices.
76
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
6.11.13 ADC10_A
The ADC10_A module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit
SAR core, sample select control, reference generator, and a conversion results buffer. A window
comparator with a lower and upper limits allows CPU-independent result monitoring with three window
comparator interrupt flags.
6.11.14 SD24_B
The SD24_B module integrates up to three independent 24-bit sigma-delta analog-to-digital converters.
Each converter is designed with a fully differential analog input pair and programmable gain amplifier input
stage. The converters are based on second-order over-sampling sigma-delta modulators and digital
decimation filters. The decimation filters are comb type filters with selectable oversampling ratios of up to
1024.
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6.11.15 TA0
TA0 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA0 can support
multiple capture/compares, PWM outputs, and interval timing (see Table 6-13). TA0 also has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each
of the capture/compare registers.
Table 6-13. TA0 Signal Connections
DEVICE INPUT SIGNAL
MODULE INPUT NAME
PM_TACLK
TACLK
MODULE BLOCK
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
Timer
NA
NA
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
PM_TACLK
INCLK
PM_TA0.0
CCI0A
DVSS
CCI0B
DVSS
GND
DVCC
VCC
PM_TA0.1
CCI1A
PM_TA0.1
ACLK (internal)
CCI1B
ADC10_A (internal)
ADC10SHSx = {1}
DVSS
GND
PM_TA0.0
CCR0
TA0
CCR1
DVCC
VCC
PM_TA0.2
CCI2A
DVSS
CCI2B
DVSS
GND
DVCC
VCC
TA1
SD24_B (internal)
SD24SCSx = {1}
PM_TA0.2
CCR2
TA2
6.11.16 TA1
TA1 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA1 can support multiple
capture/compares, PWM outputs, and interval timing (see Table 6-14). TA1 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-14. TA1 Signal Connections
DEVICE INPUT SIGNAL
MODULE INPUT NAME
PM_TACLK
TACLK
78
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
PM_TACLK
INCLK
PM_TA1.0
CCI0A
DVSS
CCI0B
DVSS
GND
DVCC
VCC
PM_TA1.1
CCI1A
ACLK (internal)
CCI1B
DVSS
GND
DVCC
VCC
Detailed Description
MODULE BLOCK
Timer
MODULE OUTPUT
SIGNAL
NA
DEVICE OUTPUT
SIGNAL
PZ
NA
PM_TA1.0
CCR0
TA0
PM_TA1.1
CCR1
TA1
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6.11.17 TA2
TA2 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA2 can support multiple
capture/compares, PWM outputs, and interval timing (see Table 6-15). TA2 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-15. TA2 Signal Connections
DEVICE INPUT SIGNAL
MODULE INPUT NAME
PM_TACLK
TACLK
MODULE BLOCK
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
Timer
NA
NA
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
PM_TACLK
INCLK
PM_TA2.0
CCI0A
DVSS
CCI0B
DVSS
GND
DVCC
VCC
PM_TA2.1
CCI1A
PM_TA2.1
ACLK (internal)
CCI1B
SD24_B (internal)
SD24SCSx = {2}
DVSS
GND
DVCC
VCC
PM_TA2.0
CCR0
TA0
CCR1
TA1
6.11.18 TA3
TA3 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA3 can support multiple
capture/compares, PWM outputs, and interval timing (see Table 6-16). TA3 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-16. TA3 Signal Connections
DEVICE INPUT SIGNAL
MODULE INPUT NAME
PM_TACLK
TACLK
MODULE BLOCK
MODULE OUTPUT
SIGNAL
Timer
NA
DEVICE OUTPUT
SIGNAL
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
PM_TACLK
INCLK
PM_TA3.0
CCI0A
PM_TA3.0
DVSS
CCI0B
TA0
ADC10_A (internal)
ADC10SHSx = {2}
DVSS
GND
TA1
CCR0
DVCC
VCC
PM_TA3.1
CCI1A
PM_TA3.1
ACLK (internal)
CCI1B
SD24_B (internal)
SD24SCSx = {3}
DVSS
GND
DVCC
VCC
CCR1
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6.11.19 SD24_B Triggers
Table 6-17 lists the input trigger connections to SD24_B converters from Timer_A modules and output
trigger pulse connection from SD24_B to ADC10_A.
Table 6-17. SD24_B Input/Output Trigger Connections
DEVICE INPUT SIGNAL MODULE INPUT SIGNAL
TA0.1 (internal)
SD24_B
SD24SCSx = {1}
TA2.1 (internal)
SD24_B
SD24SCSx = {2}
TA3.1 (internal)
SD24_B
SD24SCSx = {3}
MODULE BLOCK
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
Trigger Pulse
ADC10_A (internal)
ADC10SHSx = {3}
SD24_B
6.11.20 ADC10_A Triggers
Table 6-18 lists the input trigger connections to ADC10_A from Timer_A modules and SD24_B.
Table 6-18. ADC10_A Input Trigger Connections
DEVICE INPUT SIGNAL
MODULE INPUT SIGNAL
TA0.1 (internal)
ADC10_A
ADC10SHSx = {1}
TA3.0 (internal)
ADC10_A
ADC10SHSx = {2}
SD24_B
trigger pulse (internal)
ADC10_A
ADC10SHSx = {3}
MODULE BLOCK
ADC10_A
6.11.21 Real-Time Clock (RTC_C)
The RTC_C module can be configured for calendar mode providing seconds, hours, day of week, day of
month, month, and year. The RTC_C control and configuration registers are password protected to ensure
clock integrity against runaway code. Calendar mode integrates an internal calendar that compensates for
months with less than 31 days and includes leap year correction. The RTC_C also supports flexible alarm
functions, offset calibration, and temperature compensation. The RTC_C on this device operates on
dedicated AUXVCC3 supply and supports operation in LPM3.5.
6.11.22 Reference (REF) Module Voltage Reference
The REF module generates all critical reference voltages that can be used by the various analog
peripherals in the device. These include the ADC10_A, LCD_C, and SD24_B modules.
6.11.23 LCD_C
The LCD_C driver generates the segment and common signals required to drive a liquid crystal display
(LCD). The LCD_C controller has dedicated data memories to hold segment drive information. Common
and segment signals are generated as defined by the mode. Static, 2-mux, 3-mux, 4-mux, up to 8-mux
LCDs are supported. The module can provide a LCD voltage independent of the supply voltage with its
integrated charge pump. It is possible to control the level of the LCD voltage, and thus contrast, by
software. The module also provides an automatic blinking capability for individual segments in static,
2‑mux, 3-mux, and 4-mux modes.
80
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6.11.24 Embedded Emulation Module (EEM) (S Version)
The EEM supports real-time in-system debugging. The S version of the EEM has the following features:
• Three hardware triggers or breakpoints on memory access
• One hardware trigger or breakpoint on CPU register write access
• Up to four hardware triggers can be combined to form complex triggers or breakpoints
• One cycle counter
• Clock control on module level
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6.11.25 Peripheral File Map
Table 6-19 lists the base address for the registers of each supported peripheral.
Table 6-19. Peripherals
BASE ADDRESS
OFFSET ADDRESS
RANGE
Special Functions (see Table 6-20)
0100h
000h to 01Fh
PMM (see Table 6-21)
0120h
000h to 01Fh
Flash Control (see Table 6-22)
0140h
000h to 00Fh
CRC16 (see Table 6-23)
0150h
000h to 007h
RAM Control (see Table 6-24)
0158h
000h to 001h
Watchdog (see Table 6-25)
015Ch
000h to 001h
UCS (see Table 6-26)
0160h
000h to 01Fh
SYS (see Table 6-27)
0180h
000h to 01Fh
Shared Reference (see Table 6-28)
01B0h
000h to 001h
Port Mapping Control (see Table 6-29)
01C0h
000h to 007h
Port Mapping Port P1 (see Table 6-30)
01C8h
000h to 007h
Port Mapping Port P2 (see Table 6-31)
01D0h
000h to 007h
Port Mapping Port P3 (see Table 6-32)
01D8h
000h to 007h
Port P1 and P2 (see Table 6-33)
0200h
000h to 01Fh
Port P3 and P4 (see Table 6-34)
0220h
000h to 00Bh
Port P5 and P6 (see Table 6-35)
0240h
000h to 00Bh
Port P7 and P8 (see Table 6-36)
(Port P7 and P8 not available in MSP430F67xxIPN)
0260h
000h to 00Bh
Port P9 (Port P9 not available in MSP430F67xxIPN)
(see Table 6-37)
0280h
000h to 00Bh
Port PJ (refer toTable 6-38)
0320h
000h to 01Fh
Timer TA0 (see Table 6-39)
0340h
000h to 03Fh
Timer TA1 (see Table 6-40)
0380h
000h to 03Fh
Timer TA2 (see Table 6-41)
0400h
000h to 03Fh
Timer TA3 (see Table 6-42)
0440h
000h to 03Fh
Backup Memory (see Table 6-43)
0480h
000h to 00Fh
RTC_C (see Table 6-44)
04A0h
000h to 01Fh
32-Bit Hardware Multiplier (see Table 6-45)
04C0h
000h to 02Fh
DMA General Control (see Table 6-46)
0500h
000h to 00Fh
DMA Channel 0 (see Table 6-47)
0500h
010h to 01Fh
DMA Channel 1 (see Table 6-48)
0500h
020h to 02Fh
DMA Channel 2 (see Table 6-49)
0500h
030h to 03Fh
eUSCI_A0 (see Table 6-50)
05C0h
000h to 01Fh
eUSCI_A1 (see Table 6-51)
05E0h
000h to 01Fh
eUSCI_A2 (see Table 6-52)
0600h
000h to 01Fh
eUSCI_B0 (see Table 6-53)
0640h
000h to 02Fh
ADC10_A (see Table 6-54)
0740h
000h to 01Fh
SD24_B(see Table 6-55)
0800h
000h to 06Fh
Auxiliary Supply (see Table 6-49)
09E0h
000h to 01Fh
LCD_C (see Table 6-57)
0A00h
000h to 05Fh
MODULE NAME
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 6-20. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SFR interrupt enable
SFRIE1
00h
SFR interrupt flag
SFRIFG1
02h
SFR reset pin control
SFRRPCR
04h
Table 6-21. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
OFFSET
PMM control 0
PMMCTL0
00h
PMM control 1
PMMCTL1
02h
SVS high-side control
SVSMHCTL
04h
SVS low-side control
SVSMLCTL
06h
PMM interrupt flags
PMMIFG
0Ch
PMM interrupt enable
PMMIE
0Eh
PMM power mode 5 control 0
PM5CTL0
10h
Table 6-22. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Flash control 1
FCTL1
00h
Flash control 3
FCTL3
04h
Flash control 4
FCTL4
06h
Table 6-23. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
OFFSET
CRC data input
CRC16DI
00h
CRC data input reverse byte
CRC16DIRB
02h
CRC result
CRCINIRES
04h
CRC result reverse byte
CRCRESR
06h
Table 6-24. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION
RAM control 0
REGISTER
RCCTL0
OFFSET
00h
Table 6-25. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
Watchdog timer control
REGISTER
WDTCTL
OFFSET
00h
Table 6-26. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
OFFSET
UCS control 0
UCSCTL0
00h
UCS control 1
UCSCTL1
02h
UCS control 2
UCSCTL2
04h
UCS control 3
UCSCTL3
06h
UCS control 4
UCSCTL4
08h
UCS control 5
UCSCTL5
0Ah
UCS control 6
UCSCTL6
0Ch
UCS control 7
UCSCTL7
0Eh
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Table 6-26. UCS Registers (Base Address: 0160h) (continued)
REGISTER DESCRIPTION
UCS control 8
REGISTER
UCSCTL8
OFFSET
10h
Table 6-27. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
OFFSET
System control
SYSCTL
00h
Bootloader configuration area
SYSBSLC
02h
JTAG mailbox control
SYSJMBC
06h
JTAG mailbox input 0
SYSJMBI0
08h
JTAG mailbox input 1
SYSJMBI1
0Ah
JTAG mailbox output 0
SYSJMBO0
0Ch
JTAG mailbox output 1
SYSJMBO1
0Eh
Bus error vector generator
SYSBERRIV
18h
User NMI vector generator
SYSUNIV
1Ah
System NMI vector generator
SYSSNIV
1Ch
Reset vector generator
SYSRSTIV
1Eh
Table 6-28. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
Shared reference control
REGISTER
REFCTL
OFFSET
00h
Table 6-29. Port Mapping Controller (Base Address: 01C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port mapping password
PMAPPWD
00h
Port mapping control
PMAPCTL
02h
Table 6-30. Port Mapping for Port P1 (Base Address: 01C8h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1.0 mapping
P1MAP0
00h
Port P1.1 mapping
P1MAP1
01h
Port P1.2 mapping
P1MAP2
02h
Port P1.3 mapping
P1MAP3
03h
Port P1.4 mapping
P1MAP4
04h
Port P1.5 mapping
P1MAP5
05h
Port P1.6 mapping
P1MAP6
06h
Port P1.7 mapping
P1MAP7
07h
Table 6-31. Port Mapping for Port P2 (Base Address: 01D0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P2.0 mapping
P2MAP0
00h
Port P2.1 mapping
P2MAP2
01h
Port P2.2 mapping
P2MAP2
02h
Port P2.3 mapping
P2MAP3
03h
Port P2.4 mapping
P2MAP4
04h
Port P2.5 mapping
P2MAP5
05h
Port P2.6 mapping
P2MAP6
06h
Port P2.7 mapping
P2MAP7
07h
84
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Table 6-32. Port Mapping for Port P3 (Base Address: 01D8h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3.0 mapping
P3MAP0
00h
Port P3.1 mapping
P3MAP3
01h
Port P3.2 mapping
P3MAP2
02h
Port P3.3 mapping
P3MAP3
03h
Port P3.4 mapping
P3MAP4
04h
Port P3.5 mapping
P3MAP5
05h
Port P3.6 mapping
P3MAP6
06h
Port P3.7 mapping
P3MAP7
07h
Table 6-33. Port P1 and P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1 input
P1IN
00h
Port P1 output
P1OUT
02h
Port P1 direction
P1DIR
04h
Port P1 resistor enable
P1REN
06h
Port P1 drive strength
P1DS
08h
Port P1 selection
P1SEL
0Ah
Port P1 interrupt vector word
P1IV
0Eh
Port P1 interrupt edge select
P1IES
18h
Port P1 interrupt enable
P1IE
1Ah
Port P1 interrupt flag
P1IFG
1Ch
Port P2 input
P2IN
01h
Port P2 output
P2OUT
03h
Port P2 direction
P2DIR
05h
Port P2 resistor enable
P2REN
07h
Port P2 drive strength
P2DS
09h
Port P2 selection
P2SEL
0Bh
Port P2 interrupt vector word
P2IV
1Eh
Port P2 interrupt edge select
P2IES
19h
Port P2 interrupt enable
P2IE
1Bh
Port P2 interrupt flag
P2IFG
1Dh
Table 6-34. Port P3 and P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 input
P3IN
00h
Port P3 output
P3OUT
02h
Port P3 direction
P3DIR
04h
Port P3 resistor enable
P3REN
06h
Port P3 drive strength
P3DS
08h
Port P3 selection
P3SEL
0Ah
Port P4 input
P4IN
01h
Port P4 output
P4OUT
03h
Port P4 direction
P4DIR
05h
Port P4 resistor enable
P4REN
07h
Port P4 drive strength
P4DS
09h
Port P4 selection
P4SEL
0Bh
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85
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MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
www.ti.com
Table 6-35. Port P5 and P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P5 input
P5IN
00h
Port P5 output
P5OUT
02h
Port P5 direction
P5DIR
04h
Port P5 resistor enable
P5REN
06h
Port P5 drive strength
P5DS
08h
Port P5 selection
P5SEL
0Ah
Port P6 input
P6IN
01h
Port P6 output
P6OUT
03h
Port P6 direction
P6DIR
05h
Port P6 resistor enable
P6REN
07h
Port P6 drive strength
P6DS
09h
Port P6 selection
P6SEL
0Bh
Table 6-36. Port P7 and P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P7 input
P7IN
00h
Port P7 output
P7OUT
02h
Port P7 direction
P7DIR
04h
Port P7 resistor enable
P7REN
06h
Port P7 drive strength
P7DS
08h
Port P7 selection
P7SEL
0Ah
Port P8 input
P8IN
01h
Port P8 output
P8OUT
03h
Port P8 direction
P8DIR
05h
Port P8 resistor enable
P8REN
07h
Port P8 drive strength
P8DS
09h
Port P8 selection
P8SEL
0Bh
Table 6-37. Port P9 Registers (Base Address: 0280h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P9 input
P9IN
00h
Port P9 output
P9OUT
02h
Port P9 direction
P9DIR
04h
Port P9 resistor enable
P9REN
06h
Port P9 drive strength
P9DS
08h
Port P9 selection
P9SEL
0Ah
Table 6-38. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port PJ input
PJIN
00h
Port PJ output
PJOUT
02h
Port PJ direction
PJDIR
04h
Port PJ resistor enable
PJREN
06h
Port PJ drive strength
PJDS
08h
Port PJ selection
PJSEL
0Ah
86
Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 6-39. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA0 control
TA0CTL
00h
Capture/compare control 0
TA0CCTL0
02h
Capture/compare control 1
TA0CCTL1
04h
Capture/compare control 2
TA0CCTL2
06h
TA0 counter
TA0R
10h
Capture/compare 0
TA0CCR0
12h
Capture/compare 1
TA0CCR1
14h
Capture/compare 2
TA0CCR2
16h
TA0 expansion 0
TA0EX0
20h
TA0 interrupt vector
TA0IV
2Eh
Table 6-40. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA1 control
TA1CTL
00h
Capture/compare control 0
TA1CCTL0
02h
Capture/compare control 1
TA1CCTL1
04h
TA1 counter
TA1R
10h
Capture/compare 0
TA1CCR0
12h
Capture/compare 1
TA1CCR1
14h
TA1 expansion 0
TA1EX0
20h
TA1 interrupt vector
TA1IV
2Eh
Table 6-41. TA2 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA2 control
TA2CTL
00h
Capture/compare control 0
TA2CCTL0
02h
Capture/compare control 1
TA2CCTL1
04h
TA2 counter
TA2R
10h
Capture/compare 0
TA2CCR0
12h
Capture/compare 1
TA2CCR1
14h
TA2 expansion 0
TA2EX0
20h
TA2 interrupt vector
TA2IV
2Eh
Table 6-42. TA3 Registers (Base Address: 0440h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA3 control
TA3CTL
00h
Capture/compare control 0
TA3CCTL0
02h
Capture/compare control 1
TA3CCTL1
04h
TA3 counter
TA3R
10h
Capture/compare 0
TA3CCR0
12h
Capture/compare 1
TA3CCR1
14h
TA3 expansion 0
TA3EX0
20h
TA3 interrupt vector
TA3IV
2Eh
Detailed Description
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Copyright © 2011–2018, Texas Instruments Incorporated
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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Table 6-43. Backup Memory Registers (Base Address: 0480h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Backup memory 0
BAKMEM0
00h
Backup memory 1
BAKMEM1
02h
Backup memory 2
BAKMEM2
04h
Backup memory 3
BAKMEM3
06h
Table 6-44. RTC_C Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
RTC control 0
RTCCTL0
00h
RTC password
RTCPWD
01h
RTC control 1
RTCCTL1
02h
RTC control 3
RTCCTL3
03h
RTC offset calibration
RTCOCAL
04h
RTC temperature compensation
RTCTCMP
06h
RTC prescaler 0 control
RTCPS0CTL
08h
RTC prescaler 1 control
RTCPS1CTL
0Ah
RTC prescaler 0
RTCPS0
0Ch
RTC prescaler 1
RTCPS1
0Dh
RTC interrupt vector word
RTCIV
0Eh
RTC seconds
RTCSEC
10h
RTC minutes
RTCMIN
11h
RTC hours
RTCHOUR
12h
RTC day of week
RTCDOW
13h
RTC days
RTCDAY
14h
RTC month
RTCMON
15h
RTC year
RTCYEAR
16h
RTC alarm minutes
RTCAMIN
18h
RTC alarm hours
RTCAHOUR
19h
RTC alarm day of week
RTCADOW
1Ah
RTC alarm days
RTCADAY
1Bh
Binary-to-BCD conversion
BIN2BCD
1Ch
BCD-to-binary conversion
BCD2BIN
1Eh
88
Detailed Description
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 6-45. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
16-bit operand 1 – multiply
MPY
00h
16-bit operand 1 – signed multiply
MPYS
02h
16-bit operand 1 – multiply accumulate
MAC
04h
16-bit operand 1 – signed multiply accumulate
MACS
06h
16-bit operand 2
OP2
08h
16 × 16 result low word
RESLO
0Ah
16 × 16 result high word
RESHI
0Ch
16 × 16 sum extension
SUMEXT
0Eh
32-bit operand 1 – multiply low word
MPY32L
10h
32-bit operand 1 – multiply high word
MPY32H
12h
32-bit operand 1 – signed multiply low word
MPYS32L
14h
32-bit operand 1 – signed multiply high word
MPYS32H
16h
32-bit operand 1 – multiply accumulate low word
MAC32L
18h
32-bit operand 1 – multiply accumulate high word
MAC32H
1Ah
32-bit operand 1 – signed multiply accumulate low word
MACS32L
1Ch
32-bit operand 1 – signed multiply accumulate high word
MACS32H
1Eh
32-bit operand 2 – low word
OP2L
20h
32-bit operand 2 – high word
OP2H
22h
32 × 32 result 0 – least significant word
RES0
24h
32 × 32 result 1
RES1
26h
32 × 32 result 2
RES2
28h
32 × 32 result 3 – most significant word
RES3
2Ah
MPY32 control 0
MPY32CTL0
2Ch
Table 6-46. DMA General Control Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA module control 0
DMACTL0
00h
DMA module control 1
DMACTL1
02h
DMA module control 2
DMACTL2
04h
DMA module control 3
DMACTL3
06h
DMA module control 4
DMACTL4
08h
DMA interrupt vector
DMAIV
0Eh
Table 6-47. DMA Channel 0 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 0 control
DMA0CTL
10h
DMA channel 0 source address low
DMA0SAL
12h
DMA channel 0 source address high
DMA0SAH
14h
DMA channel 0 destination address low
DMA0DAL
16h
DMA channel 0 destination address high
DMA0DAH
18h
DMA channel 0 transfer size
DMA0SZ
1Ah
Detailed Description
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Copyright © 2011–2018, Texas Instruments Incorporated
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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Table 6-48. DMA Channel 1 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 1 control
DMA1CTL
20h
DMA channel 1 source address low
DMA1SAL
22h
DMA channel 1 source address high
DMA1SAH
24h
DMA channel 1 destination address low
DMA1DAL
26h
DMA channel 1 destination address high
DMA1DAH
28h
DMA channel 1 transfer size
DMA1SZ
2Ah
Table 6-49. DMA Channel 2 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 2 control
DMA2CTL
30h
DMA channel 2 source address low
DMA2SAL
32h
DMA channel 2 source address high
DMA2SAH
34h
DMA channel 2 destination address low
DMA2DAL
36h
DMA channel 2 destination address high
DMA2DAH
38h
DMA channel 2 transfer size
DMA2SZ
3Ah
Table 6-50. eUSCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_A control word 0
UCA0CTLW0
00h
eUSCI _A control word 1
UCA0CTLW1
02h
eUSCI_A baud rate 0
UCA0BR0
06h
eUSCI_A baud rate 1
UCA0BR1
07h
eUSCI_A modulation control
UCA0MCTLW
08h
eUSCI_A status
UCA0STAT
0Ah
eUSCI_A receive buffer
UCA0RXBUF
0Ch
eUSCI_A transmit buffer
UCA0TXBUF
0Eh
eUSCI_A LIN control
UCA0ABCTL
10h
eUSCI_A IrDA transmit control
UCA0IRTCTL
12h
eUSCI_A IrDA receive control
UCA0IRRCTL
13h
eUSCI_A interrupt enable
UCA0IE
1Ah
eUSCI_A interrupt flags
UCA0IFG
1Ch
eUSCI_A interrupt vector word
UCA0IV
1Eh
90
Detailed Description
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 6-51. eUSCI_A1 Registers (Base Address:05E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_A control word 0
UCA1CTLW0
00h
eUSCI _A control word 1
UCA1CTLW1
02h
eUSCI_A baud rate 0
UCA1BR0
06h
eUSCI_A baud rate 1
UCA1BR1
07h
eUSCI_A modulation control
UCA1MCTLW
08h
eUSCI_A status
UCA1STAT
0Ah
eUSCI_A receive buffer
UCA1RXBUF
0Ch
eUSCI_A transmit buffer
UCA1TXBUF
0Eh
eUSCI_A LIN control
UCA1ABCTL
10h
eUSCI_A IrDA transmit control
UCA1IRTCTL
12h
eUSCI_A IrDA receive control
UCA1IRRCTL
13h
eUSCI_A interrupt enable
UCA1IE
1Ah
eUSCI_A interrupt flags
UCA1IFG
1Ch
eUSCI_A interrupt vector word
UCA1IV
1Eh
Table 6-52. eUSCI_A2 Registers (Base Address:0600h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_A control word 0
UCA2CTLW0
00h
eUSCI _A control word 1
UCA2CTLW1
02h
eUSCI_A baud rate 0
UCA2BR0
06h
eUSCI_A baud rate 1
UCA2BR1
07h
eUSCI_A modulation control
UCA2MCTLW
08h
eUSCI_A status
UCA2STAT
0Ah
eUSCI_A receive buffer
UCA2RXBUF
0Ch
eUSCI_A transmit buffer
UCA2TXBUF
0Eh
eUSCI_A LIN control
UCA2ABCTL
10h
eUSCI_A IrDA transmit control
UCA2IRTCTL
12h
eUSCI_A IrDA receive control
UCA2IRRCTL
13h
eUSCI_A interrupt enable
UCA2IE
1Ah
eUSCI_A interrupt flags
UCA2IFG
1Ch
eUSCI_A interrupt vector word
UCA2IV
1Eh
Detailed Description
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Copyright © 2011–2018, Texas Instruments Incorporated
91
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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Table 6-53. eUSCI_B0 Registers (Base Address: 0640h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_B control word 0
UCB0CTLW0
00h
eUSCI_B control word 1
UCB0CTLW1
02h
eUSCI_B bit rate 0
UCB0BR0
06h
eUSCI_B bit rate 1
UCB0BR1
07h
eUSCI_B status word
UCB0STATW
08h
eUSCI_B byte counter threshold
UCB0TBCNT
0Ah
eUSCI_B receive buffer
UCB0RXBUF
0Ch
eUSCI_B transmit buffer
UCB0TXBUF
0Eh
eUSCI_B I2C own address 0
UCB0I2COA0
14h
eUSCI_B I2C own address 1
UCB0I2COA1
16h
eUSCI_B I2C own address 2
UCB0I2COA2
18h
eUSCI_B I2C own address 3
UCB0I2COA3
1Ah
eUSCI_B received address
UCB0ADDRX
1Ch
eUSCI_B address mask
UCB0ADDMASK
1Eh
eUSCI I2C slave address
UCB0I2CSA
20h
eUSCI interrupt enable
UCB0IE
2Ah
eUSCI interrupt flags
UCB0IFG
2Ch
eUSCI interrupt vector word
UCB0IV
2Eh
Table 6-54. ADC10_A Registers (Base Address: 0740h)
REGISTER DESCRIPTION
REGISTER
OFFSET
ADC10_A control 0
ADC10CTL0
00h
ADC10_A control 1
ADC10CTL1
02h
ADC10_A control 2
ADC10CTL2
04h
ADC10_A window comparator low threshold
ADC10LO
06h
ADC10_A window comparator high threshold
ADC10HI
08h
ADC10_A memory control 0
ADC10MCTL0
0Ah
ADC10_A conversion memory
ADC10MCTL0
12h
ADC10_A interrupt enable
ADC10IE
1Ah
ADC10_A interrupt flags
ADC10IGH
1Ch
ADC10_A interrupt vector word
ADC10IV
1Eh
92
Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 6-55. SD24_B Registers (Base Address: 0800h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SD24_B control 0
SD24BCTL0
00h
SD24_B control 1
SD24BCTL1
02h
SD24_B interrupt flag
SD24BIFG
0Ah
SD24_B interrupt enable
SD24BIE
0Ch
SD24_B interrupt vector
SD24BIV
0Eh
SD24_B converter 0 control
SD24BCCTL0
10h
SD24_B converter 0 input control
SD24BINCTL0
12h
SD24_B converter 0 OSR control
SD24BOSR0
14h
SD24_B converter 0 preload
SD24BPRE0
16h
SD24_B converter 1 control
SD24BCCTL1
18h
SD24_B converter 1 input control
SD24BINCTL1
1Ah
SD24_B converter 1 OSR control
SD24BOSR1
1Ch
SD24_B converter 1 preload
SD24BPRE1
1Eh
SD24_B converter 2 control
SD24BCCTL2
20h
SD24_B converter 2 input control
SD24BINCTL2
22h
SD24_B converter 2 OSR control
SD24BOSR2
24h
SD24_B converter 2 preload
SD24BPRE2
26h
SD24_B converter 0 conversion memory low word
SD24BMEML0
50h
SD24_B converter 0 conversion memory high word
SD24BMEMH0
52h
SD24_B converter 1 conversion memory low word
SD24BMEML1
54h
SD24_B converter 1 conversion memory high word
SD24BMEMH1
56h
SD24_B converter 2 conversion memory low word
SD24BMEML2
58h
SD24_B converter 2 conversion memory high word
SD24BMEMH2
5Ah
Table 6-56. Auxiliary Supplies Registers (Base Address: 09E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Auxiliary supply control 0
AUXCTL0
00h
Auxiliary supply control 1
AUXCTL1
02h
Auxiliary supply control 2
AUXCTL2
04h
AUX2 charger control
AUX2CHCTL
12h
AUX3 charger control
AUX3CHCTL
14h
AUX ADC control
AUXADCCTL
16h
AUX interrupt flag
AUXIFG
1Ah
AUX interrupt enable
AUXIE
1Ch
AUX interrupt vector word
AUXIV
1Eh
Detailed Description
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Copyright © 2011–2018, Texas Instruments Incorporated
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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Table 6-57. LCD_C Registers (Base Address: 0A00h)
REGISTER DESCRIPTION
REGISTER
OFFSET
LCD_C control 0
LCDCCTL0
000h
LCD_C control 1
LCDCCTL1
002h
LCD_C blinking control
LCDCBLKCTL
004h
LCD_C memory control
LCDCMEMCTL
006h
LCD_C voltage control
LCDCVCTL
008h
LCD_C port control 0
LCDCPCTL0
00Ah
LCD_C port control 1
LCDCPCTL1
00Ch
LCD_C port control 2
LCDCPCTL2
00Eh
LCD_C charge pump control
LCDCCPCTL
012h
LCD_C interrupt vector
LCDCIV
01Eh
LCD_C memory 1
LCDM1
020h
LCD_C memory 2
LCDM2
021h
Static and 2- to 4-mux modes
⋮
⋮
⋮
LCD_C memory 20
LCDM20
033h
LCD_C blinking memory 1
LCDBM1
040h
LCD_C blinking memory 2
LCDBM2
041h
⋮
⋮
LCD_C blinking memory 20
⋮
LCDBM20
053h
LCD_C memory 1
LCDM1
020h
LCD_C memory 2
LCDM2
021h
5- to 8-mux modes
⋮
⋮
LCD_C memory 40
94
Detailed Description
⋮
LCDM40
047h
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
6.12 Input/Output Diagrams
6.12.1 Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger (MSP430F67xxIPZ and
MSP430F67xxIPN)
Figure 6-2 shows the port diagram. Table 6-58 summarizes the selection of the pin functions.
Pad Logic
To and from Reference
To ADC10_A
INCHx = y
P1REN.x
P1MAP.x = PMAP_ANALOG
P1DIR.x
0
From Port Mapping
1
P1OUT.x
0
From Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1.0/PM_TA0.0/VeREF-/A2
P1.1/PM_TA0.1/VeREF+/A1
P1IN.x
Bus
Keeper
EN
To Port Mapping
D
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
Figure 6-2. Port P1 (P1.0 and P1.1) Diagram (MSP430F67xxIPZ and MSP430F67xxIPN)
Detailed Description
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
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95
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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Table 6-58. Port P1 (P1.0 and P1.1) Pin Functions (MSP430F67xxIPZ and MSP430F67xxIPN)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
I: 0; O: 1
0
X
0
1
default
TA0.TA0
1
1
default
VeREF-/A2 (2)
X
1
= 31
I: 0; O: 1
0
X
TA0.CCI1A
0
1
default
TA0.TA1
1
1
default
VeREF+/A1 (2)
X
1
= 31
P1.0 (I/O)
P1.0/PM_TA0.0/
VeREF-/A2
0
TA0.CCI0A
P1.1 (I/O)
P1.1/PM_TA0.1/
VeREF+/A1
(1)
(2)
96
1
CONTROL BITS OR SIGNALS (1)
P1MAPx
X = Don't care
Setting P1SEL.x bit together with P1MAPx = PM_ANALOG disables the output driver and the input Schmitt trigger.
Detailed Description
Copyright © 2011–2018, Texas Instruments Incorporated
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
6.12.2 Port P1 (P1.2) Input/Output With Schmitt Trigger (MSP430F67xxIPZ and
MSP430F67xxIPN)
Figure 6-3 shows the port diagram. Table 6-59 summarizes the selection of the pin functions.
Pad Logic
To ADC10_A
INCHx = y
P1REN.x
P1MAP.x = PMAP_ANALOG
P1DIR.x
0
From Port Mapping
1
P1OUT.x
0
From Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
Bus
Keeper
EN
To Port Mapping
D
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
Figure 6-3. Port P1 (P1.2) Pin Functions (MSP430F67xxIPZ and MSP430F67xxIPN)
Table 6-59. Port P1 (P1.2) Pin Functions (MSP430F67xxIPZ and MSP430F67xxIPN)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
P1MAPx
I: 0; O: 1
0
X
UCA0RXD/UCA0SOMI
X
1
default
A0 (2)
X
1
= 31
P1.2 (I/O)
P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A0
(1)
(2)
2
CONTROL BITS OR SIGNALS (1)
X = Don't care
Setting P1SEL.x bit together with P1MAPx = PM_ANALOG disables the output driver and the input Schmitt trigger.
Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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6.12.3 Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger (MSP430F67xxIPZ and
MSP430F67xxIPN)
Figure 6-4 shows the port diagram. Table 6-60 summarizes the selection of the pin functions.
To LCD_C
Pad Logic
P1REN.x
P1MAP.x = PMAP_ANALOG
P1DIR.x
0
From Port Mapping
1
P1OUT.x
0
From Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03
P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13
P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23
P1IN.x
Bus
Keeper
EN
To Port Mapping
D
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
Figure 6-4. Port P1 (P1.3 to P1.5) Diagram (MSP430F67xxIPZ and MSP430F67xxIPN)
Table 6-60. Port P1 (P1.3 to P1.5) Pin Functions (MSP430F67xxIPZ and MSP430F67xxIPN)
PIN NAME (P1.x)
x
P1.3/PM_UCA0TXD/
PM_UCA0SIMO/R03
3
FUNCTION
P1.3 (I/O)
P1.4/PM_UCA1RXD/
PM_UCA1SOMI/
LCDREF/R13
(1)
(2)
98
P1MAPx
0
X
X
1
default
R03 (2)
X
1
= 31
I: 0; O: 1
0
X
X
1
default
UCA1RXD/UCA1SOMI
LCDREF/R13 (2)
5
P1SEL.x
I: 0; O: 1
X
1
= 31
I: 0; O: 1
0
X
UCA1TXD/UCA1SIMO
X
1
default
R23 (2)
X
1
= 31
P1.5 (I/O)
P1.5/PM_UCA1TXD/
PM_UCA1SIMO/R23
P1DIR.x
UCA0TXD/UCA0SIMO
P1.4 (I/O)
4
CONTROL BITS OR SIGNALS (1)
X = Don't care
Setting P1SEL.x bit together with P1MAPx = PM_ANALOG disables the output driver and the input Schmitt trigger.
Detailed Description
Copyright © 2011–2018, Texas Instruments Incorporated
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
6.12.4 Port P1 (P1.6 and P1.7) (MSP430F67xxIPZ and MSP430F67xxIPN),
Port P2 (P2.0 and P2.1) (MSP430F67xxIPZ Only) Input/Output With Schmitt Trigger
Figure 6-5 shows the port diagram. Table 6-61 and Table 6-62 summarize the selection of the pin
functions.
COM4 to COM7
From LCD_C
Pad Logic
PyREN.x
PyMAP.x = PMAP_ANALOG
PyDIR.x
0
From Port Mapping
1
PyOUT.x
0
From Port Mapping
1
DVSS
0
DVCC
1
Direction
0: Input
1: Output
PyDS.x
0: Low drive
1: High drive
PySEL.x
PyIN.x
P1.6/PM_UCA0CLK/COM4
P1.7/PM_UCB0CLK/COM5
P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6
P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7
Bus
Keeper
EN
To Port Mapping
1
D
PyIE.x
EN
PyIRQ.x
Q
PyIFG.x
PySEL.x
PyIES.x
Set
Interrupt
Edge
Select
Figure 6-5. Port P1 (P1.6 and P1.7) (MSP430F67xxIPZ and MSP430F67xxIPN), Port P2 (P2.0 and P2.1)
(MSP430F67xxIPZ Only) Diagram
Detailed Description
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
Copyright © 2011–2018, Texas Instruments Incorporated
99
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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Table 6-61. Port P1 (P1.6 and P1.7) Pin Functions (MSP430F67xxIPZ and MSP430F67xxIPN)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P1.x)
P1.6/PM_UCA0CLK/COM4
x
6
FUNCTION
P1DIR.x
P1SEL.x
P1MAPx
COM4, COM5
Enable Signal
P1.6 (I/O)
I: 0; O: 1
0
X
0
UCA0CLK
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
COM4
P1.7/PM_UCB0CLK/COM5
(1)
7
X
X
X
1
P1.7 (I/O)
I: 0; O: 1
0
X
0
UCB0CLK
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
COM5
X
X
X
1
X = Don't care
Table 6-62. Port P2 (P2.0 and P2.1) Pin Functions (MSP430F67xxIPZ Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL.x
P2MAPx
COM6, COM7
Enable Signal
I: 0; O: 1
0
X
0
UCB0SOMI/UCB0SCL
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
P2.0 (I/O)
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6
0
COM6
X
X
X
1
I: 0; O: 1
0
X
0
UCB0SIMO/UCB0SDA
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
COM7
X
X
X
1
P2.1 (I/O)
P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7
(1)
100
1
X = Don't care
Detailed Description
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
6.12.5 Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
Figure 6-6 shows the port diagram. Table 6-63 summarizes the selection of the pin functions.
Pad Logic
P2REN.x
P2MAP.x = PMAP_ANALOG
P2DIR.x
0
From Port Mapping
1
P2OUT.x
0
From Port Mapping
1
DVSS
0
DVCC
1
Direction
0: Input
1: Output
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2IN.x
Bus
Keeper
EN
To Port Mapping
1
P2.2/PM_UCA2RXD/PM_UCA2SOMI
P2.3/PM_UCA2TXD/PM_UCA2SIMO
P2.4/PM_UCA1CLK
P2.5/PM_UCA2CLK
P2.6/PM_TA1.0
P2.7/PM_TA1.1
D
P2IE.x
EN
P2IRQ.x
Q
P2IFG.x
P2SEL.x
P2IES.x
Set
Interrupt
Edge
Select
Figure 6-6. Port P2 (P2.2 to P2.7) Diagram (MSP430F67xxIPZ Only)
Detailed Description
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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Table 6-63. Port P2 (P2.2 to P2.7) Pin Functions (MSP430F67xxIPZ Only)
PIN NAME (P2.x)
x
FUNCTION
P2.2 (I/O)
P2.2/PM_UCA2RXD/
PM_UCA2SOMI
2
UCA2RXD/UCA2SOMI
Output driver and input Schmitt trigger disabled
P2.3 (I/O)
P2.3/PM_UCA2TXD/
PM_UCA2SIMO
3
UCA2TXD/UCA2SIMO
Output driver and input Schmitt trigger disabled
P2.4/PM_UCA1CLK
4
5
6
(1)
102
P2MAPx
X
X
1
default
= 31
X
1
I: 0; O: 1
0
X
X
1
default
= 31
1
0
X
UCA1CLK
X
1
default
= 31
X
1
P2.5 (I/O)
I: 0; O: 1
0
X
UCA2CLK
X
1
default
Output driver and input Schmitt trigger disabled
X
1
= 31
I: 0; O: 1
0
X
TA1.CC10A
0
1
default
TA1.TA0
1
1
default
= 31
X
1
I: 0; O: 1
0
X
0
1
default
TA1.TA1
1
1
default
Output driver and input Schmitt trigger disabled
X
1
= 31
P2.7 (I/O)
7
0
X
Output driver and input Schmitt trigger disabled
P2.7/PM_TA1.1
P2SEL.x
I: 0; O: 1
P2.6 (I/O)
P2.6/PM_TA1.0
P2DIR.x
I: 0; O: 1
P2.4 (I/O)
Output driver and input Schmitt trigger disabled
P2.5/PM_UCA2CLK
CONTROL BITS OR SIGNALS (1)
TA1.CCI1A
X = Don't care
Detailed Description
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
6.12.6 Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
Figure 6-7 shows the port diagram. Table 6-64 summarizes the selection of the pin functions.
Pad Logic
P3REN.x
P3MAP.x = PMAP_ANALOG
P3DIR.x
0
From Port Mapping
1
P3OUT.x
0
From Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P3.0/PM_TA2.0
P3.1/PM_TA2.1
P3.2/PM_TACLK/PM_RTCCLK
P3.3/PM_TA0.2
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
Bus
Keeper
EN
To Port Mapping
D
Figure 6-7. Port P3 (P3.0 to P3.3) Diagram (MSP430F67xxIPZ Only)
Table 6-64. Port P3 (P3.0 to P3.3) Pin Functions (MSP430F67xxIPZ Only)
PIN NAME (P3.x)
x
FUNCTION
P3.0 (I/O)
P3.0/PM_TA2.0
0
2
0
X
1
default
TA2.TA0
1
1
default
= 31
X
1
I: 0; O: 1
0
X
0
1
default
TA2.TA1
1
1
default
Output driver and input Schmitt trigger disabled
X
1
= 31
I: 0; O: 1
0
X
0
1
default
RTCCLK
1
1
default
Output driver and input Schmitt trigger disabled
X
1
= 31
I: 0; O: 1
0
X
TA0.CCI2A
0
1
default
TA0.TA2
1
1
default
Output driver and input Schmitt trigger disabled
X
1
= 31
TA2.CCI1A
TACLK
P3.3 (I/O)
P3.3/PM_TA0.2
(1)
3
P3MAPx
0
P3.2 (I/O)
P3.2/PM_TACLK/
PM_RTCCLK
P3SEL.x
I: 0; O: 1
P3.1 (I/O)
1
P3DIR.x
TA2.CC10A
Output driver and input Schmitt trigger disabled
P3.1/PM_TA2.1
CONTROL BITS OR SIGNALS (1)
X = Don't care
Detailed Description
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Copyright © 2011–2018, Texas Instruments Incorporated
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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6.12.7 Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
Figure 6-8 shows the port diagram. Table 6-65 summarizes the selection of the pin functions.
S39 to S37
LCDS39 to LCDS37
Pad Logic
P3REN.x
P3MAP.x = PMAP_ANALOG
P3DIR.x
0
From Port Mapping
1
P3OUT.x
0
From Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3.4/PM_SDCLK/S39
P3.5/PM_SD0DIO/S38
P3.6/PM_SD1DIO/S37
P3.7/PM_SD2DIO/S36
P3IN.x
EN
To Port Mapping
Bus
Keeper
D
Figure 6-8. Port P3 (P3.4 to P3.7) Diagram (MSP430F67xxIPZ Only)
104
Detailed Description
Copyright © 2011–2018, Texas Instruments Incorporated
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 6-65. Port P3 (P3.4 to P3.7) Pin Functions (MSP430F67xxIPZ Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P3.x)
x
FUNCTION
P3DIR.x
P3SEL.x
P3MAPx
LCDS39...
LCDS36
I: 0; O: 1
0
X
0
SDCLK
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
P3.4 (I/O)
P3.4/PM_SDCLK/S39
4
S39
X
X
X
1
I: 0; O: 1
0
X
0
SD0DIO
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
P3.5 (I/O)
P3.5/PM_SD0DIO/S38
5
S38
X
X
X
1
I: 0; O: 1
0
X
0
SD1DIO
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S37
X
X
X
1
P3.6 (I/O)
P3.6/PM_SD1DIO/S37
6
P3.7 (I/O)
P3.7/PM_SD2DIO/S36
(1)
7
I: 0; O: 1
0
X
0
SD2DIO
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S36
X
X
X
1
X = Don't care
Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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6.12.8 Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7), Port P7 (P7.0 to
P7.7), Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
Figure 6-9 shows the port diagram. Table 6-66 through Table 6-70 summarize the selection of the pin
functions.
Sz
LCDSz
Pad Logic
PyREN.x
PyDIR.x
0
0
DVSS
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
PyOUT.x
DVSS
PyDS.x
0: Low drive
1: High drive
PySEL.x
Py.x/Sz
PyIN.x
EN
Not Used
Bus
Keeper
D
Figure 6-9. Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7), Port P7 (P7.0 to P7.7), Port
P8 (P8.0 to P8.3) Diagram (MSP430F67xxIPZ Only)
106
Detailed Description
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 6-66. Port P4 (P4.0 to P4.7) Pin Functions (MSP430F67xxIPZ Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P4.x)
x
FUNCTION
P4DIR.x
P4SEL.x
LCDS35...
LCDS28
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S35
X
X
1
P4.0 (I/O)
P4.0/S35
0
P4.1 (I/O)
P4.1/S34
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S34
X
X
1
P4.2 (I/O)
P4.2/S33
2
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S33
P4.3 (I/O)
P4.3/S32
3
N/A
4
5
6
(1)
7
1
0
1
1
0
X
1
I: 0; O: 1
0
0
0
1
0
N/A
DVSS
1
1
0
S31
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S30
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S29
X
X
1
P4.7 (I/O)
P4.7/S28
0
0
X
P4.6 (I/O)
P4.6/S29
1
0
S32
P4.5 (I/O)
P4.5/S30
X
DVSS
P4.4 (I/O)
P4.4/S31
X
I: 0; O: 1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S28
X
X
1
X = Don't care
Detailed Description
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Copyright © 2011–2018, Texas Instruments Incorporated
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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Table 6-67. Port P5 (P5.0 to P5.7) Pin Functions (MSP430F67xxIPZ Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
P5SEL.x
LCDS27...
LCDS20
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S27
X
X
1
P5.0 (I/O)
P5.0/S27
0
P5.1 (I/O)
P5.1/S26
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S26
X
X
1
P5.2 (I/O)
P5.2/S25
2
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S25
P5.3 (I/O)
P5.3/S24
3
N/A
4
5
6
(1)
108
7
1
0
1
1
0
X
1
I: 0; O: 1
0
0
0
1
0
N/A
DVSS
1
1
0
S23
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S22
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S21
X
X
1
P5.7 (I/O)
P5.7/S20
0
0
X
P5.6 (I/O)
P5.6/S21
1
0
S24
P5.5 (I/O)
P5.5/S22
X
DVSS
P5.4 (I/O)
P5.4/S23
X
I: 0; O: 1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S20
X
X
1
X = Don't care
Detailed Description
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 6-68. Port P6 (P6.0 to P6.7) Pin Functions (MSP430F67xxIPZ Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P6.x)
x
FUNCTION
P6DIR.x
P6SEL.x
LCDS19...
LCDS12
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S19
X
X
1
P6.0 (I/O)
P6.0/S19
0
P6.1 (I/O)
P6.1/S18
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S18
X
X
1
P6.2 (I/O)
P6.2/S17
2
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S17
P6.3 (I/O)
P6.3/S16
3
N/A
4
5
6
(1)
7
1
0
1
1
0
X
1
I: 0; O: 1
0
0
0
1
0
N/A
DVSS
1
1
0
S15
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S14
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S13
X
X
1
P6.7 (I/O)
P6.7/S12
0
0
X
P6.6 (I/O)
P6.6/S13
1
0
S16
P6.5 (I/O)
P6.5/S14
X
DVSS
P6.4 (I/O)
P6.4/S15
X
I: 0; O: 1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S12
X
X
1
X = Don't care
Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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Table 6-69. Port P7 (P7.0 to P7.7) Pin Functions (MSP430F67xxIPZ Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P7.x)
x
FUNCTION
P7DIR.x
P7SEL.x
LCDS11...
LCDS4
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S11
X
X
1
P7.0 (I/O)
P7.0/S11
0
P7.1 (I/O)
P7.1/S10
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S10
X
X
1
P7.2 (I/O)
P7.2/S9
2
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S9
P7.3 (I/O)
P7.3/S8
3
N/A
4
5
6
(1)
110
7
1
0
1
1
0
X
1
I: 0; O: 1
0
0
0
1
0
N/A
DVSS
1
1
0
S7
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S6
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S5
X
X
1
P7.7 (I/O)
P7.7/S4
0
0
X
P7.6 (I/O)
P7.6/S5
1
0
S8
P7.5 (I/O)
P7.5/S6
X
DVSS
P7.4 (I/O)
P7.4/S7
X
I: 0; O: 1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S4
X
X
1
X = Don't care
Detailed Description
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 6-70. Port P8 (P8.0 to P8.3) Pin Functions (MSP430F67xxIPZ Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P8.x)
x
FUNCTION
P8DIR.x
P8SEL.x
LCDS3...
LCDS0
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S3
X
X
1
P8.0 (I/O)
P8.0/S3
0
P8.1 (I/O)
P8.1/S2
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S2
X
X
1
P8.2 (I/O)
P8.2/S1
2
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S1
P8.3 (I/O)
P8.3/S0
(1)
3
N/A
X
X
1
I: 0; O: 1
0
0
0
1
0
DVSS
1
1
0
S0
X
X
1
X = Don't care
Detailed Description
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
Copyright © 2011–2018, Texas Instruments Incorporated
111
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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6.12.9 Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
Figure 6-10 shows the port diagram. Table 6-71 summarizes the selection of the pin functions.
Pad Logic
P8REN.x
P8DIR.x
0
0
DVCC
1
1
Direction
0: Input
1: Output
1
P8OUT.x
DVSS
0
1
Module X OUT
P8.4/TA1.0
P8.5/TA1.1
P8.6/TA2.0
P8.7/TA2.1
P8DS.x
0: Low drive
1: High drive
P8SEL.x
P8IN.x
EN
Module X IN
D
Figure 6-10. Port P8 (P8.4 to P8.7) Diagram (MSP430F67xxIPZ Only)
Table 6-71. Port P8 (P8.4 to P8.7) Pin Functions (MSP430F67xxIPZ Only)
PIN NAME (P8.x)
x
FUNCTION
P8DIR.x
P8SEL.x
I: 0; O: 1
0
TA1.CCI0A
0
1
TA1.TA0
1
1
P8.5 (I/O)
P8.4 (I/O)
P8.4/TA1.0
P8.5/TA1.1
P8.6/TA2.0
P8.7/TA2.1
112
Detailed Description
4
5
6
7
CONTROL BITS OR SIGNALS
I: 0; O: 1
0
TA1.CCI1A
0
1
TA1.TA1
1
1
P8.6 (I/O)
I: 0; O: 1
0
TA2.CCI0A
0
1
TA2.TA0
1
1
P8.7 (I/O)
I: 0; O: 1
0
TA2.CCI1A
0
1
TA2.TA1
1
1
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
6.12.10 Port P9 (P9.0) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
Figure 6-11 shows the port diagram. Table 6-72 summarizes the selection of the pin functions.
Pad Logic
P9REN.x
P9DIR.x
0
Module X OUT
0
DVCC
1
1
Direction
0: Input
1: Output
1
P9OUT.x
DVSS
0
1
P9.0/TACLK/RTCCLK
P9DS.x
0: Low drive
1: High drive
P9SEL.x
P9IN.x
EN
Module X IN
D
Figure 6-11. Port P9 (P9.0) Diagram (MSP430F67xxIPZ Only)
Table 6-72. Port P9 (P9.0) Pin Functions (MSP430F67xxIPZ Only)
PIN NAME (P9.x)
x
FUNCTION
P9.0 (I/O)
P9.0/TACLK/RTCCLK
0
CONTROL BITS OR SIGNALS
P9DIR.x
P9SEL.x
I: 0; O: 1
0
TACLK
0
1
RTCCLK
1
1
Detailed Description
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Copyright © 2011–2018, Texas Instruments Incorporated
113
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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6.12.11 Port P9 (P9.1 to P9.3) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
Figure 6-12 shows the port diagram. Table 6-73 summarizes the selection of the pin functions.
Pad Logic
To ADC10
INCHx = y
P9REN.x
DVSS
0
DVCC
1
1
P9DIR.x
P9OUT.x
P9.1/A5
P9.2/A4
P9.3/A3
P9DS.x
0: Low drive
1: High drive
P9SEL.x
P9IN.x
Bus
Keeper
Figure 6-12. Port P9 (P9.1 to P9.3) Diagram (MSP430F67xxIPZ Only)
Table 6-73. Port P9 (P9.1 to P9.3) Pin Functions (MSP430F67xxIPZ Only)
PIN NAME (P9.x)
P9.1/A5
x
1
P9.2/A4
2
P9.3/A3
3
(1)
(2)
114
FUNCTION
P9.1 (I/O)
A5 (2)
P9.2 (I/O)
A4 (2)
P9.3 (I/O)
A3 (2)
CONTROL BITS OR SIGNALS (1)
P9DIR.x
P9SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
X = Don't care
Setting P9SEL.x bit disables the output driver and the input Schmitt trigger.
Detailed Description
Copyright © 2011–2018, Texas Instruments Incorporated
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
6.12.12 Port P2 (P2.0 and P2.1) Input/Output With Schmitt Trigger (MSP430F67xxIPN Only)
Figure 6-13 shows the port diagram. Table 6-74 summarizes the selection of the pin functions.
S39, S38
LCDS39, LCDS38
COM6, COM7
From LCD_C
Pad Logic
P2REN.x
P2MAP.x = PMAP_ANALOG
P2DIR.x
0
From Port Mapping
1
P2OUT.x
0
From Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6/S39
P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7/S38
P2IN.x
Bus
Keeper
EN
To Port Mapping
D
P2IE.x
EN
P2IRQ.x
Q
P2IFG.x
P2SEL.x
P2IES.x
Set
Interrupt
Edge
Select
Figure 6-13. Port P2 (P2.0 and P2.1) Diagram (MSP430F67xxIPN Only)
Detailed Description
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Copyright © 2011–2018, Texas Instruments Incorporated
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
www.ti.com
Table 6-74. Port P2 (P2.0 and P2.1) Pin Functions (MSP430F67xxIPN Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P2.x)
x
FUNCTION
P2.0 (I/O)
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6/
S39
0
(1)
116
1
P2SEL.x
P2MAPx
LCDS39,
LCDS38
COM6,
COM7
Enable
Signal
I: 0; O: 1
0
X
0
0
UCB0SOMI/UCB0SCL
X
1
default
0
0
Output driver and input
Schmitt trigger disabled
X
1
= 31
0
0
COM6
X
X
X
X
1
S39
X
X
X
1
0
P2.1 (I/O)
P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7/
S38
P2DIR.x
I: 0; O: 1
0
X
0
0
UCB0SIMO/UCB0SDA
X
1
default
0
0
Output driver and input
Schmitt trigger disabled
X
1
= 31
0
0
COM7
X
X
X
X
1
S38
X
X
X
1
0
X = Don't care
Detailed Description
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
6.12.13 Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (MSP430F67xxIPN Only)
Figure 6-14 shows the port diagram. Table 6-75 summarizes the selection of the pin functions.
S37...S32
LCDS37...LCDS32
Pad Logic
P2REN.x
P2MAP.x = PMAP_ANALOG
P2DIR.x
0
From Port Mapping
1
P2OUT.x
0
From Port Mapping
1
DVSS
0
DVCC
1
Direction
0: Input
1: Output
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2IN.x
Bus
Keeper
EN
To Port Mapping
1
P2.2/PM_UCA2RXD/PM_UCA2SOMI/S37
P2.3/PM_UCA2TXD/PM_UCA2SIMO/S36
P2.4/PM_UCA1CLK/S35
P2.5/PM_UCA2CLK/S34
P2.6/PM_TA1.0/S33
P2.7/PM_TA1.1/S32
D
P2IE.x
EN
P2IRQ.x
Q
P2IFG.x
P2SEL.x
P2IES.x
Set
Interrupt
Edge
Select
Figure 6-14. Port P2 (P2.2 to P2.7) Diagram (MSP430F67xxIPN Only)
Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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Table 6-75. Port P2 (P2.2 to P2.7) Pin Functions (MSP430F67xxIPN Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL.x
P2MAPx
LCDS37...
LCDS32
I: 0; O: 1
0
X
0
UCA2RXD/UCA2SOMI
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
P2.2 (I/O)
P2.2/PM_UCA2RXD/
PM_UCA2SOMI/S37
2
S37
X
X
X
1
I: 0; O: 1
0
X
0
UCA2TXD/UCA2SIMO
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
P2.3 (I/O)
P2.3/PM_UCA2TXD/
PM_UCA2SIMO/S36
3
S36
P2.4/PM_UCA1CLK/S35
P2.5/PM_UCA2CLK/S34
4
5
X
X
X
1
P2.4 (I/O)
I: 0; O: 1
0
X
0
UCA1CLK
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S35
X
X
X
1
P2.5 (I/O)
I: 0; O: 1
0
X
0
UCA2CLK
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S34
X
X
X
1
I: 0; O: 1
0
X
0
TA1.CCI0A
0
1
default
0
TA1.TA0
1
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
P2.6 (I/O)
P2.6/PM_TA1.0/S33
6
S33
X
X
X
1
I: 0; O: 1
0
X
0
TA1.CCI1A
0
1
default
0
TA1.TA1
1
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S32
X
X
X
1
P2.7 (I/O)
P2.7/PM_TA1.1/S32
(1)
118
7
X = Don't care
Detailed Description
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
6.12.14 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger (MSP430F67xxIPN Only)
Figure 6-15 shows the port diagram. Table 6-76 summarizes the selection of the pin functions.
S31 to S24
LCDS31 to LCDS24
Pad Logic
P3REN.x
P3MAP.x = PMAP_ANALOG
P3DIR.x
0
From Port Mapping
1
P3OUT.x
0
From Port Mapping
1
DVSS
0
DVCC
1
Direction
0: Input
1: Output
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
EN
To Port Mapping
1
Bus
Keeper
P3.0/PM_TA2.0/S31
P3.1/PM_TA2.1/S30
P3.2/PM_TACLK/PM_RTCCLK/S29
P3.3/PM_TA0.2/S28
P3.4/PM_SDCLK/S27
P3.5/PM_SD0DIO/S26
P3.6/PM_SD1DIO/S25
P3.7/PM_SD2DIO/S24
D
Figure 6-15. Port P3 (P3.0 to P3.7) Diagram (MSP430F67xxIPN Only)
Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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Table 6-76. Port P3 (P3.0 to P3.7) Pin Functions (MSP430F67xxIPN Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P3.x)
x
FUNCTION
P3DIR.x
P3SEL.x
P3MAPx
LCDS31...
LCDS24
I: 0; O: 1
0
X
0
TA2.CCI0A
0
1
default
0
TA2.TA0
1
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
P3.0 (I/O)
P3.0/PM_TA2.0/S31
0
S31
X
X
X
1
I: 0; O: 1
0
X
0
TA2.CCI1A
0
1
default
0
TA2.TA1
1
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
P3.1 (I/O)
P3.1/PM_TA2.1/S30
1
S30
X
X
X
1
I: 0; O: 1
0
X
0
TACLK
0
1
default
0
RTCCLK
1
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S29
X
X
X
1
P3.2 (I/O)
P3.2/PM_TACLK/
PM_RTCCLK/S29
2
P3.3 (I/O)
P3.3/PM_TA0.2/S28
3
I: 0; O: 1
0
X
0
TA0.CCI2A
0
1
default
0
TA0.TA2
1
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S28
X
X
X
1
I: 0; O: 1
0
X
0
SDCLK
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
P3.4 (I/O)
P3.4/PM_SDCLK/S27
4
S27
X
X
X
1
I: 0; O: 1
0
X
0
SD0DIO
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
P3.5 (I/O)
P3.5/PM_SD0DIO/S26
5
S26
X
X
X
1
I: 0; O: 1
0
X
0
SD1DIO
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S25
X
X
X
1
P3.6 (I/O)
P3.6/PM_SD1DIO/S25
6
P3.7 (I/O)
P3.7/PM_SD2DIO/S24
(1)
120
7
I: 0; O: 1
0
X
0
SD2DIO
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S24
X
X
X
1
X = Don't care
Detailed Description
Copyright © 2011–2018, Texas Instruments Incorporated
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
6.12.15 Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7) Input/Output
With Schmitt Trigger (MSP430F67xxIPN Only)
Figure 6-16 shows the port diagram. Table 6-77 through Table 6-79 summarize the selection of the pin
functions.
Sz
LCDSz
Pad Logic
PyREN.x
PyDIR.x
0
0
DVSS
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
PyOUT.x
DVSS
PyDS.x
0: Low drive
1: High drive
PySEL.x
Py.x/Sz
PyIN.x
EN
Not Used
Bus
Keeper
D
Figure 6-16. Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7) Diagram
(MSP430F67xxIPN Only)
Detailed Description
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
Copyright © 2011–2018, Texas Instruments Incorporated
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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Table 6-77. Port P4 (P4.0 to P4.7) Pin Functions (MSP430F67xxIPN Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P4.x)
x
FUNCTION
P4DIR.x
P4SEL.x
LCDS23...
LCDS16
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S23
X
X
1
P4.0 (I/O)
P4.0/S23
0
P4.1 (I/O)
P4.1/S22
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S22
X
X
1
P4.2 (I/O)
P4.2/S21
2
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S21
P4.3 (I/O)
P4.3/S20
3
N/A
4
5
6
(1)
122
7
1
0
1
1
0
X
1
I: 0; O: 1
0
0
0
1
0
N/A
DVSS
1
1
0
S19
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S18
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S17
X
X
1
P4.7 (I/O)
P4.7/S16
0
0
X
P4.6 (I/O)
P4.6/S17
1
0
S20
P4.5 (I/O)
P4.5/S18
X
DVSS
P4.4 (I/O)
P4.4/S19
X
I: 0; O: 1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S16
X
X
1
X = Don't care
Detailed Description
Copyright © 2011–2018, Texas Instruments Incorporated
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Table 6-78. Port P5 (P5.0 to P5.7) Pin Functions (MSP430F67xxIPN Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
P5SEL.x
LCDS15...
LCDS8
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S15
X
X
1
P5.0 (I/O)
P5.0/S15
0
P5.1 (I/O)
P5.1/S14
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S14
X
X
1
P5.2 (I/O)
P5.2/S13
2
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S13
P5.3 (I/O)
P5.3/S12
3
N/A
4
5
6
(1)
7
1
0
1
1
0
X
1
I: 0; O: 1
0
0
0
1
0
N/A
DVSS
1
1
0
S11
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S10
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S9
X
X
1
P5.7 (I/O)
P5.7/S8
0
0
X
P5.6 (I/O)
P5.6/S9
1
0
S12
P5.5 (I/O)
P5.5/S10
X
DVSS
P5.4 (I/O)
P5.4/S11
X
I: 0; O: 1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S8
X
X
1
X = Don't care
Detailed Description
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
Copyright © 2011–2018, Texas Instruments Incorporated
123
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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Table 6-79. Port P6 (P6.0 to P6.7) Pin Functions (MSP430F67xxIPN Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P6.x)
x
FUNCTION
P6DIR.x
P6SEL.x
LCDS7...
LCDS0
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S7
X
X
1
P6.0 (I/O)
P6.0/S7
0
P6.1 (I/O)
P6.1/S6
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S6
X
X
1
P6.2 (I/O)
P6.2/S5
2
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S5
P6.3 (I/O)
P6.3/S4
3
N/A
4
5
6
(1)
124
7
1
0
1
1
0
X
1
I: 0; O: 1
0
0
0
1
0
N/A
DVSS
1
1
0
S3
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S2
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S1
X
X
1
P6.7 (I/O)
P6.7/S0
0
0
X
P6.6 (I/O)
P6.6/S1
1
0
S4
P6.5 (I/O)
P6.5/S2
X
DVSS
P6.4 (I/O)
P6.4/S3
X
I: 0; O: 1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S0
X
X
1
X = Don't care
Detailed Description
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
6.12.16 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
Figure 6-17 shows the port diagram. Table 6-80 summarizes the selection of the pin functions.
Pad Logic
PJREN.x
PJDIR.x
0
DVCC
1
PJOUT.x
00
From JTAG
01
SMCLK
10
DVSS
0
DVCC
1
PJDS.0
0: Low drive
1: High drive
11
1
PJ.0/SMCLK/TDO
PJSEL.x
From JTAG
PJIN.x
Bus
Holder
EN
D
Figure 6-17. Port PJ (PJ.0) Diagram
Detailed Description
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Copyright © 2011–2018, Texas Instruments Incorporated
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
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6.12.17 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt
Trigger or Output
Figure 6-18 shows the port diagram. Table 6-80 summarizes the selection of the pin functions.
Pad Logic
PJREN.x
PJDIR.x
DVSS
DVSS
0
DVCC
1
1
0
1
PJOUT.x
00
From JTAG
01
MCLK/ADC10CLK/ACLK
10
PJ.1/MCLK/TDI/TCLK
PJ.2/ADC10CLK/TMS
PJ.3/ACLK/TCK
PJDS.x
0: Low drive
1: High drive
11
PJSEL.x
From JTAG
PJIN.x
Bus
Holder
EN
D
To JTAG
Figure 6-18. Port PJ (PJ.1 to PJ.3) Diagram
Table 6-80. Port PJ (PJ.0 to PJ.3) Pin Functions
CONTROL BITS OR SIGNALS (1)
PIN NAME (PJ.x)
x
FUNCTION
PJ.0 (I/O) (2)
PJ.0/SMCLK/TDO
0
1
0
0
1
1
0
TDO (3)
X
X
1
I: 0; O: 1
0
0
1
1
0
X
X
1
I: 0; O: 1
0
0
1
1
0
X
X
1
I: 0; O: 1
0
0
1
1
0
X
X
1
(2)
MCLK
PJ.2 (I/O)
2
ACLK
TCK
(1)
(2)
(3)
(4)
126
(2)
(3) (4)
PJ.3 (I/O)
3
(3) (4)
ADC10CLK
TMS
PJ.3/ACLK/TCK
JTAG
Mode
Signal
I: 0; O: 1
TDI/TCLK
PJ.2/ADC10CLK/TMS
PJSEL.x
SMCLK
PJ.1 (I/O)
PJ.1/MCLK/TDI/TCLK
PJDIR.x
(3) (4)
(2)
X = Don't care
Default condition
The pin direction is controlled by the JTAG module.
In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.
Detailed Description
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.ti.com
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
6.13 Device Descriptors (TLV)
Table 6-81 and Table 6-82 list the contents of the device descriptor tag-length-value (TLV) structure for
each device type.
Table 6-81. MSP430F673x Device Descriptors
DESCRIPTION
Info Block
Die Record
ADC10
Calibration
ADDRESS
SIZE
(bytes)
VALUE
F6736PZ
F6736PN
F6735PZ
F6735PN
F6734PZ
F6734PN
F6733PZ
F6733PN
F6731PZ
F6731PN
F6730PZ
F6730PN
06h
Info length
01A00h
1
06h
06h
06h
06h
06h
CRC length
01A01h
1
06h
06h
06h
06h
06h
06h
CRC value
01A02h
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Device ID
01A04h
1
6Ch
6Bh
6Ah
65h
63h
62h
Device ID
01A05h
1
81h
81h
81h
80h
80h
80h
Hardware revision
01A06h
1
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Firmware revision
01A07h
1
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Die record tag
01A08h
1
08h
08h
08h
08h
08h
08h
Die record length
01A09h
1
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
Lot/wafer ID
01A0Ah
4
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Die X position
01A0Eh
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Die Y position
01A10h
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Test results
01A12h
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC10 calibration tag
01A14h
1
13h
13h
13h
13h
13h
13h
ADC10 calibration length
01A15h
1
10h
10h
10h
10h
10h
10h
ADC gain factor
01A16h
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC offset
01A18h
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 1.5-V reference
Temperature sensor 30°C
01A1Ah
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 1.5-V reference
Temperature sensor 85°C
01A1Ch
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 2.0-V reference
Temperature sensor 30°C
01A1Eh
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 2.0-V reference
Temperature sensor 85°C
01A20h
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 2.5-V reference
Temperature sensor 30°C
01A22h
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 2.5-V reference
Temperature sensor 85°C
01A24h
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
www.ti.com
Table 6-82. MSP430F672x Device Descriptors
DESCRIPTION
Info Block
Die Record
ADC10
Calibration
128
ADDRESS
SIZE
(bytes)
VALUE
F6726PZ
F6726PN
F6725PZ
F6725PN
F6724PZ
F6724PN
F6723PZ
F6723PN
F6721PZ
F6721PN
F6720PZ
F6720PN
06h
Info length
01A00h
1
06h
06h
06h
06h
06h
CRC length
01A01h
1
06h
06h
06h
06h
06h
06h
CRC value
01A02h
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Device ID
01A04h
1
6Fh
6Eh
6Dh
61h
59h
58h
Device ID
01A05h
1
81h
81h
81h
80h
80h
80h
Hardware revision
01A06h
1
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Firmware revision
01A07h
1
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Die record tag
01A08h
1
08h
08h
08h
08h
08h
08h
Die record length
01A09h
1
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
Lot/wafer ID
01A0Ah
4
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Die X position
01A0Eh
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Die Y position
01A10h
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Test results
01A12h
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC10 calibration tag
01A14h
1
13h
13h
13h
13h
13h
13h
ADC10 calibration length
01A15h
1
10h
10h
10h
10h
10h
10h
ADC gain factor
01A16h
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC offset
01A18h
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 1.5-V reference
Temperature sensor 30°C
01A1Ah
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 1.5-V reference
Temperature sensor 85°C
01A1Ch
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 2.0-V reference
Temperature sensor 30°C
01A1Eh
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 2.0-V reference
Temperature sensor 85°C
01A20h
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 2.5-V reference
Temperature sensor 30°C
01A22h
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 2.5-V reference
Temperature sensor 85°C
01A24h
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.ti.com
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
7 Device and Documentation Support
7.1
Getting Started and Next Steps
For more information on the MSP430™ family of devices and the tools and libraries that are available to
help with your development, visit the Getting Started page.
7.2
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS.
These prefixes represent evolutionary stages of product development from engineering prototypes (XMS)
through fully qualified production devices (MSP).
XMS – Experimental device that is not necessarily representative of the final device's electrical
specifications
MSP – Fully qualified production device
XMS devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production
devices. TI recommends that these devices not be used in any production system because their expected
end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
temperature range, package type, and distribution format. Figure 7-1 provides a legend for reading the
complete device name.
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
www.ti.com
MSP 430 F 5 438 A I ZQW T -EP
Processor Family
Optional: Additional Features
MCU Platform
Optional: Tape and Reel
Device Type
Packaging
Series
Feature Set
Processor Family
MCU Platform
Optional: Temperature Range
Optional: A = Revision
CC = Embedded RF Radio
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
430 = MSP430 low-power microcontroller platform
Device Type
Memory Type
C = ROM
F = Flash
FR = FRAM
G = Flash or FRAM (Value Line)
L = No Nonvolatile Memory
Specialized Application
AFE = Analog Front End
BQ = Contactless Power
CG = ROM Medical
FE = Flash Energy Meter
FG = Flash Medical
FW = Flash Electronic Flow Meter
Series
1 = Up to 8 MHz
2 = Up to 16 MHz
3 = Legacy
4 = Up to 16 MHz with LCD
5 = Up to 25 MHz
6 = Up to 25 MHz with LCD
0 = Low-Voltage Series
Feature Set
Various levels of integration within a series
Optional: A = Revision
N/A
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional: Tape and Reel
T = Small reel
R = Large reel
No markings = Tube or tray
Optional: Additional Features -EP = Enhanced Product (–40°C to 105°C)
-HT = Extreme Temperature Parts (–55°C to 150°C)
-Q1 = Automotive Q100 Qualified
Figure 7-1. Device Nomenclature
130
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.ti.com
7.3
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Tools and Software
All MSP microcontrollers are supported by a wide variety of software and hardware development tools.
Tools are available from TI and various third parties. See them all at MSP430 Ultra-Low-Power MCUs –
Tools & software.
Table 7-1 lists the debug features of the MSP430F673x and MSP430F672x MCUs. See the Code
Composer Studio for MSP430 User's Guide for details on the available features.
Table 7-1. Hardware Debug Features
MSP430
ARCHITECTURE
4-WIRE
JTAG
2-WIRE
JTAG
BREAKPOINTS
(N)
RANGE
BREAKPOINTS
CLOCK
CONTROL
STATE
SEQUENCER
TRACE
BUFFER
LPMX.5
DEBUGGING
SUPPORT
MSP430Xv2
Yes
Yes
3
Yes
Yes
No
No
No
Design Kits and Evaluation Modules
MSP-TS430PZ100B - 100-pin Target Development Board for MSP430F6x MCUs
The
MSPTS430PZ100B is a stand-alone 100-pin ZIF socket target board used to program and debug
the MSP430 MCU in-system through the JTAG interface or the Spy Bi-Wire (2-wire JTAG)
protocol.
100-pin Target Development Board and MSP-FET Programmer Bundle for MSP430F6x MCUs
The
MSP-FET is a powerful flash emulation tool to quickly begin application development on the
MSP430 MCU. It includes USB debugging interface used to program and debug the
MSP430 in-system through the JTAG interface or the pin saving Spy Bi-Wire (2-wire JTAG)
protocol.
EVM430-F6736 - MSP430F6736 EVM for Metering This EVM430-F6736 is a single-phase electricity
meter evaluation module based on the MSP430F6736 device. The E-meter can be
connected to the main power lines and has inputs for voltage and current, as well as a third
connection to setup anti-tampering.
Software
MSP430Ware™ Software MSP430Ware software is a collection of code examples, data sheets, and
other design resources for all MSP430 devices delivered in a convenient package. In
addition to providing a complete collection of existing MSP430 design resources,
MSP430Ware software also includes a high-level API called MSP Driver Library. This library
makes it easy to program MSP430 hardware. MSP430Ware software is available as a
component of CCS or as a stand-alone package.
Energy Measurement Design Center for MSP430 MCUs The Energy Measurement Design Center is a
rapid development tool that enables energy measurement using TI MSP430i20xx and
MSP430F67xx flash-based microcontrollers (MCUs). It includes a graphical user interface
(GUI), documentation, software library, and examples that can simplify development and
accelerate designs in a wide range of power monitoring and energy measurement
applications, including smart grid and building automation. Using the Design Center, you can
configure, calibrate, and view results without writing a single line of code.
MSP Driver Library The abstracted API of MSP Driver Library provides easy-to-use function calls that
free you from directly manipulating the bits and bytes of the MSP430 hardware. Thorough
documentation is delivered through a helpful API Guide, which includes details on each
function call and the recognized parameters. Developers can use Driver Library functions to
write complete projects with minimal overhead.
IEC60730 Software Package The IEC60730 MSP430 software package was developed to help
customers comply with IEC 60730-1:2010 (Automatic Electrical Controls for Household and
Similar Use – Part 1: General Requirements) for up to Class B products, which includes
home appliances, arc detectors, power converters, power tools, e-bikes, and many others.
The IEC60730 MSP430 software package can be embedded in customer applications
running on MSP430s to help simplify the customer’s certification efforts of functional safetycompliant consumer devices to IEC 60730-1:2010 Class B.
MSP430F673x, MSP430F672x Code Examples C code examples are available for every MSP device
that configures each of the integrated peripherals for various application needs.
Device and Documentation Support
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
www.ti.com
Capacitive Touch Software Library Free C libraries for enabling capacitive touch capabilities on
MSP430 MCUs. The MSP430 MCU version of the library features several capacitive touch
implementations including the RO and RC method.
MSP EnergyTrace™ Technology EnergyTrace technology for MSP430 microcontrollers is an energybased code analysis tool that measures and displays the energy profile of the application
and helps to optimize it for ultra-low-power consumption.
ULP (Ultra-Low Power) Advisor ULP Advisor™ software is a tool for guiding developers to write more
efficient code to fully use the unique ultra-low-power features of MSP and MSP432
microcontrollers. Aimed at both experienced and new microcontroller developers, ULP
Advisor checks your code against a thorough ULP checklist to help minimize the energy
consumption of your application. At build time, ULP Advisor provides notifications and
remarks to highlight areas of your code that can be further optimized for lower power.
Fixed Point Math Library for MSP The MSP IQmath and Qmath Libraries are a collection of highly
optimized and high-precision mathematical functions for C programmers to seamlessly port a
floating-point algorithm into fixed-point code on MSP430 and MSP432 devices. These
routines are typically used in computationally intensive real-time applications where optimal
execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and
Qmath libraries, it is possible to achieve execution speeds considerably faster and energy
consumption considerably lower than equivalent code written using floating-point math.
Floating Point Math Library for MSP430 Continuing to innovate in the low-power and low-cost
microcontroller space, TI provides MSPMATHLIB. Leveraging the intelligent peripherals of
our devices, this floating-point math library of scalar functions that are up to 26 times faster
than the standard MSP430 math functions. Mathlib is easy to integrate into your designs.
This library is free and is integrated in both Code Composer Studio IDE and IAR Embedded
Workbench IDE.
Development Tools
Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers
Code
Composer Studio (CCS) integrated development environment (IDE) supports all MSP
microcontroller devices. CCS comprises a suite of embedded software utilities used to
develop and debug embedded applications. It includes an optimizing C/C++ compiler, source
code editor, project build environment, debugger, profiler, and many other features.
Command-Line Programmer MSP Flasher is an open-source shell-based interface for programming
MSP microcontrollers through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire
(SBW) communication. MSP Flasher can download binary files (.txt or .hex) directly to the
MSP microcontroller without an IDE.
MSP MCU Programmer and Debugger The MSP-FET is a powerful emulation development tool – often
called a debug probe – which lets users quickly begin application development on MSP lowpower MCUs. Creating MCU software usually requires downloading the resulting binary
program to the MSP device for validation and debugging.
MSP-GANG Production Programmer The MSP Gang Programmer is an MSP430 or MSP432 device
programmer that can program up to eight identical MSP430 or MSP432 flash or FRAM
devices at the same time. The MSP Gang Programmer connects to a host PC using a
standard RS-232 or USB connection and provides flexible programming options that let the
user fully customize the process.
132
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.ti.com
7.4
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Documentation Support
The following documents describe the MSP430F673x and MSP430F672x MCUs. Copies of these
documents are available on the Internet at www.ti.com.
Receiving Notification of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for
your device on ti.com (for links to the product folders, see Section 7.5). In the upper right corner, click the
"Alert me" button. This registers you to receive a weekly digest of product information that has changed (if
any). For change details, check the revision history of any revised document.
Errata
MSP430F6736 Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F6735 Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F6734 Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F6733 Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F6731 Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F6730 Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F6726 Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F6725 Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F6724 Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F6723 Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F6721 Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F6720 Device Erratasheet Describes the known exceptions to the functional specifications.
User's Guides
MSP430x5xx and MSP430x6xx Family User's Guide
peripherals available in this device family.
Detailed information
on
the
modules
and
MSP430 Flash Device Bootloader (BSL) User's Guide The MSP430 bootloader (BSL) (formerly known
as the bootstrap loader) lets users communicate with embedded memory in the MSP430
microcontroller during the prototyping phase, final production, and in service. Both the
programmable memory (flash memory) and the data memory (RAM) can be modified as
required. Do not confuse the bootloader with the bootstrap loader programs found in some
digital signal processors (DSPs) that automatically load program code (and data) from
external memory to the internal memory of the DSP.
MSP430 Programming With the JTAG Interface This document describes the functions that are
required to erase, program, and verify the memory module of the MSP430 flash-based and
FRAM-based microcontroller families using the JTAG communication port. In addition, it
describes how to program the JTAG access security fuse that is available on all MSP430
devices. This document describes device access using both the standard 4-wire JTAG
interface and the 2-wire JTAG interface, which is also referred to as Spy-Bi-Wire (SBW).
MSP430 Hardware Tools User's Guide This manual describes the hardware of the TI MSP-FET430
Flash Emulation Tool (FET). The FET is the program development tool for the MSP430 ultralow-power microcontroller. Both available interface types, the parallel port interface and the
USB interface, are described.
Application Reports
MSP430 32-kHz Crystal Oscillators Selection of the correct crystal, correct load circuit, and proper
board layout are important for a stable crystal oscillator. This application report summarizes
crystal oscillator function and explains the parameters to select the correct crystal for
MSP430 ultra-low-power operation. In addition, hints and examples for correct board layout
are given. The document also contains detailed information on the possible oscillator tests to
ensure stable oscillator operation in mass production.
Device and Documentation Support
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133
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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
www.ti.com
MSP430 System-Level ESD Considerations System-Level ESD has become increasingly demanding
with silicon technology scaling towards lower voltages and the need for designing costeffective and ultra-low-power components. This application report addresses three different
ESD topics to help board designers and OEMs understand and design robust system-level
designs.
Designing With MSP430 and Segment LCDs Segment liquid crystal displays (LCDs) are needed to
provide information to users in a wide variety of applications from smart meters to electronic
shelf labels (ESLs) to medical equipment. Several MSP430 microcontroller families include
built-in low-power LCD driver circuitry that allows the MSP430 MCU to directly control the
segmented LCD glass. This application note helps explain how segmented LCDs work, the
different features of the various LCD modules across the MSP430 MCU family, LCD
hardware layout tips, guidance on writing efficient and easy-to-use LCD driver software, and
an overview of the portfolio of MSP430 devices that include different LCD features to aid in
device selection.
7.5
Related Links
Table 7-2 lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 7-2. Related Links
7.6
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
MSP430F6736
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MSP430F6735
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MSP430F6724
Click here
Click here
Click here
Click here
Click here
MSP430F6723
Click here
Click here
Click here
Click here
Click here
MSP430F6721
Click here
Click here
Click here
Click here
Click here
MSP430F6720
Click here
Click here
Click here
Click here
Click here
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
7.7
Trademarks
MSP430, MSP430Ware, EnergyTrace, ULP Advisor, Code Composer Studio, E2E are trademarks of
Texas Instruments.
All other trademarks are the property of their respective owners.
134
Device and Documentation Support
Copyright © 2011–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F6736 MSP430F6735 MSP430F6734 MSP430F6733 MSP430F6731 MSP430F6730
MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.ti.com
7.8
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
7.9
Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
7.10 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
Device and Documentation Support
Submit Documentation Feedback
Product Folder Links: MSP430F6736 MSP430F6735 MSP430F6734 MSP430F6733 MSP430F6731 MSP430F6730
MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
Copyright © 2011–2018, Texas Instruments Incorporated
135
MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018
www.ti.com
8 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
136
Mechanical, Packaging, and Orderable Information
Copyright © 2011–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F6736 MSP430F6735 MSP430F6734 MSP430F6733 MSP430F6731 MSP430F6730
MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
MSP430F6720IPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6720
MSP430F6720IPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6720
MSP430F6720IPZ
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6720
MSP430F6720IPZR
ACTIVE
LQFP
PZ
100
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6720
MSP430F6721IPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6721
MSP430F6721IPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6721
MSP430F6721IPZ
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6721
MSP430F6721IPZR
ACTIVE
LQFP
PZ
100
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6721
MSP430F6723IPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6723
MSP430F6723IPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6723
MSP430F6723IPNR-S
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6723
MSP430F6723IPZ
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6723
MSP430F6723IPZR
ACTIVE
LQFP
PZ
100
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6723
MSP430F6724IPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6724
MSP430F6724IPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6724
MSP430F6724IPZ
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6724
MSP430F6724IPZR
ACTIVE
LQFP
PZ
100
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6724
MSP430F6725IPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6725
MSP430F6725IPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6725
MSP430F6725IPZ
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6725
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Dec-2020
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
MSP430F6725IPZR
ACTIVE
LQFP
PZ
100
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6725
MSP430F6726IPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6726
MSP430F6726IPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6726
MSP430F6726IPZ
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6726
MSP430F6726IPZR
ACTIVE
LQFP
PZ
100
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6726
MSP430F6730IPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6730
MSP430F6730IPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6730
MSP430F6730IPZ
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6730
MSP430F6731IPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6731
MSP430F6731IPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6731
MSP430F6733IPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6733
MSP430F6733IPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6733
MSP430F6733IPZ
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
F6733
MSP430F6733IPZR
ACTIVE
LQFP
PZ
100
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
F6733
MSP430F6734IPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6734
MSP430F6734IPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6734
MSP430F6734IPZ
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6734
MSP430F6734IPZR
ACTIVE
LQFP
PZ
100
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6734
MSP430F6735IPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6735
MSP430F6735IPZ
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6735
MSP430F6736IPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6736
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Dec-2020
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
MSP430F6736IPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6736
MSP430F6736IPZ
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6736
MSP430F6736IPZR
ACTIVE
LQFP
PZ
100
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6736
SN0806723IPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F6723
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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