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TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280025,
TMS320F280023, TMS320F280025-Q1
TMS320F280023-Q1
TMS320F280025C, TMS320F280025C-Q1,
TMS320F280023, TMS320F280021-Q1
TMS320F280023-Q1
TMS320F280023C, TMS320F280021,
TMS320F280023C,
TMS320F280021,
TMS320F280021-Q1
SPRSP45B
– MARCH 2020 – REVISED
DECEMBER 2020
SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
TMS320F28002x Real-Time Microcontrollers
1 Features
•
•
•
•
•
•
TMS320C28x 32-bit DSP core at 100 MHz
– IEEE 754 Floating-Point Unit (FPU)
• Support for Fast Integer Division (FINTDIV)
– Trigonometric Math Unit (TMU)
• Support for Nonlinear Proportional Integral
Derivative (NLPID) control
– CRC Engine and Instructions (VCRC)
– Ten hardware breakpoints (with ERAD)
On-chip memory
– 128KB (64KW) of flash (ECC-protected)
– 24KB (12KW) of RAM (ECC or parity-protected)
– Dual-zone security
Clock and system control
– Two internal zero-pin 10-MHz oscillators
– On-chip crystal oscillator or external clock input
– Windowed watchdog timer module
– Missing clock detection circuitry
– Dual-clock Comparator (DCC)
Single 3.3-V supply
– Internal VREG generation
– Brownout reset (BOR) circuit
System peripherals
– 6-channel Direct Memory Access (DMA)
controller
– 39 individually programmable multiplexed
General-Purpose Input/Output (GPIO) pins
– 16 digital inputs on analog pins
– Enhanced Peripheral Interrupt Expansion
(ePIE)
– Multiple low-power mode (LPM) support
– Embedded Real-time Analysis and Diagnostic
(ERAD)
– Unique Identification (UID) number
Communications peripherals
– One Power-Management Bus (PMBus)
interface
– Two Inter-integrated Circuit (I2C) interfaces
– One Controller Area Network (CAN) bus port
– Two Serial Peripheral Interface (SPI) ports
– One UART-compatible Serial Communication
Interface (SCI)
– Two UART-compatible Local Interconnect
Network (LIN) interfaces
– Fast Serial Interface (FSI) with one transmitter
and one receiver (up to 200Mbps)
•
•
•
•
•
•
•
•
Analog system
– Two 3.45-MSPS, 12-bit Analog-to-Digital
Converters (ADCs)
• Up to 16 external channels
• Four integrated Post-Processing Blocks
(PPB) per ADC
– Four windowed comparators (CMPSS) with
12-bit reference Digital-to-Analog Converters
(DACs)
• Digital glitch filters
Enhanced control peripherals
– 14 ePWM channels with eight channels that
have high-resolution capability (150-ps
resolution)
• Integrated dead-band support
• Integrated hardware trip zones (TZs)
– Three Enhanced Capture (eCAP) modules
• High-resolution Capture (HRCAP) available
on one of the three eCAP modules
– Two Enhanced Quadrature Encoder Pulse
(eQEP) modules with support for CW/CCW
operation modes
Configurable Logic Block (CLB)
– Augments existing peripheral capability
– Supports position manager solutions
Host Interface Controller (HIC)
– Access to internal memory from an external
host
Background CRC (BGCRC)
– One cycle CRC computation on 32 bits of data
Diagnostic features
– Memory Power On Self Test (MPOST)
– Hardware Built-in Self Test (HWBIST)
Package options:
– 80-pin Low-profile Quad Flatpack (LQFP)
[PN suffix]
– 64-pin LQFP [PM suffix]
– 48-pin LQFP [PT suffix]
Temperature options:
– S: –40°C to 125°C junction
– Q: –40°C to 125°C free-air
(AEC Q100 qualification for automotive
applications)
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2020 Texas Instruments
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intellectual property matters and other important disclaimers. PRODUCTION DATA.
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1
TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
2 Applications
•
•
•
•
•
•
•
Appliances
– Air conditioner outdoor unit
Building automation
– Door operator drive control
Industrial machine & machine tools
– Automated sorting equipment
– Textile machine
EV charging infrastructure
– AC charging (pile) station
– DC charging (pile) station
– EV charging station power module
– Wireless EV charging station
Renewable energy storage
– Energy storage power conversion system
(PCS)
Solar energy
– Central inverter
– Micro inverter
– Solar power optimizer
– Solar arc protection
– Rapid shutdown
– Electricity meter
– String inverter
Hybrids, electric & powertrain systems
– DC/DC converter
– Inverter & motor control
– On-board (OBC) & wireless charger
•
•
•
•
•
•
•
•
Body electronics & lighting
– Automotive HVAC compressor module
– DC/AC inverter
– Headlight
AC inverter & VF drives
– AC drive control module
– AC drive position feedback
– AC drive power stage module
Linear motor transport systems
– Linear motor power stage
Single & multi axis servo drives
– Servo drive position feedback
– Servo drive power stage module
Speed controlled BLDC drives
– AC-input BLDC motor drive
– DC-input BLDC motor drive
Industrial power
– Industrial AC-DC
UPS
– Three phase UPS
– Single phase online UPS
Telecom & server power
– Merchant DC/DC
– Merchant network & server PSU
– Merchant telecom rectifiers
3 Description
The TMS320F28002x (F28002x) is a member of the C2000™ real-time microcontroller family of scalable, ultralow latency devices designed for efficiency in power electronics, including but not limited to: high power density,
high switching frequencies, and supporting the use of GaN and SiC technologies.
These include such applications as:
•
•
•
•
•
•
Industrial motor drives
Motor control
Solar inverters
Digital power
Electrical vehicles and transportation
Sensing and signal processing
The real-time control subsystem is based on TI’s 32-bit C28x DSP core, which provides 100 MHz of signalprocessing performance for floating- or fixed-point code running from either on-chip flash or SRAM. The C28x
CPU is further boosted by the Trigonometric Math Unit (TMU) and VCRC (Cyclical Redundancy Check)
extended instruction sets, speeding up common algorithms key to real-time control systems.
High-performance analog blocks are integrated on the F28002x real-time microcontroller (MCU) and are closely
coupled with the processing and PWM units to provide optimal real-time signal chain performance. Fourteen
PWM channels, all supporting frequency-independent resolution modes, enable control of various power stages
from a 3-phase inverter to advanced multi-level power topologies.
2
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TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
www.ti.com
SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
The inclusion of the Configurable Logic Block (CLB) allows the user to add custom logic and potentially integrate
FPGA-like functions into the C2000 real-time MCU.
Interfacing is supported through various industry-standard communication ports (such as SPI, SCI, I2C, PMBus,
LIN, and CAN) and offers multiple pin-muxing options for optimal signal placement. The Fast Serial Interface
(FSI) enables up to 200 Mbps of robust communications across an isolation boundary.
New to the C2000 platform is the Host Interface Controller (HIC), a high-throughput interface that allows an
external host to access the resources of the TMS320F28002x directly.
Want to learn more about features that make C2000 MCUs the right choice for your real-time control system?
Check out The Essential Guide for Developing With C2000™ Real-Time Microcontrollers and visit the C2000™
real-time control MCUs page.
Ready to get started? Check out the TMDSCNCD280025C evaluation board and download C2000Ware.
Device Information
PART NUMBER(1)
TMS320F280025C
TMS320F280025
TMS320F280023C
CONFIGURABLE LOGIC
BLOCK (CLB)
2 Tiles
–
2 Tiles
TMS320F280023
–
TMS320F280021
–
(1)
FLASH SIZE
128KB
64KB
32KB
For more information on these devices, see the Device Comparison table.
Copyright © 2020 Texas Instruments Incorporated
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3
TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
3.1 Functional Block Diagram
The Functional Block Diagram shows the CPU system and associated peripherals.
Boot ROM
C28x CPU
Secure ROM
FPU32
FINTDIV
TMU
VCRC
Flash Bank0
16 Sectors
64 KW (128 KB)
Secure Memories
shown in Red
Bus Legend
CPU
DMA
HIC
BGCRC
CPU Timers
DCC
DCSM
ePIE
ERAD
M0-M1 RAM
2 KW (4 KB)
BGCRC
LS4-LS7 RAM
8 KW (16 KB)
Crystal Oscillator
INTOSC1, INTOSC2
PLL
HIC
GS0 RAM
2 KW (4 KB)
PF1
14x ePWM Chan.
(8 Hi-Res Capable)
14x ePWM Chan.
4x CMPSS
(8 Hi-Res Capable)
3x eCAP
3x eCAP
2x CLB
(1 HRCAP Capable) (1 HRCAP Capable)
2x eQEP
(CW/CCW Support)
PF3
Result
2x 12-Bit ADC
DMA
6 Channles
PF4
Data
PF2
PF7
PF8
PF9
1x PMBUS
1x CAN
2x LIN
1x SCI
39x GPIO
2x SPI
2x I2C
Input XBAR
1x FSI RX
Output XBAR
1x FSI TX
NMI
Watchdog
Windowed
Watchdog
ePWM XBAR
CLB XBAR
Figure 3-1. Functional Block Diagram
4
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TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
www.ti.com
SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 2
3 Description.......................................................................2
3.1 Functional Block Diagram........................................... 4
4 Revision History.............................................................. 6
5 Device Comparison......................................................... 9
5.1 Related Products...................................................... 10
6 Terminal Configuration and Functions........................ 11
6.1 Pin Diagrams.............................................................11
6.2 Pin Attributes.............................................................14
6.3 Signal Descriptions................................................... 29
6.4 Pin Multiplexing.........................................................39
6.5 Pins With Internal Pullup and Pulldown.................... 46
6.6 Connections for Unused Pins................................... 47
7 Specifications................................................................ 48
7.1 Absolute Maximum Ratings ..................................... 48
7.2 ESD Ratings – Commercial...................................... 48
7.3 ESD Ratings – Automotive....................................... 49
7.4 Recommended Operating Conditions ......................49
Supply Voltages.............................................................. 50
7.5 Power Consumption Summary................................. 51
7.6 Electrical Characteristics ..........................................55
7.7 Thermal Resistance Characteristics for PN
Package...................................................................... 56
7.8 Thermal Resistance Characteristics for PM
Package...................................................................... 56
7.9 Thermal Resistance Characteristics for PT
Package...................................................................... 57
7.10 Thermal Design Considerations..............................57
7.11 System.................................................................... 58
7.12 Analog Peripherals..................................................86
7.13 Control Peripherals............................................... 106
7.14 Communications Peripherals................................ 121
Copyright © 2020 Texas Instruments Incorporated
8 Detailed Description....................................................153
8.1 Overview................................................................. 153
8.2 Functional Block Diagram....................................... 154
8.3 Memory................................................................... 155
8.4 Identification............................................................160
8.5 Bus Architecture – Peripheral Connectivity.............161
8.6 C28x Processor...................................................... 162
8.7 Embedded Real-Time Analysis and Diagnostic
(ERAD)...................................................................... 164
8.8 Background CRC-32 (BGCRC).............................. 164
8.9 Direct Memory Access (DMA).................................165
8.10 Device Boot Modes...............................................166
8.11 Dual Code Security Module.................................. 172
8.12 Watchdog.............................................................. 173
8.13 C28x Timers..........................................................174
8.14 Dual-Clock Comparator (DCC)............................. 174
8.15 Configurable Logic Block (CLB)............................176
9 Applications, Implementation, and Layout............... 178
9.1 TI Reference Design............................................... 178
10 Device and Documentation Support........................179
10.1 Getting Started and Next Steps............................ 179
10.2 Device and Development Support Tool
Nomenclature............................................................ 179
10.3 Markings............................................................... 180
10.4 Tools and Software............................................... 182
10.5 Documentation Support........................................ 183
10.6 Support Resources............................................... 184
10.7 Trademarks........................................................... 185
10.8 Electrostatic Discharge Caution............................185
10.9 Glossary................................................................185
11 Mechanical, Packaging, and Orderable
Information.................................................................. 186
11.1 Packaging Information.......................................... 186
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5
TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
4 Revision History
Changes from October 4, 2020 to December 31, 2020 (from Revision A (October 2020) to
Revision B (December 2020))
Page
• Global: Added TMS320F280025-Q1, TMS320F280025C-Q1, TMS320F280023-Q1, and TMS320F280021Q1....................................................................................................................................................................... 1
• Table 5-1 (Device Comparison): Added TMS320F280025-Q1, TMS320F280025C-Q1, TMS320F280023-Q1,
and TMS320F280021-Q1. Updated table...........................................................................................................1
• Table 6-1 (Pin Attributes): Updated muxed signal names of A7. Updated DESCRIPTION of VDD: Changed
recommended total capacitance from 22 µF to 10 µF.......................................................................................11
• Removed Digital Signals by GPIO section (Section 6.3.2 in SPRSP45A)........................................................29
• Section 6.3.2 (Digital Signals): Added section..................................................................................................29
• Table 6-4 (Power and Ground): Updated DESCRIPTION of VDD: Changed recommended total capacitance
from 22 µF to 10 µF...........................................................................................................................................29
• Section 7.2 (ESD Ratings – Commercial): Updated device numbers...............................................................48
• Section 7.3 (ESD Ratings – Automotive): Updated device numbers. Added data for 64-pin PM package...... 49
• Section 7.5.1 (System Current Consumption): Updated table..........................................................................51
• Section 7.11.1.1 (Internal 1.2-V LDO Voltage Regulator (VREG)): Updated Configuration 1.......................... 58
• Section 7.11.3.5.1 (INTOSC Characteristics): Updated table........................................................................... 69
• Table 7-5 (Flash Parameters): Changed "Nwec Write/Erase Cycles" to "Nwec Write/Erase Cycles per sector".
Added "Nwec Write/Erase Cycles for entire Flash (combined all sectors)"........................................................70
• Section 7.14.8 (Host Interface Controller (HIC)): Updated "The HIC module allows ..." paragraph............... 149
• Figure 7-70 (HIC Block Diagram): Removed "Bus Master Interface" label.....................................................149
• Figure 10-1 (Device Nomenclature): Updated figure...................................................................................... 179
• Section 10.4 (Tools and Software): Added LAUNCHXL-F280025C to Development Tools section............. 182
6
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TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Changes from March 17, 2020 to October 3, 2020 (from Revision * (March 2020) to Revision A
(October 2020))
Page
• Global: Updated the numbering format for tables, figures, and cross-references throughout the document.... 1
• Global: This document is now PRODUCTION DATA........................................................................................ 1
• Global: Removed TMS320F280024, TMS320F280024C, and TMS320F280022............................................. 1
• Global: Removed 64 QFP-Q data......................................................................................................................1
• Section 1 (Features): Updated Serial Communication Interface (SCI) feature. Updated Local Interconnect
Network (LIN) feature......................................................................................................................................... 1
• Table 5-1 (Device Comparison): Updated table..................................................................................................1
• Section 2 (Applications): Updated section.......................................................................................................... 2
• Section 3 (Description): Updated section........................................................................................................... 2
• Device Information: Updated table..................................................................................................................... 2
• Figure 3-1 (Functional Block Diagram): Updated figure..................................................................................... 4
• Table 6-1 (Pin Attributes): Updated table.......................................................................................................... 11
• Figure 6-2 (64-Pin PM Low-Profile Quad Flatpack (Top View)): Updated figure...............................................11
• Removed "64-Pin PM Low-Profile Quad Flatpack – Q-Temperature (Top View)" figure...................................11
• Removed Digital Signals section (Section 4.3.2 in SPRSP45).........................................................................29
• Digital Signals by GPIO: Added section........................................................................................................... 29
• Table 6-4 (Power and Ground): Updated DESCRIPTION of VDD and VDDIO................................................ 29
• Section 6.4.1.1 (GPIO Muxed Pins Table): Added Note about AIO pins.......................................................... 40
• Table 6-6 (GPIO Muxed Pins): Updated table.................................................................................................. 40
• Section 6.4.4 (GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR): Changed section
title from "GPIO Output X-BAR and ePWM X-BAR" to "GPIO Output X-BAR, CLB X-BAR, CLB Output XBAR, and ePWM X-BAR". Updated section..................................................................................................... 44
• Figure 6-5 (Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR Sources): Replaced "Output
X-BAR and ePWM X-BAR Sources" figure with "Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM
X-BAR Sources" figure..................................................................................................................................... 44
• Table 6-9 (Connections for Unused Pins): Added "Analog input pins" in ANALOG section............................. 47
• Section 7 (Specifications): Updated section and tables....................................................................................48
• Section 7.1 (Absolute Maximum Ratings): Updated table................................................................................ 48
• Section 7.4 (Recommended Operating Conditions): Updated SRSUPPLY values and unit................................ 48
• Section 7.6 (Electrical Characteristics): Updated ROH and ROL values............................................................ 48
• Section 7.3 (ESD Ratings – Automotive): Removed F280024, F280024C, and F280022 data....................... 49
• Section 7.5.3 (Current Consumption Graphs): Added section..........................................................................52
• Section 7.5.4 (Reducing Current Consumption): Updated section................................................................... 54
• Section 7.5.4.1 (Typical Current Reduction per Disabled Peripheral): Updated table...................................... 54
• Section 7.7 (Thermal Resistance Characteristics for PN Package): Added section.........................................56
• Section 7.8 (Thermal Resistance Characteristics for PM Package): Added section........................................ 56
• Section 7.9 (Thermal Resistance Characteristics for PT Package): Added section......................................... 57
• Section 7.11.2.2.1 (Reset (XRSn) Timing Requirements): Updated tw(RSL2).................................................... 60
• Section 7.11.2.2.2 (Reset (XRSn) Switching Characteristics): Added tboot-flash................................................ 60
• Figure 7-8 (Power-on Reset): Updated figure...................................................................................................60
• Section 7.11.3.2.1.6 (Internal Clock Frequencies): Updated MAX f(VCOCLK).....................................................65
• Section 7.11.3.5 (Internal Oscillators): Updated section...................................................................................69
• Section 7.11.3.5.1 (INTOSC Characteristics): Updated fINTOSC MIN values and MAX values......................... 69
• Section 7.11.4 (Flash Parameters): Updated section....................................................................................... 70
• Table 7-4 (Minimum Required Flash Wait States with Different Clock Sources and Frequencies): Updated
table and footnotes........................................................................................................................................... 70
• Table 7-5 (Flash Parameters): Added "The on-chip flash memory is in an erased state ..." footnote.............. 70
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7
TMS320F280025, TMS320F280025-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
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•
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8
Section 7.11.5 (Emulation/JTAG): Updated link of Hardware Breakpoints and Watchpoints for C28x in CCS....
72
Figure 7-31 (Analog Group Connections): Added figure.................................................................................. 86
Figure 7-35 (ADC Timings): Updated tINT......................................................................................................... 98
Section 7.14.2.1.1 (I2C Timing Requirements): Updated table...................................................................... 125
Section 7.14.2.1.2 (I2C Switching Characteristics): Updated table................................................................ 125
Figure 7-54 (I2C Timing Diagram): Added figure............................................................................................125
Figure 7-56 (SCI Block Diagram): Updated figure.......................................................................................... 130
Figure 7-59 (SPI Master Mode External Timing (Clock Phase = 1)): Updated parameter 24.........................134
Section 7.14.5.2.1 (SPI Slave Mode Timing Requirements): Updated MIN value of tsu(STE)S........................ 138
Section 7.14.8 (Host Interface Controller (HIC)): Updated list of features......................................................149
Figure 7-70 (HIC Block Diagram): Updated figure..........................................................................................149
Section 7.14.8.1.1 (HIC Timing Requirements): Updated table......................................................................150
Section 7.14.8.1.2 (HIC Switching Characteristics): Updated table................................................................150
Figure 7-71 (Read/Write Operation With nOE and nWE Pins): Added figure.................................................151
Figure 7-72 (Read/Write Operation With RnW Pin): Added figure..................................................................151
Figure 8-1 (Functional Block Diagram): Added "Secure Memories shown in Red" legend box..................... 154
Table 8-2 (Addresses of Flash Sectors): Updated table................................................................................. 156
Table 8-4 (Device Identification Registers): Removed PARTIDH for TMS320F280024, TMS320F280024C,
and TMS320F280022..................................................................................................................................... 160
Table 8-4: Added REVID for Revision A silicon.............................................................................................. 160
Table 8-4: Updated ADDRESS of UID_UNIQUE............................................................................................160
Section 8.10 (Device Boot Modes): Updated section..................................................................................... 166
Section 8.10.1 (Device Boot Configurations): Added Note about CAN boot mode turning on the XTAL....... 166
Figure 8-3 (Windowed Watchdog): Removed SCSR.WDOVERRIDE............................................................ 173
Section 9.1 (TI Reference Design): Updated section..................................................................................... 178
Removed Related Links section (Section 10.5 in SPRSP45).........................................................................179
Section 10.1 (Getting Started and Next Steps): Added section......................................................................179
Section 10.2 (Device and Development Support Tool Nomenclature): Updated section................................179
Figure 10-1 (Device Nomenclature): Removed 280024, 280024C, and 280022 from DEVICE..................... 179
Figure 10-2 (Package Symbolization for PM and PN Packages): Updated figure..........................................180
Figure 10-3 (Package Symbolization for PT Package): Updated figure......................................................... 180
Table 10-1 (Revision Identification): Added data for Revision A silicon..........................................................180
Section 10.4 (Tools and Software): Updated section......................................................................................182
Section 10.5 (Documentation Support): Updated section...............................................................................183
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TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
5 Device Comparison
Table 5-1. Device Comparison
FEATURE
F280025
F280025-Q1
F280025C
F280025C-Q1
(1)
F280023
F280023-Q1
F280023C
F280021
F280021-Q1
PROCESSOR AND ACCELERATORS
Frequency (MHz)
C28x
100
FPU32
Yes (with new instructions for Fast Integer Division)
VCRC
Yes
TMU – Type 1
Yes (with new instructions supporting NLPID)
Fast Integer Division
Yes
DMA – Type 0
Yes
MEMORY
Flash
128KB (64KW)
Dedicated and Local Shared RAM
32KB (16KW)
20KB (10KW)
Global Shared RAM
RAM
64KB (32KW)
4KB (2KW)
TOTAL RAM
24KB (12KW)
Code security for on-chip flash and RAM
Yes
SYSTEM
Configurable Logic Block (CLB)
(2)
(F280025C-2 tiles) (F280023C-2 tiles)
32-bit CPU timers
3
Watchdog-timer
1
Nonmaskable Interrupt Watchdog (NMIWD) timers
1
Crystal oscillator/External clock input
1
0-pin internal oscillator
2
80-pin PN
GPIO pins
39
64-pin PM
26
48-pin PT
16
4 (When cJTAG is used, TDI and TDO can be GPIO;
When INTOSC is used as clock source, X1 and X2 can be
GPIO)
Additional GPIO
80-pin PN
AIO inputs
-
16
64-pin PM
16
48-pin PT
14
External interrupts
5
ANALOG PERIPHERALS
Number of ADCs
ADC 12-bit
2
MSPS
Conversion-time (ns)
ADC channels (single-ended)
3.45
(3)
290
80-pin PN
16
64-pin PM
16
48-pin PT
14
Temperature sensor
1
CMPSS (each has two comparators and two internal DACs)
4
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9
TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table 5-1. Device Comparison (continued)
FEATURE
(1)
F280025
F280025-Q1
F280025C
F280025C-Q1
F280023
F280023-Q1
F280023C
F280021
F280021-Q1
(4)
CONTROL PERIPHERALS
eCAP/HRCAP modules – Type 1
3 (1 with HRCAP capability)
ePWM/HRPWM channels – Type 4
14 (8 with HRPWM capability)
eQEP modules – Type 2
2
COMMUNICATION PERIPHERALS
(4)
CAN – Type 0
1
I2C – Type 1
2
SCI – Type 0 (UART-Compatible)
1
SPI – Type 2
2
LIN – Type 1 (UART-Compatible)
2
PMBus – Type 0
1
FSI – Type 1
1 (1 RX and 1 TX)
PACKAGE, TEMPERATURE, AND QUALIFICATION OPTIONS
80-pin PN
S: –40°C to 125°C (TJ)
64-pin PM
–
F280025
F280025C
F280023
F280023C
48-pin PT
F280021
80-pin PN
(5)
Q: –40°C to 125°C (TA)
64-pin PM
–
F280025-Q1
F280025C-Q1
F280023-Q1
48-pin PT
(1)
(2)
(3)
(4)
(5)
–
–
F280021-Q1
A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module.
C devices include additional Motor Control libraries in ROM. Contact TI for more information.
Time between start of sample-and-hold window to start of sample-and-hold window of the next conversion.
For devices that are available in more than one package, the peripheral count listed in the smaller package is reduced because the
smaller package has less device pins available. The number of peripherals internally present on the device is not reduced co
The letter Q refers to AEC Q100 qualification for automotive applications.
5.1 Related Products
TMS320F2803x Real-Time Microcontrollers
The F2803x series increases the pin-count and memory size options. The F2803x series also introduces the
parallel control law accelerator (CLA) option.
TMS320F2807x Real-Time Microcontrollers
The F2807x series offers the most performance, largest pin counts, flash memory sizes, and peripheral options.
The F2807x series includes the latest generation of accelerators, ePWM peripherals, and analog technology.
TMS320F28004x Real-Time Microcontrollers
The F28004x series is a reduced version of the F2807x series with the latest generational enhancements.
TMS320F2838x Real-Time Microcontrollers
The F2838x series offers more performance, larger pin counts, flash memory sizes, peripheral and wide variety
of connectivity options. The F2838x series includes the latest generation of accelerators, ePWM peripherals, and
analog technology. Configurable logic block (CLB) versions are available.
10
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TMS320F280023 TMS320F280023-Q1 TMS320F280023C TMS320F280021 TMS320F280021-Q1
TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
www.ti.com
SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
6 Terminal Configuration and Functions
6.1 Pin Diagrams
GPIO3
GPIO4
GPIO8
GPIO42
GPIO39
VSS
GPIO43
VDD
VDDIO
GPIO19,X1
GPIO18,X2
GPIO32
GPIO35/TDI
TMS
GPIO37/TDO
TCK
GPIO27
GPIO26
GPIO25
GPIO24
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
Figure 6-1 shows the pin assignments on the 80-pin PN low-profile quad flatpack (Q temperature). Figure 6-2
shows the pin assignments on the 64-pin PM low-profile quad flatpack. Figure 6-3 shows the pin assignments on
the 48-Pin PT low-profile quad flatpack.
GPIO2
61
40
GPIO17
GPIO1
62
39
GPIO16
GPIO0
63
38
GPIO33
GPIO40
64
37
GPIO11
GPIO23
65
36
GPIO12
GPIO41
66
35
GPIO13
GPIO22
67
34
FLT1
GPIO7
68
33
FLT2
GPIO44
69
32
VDDIO
VSS
70
31
VDD
VDD
71
30
VSS
VDDIO
72
29
A10,C10
GPIO45
73
28
A9,C8
GPIO5
74
27
A4,C14
20
VREFHI
19
A0,C15
A1
A5,C2
A11,C0
A14,C4
A15,C7
A2,C9
A3,C5
C6
A6
VSS
VDD
VDDIO
GPIO46
XRSn
GPIO28
GPIO29
GPIO31
GPIO30
18
VREFLO
17
A12,C1
21
16
22
80
15
79
GPIO6
14
GPIO14
13
A7,C3
12
23
11
78
10
GPIO15
9
A8,C11
8
24
7
77
6
GPIO34
5
VSSA
4
VDDA
25
3
26
76
2
75
1
GPIO9
GPIO10
Not to scale
A. Only the GPIO function is shown on GPIO terminals. See Table 6-1 for the complete, muxed signal name.
Figure 6-1. 80-Pin PN Low-Profile Quad Flatpack (Top View)
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TMS320F280023 TMS320F280023-Q1 TMS320F280023C TMS320F280021 TMS320F280021-Q1
11
TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
www.ti.com
GPIO4
GPIO8
GPIO39
VSS
VDD
VDDIO
GPIO19_X1
GPIO18_X2
GPIO32
GPIO35/TDI
TMS
GPIO37/TDO
TCK
GPIO24
GPIO17
GPIO16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
GPIO40
53
28
VDDIO
GPIO23
54
27
VDD
GPIO41
55
26
VSS
GPIO22
56
25
A10,C10
GPIO7
57
24
A9,C8
VSS
58
23
A4,C14
VDD
59
22
VDDA
VDDIO
60
21
VSSA
GPIO5
61
20
A8,C11
GPIO9
62
19
A7,C3
GPIO10
63
18
A12,C1
GPIO6
64
17
VREFLO
VREFHI
A0,C15
A1
A5,C2
A11,C0
A14,C4
A15,C7
A2,C9
A3,C5,VDAC
C6
A6
VSS
VDD
XRSn
GPIO28
GPIO29
16
GPIO13
15
29
14
52
13
GPIO0
12
GPIO12
11
30
10
51
9
GPIO1
8
GPIO11
7
31
6
50
5
GPIO2
4
GPIO33
3
32
2
49
1
GPIO3
Not to scale
A. Only the GPIO function is shown on GPIO terminals. See Table 6-1 for the complete, muxed signal name.
Figure 6-2. 64-Pin PM Low-Profile Quad Flatpack (Top View)
12
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TMS320F280023 TMS320F280023-Q1 TMS320F280023C TMS320F280021 TMS320F280021-Q1
TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
www.ti.com
VDD
VDDIO
GPIO19_X1
GPIO18_X2
GPIO32
GPIO35/TDI
TMS
GPIO37/TDO
TCK
GPIO24
GPIO16
GPIO33
36
35
34
33
32
31
30
29
28
27
26
25
SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
GPIO2
40
21
A10,C10
GPIO1
41
20
A9,C8
GPIO0
42
19
A4,C14
GPIO7
43
18
VDDA
VSS
44
17
VSSA
VDD
45
16
A8,C11
VDDIO
46
15
A7,C3
GPIO5
47
14
A12,C1
GPIO6
48
13
VREFLO
VREFHI
A0,C15
A1
A5,C2
A11,C0
A15,C7
A2,C9
A3,C5,VDAC
A6,C6
XRSn
GPIO28
GPIO29
12
VSS
11
22
10
39
9
GPIO3
8
GPIO13
7
23
6
38
5
GPIO4
4
GPIO12
3
24
2
37
1
VSS
Not to scale
A. Only the GPIO function is shown on GPIO terminals. See Table 6-1 for the complete, muxed signal name.
Figure 6-3. 48-Pin PT Low-Profile Quad Flatpack (Top View)
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TMS320F280023 TMS320F280023-Q1 TMS320F280023C TMS320F280021 TMS320F280021-Q1
13
TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
6.2 Pin Attributes
Table 6-1. Pin Attributes
SIGNAL NAME
MUX
POSITION
80 QFP
64 QFP
48 QFP
PIN
TYPE
DESCRIPTION
ANALOG
A0
I
ADC-A Input 0
C15
I
ADC-C Input 15
CMP3_HP2
I
CMPSS-3 High Comparator Positive Input 2
19
CMP3_LP2
AIO231
15
11
I
CMPSS-3 Low Comparator Positive Input 2
0, 4, 8, 12
I
Analog Pin Used For Digital Input 231
15
I
HIC Base Address Range Select 1
HIC_BASESEL1
A1
I
Analog Input
CMP1_HP4
I
CMPSS-1 High Comparator Positive Input 4
CMP1_LP4
AIO232
I
CMPSS-1 Low Comparator Positive Input 4
0, 4, 8, 12
I
Analog Pin Used For Digital Input 232
15
I
HIC Base Address Range Select 0
I
ADC-A Input 10
18
HIC_BASESEL0
14
10
A10
C10
I
ADC-C Input 10
CMP2_HP3
I
CMPSS-2 High Comparator Positive Input 3
I
CMPSS-2 High Comparator Negative Input 0
I
CMPSS-2 Low Comparator Positive Input 3
I
CMPSS-2 Low Comparator Negative Input 0
0, 4, 8, 12
I
Analog Pin Used For Digital Input 230
15
I
HIC Base Address Range Select 2
I
ADC-A Input 11
CMP2_HN0
29
CMP2_LP3
25
21
CMP2_LN0
AIO230
HIC_BASESEL2
A11
C0
I
ADC-C Input 0
CMP1_HP1
I
CMPSS-1 High Comparator Positive Input 1
I
CMPSS-1 High Comparator Negative Input 1
I
CMPSS-1 Low Comparator Positive Input 1
I
CMPSS-1 Low Comparator Negative Input 1
CMP1_HN1
16
CMP1_LP1
12
8
CMP1_LN1
AIO237
0, 4, 8, 12
I
Analog Pin Used For Digital Input 237
HIC_A6
15
I
HIC Address 6
A12
I
ADC-A Input 12
C1
I
ADC-C Input 1
CMP2_HP1
I
CMPSS-2 High Comparator Positive Input 1
CMP4_HP2
I
CMPSS-4 High Comparator Positive Input 2
CMP2_HN1
I
CMPSS-2 High Comparator Negative Input 1
22
CMP2_LP1
18
14
I
CMPSS-2 Low Comparator Positive Input 1
CMP4_LP2
I
CMPSS-4 Low Comparator Positive Input 2
CMP2_LN1
I
CMPSS-2 Low Comparator Negative Input 1
0, 4, 8, 12
I
Analog Pin Used For Digital Input 238
15
I
HIC Chip Select
AIO238
HIC_NCS
A14
I
ADC-A Input 14
C4
I
ADC-C Input 4
I
CMPSS-3 High Comparator Positive Input 4
I
CMPSS-3 Low Comparator Positive Input 4
CMP3_HP4
15
CMP3_LP4
11
AIO239
0, 4, 8, 12
I
Analog Pin Used For Digital Input 239
HIC_A5
15
I
HIC Address 5
14
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TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
www.ti.com
SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table 6-1. Pin Attributes (continued)
SIGNAL NAME
MUX
POSITION
80 QFP
64 QFP
48 QFP
PIN
TYPE
DESCRIPTION
A15
I
ADC-A Input 15
C7
I
ADC-C Input 7
CMP1_HP3
I
CMPSS-1 High Comparator Positive Input 3
CMP1_HN0
I
CMPSS-1 High Comparator Negative Input 0
I
CMPSS-1 Low Comparator Positive Input 3
14
CMP1_LP3
10
7
CMP1_LN0
I
CMPSS-1 Low Comparator Negative Input 0
AIO233
0, 4, 8, 12
I
Analog Pin Used For Digital Input 233
HIC_A4
15
I
HIC Address 4
A2
I
ADC-A Input 2
C9
I
ADC-C Input 9
CMP1_HP0
13
CMP1_LP0
9
6
I
CMPSS-1 High Comparator Positive Input 0
I
CMPSS-1 Low Comparator Positive Input 0
AIO224
0, 4, 8, 12
I
Analog Pin Used For Digital Input 224
HIC_A3
15
I
HIC Address 3
A3
I
ADC-A Input 3
C5
I
ADC-C Input 5
I
Optional external reference voltage for on-chip
CMPSS DACs. There is an internal capacitor to
VSSA on this pin whether used for ADC input or
CMPSS DAC reference which cannot be disabled. If
this pin is being used as a reference for the CMPSS
DACs, place at least a 1-µF capacitor on this pin.
CMP3_HP3
I
CMPSS-3 High Comparator Positive Input 3
CMP3_HN0
I
CMPSS-3 High Comparator Negative Input 0
CMP3_LP3
I
CMPSS-3 Low Comparator Positive Input 3
CMP3_LN0
I
CMPSS-3 Low Comparator Negative Input 0
VDAC
12
8
5
AIO242
0, 4, 8, 12
I
Analog Pin Used For Digital Input 242
HIC_A2
15
I
HIC Address 2
A4
I
ADC-A Input 4
C14
I
ADC-C Input 14
CMP2_HP0
I
CMPSS-2 High Comparator Positive Input 0
CMP4_HP3
I
CMPSS-4 High Comparator Positive Input 3
CMP4_HN0
I
CMPSS-4 High Comparator Negative Input 0
I
CMPSS-2 Low Comparator Positive Input 0
CMP4_LP3
I
CMPSS-4 Low Comparator Positive Input 3
CMP4_LN0
I
CMPSS-4 Low Comparator Negative Input 0
0, 4, 8, 12
I
Analog Pin Used For Digital Input 225
15
27
CMP2_LP0
AIO225
HIC_NWE
23
19
I
HIC Data Write Enable
A5
I
ADC-A Input 5
C2
I
ADC-C Input 2
CMP3_HP1
I
CMPSS-3 High Comparator Positive Input 1
CMP3_HN1
17
CMP3_LP1
CMP3_LN1
13
9
I
CMPSS-3 High Comparator Negative Input 1
I
CMPSS-3 Low Comparator Positive Input 1
I
CMPSS-3 Low Comparator Negative Input 1
AIO244
0, 4, 8, 12
I
Analog Pin Used For Digital Input 244
HIC_A7
15
I
HIC Address 7
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15
TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
www.ti.com
SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table 6-1. Pin Attributes (continued)
SIGNAL NAME
MUX
POSITION
80 QFP
64 QFP
48 QFP
PIN
TYPE
DESCRIPTION
A6
I
Analog Input
CMP1_HP2
I
CMPSS-1 High Comparator Positive Input 2
10
CMP1_LP2
6
4
I
CMPSS-1 Low Comparator Positive Input 2
AIO228
0, 4, 8, 12
I
Analog Pin Used For Digital Input 228
HIC_A0
15
I
HIC Address 0
A7
I
ADC-A Input 7
C3
I
ADC-C Input 3
CMP4_HP1
I
CMPSS-4 High Comparator Positive Input 1
CMP4_HN1
I
CMPSS-4 High Comparator Negative Input 1
I
CMPSS-4 Low Comparator Positive Input 1
23
CMP4_LP1
19
15
CMP4_LN1
AIO245
I
CMPSS-4 Low Comparator Negative Input 1
0, 4, 8, 12
I
Analog Pin Used For Digital Input 245
15
O
HIC Output Enable
I
ADC-A Input 8
HIC_NOE
A8
C11
I
ADC-C Input 11
CMP2_HP4
I
CMPSS-2 High Comparator Positive Input 4
I
CMPSS-4 High Comparator Positive Input 4
I
CMPSS-2 Low Comparator Positive Input 4
I
CMPSS-4 Low Comparator Positive Input 4
0, 4, 8, 12
I
Analog Pin Used For Digital Input 241
15
I
HIC Byte Enable 1
A9
I
ADC-A Input 9
C8
I
ADC-C Input 8
CMP2_HP2
I
CMPSS-2 High Comparator Positive Input 2
I
CMPSS-4 High Comparator Positive Input 0
I
CMPSS-2 Low Comparator Positive Input 2
I
CMPSS-4 Low Comparator Positive Input 0
0, 4, 8, 12
I
Analog Pin Used For Digital Input 227
15
I
HIC Byte Enable 0
CMP4_HP4
24
CMP2_LP4
20
16
CMP4_LP4
AIO241
HIC_NBE1
CMP4_HP0
28
CMP2_LP2
24
20
CMP4_LP0
AIO227
HIC_NBE0
C6
I
Analog Input
CMP3_HP0
I
CMPSS-3 High Comparator Positive Input 0
CMP3_LP0
I
CMPSS-3 Low Comparator Positive Input 0
AIO226
0, 4, 8, 12
I
Analog Pin Used For Digital Input 226
HIC_A1
15
I
HIC Address 1
11
7
4
VREFHI
20
16
12
I
ADC- High Reference. In external reference mode,
externally drive the high reference voltage onto this
pin. In internal reference mode, a voltage is driven
onto this pin by the device. In either mode, place at
least a 2.2-µF capacitor on this pin. This capacitor
should be placed as close to the device as possible
between the VREFHI and VREFLO pins.
VREFLO
21
17
13
I
ADC- Low Reference
16
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TMS320F280023 TMS320F280023-Q1 TMS320F280023C TMS320F280021 TMS320F280021-Q1
TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table 6-1. Pin Attributes (continued)
SIGNAL NAME
MUX
POSITION
80 QFP
64 QFP
48 QFP
PIN
TYPE
DESCRIPTION
GPIO
GPIO0
0, 4, 8, 12
I/O
General-Purpose Input Output 0
ePWM-1 Output A
EPWM1_A
1
O
I2CA_SDA
6
I/OD
I2C-A Open-Drain Bidirectional Data
SPIA_STE
7
I/O
SPI-A Slave Transmit Enable (STE)
63
52
42
FSIRXA_CLK
9
I
FSIRX-A Input Clock
CLB_OUTPUTXBAR8
11
O
CLB Output X-BAR Output 8
15
I
HIC Base Address Range Select 1
0, 4, 8, 12
I/O
General-Purpose Input Output 1
ePWM-1 Output B
HIC_BASESEL1
GPIO1
EPWM1_B
1
O
I2CA_SCL
6
I/OD
SPIA_SOMI
7
I/O
SPI-A Slave Out, Master In (SOMI)
62
51
41
I2C-A Open-Drain Bidirectional Clock
CLB_OUTPUTXBAR7
11
O
CLB Output X-BAR Output 7
HIC_A2
13
I
HIC Address 2
FSITXA_TDM_D1
14
I
FSITX-A Time Division Multiplexed Additional Data
Input
HIC_D10
15
I/O
GPIO2
HIC Data 10
0, 4, 8, 12
I/O
General-Purpose Input Output 2
EPWM2_A
1
O
ePWM-2 Output A
OUTPUTXBAR1
5
O
Output X-BAR Output 1
PMBUSA_SDA
6
I/OD
SPIA_SIMO
7
I/O
SPI-A Slave In, Master Out (SIMO)
PMBus-A Open-Drain Bidirectional Data
SCIA_TX
9
O
SCI-A Transmit Data
FSIRXA_D1
10
I
FSIRX-A Data Input 1
I2CB_SDA
11
I/OD
HIC_A1
13
I
HIC Address 1
CANA_TX
14
O
CAN-A Transmit
HIC_D9
15
I/O
HIC Data 9
GPIO3
0, 4, 8, 12
I/O
General-Purpose Input Output 3
EPWM2_B
61
50
40
I2C-B Open-Drain Bidirectional Data
1
O
ePWM-2 Output B
2, 5
O
Output X-BAR Output 2
PMBUSA_SCL
6
I/OD
SPIA_CLK
7
I/O
SCIA_RX
9
FSIRXA_D0
10
I
I2CB_SCL
11
I/OD
HIC_NOE
13
O
HIC Output Enable
CANA_RX
14
I
CAN-A Receive
HIC_D4
15
I/O
OUTPUTXBAR2
Copyright © 2020 Texas Instruments Incorporated
60
49
39
I
PMBus-A Open-Drain Bidirectional Clock
SPI-A Clock
SCI-A Receive Data
FSIRX-A Data Input 0
I2C-B Open-Drain Bidirectional Clock
HIC Data 4
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17
TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table 6-1. Pin Attributes (continued)
SIGNAL NAME
GPIO4
MUX
POSITION
80 QFP
64 QFP
48 QFP
PIN
TYPE
DESCRIPTION
0, 4, 8, 12
I/O
General-Purpose Input Output 4
EPWM3_A
1
O
ePWM-3 Output A
OUTPUTXBAR3
5
O
Output X-BAR Output 3
CANA_TX
6
O
CAN-A Transmit
SPIB_CLK
7
I/O
SPI-B Clock
I/O
eQEP-2 Strobe
59
48
38
EQEP2_STROBE
9
FSIRXA_CLK
10
I
FSIRX-A Input Clock
CLB_OUTPUTXBAR6
11
O
CLB Output X-BAR Output 6
HIC_BASESEL2
13
I
HIC Base Address Range Select 2
HIC_NWE
15
I
HIC Data Write Enable
0, 4, 8, 12
I/O
General-Purpose Input Output 5
EPWM3_B
GPIO5
1
O
ePWM-3 Output B
OUTPUTXBAR3
3
O
Output X-BAR Output 3
CANA_RX
6
I
CAN-A Receive
SPIA_STE
7
I/O
SPI-A Slave Transmit Enable (STE)
O
FSITX-A Data Output 1
O
CLB Output X-BAR Output 5
HIC Address 7
74
61
47
FSITXA_D1
9
CLB_OUTPUTXBAR5
10
HIC_A7
13
I
HIC_D4
14
I/O
HIC Data 4
HIC_D15
15
I/O
HIC Data 15
0, 4, 8, 12
I/O
General-Purpose Input Output 6
EPWM4_A
GPIO6
1
O
ePWM-4 Output A
OUTPUTXBAR4
2
O
Output X-BAR Output 4
SYNCOUT
3
O
External ePWM Synchronization Pulse
EQEP1_A
5
I
eQEP-1 Input A
SPIB_SOMI
7
FSITXA_D0
80
64
48
I/O
SPI-B Slave Out, Master In (SOMI)
9
O
FSITX-A Data Output 0
FSITXA_D1
11
O
FSITX-A Data Output 1
HIC_NBE1
13
I
HIC Byte Enable 1
CLB_OUTPUTXBAR8
14
O
CLB Output X-BAR Output 8
HIC_D14
15
I/O
HIC Data 14
0, 4, 8, 12
I/O
General-Purpose Input Output 7
EPWM4_B
1
O
ePWM-4 Output B
OUTPUTXBAR5
3
O
Output X-BAR Output 5
EQEP1_B
5
I
eQEP-1 Input B
SPIB_SIMO
7
FSITXA_CLK
GPIO7
68
57
43
I/O
SPI-B Slave In, Master Out (SIMO)
9
O
FSITX-A Output Clock
CLB_OUTPUTXBAR2
10
O
CLB Output X-BAR Output 2
HIC_A6
13
I
HIC Address 6
HIC_D14
15
I/O
18
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HIC Data 14
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TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table 6-1. Pin Attributes (continued)
SIGNAL NAME
GPIO8
MUX
POSITION
80 QFP
64 QFP
48 QFP
PIN
TYPE
DESCRIPTION
0, 4, 8, 12
I/O
General-Purpose Input Output 8
EPWM5_A
1
O
ePWM-5 Output A
ADCSOCAO
3
O
ADC Start of Conversion A for External ADC
EQEP1_STROBE
5
I/O
eQEP-1 Strobe
SCIA_TX
6
O
SCI-A Transmit Data
SPIA_SIMO
7
I/O
SPI-A Slave In, Master Out (SIMO)
I2CA_SCL
9
FSITXA_D1
10
O
FSITX-A Data Output 1
CLB_OUTPUTXBAR5
11
O
CLB Output X-BAR Output 5
HIC_A0
13
I
HIC Address 0
58
47
I/OD
FSITXA_TDM_CLK
14
I
HIC_D8
15
I/O
GPIO9
I2C-A Open-Drain Bidirectional Clock
FSITX-A Time Division Multiplexed Clock Input
HIC Data 8
0, 4, 8, 12
I/O
General-Purpose Input Output 9
EPWM5_B
1
O
ePWM-5 Output B
OUTPUTXBAR6
3
O
Output X-BAR Output 6
EQEP1_INDEX
5
I/O
eQEP-1 Index
SCIA_RX
6
I
SCI-A Receive Data
SPIA_CLK
7
I/O
SPI-A Clock
FSITXA_D0
10
O
FSITX-A Data Output 0
LINB_RX
11
I
LIN-B Receive
HIC_BASESEL0
13
I
HIC Base Address Range Select 0
I2CB_SCL
14
I/OD
HIC_NRDY
75
62
I2C-B Open-Drain Bidirectional Clock
15
O
HIC Ready
0, 4, 8, 12
I/O
General-Purpose Input Output 10
EPWM6_A
1
O
ePWM-6 Output A
ADCSOCBO
3
O
ADC Start of Conversion B for External ADC
EQEP1_A
5
I
eQEP-1 Input A
SPIA_SOMI
7
I2CA_SDA
9
FSITXA_CLK
10
O
FSITX-A Output Clock
LINB_TX
11
O
LIN-B Transmit
HIC_NWE
13
I
HIC Data Write Enable
FSITX-A Time Division Multiplexed Data Input
GPIO10
FSITXA_TDM_D0
76
63
I/O
I/OD
SPI-A Slave Out, Master In (SOMI)
I2C-A Open-Drain Bidirectional Data
14
I
0, 4, 8, 12
I/O
General-Purpose Input Output 11
EPWM6_B
1
O
ePWM-6 Output B
OUTPUTXBAR7
3
O
Output X-BAR Output 7
EQEP1_B
5
I
eQEP-1 Input B
SPIA_STE
7
FSIRXA_D1
9
LINB_RX
EQEP2_A
GPIO11
I/O
37
31
SPI-A Slave Transmit Enable (STE)
I
FSIRX-A Data Input 1
10
I
LIN-B Receive
11
I
eQEP-2 Input A
SPIA_SIMO
13
I/O
SPI-A Slave In, Master Out (SIMO)
HIC_D6
14
I/O
HIC Data 6
HIC_NBE0
15
I
Copyright © 2020 Texas Instruments Incorporated
HIC Byte Enable 0
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19
TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table 6-1. Pin Attributes (continued)
SIGNAL NAME
GPIO12
MUX
POSITION
80 QFP
64 QFP
48 QFP
PIN
TYPE
DESCRIPTION
0, 4, 8, 12
I/O
General-Purpose Input Output 12
EPWM7_A
1
O
ePWM-7 Output A
EQEP1_STROBE
5
I/O
eQEP-1 Strobe
PMBUSA_CTL
7
I/O
PMBus-A Control Signal - Slave Input/Master Output
FSIRXA_D0
9
I
FSIRX-A Data Input 0
LINB_TX
10
O
LIN-B Transmit
SPIA_CLK
11
I/O
SPI-A Clock
CANA_RX
13
I
HIC_D13
14
I/O
HIC Data 13
HIC_INT
15
O
HIC Device Interrupt
GPIO13
36
30
24
CAN-A Receive
0, 4, 8, 12
I/O
General-Purpose Input Output 13
EPWM7_B
1
O
ePWM-7 Output B
EQEP1_INDEX
5
I/O
eQEP-1 Index
PMBUSA_ALERT
7
I/OD
FSIRXA_CLK
9
I
FSIRX-A Input Clock
LINB_RX
10
I
LIN-B Receive
SPIA_SOMI
11
CANA_TX
HIC_D11
35
29
23
PMBus-A Open-Drain Bidirectional Alert
I/O
SPI-A Slave Out, Master In (SOMI)
13
O
CAN-A Transmit
14
I/O
HIC Data 11
HIC_D5
15
I/O
HIC Data 5
GPIO14
General-Purpose Input Output 14
0, 4, 8, 12
I/O
I2CB_SDA
5
I/OD
OUTPUTXBAR3
6
O
PMBUSA_SDA
7
I/OD
SPIB_CLK
9
EQEP2_A
10
LINB_TX
79
I/O
I2C-B Open-Drain Bidirectional Data
Output X-BAR Output 3
PMBus-A Open-Drain Bidirectional Data
SPI-B Clock
I
eQEP-2 Input A
11
O
LIN-B Transmit
EPWM3_A
13
O
ePWM-3 Output A
CLB_OUTPUTXBAR7
14
O
CLB Output X-BAR Output 7
HIC_D15
15
I/O
HIC Data 15
GPIO15
0, 4, 8, 12
I/O
General-Purpose Input Output 15
I2CB_SCL
5
I/OD
OUTPUTXBAR4
6
O
PMBUSA_SCL
7
I/OD
SPIB_STE
9
EQEP2_B
10
LINB_RX
78
I/O
I2C-B Open-Drain Bidirectional Clock
Output X-BAR Output 4
PMBus-A Open-Drain Bidirectional Clock
SPI-B Slave Transmit Enable (STE)
I
eQEP-2 Input B
11
I
LIN-B Receive
EPWM3_B
13
O
ePWM-3 Output B
CLB_OUTPUTXBAR6
14
O
CLB Output X-BAR Output 6
HIC_D12
15
I/O
HIC Data 12
20
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TMS320F280023 TMS320F280023-Q1 TMS320F280023C TMS320F280021 TMS320F280021-Q1
TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table 6-1. Pin Attributes (continued)
SIGNAL NAME
GPIO16
SPIA_SIMO
MUX
POSITION
80 QFP
64 QFP
48 QFP
PIN
TYPE
DESCRIPTION
0, 4, 8, 12
I/O
General-Purpose Input Output 16
1
I/O
SPI-A Slave In, Master Out (SIMO)
OUTPUTXBAR7
3
O
Output X-BAR Output 7
EPWM5_A
5
O
ePWM-5 Output A
SCIA_TX
6
O
SCI-A Transmit Data
I/O
eQEP-1 Strobe
EQEP1_STROBE
9
PMBUSA_SCL
10
XCLKOUT
11
EQEP2_B
SPIB_SOMI
39
33
26
I/OD
PMBus-A Open-Drain Bidirectional Clock
O
External Clock Output. This pin outputs a divideddown version of a chosen clock signal from within the
device.
13
I
eQEP-2 Input B
14
I/O
SPI-B Slave Out, Master In (SOMI)
HIC_D1
15
I/O
HIC Data 1
GPIO17
0, 4, 8, 12
I/O
General-Purpose Input Output 17
SPIA_SOMI
1
I/O
SPI-A Slave Out, Master In (SOMI)
OUTPUTXBAR8
3
O
Output X-BAR Output 8
EPWM5_B
5
O
ePWM-5 Output B
SCIA_RX
6
I
SCI-A Receive Data
EQEP1_INDEX
9
I/O
PMBUSA_SDA
10
I/OD
40
34
eQEP-1 Index
PMBus-A Open-Drain Bidirectional Data
CANA_TX
11
O
CAN-A Transmit
HIC_D2
15
I/O
HIC Data 2
GPIO18_X2
0, 4, 8, 12
I/O
General-Purpose Input Output 18_X2
SPIA_CLK
1
I/O
SPI-A Clock
CANA_RX
3
I
CAN-A Receive
EPWM6_A
5
O
ePWM-6 Output A
I2CA_SCL
6
I/OD
I2C-A Open-Drain Bidirectional Clock
EQEP2_A
9
I
PMBUSA_CTL
10
I/O
PMBus-A Control Signal - Slave Input/Master Output
XCLKOUT
11
O
External Clock Output. This pin outputs a divideddown version of a chosen clock signal from within the
device.
LINB_TX
13
O
LIN-B Transmit
FSITXA_TDM_CLK
14
I
FSITX-A Time Division Multiplexed Clock Input
HIC_INT
15
O
HIC Device Interrupt
O
Crystal oscillator output. For more information about
the ALT functionality, see the table that is in the
External Oscillator (XTAL) section of the System
Control chapter in the TMS320F28002x Real-Time
Microcontrollers Technical Reference Manual.
X2
ALT
Copyright © 2020 Texas Instruments Incorporated
50
41
33
eQEP-2 Input A
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21
TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table 6-1. Pin Attributes (continued)
SIGNAL NAME
GPIO19_X1
MUX
POSITION
80 QFP
64 QFP
48 QFP
PIN
TYPE
DESCRIPTION
0, 4, 8, 12
I/O
General-Purpose Input Output 19_X1
SPIA_STE
1
I/O
SPI-A Slave Transmit Enable (STE)
CANA_TX
3
O
CAN-A Transmit
EPWM6_B
5
O
ePWM-6 Output B
I2CA_SDA
6
I/OD
EQEP2_B
9
I
PMBUSA_ALERT
10
I/OD
I2C-A Open-Drain Bidirectional Data
eQEP-2 Input B
PMBus-A Open-Drain Bidirectional Alert
CLB_OUTPUTXBAR1
11
O
CLB Output X-BAR Output 1
LINB_RX
13
I
LIN-B Receive
FSITXA_TDM_D0
14
I
FSITX-A Time Division Multiplexed Data Input
HIC_NBE0
15
I
HIC Byte Enable 0
ALT
I
Crystal oscillator input or single-ended clock input.
The device initialization software must configure this
pin before the crystal oscillator is enabled. To use this
oscillator, a quartz crystal circuit must be connected
to X1 and X2. This pin can also be used to feed a
single-ended 3.3-V level clock. For more information
about the ALT functionality, see the table that is in the
External Oscillator (XTAL) section of the System
Control chapter in the TMS320F28002x Real-Time
Microcontrollers Technical Reference Manual.
0, 4, 8, 12
I/O
General-Purpose Input Output 22
EQEP1_STROBE
1
I/O
eQEP-1 Strobe
SPIB_CLK
6
I/O
SPI-B Clock
LINA_TX
9
O
LIN-A Transmit
CLB_OUTPUTXBAR1
10
O
CLB Output X-BAR Output 1
LINB_TX
11
O
LIN-B Transmit
X1
GPIO22
51
67
42
34
56
HIC_A5
13
I
HIC Address 5
EPWM4_A
14
O
ePWM-4 Output A
HIC_D13
15
I/O
HIC Data 13
GPIO23
0, 4, 8, 12
I/O
General-Purpose Input Output 23
EQEP1_INDEX
1
I/O
eQEP-1 Index
SPIB_STE
6
I/O
LINA_RX
9
I
LIN-A Receive
LINB_RX
11
I
LIN-B Receive
HIC_A3
13
I
HIC Address 3
EPWM4_B
14
O
ePWM-4 Output B
HIC_D11
15
I/O
HIC Data 11
GPIO24
0, 4, 8, 12
I/O
General-Purpose Input Output 24
OUTPUTXBAR1
1
O
Output X-BAR Output 1
EQEP2_A
2
I
eQEP-2 Input A
SPIB_SIMO
6
I/O
SPI-B Slave In, Master Out (SIMO)
O
LIN-B Transmit
65
54
SPI-B Slave Transmit Enable (STE)
LINB_TX
9
PMBUSA_SCL
10
SCIA_TX
11
O
SCI-A Transmit Data
ERRORSTS
13
O
Error Status Output. When used, this signal requires
an external pulldown.
HIC_D3
15
I/O
HIC Data 3
22
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41
35
27
I/OD
PMBus-A Open-Drain Bidirectional Clock
Copyright © 2020 Texas Instruments Incorporated
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TMS320F280023 TMS320F280023-Q1 TMS320F280023C TMS320F280021 TMS320F280021-Q1
TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table 6-1. Pin Attributes (continued)
SIGNAL NAME
GPIO25
MUX
POSITION
80 QFP
64 QFP
48 QFP
PIN
TYPE
DESCRIPTION
0, 4, 8, 12
I/O
General-Purpose Input Output 25
OUTPUTXBAR2
1
O
Output X-BAR Output 2
EQEP2_B
2
I
eQEP-2 Input B
EQEP1_A
5
I
eQEP-1 Input A
SPIB_SOMI
6
42
I/O
SPI-B Slave Out, Master In (SOMI)
FSITX-A Data Output 1
FSITXA_D1
9
O
PMBUSA_SDA
10
I/OD
PMBus-A Open-Drain Bidirectional Data
SCIA_RX
11
I
SCI-A Receive Data
HIC_BASESEL0
14
I
HIC Base Address Range Select 0
0, 4, 8, 12
I/O
General-Purpose Input Output 26
GPIO26
OUTPUTXBAR3
1, 5
O
Output X-BAR Output 3
EQEP2_INDEX
2
I/O
eQEP-2 Index
SPIB_CLK
6
I/O
SPI-B Clock
FSITXA_D0
9
O
FSITX-A Data Output 0
PMBUSA_CTL
10
I/O
PMBus-A Control Signal - Slave Input/Master Output
I2CA_SDA
11
I/OD
HIC_D0
14
I/O
43
I2C-A Open-Drain Bidirectional Data
HIC Data 0
HIC_A1
15
I
GPIO27
0, 4, 8, 12
I/O
General-Purpose Input Output 27
OUTPUTXBAR4
HIC Address 1
1, 5
O
Output X-BAR Output 4
EQEP2_STROBE
2
I/O
eQEP-2 Strobe
SPIB_STE
6
I/O
SPI-B Slave Transmit Enable (STE)
O
FSITX-A Output Clock
FSITXA_CLK
9
PMBUSA_ALERT
10
I/OD
PMBus-A Open-Drain Bidirectional Alert
I2CA_SCL
11
I/OD
I2C-A Open-Drain Bidirectional Clock
HIC_D1
14
I/O
HIC_A4
15
I
GPIO28
44
HIC Data 1
HIC Address 4
0, 4, 8, 12
I/O
SCIA_RX
1
I
SCI-A Receive Data
General-Purpose Input Output 28
EPWM7_A
3
O
ePWM-7 Output A
OUTPUTXBAR5
5
O
Output X-BAR Output 5
EQEP1_A
6
I
eQEP-1 Input A
I/O
eQEP-2 Strobe
O
LIN-A Transmit
EQEP2_STROBE
9
LINA_TX
10
SPIB_CLK
11
I/O
SPI-B Clock
ERRORSTS
13
O
Error Status Output. When used, this signal requires
an external pulldown.
I2CB_SDA
14
I/OD
HIC_NOE
15
O
Copyright © 2020 Texas Instruments Incorporated
4
2
2
I2C-B Open-Drain Bidirectional Data
HIC Output Enable
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23
TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table 6-1. Pin Attributes (continued)
SIGNAL NAME
MUX
POSITION
80 QFP
64 QFP
48 QFP
PIN
TYPE
DESCRIPTION
GPIO29
0, 4, 8, 12
I/O
General-Purpose Input Output 29
SCIA_TX
1
O
SCI-A Transmit Data
EPWM7_B
3
O
ePWM-7 Output B
OUTPUTXBAR6
5
O
Output X-BAR Output 6
EQEP1_B
6
I
eQEP-1 Input B
EQEP2_INDEX
9
LINA_RX
10
SPIB_STE
11
I/O
SPI-B Slave Transmit Enable (STE)
ERRORSTS
13
O
Error Status Output. When used, this signal requires
an external pulldown.
I2CB_SCL
14
I/OD
HIC_NCS
15
I
GPIO30
3
1
1
I/O
eQEP-2 Index
I
LIN-A Receive
I2C-B Open-Drain Bidirectional Clock
HIC Chip Select
0, 4, 8, 12
I/O
CANA_RX
1
I
SPIB_SIMO
3
I/O
SPI-B Slave In, Master Out (SIMO)
OUTPUTXBAR7
5
O
Output X-BAR Output 7
EQEP1_STROBE
6
I/O
eQEP-1 Strobe
1
General-Purpose Input Output 30
CAN-A Receive
FSIRXA_CLK
9
I
FSIRX-A Input Clock
EPWM1_A
11
O
ePWM-1 Output A
HIC_D8
14
I/O
HIC Data 8
GPIO31
0, 4, 8, 12
I/O
General-Purpose Input Output 31
CANA_TX
1
O
CAN-A Transmit
SPIB_SOMI
3
I/O
SPI-B Slave Out, Master In (SOMI)
OUTPUTXBAR8
5
O
Output X-BAR Output 8
EQEP1_INDEX
6
I/O
eQEP-1 Index
FSIRXA_D1
9
I
FSIRX-A Data Input 1
EPWM1_B
11
O
ePWM-1 Output B
HIC_D10
14
I/O
HIC Data 10
GPIO32
0, 4, 8, 12
I/O
General-Purpose Input Output 32
I2CA_SDA
1
I/OD
SPIB_CLK
3
I/O
SPI-B Clock
LINA_TX
6
O
LIN-A Transmit
FSIRXA_D0
9
I
FSIRX-A Data Input 0
CANA_TX
10
O
CAN-A Transmit
ADCSOCBO
13
O
ADC Start of Conversion B for External ADC
HIC_INT
15
O
HIC Device Interrupt
GPIO33
General-Purpose Input Output 33
2
49
40
32
I2C-A Open-Drain Bidirectional Data
0, 4, 8, 12
I/O
I2CA_SCL
1
I/OD
SPIB_STE
3
I/O
SPI-B Slave Transmit Enable (STE)
OUTPUTXBAR4
5
O
Output X-BAR Output 4
LINA_RX
6
I
LIN-A Receive
38
32
25
I2C-A Open-Drain Bidirectional Clock
FSIRXA_CLK
9
I
FSIRX-A Input Clock
CANA_RX
10
I
CAN-A Receive
EQEP2_B
11
I
eQEP-2 Input B
ADCSOCAO
13
O
ADC Start of Conversion A for External ADC
HIC_D0
15
I/O
HIC Data 0
24
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TMS320F280025, TMS320F280025-Q1
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TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table 6-1. Pin Attributes (continued)
SIGNAL NAME
GPIO34
OUTPUTXBAR1
MUX
POSITION
80 QFP
64 QFP
48 QFP
PIN
TYPE
DESCRIPTION
0, 4, 8, 12
I/O
General-Purpose Input Output 34
1
O
Output X-BAR Output 1
PMBUSA_SDA
6
HIC_NBE1
13
I/OD
I2CB_SDA
14
I/OD
HIC_D9
15
I/O
HIC Data 9
GPIO35
0, 4, 8, 12
I/O
General-Purpose Input Output 35
77
I
PMBus-A Open-Drain Bidirectional Data
HIC Byte Enable 1
I2C-B Open-Drain Bidirectional Data
SCIA_RX
1
I
I2CA_SDA
3
I/OD
CANA_RX
5
I
PMBUSA_SCL
6
I/OD
LINA_RX
7
I
LIN-A Receive
I
eQEP-1 Input A
48
39
31
SCI-A Receive Data
I2C-A Open-Drain Bidirectional Data
CAN-A Receive
PMBus-A Open-Drain Bidirectional Clock
EQEP1_A
9
PMBUSA_CTL
10
I/O
HIC_NWE
14
I
HIC Data Write Enable
15
I
JTAG Test Data Input (TDI) - TDI is the default mux
selection for the pin. The internal pullup is disabled by
default. The internal pullup should be enabled or an
external pullup added on the board if this pin is used
as JTAG TDI to avoid a floating input.
TDI
GPIO37
PMBus-A Control Signal - Slave Input/Master Output
0, 4, 8, 12
I/O
General-Purpose Input Output 37
OUTPUTXBAR2
1
O
Output X-BAR Output 2
I2CA_SCL
3
I/OD
SCIA_TX
5
O
SCI-A Transmit Data
I2C-A Open-Drain Bidirectional Clock
CANA_TX
6
O
CAN-A Transmit
LINA_TX
7
O
LIN-A Transmit
EQEP1_B
9
I
eQEP-1 Input B
PMBUSA_ALERT
10
HIC_NRDY
14
TDO
GPIO39
46
37
29
I/OD
PMBus-A Open-Drain Bidirectional Alert
O
HIC Ready
15
O
JTAG Test Data Output (TDO) - TDO is the default
mux selection for the pin. The internal pullup is
disabled by default. The TDO function will tristate
when there is no JTAG activity, leaving this pin
floating; the internal pullup should be enabled or an
external pullup added on the board to avoid a floating
GPIO input.
0, 4, 8, 12
I/O
General-Purpose Input Output 39
FSIRXA_CLK
7
I
EQEP2_INDEX
9
I/O
eQEP-2 Index
56
46
FSIRX-A Input Clock
CLB_OUTPUTXBAR2
11
O
CLB Output X-BAR Output 2
SYNCOUT
13
O
External ePWM Synchronization Pulse
EQEP1_INDEX
14
I/O
eQEP-1 Index
HIC_D7
15
I/O
HIC Data 7
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25
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table 6-1. Pin Attributes (continued)
SIGNAL NAME
GPIO40
MUX
POSITION
80 QFP
64 QFP
48 QFP
PIN
TYPE
DESCRIPTION
0, 4, 8, 12
I/O
General-Purpose Input Output 40
SPIB_SIMO
1
I/O
SPI-B Slave In, Master Out (SIMO)
EPWM2_B
5
O
ePWM-2 Output B
PMBUSA_SDA
6
I/OD
FSIRXA_D0
7
EQEP1_A
LINB_TX
HIC_NBE1
HIC_D5
GPIO41
PMBus-A Open-Drain Bidirectional Data
I
FSIRX-A Data Input 0
10
I
eQEP-1 Input A
11
O
LIN-B Transmit
14
I
HIC Byte Enable 1
15
I/O
HIC Data 5
0, 4, 8, 12
I/O
General-Purpose Input Output 41
ePWM-2 Output A
64
53
EPWM2_A
5
O
PMBUSA_SCL
6
I/OD
FSIRXA_D1
7
EQEP1_B
10
LINB_RX
11
HIC_A4
SPIB_SOMI
PMBus-A Open-Drain Bidirectional Clock
I
FSIRX-A Data Input 1
I
eQEP-1 Input B
I
LIN-B Receive
13
I
HIC Address 4
14
I/O
SPI-B Slave Out, Master In (SOMI)
HIC_D12
15
I/O
HIC Data 12
GPIO42
0, 4, 8, 12
I/O
General-Purpose Input Output 42
LINA_RX
2
I
LIN-A Receive
OUTPUTXBAR5
3
O
Output X-BAR Output 5
PMBUSA_CTL
5
I/O
PMBus-A Control Signal - Slave Input/Master Output
I2CA_SDA
6
EQEP1_STROBE
10
66
57
55
I/OD
I2C-A Open-Drain Bidirectional Data
I/O
eQEP-1 Strobe
CLB_OUTPUTXBAR3
11
O
CLB Output X-BAR Output 3
HIC_D2
14
I/O
HIC Data 2
HIC_A6
15
I
GPIO43
HIC Address 6
0, 4, 8, 12
I/O
General-Purpose Input Output 43
OUTPUTXBAR6
3
O
Output X-BAR Output 6
PMBUSA_ALERT
5
I/OD
PMBus-A Open-Drain Bidirectional Alert
I2CA_SCL
6
I/OD
I2C-A Open-Drain Bidirectional Clock
EQEP1_INDEX
10
54
I/O
eQEP-1 Index
CLB_OUTPUTXBAR4
11
O
CLB Output X-BAR Output 4
HIC_D3
14
I/O
HIC Data 3
HIC_A7
15
I
GPIO44
0, 4, 8, 12
I/O
General-Purpose Input Output 44
OUTPUTXBAR7
3
O
Output X-BAR Output 7
EQEP1_A
5
I
eQEP-1 Input A
FSITXA_CLK
7
O
FSITX-A Output Clock
69
HIC Address 7
CLB_OUTPUTXBAR3
10
O
CLB Output X-BAR Output 3
HIC_D7
13
I/O
HIC Data 7
HIC_D5
15
I/O
HIC Data 5
26
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TMS320F280025, TMS320F280025-Q1
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TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table 6-1. Pin Attributes (continued)
SIGNAL NAME
GPIO45
OUTPUTXBAR8
MUX
POSITION
80 QFP
64 QFP
48 QFP
PIN
TYPE
DESCRIPTION
0, 4, 8, 12
I/O
General-Purpose Input Output 45
3
O
Output X-BAR Output 8
73
FSITXA_D0
7
O
FSITX-A Data Output 0
CLB_OUTPUTXBAR4
10
O
CLB Output X-BAR Output 4
HIC_D6
15
I/O
HIC Data 6
GPIO46
0, 4, 8, 12
I/O
General-Purpose Input Output 46
LINA_TX
3
O
LIN-A Transmit
FSITXA_D1
7
O
FSITX-A Data Output 1
HIC_NWE
15
I
HIC Data Write Enable
GPIO61
0, 4, 8, 12
I/O
General-Purpose Input Output 61
GPIO62
0, 4, 8, 12
I/O
General-Purpose Input Output 62
GPIO63
0, 4, 8, 12
I/O
General-Purpose Input Output 63
6
TEST, JTAG, AND RESET
FLT1
34
I/O
Flash test pin 1. Reserved for TI. Must be left
unconnected.
FLT2
33
I/O
Flash test pin 2. Reserved for TI. Must be left
unconnected.
TCK
45
TMS
47
XRSn
5
Copyright © 2020 Texas Instruments Incorporated
36
38
3
28
30
3
I
JTAG test clock with internal pullup.
I/O
JTAG test-mode select (TMS) with internal pullup.
This serial control input is clocked into the TAP
controller on the rising edge of TCK. This device does
not have a TRSTn pin. An external pullup resistor
(recommended 2.2 kΩ) on the TMS pin to VDDIO
should be placed on the board to keep JTAG in reset
during normal operation.
I/OD
Device Reset (in) and Watchdog Reset (out). During a
power-on condition, this pin is driven low by the
device. An external circuit may also drive this pin to
assert a device reset. This pin is also driven low by
the MCU when a watchdog reset occurs. During
watchdog reset, the XRSn pin is driven low for the
watchdog reset duration of 512 OSCCLK cycles. A
resistor between 2.2 kΩ and 10 kΩ should be placed
between XRSn and VDDIO. If a capacitor is placed
between XRSn and VSS for noise filtering, it should
be 100 nF or smaller. These values will allow the
watchdog to properly drive the XRSn pin to VOL
within 512 OSCCLK cycles when the watchdog reset
is asserted. This pin is an open-drain output with an
internal pullup. If this pin is driven by an external
device, it should be done using an open-drain device.
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table 6-1. Pin Attributes (continued)
SIGNAL NAME
MUX
POSITION
80 QFP
64 QFP
48 QFP
PIN
TYPE
DESCRIPTION
POWER AND GROUND
VDD
VDDA
8, 31,
53, 71
4, 27,
44, 59
36, 45
26
22
18
1.2-V Digital Logic Power Pins. TI recommends
placing a decoupling capacitor near each VDD pin
with a minimum total capacitance of approximately 10
µF. It is also recommended that all VDD pins be
externally connected to each other.
3.3-V Analog Power Pins. Place a minimum 2.2-µF
decoupling capacitor on each pin.
VDDIO
7, 32,
52, 72
28, 43,
60
35, 46
3.3-V Digital I/O Power Pins. Place a minimum 0.1-µF
decoupling capacitor on each pin. It is recommended
to place an additional bulk cap of around 20uF shared
by all the pins. However, the exact value of this bulk
cap will depend on the regulator being used.
VSS
9, 30,
55, 70
5, 26,
45, 58
22, 37,
44
Digital Ground
25
21
17
Analog Ground
VSSA
28
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TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
6.3 Signal Descriptions
6.3.1 Analog Signals
Table 6-2. Analog Signals
SIGNAL NAME
A0
PIN
TYPE
I
DESCRIPTION
GPIO
80 QFP
64 QFP
48 QFP
ADC-A Input 0
19
15
11
A1
I
Analog Input
18
14
10
A2
I
ADC-A Input 2
13
9
6
A3
I
ADC-A Input 3
12
8
5
A4
I
ADC-A Input 4
27
23
19
A5
I
ADC-A Input 5
17
13
9
A6
I
Analog Input
10
6
4
A7
I
ADC-A Input 7
23
19
15
A8
I
ADC-A Input 8
24
20
16
A9
I
ADC-A Input 9
28
24
20
A10
I
ADC-A Input 10
29
25
21
A11
I
ADC-A Input 11
16
12
8
A12
I
ADC-A Input 12
22
18
14
A14
I
ADC-A Input 14
15
11
A15
I
ADC-A Input 15
14
10
7
AIO224
I
Analog Pin Used For Digital Input 224
13
9
6
AIO225
I
Analog Pin Used For Digital Input 225
27
23
19
AIO226
I
Analog Pin Used For Digital Input 226
11
7
4
AIO227
I
Analog Pin Used For Digital Input 227
28
24
20
AIO228
I
Analog Pin Used For Digital Input 228
10
6
4
AIO230
I
Analog Pin Used For Digital Input 230
29
25
21
AIO231
I
Analog Pin Used For Digital Input 231
19
15
11
AIO232
I
Analog Pin Used For Digital Input 232
18
14
10
AIO233
I
Analog Pin Used For Digital Input 233
14
10
7
AIO237
I
Analog Pin Used For Digital Input 237
16
12
8
AIO238
I
Analog Pin Used For Digital Input 238
22
18
14
AIO239
I
Analog Pin Used For Digital Input 239
15
11
AIO241
I
Analog Pin Used For Digital Input 241
24
20
16
AIO242
I
Analog Pin Used For Digital Input 242
12
8
5
AIO244
I
Analog Pin Used For Digital Input 244
17
13
9
AIO245
I
Analog Pin Used For Digital Input 245
23
19
15
C0
I
ADC-C Input 0
16
12
8
C1
I
ADC-C Input 1
22
18
14
C2
I
ADC-C Input 2
17
13
9
C3
I
ADC-C Input 3
23
19
15
C4
I
ADC-C Input 4
15
11
C5
I
ADC-C Input 5
12
8
5
C6
I
Analog Input
11
7
4
C7
I
ADC-C Input 7
14
10
7
C8
I
ADC-C Input 8
28
24
20
C9
I
ADC-C Input 9
13
9
6
C10
I
ADC-C Input 10
29
25
21
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table 6-2. Analog Signals (continued)
SIGNAL NAME
PIN
TYPE
DESCRIPTION
GPIO
80 QFP
64 QFP
48 QFP
C11
I
ADC-C Input 11
24
20
16
C14
I
ADC-C Input 14
27
23
19
C15
I
ADC-C Input 15
19
15
11
CMP1_HN0
I
CMPSS-1 High Comparator Negative
Input 0
14
10
7
CMP1_HN1
I
CMPSS-1 High Comparator Negative
Input 1
16
12
8
CMP1_HP0
I
CMPSS-1 High Comparator Positive
Input 0
13
9
6
CMP1_HP1
I
CMPSS-1 High Comparator Positive
Input 1
16
12
8
CMP1_HP2
I
CMPSS-1 High Comparator Positive
Input 2
10
6
4
CMP1_HP3
I
CMPSS-1 High Comparator Positive
Input 3
14
10
7
CMP1_HP4
I
CMPSS-1 High Comparator Positive
Input 4
18
14
10
CMP1_LN0
I
CMPSS-1 Low Comparator Negative
Input 0
14
10
7
CMP1_LN1
I
CMPSS-1 Low Comparator Negative
Input 1
16
12
8
CMP1_LP0
I
CMPSS-1 Low Comparator Positive
Input 0
13
9
6
CMP1_LP1
I
CMPSS-1 Low Comparator Positive
Input 1
16
12
8
CMP1_LP2
I
CMPSS-1 Low Comparator Positive
Input 2
10
6
4
CMP1_LP3
I
CMPSS-1 Low Comparator Positive
Input 3
14
10
7
CMP1_LP4
I
CMPSS-1 Low Comparator Positive
Input 4
18
14
10
CMP2_HN0
I
CMPSS-2 High Comparator Negative
Input 0
29
25
21
CMP2_HN1
I
CMPSS-2 High Comparator Negative
Input 1
22
18
14
CMP2_HP0
I
CMPSS-2 High Comparator Positive
Input 0
27
23
19
CMP2_HP1
I
CMPSS-2 High Comparator Positive
Input 1
22
18
14
CMP2_HP2
I
CMPSS-2 High Comparator Positive
Input 2
28
24
20
CMP2_HP3
I
CMPSS-2 High Comparator Positive
Input 3
29
25
21
CMP2_HP4
I
CMPSS-2 High Comparator Positive
Input 4
24
20
16
CMP2_LN0
I
CMPSS-2 Low Comparator Negative
Input 0
29
25
21
CMP2_LN1
I
CMPSS-2 Low Comparator Negative
Input 1
22
18
14
CMP2_LP0
I
CMPSS-2 Low Comparator Positive
Input 0
27
23
19
30
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TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table 6-2. Analog Signals (continued)
SIGNAL NAME
PIN
TYPE
DESCRIPTION
GPIO
80 QFP
64 QFP
48 QFP
CMP2_LP1
I
CMPSS-2 Low Comparator Positive
Input 1
22
18
14
CMP2_LP2
I
CMPSS-2 Low Comparator Positive
Input 2
28
24
20
CMP2_LP3
I
CMPSS-2 Low Comparator Positive
Input 3
29
25
21
CMP2_LP4
I
CMPSS-2 Low Comparator Positive
Input 4
24
20
16
CMP3_HN0
I
CMPSS-3 High Comparator Negative
Input 0
12
8
5
CMP3_HN1
I
CMPSS-3 High Comparator Negative
Input 1
17
13
9
CMP3_HP0
I
CMPSS-3 High Comparator Positive
Input 0
11
7
4
CMP3_HP1
I
CMPSS-3 High Comparator Positive
Input 1
17
13
9
CMP3_HP2
I
CMPSS-3 High Comparator Positive
Input 2
19
15
11
CMP3_HP3
I
CMPSS-3 High Comparator Positive
Input 3
12
8
5
CMP3_HP4
I
CMPSS-3 High Comparator Positive
Input 4
15
11
CMP3_LN0
I
CMPSS-3 Low Comparator Negative
Input 0
12
8
5
CMP3_LN1
I
CMPSS-3 Low Comparator Negative
Input 1
17
13
9
CMP3_LP0
I
CMPSS-3 Low Comparator Positive
Input 0
11
7
4
CMP3_LP1
I
CMPSS-3 Low Comparator Positive
Input 1
17
13
9
CMP3_LP2
I
CMPSS-3 Low Comparator Positive
Input 2
19
15
11
CMP3_LP3
I
CMPSS-3 Low Comparator Positive
Input 3
12
8
5
CMP3_LP4
I
CMPSS-3 Low Comparator Positive
Input 4
15
11
CMP4_HN0
I
CMPSS-4 High Comparator Negative
Input 0
27
23
19
CMP4_HN1
I
CMPSS-4 High Comparator Negative
Input 1
23
19
15
CMP4_HP0
I
CMPSS-4 High Comparator Positive
Input 0
28
24
20
CMP4_HP1
I
CMPSS-4 High Comparator Positive
Input 1
23
19
15
CMP4_HP2
I
CMPSS-4 High Comparator Positive
Input 2
22
18
14
CMP4_HP3
I
CMPSS-4 High Comparator Positive
Input 3
27
23
19
CMP4_HP4
I
CMPSS-4 High Comparator Positive
Input 4
24
20
16
CMP4_LN0
I
CMPSS-4 Low Comparator Negative
Input 0
27
23
19
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31
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table 6-2. Analog Signals (continued)
PIN
TYPE
DESCRIPTION
CMP4_LN1
I
CMP4_LP0
SIGNAL NAME
GPIO
80 QFP
64 QFP
48 QFP
CMPSS-4 Low Comparator Negative
Input 1
23
19
15
I
CMPSS-4 Low Comparator Positive
Input 0
28
24
20
CMP4_LP1
I
CMPSS-4 Low Comparator Positive
Input 1
23
19
15
CMP4_LP2
I
CMPSS-4 Low Comparator Positive
Input 2
22
18
14
CMP4_LP3
I
CMPSS-4 Low Comparator Positive
Input 3
27
23
19
CMP4_LP4
I
CMPSS-4 Low Comparator Positive
Input 4
24
20
16
HIC_A0
I
HIC Address 0
10
6
4
HIC_A1
I
HIC Address 1
11
7
4
HIC_A2
I
HIC Address 2
12
8
5
HIC_A3
I
HIC Address 3
13
9
6
HIC_A4
I
HIC Address 4
14
10
7
HIC_A5
I
HIC Address 5
15
11
HIC_A6
I
HIC Address 6
16
12
8
HIC_A7
I
HIC Address 7
17
13
9
HIC_BASESEL0
I
HIC Base Address Range Select 0
18
14
10
HIC_BASESEL1
I
HIC Base Address Range Select 1
19
15
11
HIC_BASESEL2
I
HIC Base Address Range Select 2
29
25
21
HIC_NBE0
I
HIC Byte Enable 0
28
24
20
HIC_NBE1
I
HIC Byte Enable 1
24
20
16
HIC_NCS
I
HIC Chip Select
22
18
14
HIC_NOE
O
HIC Output Enable
23
19
15
HIC_NWE
I
HIC Data Write Enable
27
23
19
I
Optional external reference voltage
for on-chip CMPSS DACs. There is
an internal capacitor to VSSA on this
pin whether used for ADC input or
CMPSS DAC reference which cannot
be disabled. If this pin is being used
as a reference for the CMPSS DACs,
place at least a 1-μF capacitor on this
pin.
12
8
5
VREFHI
I
ADC- High Reference. In external
reference mode, externally drive the
high reference voltage onto this pin.
In internal reference mode, a voltage
is driven onto this pin by the device.
In either mode, place at least a 2.2µF capacitor on this pin. This
capacitor should be placed as close
to the device as possible between the
VREFHI and VREFLO pins.
20
16
12
VREFLO
I
ADC- Low Reference
21
17
13
VDAC
32
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TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
6.3.2 Digital Signals
Table 6-3. Digital Signals
SIGNAL NAME
PIN
TYPE
DESCRIPTION
GPIO
80 QFP
64 QFP
48 QFP
ADCSOCAO
O
ADC Start of Conversion A for
External ADC
33, 8
38, 58
32, 47
25
ADCSOCBO
O
ADC Start of Conversion B for
External ADC
10, 32
49, 76
40, 63
32
CANA_RX
I
CAN-A Receive
12, 18, 3, 30,
33, 35, 5
1, 36, 38, 48,
50, 60, 74
30, 32, 39,
41, 49, 61
24, 25, 31,
33, 39, 47
CANA_TX
O
CAN-A Transmit
13, 17, 19, 2, 2, 35, 40, 46,
29, 34, 37,
31, 32, 37, 4 49, 51, 59, 61 40, 42, 48, 50
23, 29, 32,
34, 38, 40
CLB_OUTPUTXBAR1
O
CLB Output X-BAR Output 1
19, 22
51, 67
42, 56
34
CLB_OUTPUTXBAR2
O
CLB Output X-BAR Output 2
39, 7
56, 68
46, 57
43
CLB_OUTPUTXBAR3
O
CLB Output X-BAR Output 3
42, 44
57, 69
CLB_OUTPUTXBAR4
O
CLB Output X-BAR Output 4
43, 45
54, 73
CLB_OUTPUTXBAR5
O
CLB Output X-BAR Output 5
5, 8
58, 74
47, 61
47
CLB_OUTPUTXBAR6
O
CLB Output X-BAR Output 6
15, 4
59, 78
48
38
CLB_OUTPUTXBAR7
O
CLB Output X-BAR Output 7
1, 14
62, 79
51
41
CLB_OUTPUTXBAR8
O
CLB Output X-BAR Output 8
6
63, 80
52, 64
42, 48
EPWM1_A
O
ePWM-1 Output A
30
1, 63
52
42
EPWM1_B
O
ePWM-1 Output B
1, 31
2, 62
51
41
EPWM2_A
O
ePWM-2 Output A
2, 41
61, 66
50, 55
40
EPWM2_B
O
ePWM-2 Output B
3, 40
60, 64
49, 53
39
EPWM3_A
O
ePWM-3 Output A
14, 4
59, 79
48
38
EPWM3_B
O
ePWM-3 Output B
15, 5
74, 78
61
47
EPWM4_A
O
ePWM-4 Output A
22, 6
67, 80
56, 64
48
EPWM4_B
O
ePWM-4 Output B
23, 7
65, 68
54, 57
43
EPWM5_A
O
ePWM-5 Output A
16, 8
39, 58
33, 47
26
EPWM5_B
O
ePWM-5 Output B
17, 9
40, 75
34, 62
EPWM6_A
O
ePWM-6 Output A
10, 18
50, 76
41, 63
EPWM6_B
O
ePWM-6 Output B
11, 19
37, 51
31, 42
34
EPWM7_A
O
ePWM-7 Output A
12, 28
36, 4
2, 30
2, 24
EPWM7_B
O
ePWM-7 Output B
EQEP1_A
I
eQEP-1 Input A
EQEP1_B
I
eQEP-1 Input B
13, 29
3, 35
1, 29
1, 23
10, 25, 28,
35, 40, 44, 6
4, 42, 48, 64,
69, 76, 80
2, 39, 53, 63,
64
2, 31, 48
11, 29, 37, 41, 3, 37, 46, 66,
7
68
1, 31, 37, 55,
57
1, 29, 43
29, 34, 46,
54, 62
23
EQEP1_INDEX
I/O
eQEP-1 Index
13, 17, 23,
31, 39, 43, 9
EQEP1_STROBE
I/O
eQEP-1 Strobe
12, 16, 22,
30, 42, 8
I
eQEP-2 Input A
EQEP2_A
EQEP2_B
I
33
2, 35, 40, 54,
56, 65, 75
1, 36, 39, 57,
30, 33, 47, 56
58, 67
11, 14, 18, 24 37, 41, 50, 79
24, 26
31, 35, 41
27, 33
eQEP-2 Input B
15, 16, 19,
25, 33
38, 39, 42,
51, 78
32, 33, 42
25, 26, 34
EQEP2_INDEX
I/O
eQEP-2 Index
26, 29, 39
3, 43, 56
1, 46
1
EQEP2_STROBE
I/O
eQEP-2 Strobe
27, 28, 4
4, 44, 59
2, 48
2, 38
ERRORSTS
O
Error Status Output. When used, this
signal requires an external pulldown.
24, 28, 29
3, 4, 41
1, 2, 35
1, 2, 27
FSIRXA_CLK
I
FSIRX-A Input Clock
13, 30, 33,
39, 4
1, 35, 38, 56,
59, 63
29, 32, 46,
48, 52
23, 25, 38, 42
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33
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TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table 6-3. Digital Signals (continued)
SIGNAL NAME
PIN
TYPE
DESCRIPTION
GPIO
80 QFP
64 QFP
48 QFP
FSIRXA_D0
I
FSIRX-A Data Input 0
12, 3, 32, 40
36, 49, 60, 64 30, 40, 49, 53
FSIRXA_D1
I
FSIRX-A Data Input 1
11, 2, 31, 41
2, 37, 61, 66
31, 50, 55
40
FSITXA_CLK
O
FSITX-A Output Clock
10, 27, 44, 7
44, 68, 69, 76
57, 63
43
FSITXA_D0
O
FSITX-A Data Output 0
26, 45, 6, 9
43, 73, 75, 80
62, 64
48
FSITXA_D1
O
FSITX-A Data Output 1
25, 46, 5, 6, 8
42, 58, 6, 74,
80
47, 61, 64
47, 48
FSITXA_TDM_CLK
I
FSITX-A Time Division Multiplexed
Clock Input
18, 8
50, 58
41, 47
33
FSITXA_TDM_D0
I
FSITX-A Time Division Multiplexed
Data Input
10, 19
51, 76
42, 63
34
FSITXA_TDM_D1
I
FSITX-A Time Division Multiplexed
Additional Data Input
1
62
51
41
63
52
42
GPIO0
I/O
General-Purpose Input Output 0
24, 32, 39
GPIO1
I/O
General-Purpose Input Output 1
1
62
51
41
GPIO2
I/O
General-Purpose Input Output 2
2
61
50
40
GPIO3
I/O
General-Purpose Input Output 3
3
60
49
39
GPIO4
I/O
General-Purpose Input Output 4
4
59
48
38
GPIO5
I/O
General-Purpose Input Output 5
5
74
61
47
GPIO6
I/O
General-Purpose Input Output 6
6
80
64
48
GPIO7
I/O
General-Purpose Input Output 7
7
68
57
43
GPIO8
I/O
General-Purpose Input Output 8
8
58
47
GPIO9
I/O
General-Purpose Input Output 9
9
75
62
GPIO10
I/O
General-Purpose Input Output 10
10
76
63
GPIO11
I/O
General-Purpose Input Output 11
11
37
31
GPIO12
I/O
General-Purpose Input Output 12
12
36
30
24
GPIO13
I/O
General-Purpose Input Output 13
13
35
29
23
GPIO14
I/O
General-Purpose Input Output 14
14
79
GPIO15
I/O
General-Purpose Input Output 15
15
78
GPIO16
I/O
General-Purpose Input Output 16
16
39
33
26
GPIO17
I/O
General-Purpose Input Output 17
17
40
34
GPIO18_X2
I/O
General-Purpose Input Output 18_X2
18
50
41
33
GPIO19_X1
I/O
General-Purpose Input Output 19_X1
19
51
42
34
GPIO22
I/O
General-Purpose Input Output 22
22
67
56
GPIO23
I/O
General-Purpose Input Output 23
23
65
54
GPIO24
I/O
General-Purpose Input Output 24
24
41
35
27
GPIO25
I/O
General-Purpose Input Output 25
25
42
GPIO26
I/O
General-Purpose Input Output 26
26
43
GPIO27
I/O
General-Purpose Input Output 27
27
44
GPIO28
I/O
General-Purpose Input Output 28
28
4
2
2
GPIO29
I/O
General-Purpose Input Output 29
29
3
1
1
GPIO30
I/O
General-Purpose Input Output 30
30
1
GPIO31
I/O
General-Purpose Input Output 31
31
2
GPIO32
I/O
General-Purpose Input Output 32
32
49
40
32
GPIO33
I/O
General-Purpose Input Output 33
33
38
32
25
GPIO34
I/O
General-Purpose Input Output 34
34
77
GPIO35
I/O
General-Purpose Input Output 35
35
48
39
31
34
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TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
www.ti.com
SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table 6-3. Digital Signals (continued)
SIGNAL NAME
PIN
TYPE
DESCRIPTION
GPIO
80 QFP
64 QFP
48 QFP
29
GPIO37
I/O
General-Purpose Input Output 37
37
46
37
GPIO39
I/O
General-Purpose Input Output 39
39
56
46
GPIO40
I/O
General-Purpose Input Output 40
40
64
53
GPIO41
I/O
General-Purpose Input Output 41
41
66
55
GPIO42
I/O
General-Purpose Input Output 42
42
57
GPIO43
I/O
General-Purpose Input Output 43
43
54
GPIO44
I/O
General-Purpose Input Output 44
44
69
GPIO45
I/O
General-Purpose Input Output 45
45
73
GPIO46
I/O
General-Purpose Input Output 46
46
6
GPIO61
I/O
General-Purpose Input Output 61
61
GPIO62
I/O
General-Purpose Input Output 62
62
GPIO63
I/O
General-Purpose Input Output 63
63
HIC_A0
I
HIC Address 0
8
58
47
HIC_A1
I
HIC Address 1
2, 26
43, 61
50
40
HIC_A2
I
HIC Address 2
1
62
51
41
HIC_A3
I
HIC Address 3
23
65
54
HIC_A4
I
HIC Address 4
27, 41
44, 66
55
HIC_A5
I
HIC Address 5
22
67
56
HIC_A6
I
HIC Address 6
42, 7
57, 68
57
43
HIC_A7
I
HIC Address 7
43, 5
54, 74
61
47
HIC_BASESEL0
I
HIC Base Address Range Select 0
25, 9
42, 75
62
HIC_BASESEL1
I
HIC Base Address Range Select 1
63
52
42
HIC_BASESEL2
I
HIC Base Address Range Select 2
4
59
48
38
HIC_D0
I/O
HIC Data 0
26, 33
38, 43
32
25
HIC_D1
I/O
HIC Data 1
16, 27
39, 44
33
26
HIC_D2
I/O
HIC Data 2
17, 42
40, 57
34
HIC_D3
I/O
HIC Data 3
24, 43
41, 54
35
27
HIC_D4
I/O
HIC Data 4
3, 5
60, 74
49, 61
39, 47
HIC_D5
I/O
HIC Data 5
13, 40, 44
35, 64, 69
29, 53
23
HIC_D6
I/O
HIC Data 6
11, 45
37, 73
31
HIC_D7
I/O
HIC Data 7
39, 44
56, 69
46
HIC_D8
I/O
HIC Data 8
30, 8
1, 58
47
HIC_D9
I/O
HIC Data 9
2, 34
61, 77
50
40
HIC_D10
I/O
HIC Data 10
1, 31
2, 62
51
41
HIC_D11
I/O
HIC Data 11
13, 23
35, 65
29, 54
23
HIC_D12
I/O
HIC Data 12
15, 41
66, 78
55
HIC_D13
I/O
HIC Data 13
12, 22
36, 67
30, 56
24
HIC_D14
I/O
HIC Data 14
6, 7
68, 80
57, 64
43, 48
HIC_D15
I/O
HIC Data 15
14, 5
74, 79
61
47
HIC_INT
O
HIC Device Interrupt
12, 18, 32
36, 49, 50
30, 40, 41
24, 32, 33
HIC_NBE0
I
HIC Byte Enable 0
11, 19
37, 51
31, 42
34
HIC_NBE1
I
HIC Byte Enable 1
34, 40, 6
64, 77, 80
53, 64
48
HIC_NCS
I
HIC Chip Select
29
3
1
1
HIC_NOE
O
HIC Output Enable
28, 3
4, 60
2, 49
2, 39
HIC_NRDY
O
HIC Ready
37, 9
46, 75
37, 62
29
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35
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TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table 6-3. Digital Signals (continued)
SIGNAL NAME
PIN
TYPE
HIC_NWE
I
DESCRIPTION
HIC Data Write Enable
GPIO
80 QFP
64 QFP
48 QFP
48, 59, 6, 76
39, 48, 63
31, 38
1, 18, 27, 33,
38, 44, 46,
37, 43, 8
50, 54, 58, 62
10, 35, 4, 46
32, 37, 41,
47, 51
25, 29, 33, 41
I2CA_SCL
I/OD I2C-A Open-Drain Bidirectional Clock
I2CA_SDA
I/OD I2C-A Open-Drain Bidirectional Data
10, 19, 26,
32, 35, 42
43, 48, 49,
51, 57, 63, 76
39, 40, 42,
52, 63
31, 32, 34, 42
I2CB_SCL
I/OD I2C-B Open-Drain Bidirectional Clock
15, 29, 3, 9
3, 60, 75, 78
1, 49, 62
1, 39
I2CB_SDA
I/OD I2C-B Open-Drain Bidirectional Data
14, 2, 28, 34
4, 61, 77, 79
2, 50
2, 40
3, 38, 48, 57,
65
1, 32, 39, 54
1, 25, 31
4, 46, 49, 6,
67
2, 37, 40, 56
2, 29, 32
LINA_RX
I
LIN-A Receive
23, 29, 33,
35, 42
LINA_TX
O
LIN-A Transmit
22, 28, 32,
37, 46
LINB_RX
I
LIN-B Receive
11, 13, 15, 19, 35, 37, 51,
23, 41, 9
65, 66, 75, 78
29, 31, 42,
54, 55, 62
23, 34
LINB_TX
O
LIN-B Transmit
10, 12, 14,
36, 41, 50,
18, 22, 24, 40 64, 67, 76, 79
30, 35, 41,
53, 56, 63
24, 27, 33
OUTPUTXBAR1
O
Output X-BAR Output 1
2, 24, 34
41, 61, 77
35, 50
27, 40
OUTPUTXBAR2
O
Output X-BAR Output 2
25, 3, 37
42, 46, 60
37, 49
29, 39
OUTPUTXBAR3
O
Output X-BAR Output 3
14, 26, 4, 5
43, 59, 74, 79
48, 61
38, 47
OUTPUTXBAR4
O
Output X-BAR Output 4
15, 27, 33, 6
38, 44, 78, 80
32, 64
25, 48
OUTPUTXBAR5
O
Output X-BAR Output 5
28, 42, 7
4, 57, 68
2, 57
2, 43
OUTPUTXBAR6
O
Output X-BAR Output 6
29, 43, 9
3, 54, 75
1, 62
1
OUTPUTXBAR7
O
Output X-BAR Output 7
11, 16, 30, 44
1, 37, 39, 69
31, 33
26
OUTPUTXBAR8
O
Output X-BAR Output 8
PMBUSA_ALERT
PMBus-A Open-Drain Bidirectional
I/OD
Alert
PMBus-A Control Signal - Slave
Input/Master Output
17, 31, 45
2, 40, 73
34
13, 19, 27,
37, 43
35, 44, 46,
51, 54
29, 37, 42
23, 29, 34
12, 18, 26,
35, 42
36, 43, 48,
50, 57
30, 39, 41
24, 31, 33
PMBUSA_CTL
I/O
PMBUSA_SCL
I/OD
PMBus-A Open-Drain Bidirectional
Clock
15, 16, 24, 3,
35, 41
39, 41, 48,
60, 66, 78
33, 35, 39,
49, 55
26, 27, 31, 39
PMBUSA_SDA
I/OD
PMBus-A Open-Drain Bidirectional
Data
14, 17, 2, 25,
34, 40
40, 42, 61,
64, 77, 79
34, 50, 53
40
SCIA_RX
I
SCI-A Receive Data
17, 25, 28, 3,
35, 9
4, 40, 42, 48,
60, 75
2, 34, 39, 49,
62
2, 31, 39
SCIA_TX
O
SCI-A Transmit Data
16, 2, 24, 29,
37, 8
3, 39, 41, 46,
58, 61
1, 33, 35, 37,
47, 50
1, 26, 27, 29,
40
SPIA_CLK
I/O
SPI-A Clock
12, 18, 3, 9
36, 50, 60, 75 30, 41, 49, 62
24, 33, 39
SPIA_SIMO
I/O
SPI-A Slave In, Master Out (SIMO)
11, 16, 2, 8
37, 39, 58, 61 31, 33, 47, 50
26, 40
SPIA_SOMI
I/O
SPI-A Slave Out, Master In (SOMI)
1, 10, 13, 17
35, 40, 62, 76 29, 34, 51, 63
23, 41
SPIA_STE
I/O
SPI-A Slave Transmit Enable (STE)
11, 19, 5
37, 51, 63, 74 31, 42, 52, 61
34, 42, 47
SPIB_CLK
I/O
SPI-B Clock
4, 43, 49, 59,
67, 79
2, 40, 48, 56
2, 32, 38
SPIB_SIMO
I/O
SPI-B Slave In, Master Out (SIMO)
24, 30, 40, 7
1, 41, 64, 68
35, 53, 57
27, 43
2, 39, 42, 66,
80
33, 55, 64
26, 48
14, 22, 26,
28, 32, 4
SPIB_SOMI
I/O
SPI-B Slave Out, Master In (SOMI)
16, 25, 31,
41, 6
SPIB_STE
I/O
SPI-B Slave Transmit Enable (STE)
15, 23, 27,
29, 33
3, 38, 44, 65,
78
1, 32, 54
1, 25
SYNCOUT
O
External ePWM Synchronization
Pulse
39, 6
56, 80
46, 64
48
36
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table 6-3. Digital Signals (continued)
SIGNAL NAME
PIN
TYPE
DESCRIPTION
GPIO
80 QFP
64 QFP
48 QFP
I
JTAG Test Data Input (TDI) - TDI is
the default mux selection for the pin.
The internal pullup is disabled by
default. The internal pullup should be
enabled or an external pullup added
on the board if this pin is used as
JTAG TDI to avoid a floating input.
35
48
39
31
O
JTAG Test Data Output (TDO) - TDO
is the default mux selection for the
pin. The internal pullup is disabled by
default. The TDO function will tristate
when there is no JTAG activity,
leaving this pin floating; the internal
pullup should be enabled or an
external pullup added on the board to
avoid a floating GPIO input.
37
46
37
29
I
Crystal oscillator input or singleended clock input. The device
initialization software must configure
this pin before the crystal oscillator is
enabled. To use this oscillator, a
quartz crystal circuit must be
connected to X1 and X2. This pin can
also be used to feed a single-ended
3.3-V level clock. For more
information about the ALT
functionality, see the table that is in
the External Oscillator (XTAL) section
of the System Control chapter in the
TMS320F28002x Real-Time
Microcontrollers Technical Reference
Manual.
19
51
42
34
O
Crystal oscillator output. For more
information about the ALT
functionality, see the table that is in
the External Oscillator (XTAL) section
of the System Control chapter in the
TMS320F28002x Real-Time
Microcontrollers Technical Reference
Manual.
18
50
41
33
O
External Clock Output. This pin
outputs a divided-down version of a
chosen clock signal from within the
device.
16, 18
39, 50
33, 41
26, 33
80 QFP
64 QFP
48 QFP
31, 53, 71, 8
27, 4, 44, 59
36, 45
26
22
18
TDI
TDO
X1
X2
XCLKOUT
6.3.3 Power and Ground
Table 6-4. Power and Ground
SIGNAL NAME
PIN
TYPE
DESCRIPTION
VDD
1.2-V Digital Logic Power Pins. TI
recommends placing a decoupling
capacitor near each VDD pin with a
minimum total capacitance of
approximately 10 µF. It is also
recommended that all VDD pins be
externally connected to each other.
VDDA
3.3-V Analog Power Pins. Place a
minimum 2.2-µF decoupling capacitor
on each pin.
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table 6-4. Power and Ground (continued)
SIGNAL NAME
PIN
TYPE
DESCRIPTION
GPIO
80 QFP
64 QFP
48 QFP
VDDIO
3.3-V Digital I/O Power Pins. Place a
minimum 0.1-µF decoupling capacitor
on each pin. It's recommended to
place an additional bulk cap of
around 20uF shared by all the pins.
However, the exact value of this bulk
cap will depend on the regulator
being used.
32, 52, 7, 72
28, 43, 60
35, 46
VSS
Digital Ground
30, 55, 70, 9
26, 45, 5, 58
22, 37, 44
VSSA
Analog Ground
25
21
17
80 QFP
64 QFP
48 QFP
6.3.4 Test, JTAG, and Reset
Table 6-5. Test, JTAG, and Reset
SIGNAL NAME
PIN
TYPE
DESCRIPTION
GPIO
FLT1
I/O
Flash test pin 1. Reserved for TI.
Must be left unconnected.
34
FLT2
I/O
Flash test pin 2. Reserved for TI.
Must be left unconnected.
33
TCK
I
JTAG test clock with internal pullup.
45
36
28
I/O
JTAG test-mode select (TMS) with
internal pullup. This serial control
input is clocked into the TAP
controller on the rising edge of TCK.
This device does not have a TRSTn
pin. An external pullup resistor
(recommended 2.2 kΩ) on the TMS
pin to VDDIO should be placed on
the board to keep JTAG in reset
during normal operation.
47
38
30
5
3
3
TMS
XRSn
38
Device Reset (in) and Watchdog
Reset (out). During a power-on
condition, this pin is driven low by the
device. An external circuit may also
drive this pin to assert a device reset.
This pin is also driven low by the
MCU when a watchdog reset occurs.
During watchdog reset, the XRSn pin
is driven low for the watchdog reset
duration of 512 OSCCLK cycles. A
resistor between 2.2 kΩ and 10 kΩ
should be placed between XRSn and
I/OD
VDDIO. If a capacitor is placed
between XRSn and VSS for noise
filtering, it should be 100 nF or
smaller. These values will allow the
watchdog to properly drive the XRSn
pin to VOL within 512 OSCCLK
cycles when the watchdog reset is
asserted. This pin is an open-drain
output with an internal pullup. If this
pin is driven by an external device, it
should be done using an open-drain
device.
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
6.4 Pin Multiplexing
6.4.1 GPIO Muxed Pins
Table 6-6 lists the GPIO muxed pins. The default mode for each GPIO pin is the GPIO function, except GPIO35
and GPIO37, which default to TDI and TDO, respectively. Secondary functions can be selected by setting both
the GPyGMUXn.GPIOz and GPyMUXn.GPIOz register bits. The GPyGMUXn register should be configured
before the GPyMUXn to avoid transient pulses on GPIOs from alternate mux selections. Columns that are not
shown and blank cells are reserved GPIO Mux settings. GPIO ALT functions cannot be configured with the
GPyMUXn and GPyGMUXn registers. These are special functions that need to be configured from the module.
Note
GPIO20, GPIO21, GPIO36 and GPIO38 do not exist on this device. GPIO61 to GPIO63 exist but are
not pinned out on any packages. Boot ROM enables pullups on GPIO61 to GPIO63. For more details,
see Section 6.5.
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
6.4.1.1 GPIO Muxed Pins Table
Table 6-6. GPIO Muxed Pins
0, 4, 8, 12
7
9
GPIO0
EPWM1_A
I2CA_SDA
SPIA_STE
FSIRXA_CLK
GPIO1
EPWM1_B
I2CA_SCL
SPIA_SOMI
GPIO2
EPWM2_A
OUTPUTXBAR1
PMBUSA_SDA
SPIA_SIMO
SCIA_TX
FSIRXA_D1
I2CB_SDA
GPIO3
EPWM2_B
OUTPUTXBAR2
PMBUSA_SCL
SPIA_CLK
SCIA_RX
FSIRXA_D0
I2CB_SCL
SPIB_CLK
EQEP2_STROB
E
FSIRXA_CLK
CLB_OUTPUTX
BAR6
HIC_BASESEL2
SPIA_STE
FSITXA_D1
CLB_OUTPUTX
BAR5
GPIO4
1
2
3
OUTPUTXBAR2
EPWM3_A
GPIO5
EPWM3_B
GPIO6
EPWM4_A
GPIO7
EPWM4_B
5
OUTPUTXBAR3
OUTPUTXBAR3
OUTPUTXBAR4
EQEP1_A
SPIB_SOMI
FSITXA_D0
OUTPUTXBAR5
EQEP1_B
SPIB_SIMO
FSITXA_CLK
SCIA_TX
SPIA_SIMO
SCIA_RX
SPIA_CLK
EPWM5_A
ADCSOCAO
GPIO9
EPWM5_B
OUTPUTXBAR6
EQEP1_INDEX
GPIO10
EPWM6_A
ADCSOCBO
GPIO11
EPWM6_B
OUTPUTXBAR7
EPWM7_A
EPWM7_B
10
11
I2CA_SCL
13
14
CLB_OUTPUTX
BAR8
CLB_OUTPUTX
BAR7
SYNCOUT
GPIO8
GPIO13
CANA_TX
CANA_RX
EQEP1_STROB
E
GPIO12
6
FSITXA_D1
CLB_OUTPUTX
BAR2
15
ALT
HIC_BASESEL1
FSITXA_TDM_D
1
HIC_D10
HIC_A1
CANA_TX
HIC_D9
HIC_NOE
CANA_RX
HIC_D4
HIC_A2
HIC_NWE
HIC_A7
HIC_D4
HIC_D15
HIC_NBE1
CLB_OUTPUTX
BAR8
HIC_D14
HIC_A6
FSITXA_D1
CLB_OUTPUTX
BAR5
HIC_A0
FSITXA_D0
LINB_RX
HIC_D14
FSITXA_TDM_C
LK
HIC_D8
HIC_BASESEL0
I2CB_SCL
HIC_NRDY
EQEP1_A
SPIA_SOMI
I2CA_SDA
FSITXA_CLK
LINB_TX
HIC_NWE
FSITXA_TDM_D
0
EQEP1_B
SPIA_STE
FSIRXA_D1
LINB_RX
EQEP2_A
SPIA_SIMO
HIC_D6
HIC_NBE0
EQEP1_STROB
E
PMBUSA_CTL
FSIRXA_D0
LINB_TX
SPIA_CLK
CANA_RX
HIC_D13
HIC_INT
EQEP1_INDEX
PMBUSA_ALER
T
FSIRXA_CLK
LINB_RX
SPIA_SOMI
CANA_TX
HIC_D11
HIC_D5
GPIO14
I2CB_SDA
OUTPUTXBAR3
PMBUSA_SDA
SPIB_CLK
EQEP2_A
LINB_TX
EPWM3_A
CLB_OUTPUTX
BAR7
HIC_D15
GPIO15
I2CB_SCL
OUTPUTXBAR4
PMBUSA_SCL
SPIB_STE
EQEP2_B
LINB_RX
EPWM3_B
CLB_OUTPUTX
BAR6
HIC_D12
PMBUSA_SCL
XCLKOUT
EQEP2_B
SPIB_SOMI
HIC_D1
PMBUSA_SDA
CANA_TX
HIC_INT
X2
X1
GPIO16
SPIA_SIMO
OUTPUTXBAR7
EPWM5_A
SCIA_TX
EQEP1_STROB
E
GPIO17
SPIA_SOMI
OUTPUTXBAR8
EPWM5_B
SCIA_RX
EQEP1_INDEX
HIC_D2
GPIO18_X2
SPIA_CLK
CANA_RX
EPWM6_A
I2CA_SCL
EQEP2_A
PMBUSA_CTL
XCLKOUT
LINB_TX
FSITXA_TDM_C
LK
GPIO19_X1
SPIA_STE
CANA_TX
EPWM6_B
I2CA_SDA
EQEP2_B
PMBUSA_ALER
T
CLB_OUTPUTX
BAR1
LINB_RX
FSITXA_TDM_D
0
HIC_NBE0
SPIB_CLK
LINA_TX
CLB_OUTPUTX
BAR1
LINB_TX
HIC_A5
EPWM4_A
HIC_D13
EPWM4_B
HIC_D11
GPIO22
EQEP1_STROB
E
GPIO23
EQEP1_INDEX
GPIO24
OUTPUTXBAR1
EQEP2_A
GPIO25
OUTPUTXBAR2
EQEP2_B
GPIO26
OUTPUTXBAR3
GPIO27
OUTPUTXBAR4
40
SPIB_STE
LINA_RX
LINB_RX
HIC_A3
SPIB_SIMO
LINB_TX
PMBUSA_SCL
SCIA_TX
ERRORSTS
EQEP1_A
SPIB_SOMI
FSITXA_D1
PMBUSA_SDA
SCIA_RX
HIC_BASESEL0
EQEP2_INDEX
OUTPUTXBAR3
SPIB_CLK
FSITXA_D0
PMBUSA_CTL
I2CA_SDA
HIC_D0
HIC_A1
EQEP2_STROB
E
OUTPUTXBAR4
SPIB_STE
FSITXA_CLK
PMBUSA_ALER
T
I2CA_SCL
HIC_D1
HIC_A4
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TMS320F280025, TMS320F280025-Q1
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TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table 6-6. GPIO Muxed Pins (continued)
0, 4, 8, 12
1
2
3
5
6
7
9
10
11
13
14
15
EQEP1_A
EQEP2_STROB
E
LINA_TX
SPIB_CLK
ERRORSTS
I2CB_SDA
HIC_NOE
LINA_RX
SPIB_STE
ERRORSTS
I2CB_SCL
HIC_NCS
GPIO28
SCIA_RX
EPWM7_A
OUTPUTXBAR5
GPIO29
SCIA_TX
EPWM7_B
OUTPUTXBAR6
EQEP1_B
EQEP2_INDEX
FSIRXA_CLK
CANA_RX
SPIB_SIMO
OUTPUTXBAR7
EQEP1_STROB
E
GPIO31
CANA_TX
SPIB_SOMI
OUTPUTXBAR8
EQEP1_INDEX
FSIRXA_D1
GPIO32
I2CA_SDA
SPIB_CLK
LINA_TX
FSIRXA_D0
CANA_TX
GPIO33
I2CA_SCL
SPIB_STE
LINA_RX
FSIRXA_CLK
CANA_RX
GPIO34
OUTPUTXBAR1
GPIO35
SCIA_RX
GPIO30
GPIO37
OUTPUTXBAR4
I2CA_SDA
OUTPUTXBAR2
I2CA_SCL
CANA_RX
SCIA_TX
PMBUSA_SCL
CANA_TX
SPIB_SIMO
EQEP2_B
LINA_RX
HIC_D0
I2CB_SDA
HIC_D9
EQEP1_A
PMBUSA_CTL
HIC_NWE
TDI
LINA_TX
EQEP1_B
PMBUSA_ALER
T
HIC_NRDY
TDO
FSIRXA_CLK
EQEP2_INDEX
EQEP1_INDEX
HIC_D7
CLB_OUTPUTX
BAR2
FSIRXA_D0
EQEP1_A
LINB_TX
EPWM2_A
PMBUSA_SCL
FSIRXA_D1
EQEP1_B
LINB_RX
OUTPUTXBAR5
PMBUSA_CTL
I2CA_SDA
EQEP1_STROB
E
GPIO43
OUTPUTXBAR6
PMBUSA_ALER
T
I2CA_SCL
EQEP1_INDEX
GPIO44
OUTPUTXBAR7
EQEP1_A
GPIO45
GPIO46
LINA_RX
HIC_INT
ADCSOCAO
HIC_NBE1
PMBUSA_SDA
GPIO42
HIC_D10
ADCSOCBO
EPWM2_B
GPIO41
HIC_D8
EPWM1_B
PMBUSA_SDA
GPIO39
GPIO40
EPWM1_A
FSITXA_CLK
CLB_OUTPUTX
BAR3
OUTPUTXBAR8
FSITXA_D0
CLB_OUTPUTX
BAR4
LINA_TX
FSITXA_D1
ALT
SYNCOUT
HIC_NBE1
HIC_D5
SPIB_SOMI
HIC_D12
CLB_OUTPUTX
BAR3
HIC_D2
HIC_A6
CLB_OUTPUTX
BAR4
HIC_D3
HIC_A7
HIC_A4
HIC_D7
HIC_D5
HIC_D6
HIC_NWE
GPIO61
GPIO62
GPIO63
AIO224
HIC_A3
AIO225
HIC_NWE
AIO226
HIC_A1
AIO227
HIC_NBE0
AIO228
HIC_A0
AIO230
HIC_BASESEL2
AIO231
HIC_BASESEL1
AIO232
HIC_BASESEL0
AIO233
HIC_A4
AIO237
HIC_A6
AIO238
HIC_NCS
AIO239
HIC_A5
AIO241
HIC_NBE1
AIO242
HIC_A2
AIO244
HIC_A7
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table 6-6. GPIO Muxed Pins (continued)
0, 4, 8, 12
1
2
3
5
6
7
9
10
11
13
14
AIO245
15
ALT
HIC_NOE
Note
The analog pins that contain AIOs are in analog mode by default. AIO mode is enabled by configuring the AMSEL option of GPIOH for the
analog pin. In addition, if using the HIC mux options on the AIO pins, an external pullup is required.
42
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TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
6.4.2 Digital Inputs on ADC Pins (AIOs)
GPIOs on port H (GPIO224–GPIO245) are multiplexed with analog pins. These are also referred to as AIOs.
These pins can only function in input mode. By default, these pins will function as analog pins and the GPIOs
are in a high-Z state. The GPHAMSEL register is used to configure these pins for digital or analog operation.
Note
If digital signals with sharp edges (high dv/dt) are connected to the AIOs, cross-talk can occur with
adjacent analog signals. The user should therefore limit the edge rate of signals connected to AIOs if
adjacent channels are being used for analog functions.
6.4.3 GPIO Input X-BAR
The Input X-BAR is used to route signals from a GPIO to many different IP blocks such as the ADCs, eCAPs,
ePWMs, and external interrupts (see Figure 6-4). Table 6-7 lists the input X-BAR destinations. For details on
configuring the Input X-BAR, see the Crossbar (X-BAR) chapter of the TMS320F28002x Real-Time
Microcontrollers Technical Reference Manual.
GPIO0
GPIOx
Asynchronous
Synchronous
Sync. + Qual.
Input X-BAR
Other Sources
eCAP
Modules
15:0
INPUT16
INPUT15
INPUT14
INPUT13
INPUT12
INPUT11
INPUT10
INPUT9
INPUT8
INPUT7
INPUT6
INPUT5
INPUT4
INPUT3
INPUT2
INPUT1
INPUT[16:1]
127:16
DCCx Clock Source-1
TZ1,TRIP1
TZ2,TRIP2
TZ3,TRIP3
TRIP6
DCCx Clock Source-0
CPU PIE
XINT1
XINT2
XINT3
XINT4
XINT5
TRIP4
TRIP5
ePWM
X-BAR
ePWM
Modules
TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12
Other
Sources
ADC
ADCEXTSOC
EXTSYNCIN1
EXTSYNCIN2
ePWM and eCAP
Sync Scheme
Other Sources
Output X-BAR
Figure 6-4. Input X-BAR
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table 6-7. Input X-BAR Destinations
INPUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ECAP / HRCAP
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
EPWM X-BAR
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
CLB X-BAR
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
OUTPUT X-BAR
Yes
Yes
Yes
CPU XINT
EPWM TRIP
Yes
Yes
Yes
XINT1
XINT2
XINT3
TZ1, TZ2, TZ3,
TRIP1 TRIP2 TRIP3
XINT4 XINT5
TRIP6
ADC START OF
CONVERSION
ADCEX
TSOC
EPWM / ECAP
SYNC
EXTSY
NCIN1
EXTSY
NCIN2
DCCx
CLK1 CLK0
6.4.4 GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
The Output X-BAR has eight outputs that can be selected on the GPIO mux as OUTPUTXBARx. The CLB XBAR has eight outputs that are connected to the CLB global mux as AUXSIGx. The CLB Output X-BAR has
eight outputs that can be selected on the GPIO mux as CLB_OUTPUTXBARx. The ePWM X-BAR has eight
outputs that are connected to the TRIPx inputs of the ePWM. The sources for the Output X-BAR, CLB X-BAR,
CLB Output X-BAR, and ePWM X-BAR are shown in Figure 6-5. For details on the Output X-BAR, CLB X-BAR,
CLB Output X-BAR, and ePWM X-BAR, see the Crossbar (X-BAR) chapter of the TMS320F28002x Real-Time
Microcontrollers Technical Reference Manual.
44
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TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
CMPSSx
ePWM and eCAP
Sync Chain
CTRIPOUTH
CTRIPOUTL
(Output X-BAR only)
CTRIPH
CTRIPL
(ePWM X-BAR only)
EXTSYNCOUT
ADCSOCA0
Select Circuit
ADCSOCA0
ADCSOCB0
Select Circuit
ADCSOCB0
eCAPx
ECAPxOUT
ADCx
EVT1
EVT2
EVT3
EVT4
Input X-BAR
CLB
X-BAR
AUXSIG1
AUXSIG2
AUXSIG3
AUXSIG4
AUXSIG5
AUXSIG6
AUXSIG7
AUXSIG8
CLB
Global
Mux
TRIP4
TRIP5
EPWM
X-BAR
INPUT1-6
INPUT7-14
(ePWM X-BAR only)
TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12
All
ePWM
Modules
eQEPx
Output
X-BAR
OUTPUTXBAR1
OUTPUTXBAR2
OUTPUTXBAR3
OUTPUTXBAR4
OUTPUTXBAR5
OUTPUTXBAR6
OUTPUTXBAR7
OUTPUTXBAR8
GPIO
Mux
X-BAR Flags
(shared)
CLB Input X-BAR
CLB TILEx
CLB
Output
X-BAR
CLB_OUTPUTXBAR1
CLB_OUTPUTXBAR2
CLB_OUTPUTXBAR3
CLB_OUTPUTXBAR4
CLB_OUTPUTXBAR5
CLB_OUTPUTXBAR6
CLB_OUTPUTXBAR7
CLB_OUTPUTXBAR8
Figure 6-5. Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR Sources
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45
TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
6.5 Pins With Internal Pullup and Pulldown
Some pins on the device have internal pullups or pulldowns. Table 6-8 lists the pull direction and when it is
active. The pullups on GPIO pins are disabled by default and can be enabled through software. To avoid any
floating unbonded inputs, the Boot ROM will enable internal pullups on GPIO pins that are not bonded out in a
particular package. Other pins noted in Table 6-8 with pullups and pulldowns are always on and cannot be
disabled.
Table 6-8. Pins With Internal Pullup and Pulldown
PIN
GPIOx
RESET
(XRSn = 0)
DEVICE BOOT
APPLICATION
Pullup disabled
Pullup disabled(1)
Application defined
GPIO35/TDI
Pullup disabled
GPIO37/TDO
Pullup disabled
Application defined
Application defined
TCK
Pullup active
TMS
Pullup active
XRSn
Pullup active
Other pins (including AIOs)
(1)
46
No pullup or pulldown present
Pins not bonded out in a given package will have the internal pullups enabled by the Boot ROM.
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TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
6.6 Connections for Unused Pins
For applications that do not need to use all functions of the device, Table 6-9 lists acceptable conditioning for any
unused pins. When multiple options are listed in Table 6-9, any option is acceptable. Pins not listed in Table 6-9
must be connected according to Section 6.
Table 6-9. Connections for Unused Pins
SIGNAL NAME
ACCEPTABLE PRACTICE
ANALOG
VREFHI
Tie to VDDA (applies only if ADC is not used in the application)
VREFLO
Tie to VSSA
Analog input pins
•
•
•
No Connect
Tie to VSSA
Tie to VSSA through resistor
FLT1 (Flash Test pin 1)
•
•
No Connect
Tie to VSS through 4.7-kΩ or larger resistor
FLT2 (Flash Test pin 2)
•
•
No Connect
Tie to VSS through 4.7-kΩ or larger resistor
GPIOx
•
•
•
No connection (input mode with internal pullup enabled)
No connection (output mode with internal pullup disabled)
Pullup or pulldown resistor (any value resistor, input mode, and with internal pullup disabled)
GPIO35/TDI
When TDI mux option is selected (default), the GPIO is in Input mode.
• Internal pullup enabled
• External pullup resistor
GPIO37/TDO
When TDO mux option is selected (default), the GPIO is in Output mode only during JTAG activity;
otherwise, it is in a tri-state condition. The pin must be biased to avoid extra current on the input buffer.
• Internal pullup enabled
• External pullup resistor
TCK
•
•
TMS
Pullup resistor
GPIO19/X1
Turn XTAL off and:
• Input mode with internal pullup enabled
• Input mode with external pullup or pulldown resistor
• Output mode with internal pullup disabled
GPIO18/X2
Turn XTAL off and:
• Input mode with internal pullup enabled
• Input mode with external pullup or pulldown resistor
• Output mode with internal pullup disabled
VDD
All VDD pins must be connected per Section 6.3. Pins should not be used to bias any external circuits.
VDDA
If a dedicated analog supply is not used, tie to VDDIO.
VDDIO
All VDDIO pins must be connected per Section 6.3.
VSS
All VSS pins must be connected to board ground.
VSSA
If an analog ground is not used, tie to VSS.
DIGITAL
No Connect
Pullup resistor
POWER AND GROUND
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47
TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
7 Specifications
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only and functional operation of the device beyond the Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability. All voltage values are with respect to VSS, unless otherwise noted.
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Supply voltage
Input voltage
Output voltage
Input clamp current
MIN
MAX
VDDIO with respect to VSS
–0.3
4.6
VDDA with respect to VSSA
–0.3
4.6
VIN (3.3 V)
–0.3
4.6
V
V
VO
–0.3
4.6
Digital/analog input (per pin), IIK (VIN < VSS/VSSA or VIN >
VDDIO/VDDA)(2)
–20
20
Total for all inputs, IIKTOTAL
(VIN < VSS/VSSA or VIN > VDDIO/VDDA)
–20
20
UNIT
V
mA
Output current
Digital output (per pin), IOUT
–20
20
mA
Free-Air temperature
TA
–40
125
°C
Operating junction temperature
TJ
–40
150
°C
Storage temperature(1)
Tstg
–65
150
°C
(1)
(2)
Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device
life. For additional information, see the Semiconductor and IC Package Thermal Metrics Application Report.
Continuous clamp current per pin is ±2 mA. Do not operate in this condition continuously as VDDIO/VDDA voltage may internally rise and
impact other electrical specifications.
7.2 ESD Ratings – Commercial
VALUE
UNIT
F280025, F280025C, F280023, F280023C in 80-pin PN package
V(ESD)
Electrostatic discharge
(ESD)
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification
JESD22-C101 or ANSI/ESDA/JEDEC JS-002(2)
±500
V
F280025, F280025C, F280023, F280023C in 64-pin PM package
V(ESD)
Electrostatic discharge
(ESD)
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification
JESD22-C101 or ANSI/ESDA/JEDEC JS-002(2)
±500
V
F280025, F280025C, F280023, F280023C, F280021 in 48-pin PT package
V(ESD)
(1)
(2)
48
Electrostatic discharge
(ESD)
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification
JESD22-C101 or ANSI/ESDA/JEDEC JS-002(2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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TMS320F280025, TMS320F280025-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
7.3 ESD Ratings – Automotive
VALUE
UNIT
F280025-Q1, F280025C-Q1, F280023-Q1 in 80-pin PN package
V(ESD)
Electrostatic discharge
Human body model (HBM), per
AEC Q100-002(1)
All pins
±2000
Charged device model (CDM),
per AEC Q100-011
All pins
±500
Corner pins on 80-pin PN:
1, 20, 21, 40, 41, 60, 61, 80
±750
Human body model (HBM), per
AEC Q100-002(1)
All pins
±2000
Charged device model (CDM),
per AEC Q100-011
All pins
±500
Corner pins on 64-pin PM:
1, 16, 17, 32, 33, 48, 49, 64
±750
Human body model (HBM), per
AEC Q100-002(1)
All pins
±2000
Charged device model (CDM),
per AEC Q100-011
All pins
±500
Corner pins on 48-pin PT:
1, 12, 13, 24, 25, 36, 37, 48
±750
V
F280025-Q1, F280025C-Q1, F280023-Q1 in 64-pin PM package
V(ESD)
Electrostatic discharge
V
F280025-Q1, F280025C-Q1, F280023-Q1, F280021-Q1 in 48-pin PT package
V(ESD)
(1)
Electrostatic discharge
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.4 Recommended Operating Conditions
Device supply voltage, VDDIO and
VDDA
Internal BOR
enabled(3)
Internal BOR disabled
MIN
NOM
(2)
3.3
3.63
2.8
3.3
3.63
VBOR-VDDIO(MAX) + VBOR-GB
MAX UNIT
V
Device ground, VSS
0
V
Analog ground, VSSA
0
V
SRSUPPLY
Supply ramp rate of VDDIO,
VDDA with respect to VSS.(4)
tVDDIO-RAMP
VDDIO supply ramp time from
1 V to VBOR-VDDIO(MAX)
Digital input voltage
VIN
Analog input voltage
20
100 mV/us
10
VSS – 0.3
VDDIO + 0.3
VSSA – 0.3
VDDA + 0.3
ms
V
V
VBOR-GB
VDDIO BOR guard band(5)
Junction temperature, TJ
S version(1)
–40
125
°C
Free-Air temperature, TA
Q version(1)
(AEC Q100 qualification)
–40
125
°C
(1)
(2)
(3)
(4)
(5)
0.1
V
Operation above TJ = 105°C for extended duration will reduce the lifetime of the device. See Calculating Useful Lifetimes of Embedded
Processors for more information.
The VDDIO BOR voltage (VBOR-VDDIO[MAX]) in Electrical Characteristics table determines the lower voltage bound for device
operation. TI recommends that system designers budget an additional guard band (VBOR-GB) as shown in Supply Voltages figure.
Internal BOR is enabled by default.
Supply ramp rate faster than this can trigger the on-chip ESD protection.
TI recommends VBOR-GB to avoid BOR resets due to normal supply noise or load-transient events on the 3.3-V VDDIO system
regulator. Good system regulator design and decoupling capacitance (following the system regulator specifications) are important to
prevent activation of the BOR during normal device operation. The value of VBOR-GB is a system-level design consideration; the voltage
listed here is typical for many applications.
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49
TMS320F280025, TMS320F280025-Q1
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Supply Voltages
3.63 V
+10%
3.3 V
0%
3.1 V
–6.1%
3.0 V
–9.1%
Recommended
System Voltage
Regulator Range
F28002x
VDDIO
Operating
Range
VBOR-GB
BOR Guard Band
VBOR-VDDIO
Internal BOR Threshold
2.81 V
2.80 V
–14.8%
–15.1%
Figure 7-1. Supply Voltages
50
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TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
7.5 Power Consumption Summary
Current values listed in this section are representative for the test conditions given and not the absolute
maximum possible. The actual device currents in an application will vary with application code and pin
configurations. Section 7.5.1 lists the system current consumption values.
7.5.1 System Current Consumption
over operating free-air temperature range (unless otherwise noted).
TYP : Vnom, 30℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
35
72
mA
3
5
mA
16
33
mA
0.01
0.1
mA
8
22
mA
0.01
0.1
mA
1
16
mA
0.01
0.1
mA
72
106
mA
0.1
2.5
mA
OPERATING MODE
IDDIO
VDDIO current consumption during
operational usage
IDDA
VDDA current consumption during
operational usage
This is an estimation of current
for a typical heavily loaded
application. Actual currents will
vary depending on system
activity, I/O electrical loading and
switching frequency.
IDLE MODE
IDDIO
VDDIO current consumption while
device is in Idle mode
IDDA
VDDA current consumption while
device is in Idle mode
- CPU is in IDLE mode
- Flash is powered down
- XCLKOUT is turned off
- Pull up is enabled for IO pins
STANDBY MODE
IDDIO
VDDIO current consumption while
device is in Standby mode
IDDA
VDDA current consumption while
device is in Standby mode
- CPU is in STANDBY mode
- Flash is powered down
- XCLKOUT is turned off
- Pull up is enabled for IO pins
HALT MODE
IDDIO
VDDIO current consumption while
device is in Halt mode
IDDA
VDDA current consumption while
device is in Halt mode
- CPU is in HALT mode
- Flash is powered down
- XCLKOUT is turned off
- Pull up is enabled for IO pins
FLASH ERASE/PROGRAM
IDDIO
VDDIO current consumption during
Erase/Program cycle(1)
IDDA
VDDA current consumption during
Erase/Program cycle
- CPU is running from RAM.
- SYSCLK at 100 MHz.
- I/Os are inputs with pullups
enabled.
- Peripheral clocks are turned off.
RESET MODE
IDDIO
VDDIO current consumption while
reset is active(2)
8.6
mA
IDDA
VDDA current consumption while reset
is active(2)
0.1
mA
(1)
(2)
Brownout events during flash programming can corrupt flash data and permanently lock the device. Programming environments using
alternate power sources (such as a USB programmer) must be capable of supplying the rated current for the device and other system
components with sufficient margin to avoid supply brownout conditions.
This is the current consumption while reset is active, i.e XRSn is low.
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TMS320F280025, TMS320F280025-Q1
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7.5.2 Operating Mode Test Description
Section 7.5.1 and Section 7.5.4.1 list the current consumption values for the operational mode of the device. The
operational mode provides an estimation of what an application might encounter. The test condition for these
measurements has the following properties:
• Code is executing from RAM.
• FLASH is read and kept in active state.
• No external components are driven by I/O pins.
• All peripherals have clocks enabled.
• All CPUs are actively executing code.
• All analog peripherals are powered up. ADCs and DACs are periodically converting.
7.5.3 Current Consumption Graphs
Figure 7-2, Figure 7-3, Figure 7-4, Figure 7-5, and Figure 7-6 show a typical representation of the relationship
between frequency, temperature, core supply, and current consumption on the device. Actual results will vary
based on the system implementation and conditions.
Figure 7-3 shows the typical operating current profile across temperature and core supply voltage. Figure 7-4
shows the typical idle current profile across temperature and core supply voltage. Figure 7-5 shows the typical
standby current profile across temperature and core supply voltage. Figure 7-6 shows the typical halt current
profile across temperature and core supply voltage.
52
Figure 7-2. Operating Current Versus Frequency
Figure 7-3. Operating Current Versus Temperature
Figure 7-4. Current Versus Temperature –
IDLE Mode
Figure 7-5. Current Versus Temperature –
STANDBY Mode
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TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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Figure 7-6. Current Versus Temperature – HALT Mode
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53
TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
7.5.4 Reducing Current Consumption
The F28002x devices provide some methods to reduce the device current consumption:
• One of the two low-power modes—IDLE or STANDBY—could be entered during idle periods in the
application.
• The flash module may be powered down if the code is run from RAM.
• Disable the pullups on pins that assume an output function.
• Each peripheral has an individual clock-enable bit (PCLKCRx). Reduced current consumption may be
achieved by turning off the clock to any peripheral that is not used in a given application. Section 7.5.4.1 lists
the typical current reduction that may be achieved by disabling the clocks using the PCLKCRx register.
• To realize the lowest VDDA current consumption in an LPM, see the Analog-to-Digital Converter (ADC)
chapter of the TMS320F28002x Real-Time Microcontrollers Technical Reference Manual to ensure each
module is powered down as well.
7.5.4.1 Typical Current Reduction per Disabled Peripheral
PERIPHERAL
IDDIO CURRENT REDUCTION (mA)
ADC(1)
0.67
BGCRC
0.26
CAN
1.18
CLB
1.18
CMPSS(1)
0.34
CPU TIMER
0.02
CPUCRC
0.01
DCC
0.18
DMA
0.56
eCAP1 and eCAP2
0.22
eCAP3(2)
0.28
ePWM
0.78
eQEP
0.11
FSI
0.74
HIC
0.21
HRPWM
0.87
I2C
0.24
LIN
0.32
PBIST
0.19
PMBUS
0.26
SCI
0.16
SPI
0.08
(1)
(2)
54
This current represents the current drawn by the digital portion of the each module.
eCAP3 can also be configured as HRCAP.
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TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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7.6 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
Digital and Analog IO
VOH
High-level output voltage
VOL
Low-level output voltage
IOH
High-level output source current for all output pins
IOL
Low-level output sink current for all output pins
ROH
High-level output impedance for all output pins
IOH = IOH MIN
VDDIO * 0.8
IOH = –100 μA
VDDIO – 0.2
V
IOL = IOL MAX
0.4
IOL = 100 µA
0.2
–4
V
mA
4
mA
45
65
100
Ω
60
90
Ω
ROL
Low-level output impedance for all output pins
45
VIH
High-level input voltage
2.0
V
VIL
Low-level input voltage
VHYSTERESIS
Input hysteresis
0.8
IPULLDOWN
Input current
Pins with pulldown
VDDIO = 3.3 V
VIN = VDDIO
120
µA
IPULLUP
Input current
Digital inputs with pullup VDDIO = 3.3 V
enabled(1)
VIN = 0 V
160
µA
125
Digital inputs
ILEAK
Pin leakage
Analog pins (except
ADCINA3/VDAC)
ADCINA3/VDAC
CI
Input capacitance
V
mV
Pullups and outputs
disabled
0 V ≤ VIN ≤ VDDIO
0.1
µA
Analog drivers
disabled
0 V ≤ VIN ≤ VDDA
0.1
2
Digital inputs
11
2
pF
Analog pins(2)
VREG and BOR
VPOR-VDDIO
VDDIO power on reset
voltage
VBOR-VDDIO
VDDIO brown out reset voltage(3)
2.81
VVREG
Internal voltage regulator output
1.14
(1)
(2)
(3)
VDDIO power on reset
voltage
2.3
1.2
V
3.0
V
1.32
V
See Pins With Internal Pullup and Pulldown table for a list of pins with a pullup or pulldown.
The analog pins are specified separately; see Per-Channel Parasitic Capacitance table.
See the Supply Voltages figure in the Recommended Operating Conditions section.
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7.7 Thermal Resistance Characteristics for PN Package
°C/W(1)
AIR FLOW (lfm)(2)
RΘJC
Junction-to-case thermal resistance
14.2
N/A
RΘJB
Junction-to-board thermal resistance
21.9
N/A
RΘJA (High k PCB)
PsiJT
Junction-to-package top
PsiJB
(1)
(2)
Junction-to-free air thermal resistance
Junction-to-board
49.9
0
38.3
150
36.7
250
34.4
500
0.8
0
1.18
150
1.34
250
1.62
500
21.6
0
20.7
150
20.5
250
20.1
500
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
lfm = linear feet per minute
7.8 Thermal Resistance Characteristics for PM Package
°C/W(1)
AIR FLOW (lfm)(2)
RΘJC
Junction-to-case thermal resistance
12.4
N/A
RΘJB
Junction-to-board thermal resistance
25.6
N/A
RΘJA (High k PCB)
Junction-to-free air thermal resistance
51.8
0
42.2
150
RΘJMA
Junction-to-moving air thermal resistance
39.4
250
36.5
500
0.5
0
0.9
150
1.1
250
PsiJT
PsiJB
(1)
(2)
56
Junction-to-package top
Junction-to-board
1.4
500
25.1
0
23.8
150
23.4
250
22.7
500
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
lfm = linear feet per minute
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TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
7.9 Thermal Resistance Characteristics for PT Package
°C/W(1)
AIR FLOW (lfm)(2)
RΘJC
Junction-to-case thermal resistance
13.6
N/A
RΘJB
Junction-to-board thermal resistance
30.6
N/A
RΘJA (High k PCB)
PsiJT
PsiJB
(1)
(2)
Junction-to-free air thermal resistance
Junction-to-package top
Junction-to-board
64
0
50.4
150
48.2
250
45
500
0.56
0
0.94
150
1.1
250
1.38
500
30.1
0
28.7
150
28.4
250
28
500
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
lfm = linear feet per minute
7.10 Thermal Design Considerations
Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems that
exceed the recommended maximum power dissipation in the end product may require additional thermal
enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor
that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care
should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the operating
junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. The thermal
application report Semiconductor and IC Package Thermal Metrics helps to understand the thermal metrics and
definitions.
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7.11 System
7.11.1 Power Management
TMS320F28002x real-time MCUs use an internal 1.2-V LDO Voltage Regulator (VREG) to supply the required
1.2 V to the core (VDD).
7.11.1.1 Internal 1.2-V LDO Voltage Regulator (VREG)
The internal VREG is supplied by VDDIO and generates the 1.2 V required to power the VDD pins. The internal
VREG is always enabled and, as such, is the required supply source for the VDD pins. Although the internal
VREG eliminates the need to use an external power supply for VDD, decoupling capacitors are required on each
VDD pin for VREG stability. There are two recommended capacitor configurations (described in the list that
follows) for the VDD rail when using the internal VREG. The signal description for VDD can be found in Table
6-4.
•
•
Configuration 1: Place a small decoupling capacitor to VSS on each pin as close to the device as possible. In
addition, a bulk capacitance must be placed on the VDD node to VSS (one 10-µF capacitor or two parallel
4.7-µF capacitors).
Configuration 2: Distribute the total capacitance to VSS evenly across all VDD pins (total capacitance divided
by number of available VDD pins).
7.11.1.2 Power Sequencing
Signal Pin Requirements: Before powering the device, no voltage larger than 0.3 V above VDDIO can be
applied to any digital pin, and no voltage larger than 0.3 V above VDDA can be applied to any analog pin
(including VREFHI).
VDDIO and VDDA Requirements: The 3.3-V supplies VDDIO and VDDA should be powered up together and
kept within 0.3 V of each other during functional operation.
VDD Requirements: The VDD sequencing requirements are handled by the device.
7.11.1.3 Power-On Reset (POR)
An internal power-on reset (POR) circuit holds the device in reset and keeps the I/Os in a high-impedance state
during power up. The POR is in control and forces XRSn low internally until the voltage on VDDIO crosses the
POR threshold. When the voltage crosses the POR threshold, the internal brownout-reset (BOR) circuit takes
control and holds the device in reset until the voltage crosses the BOR threshold (for internal BOR details, see
Section 7.11.1.4).
7.11.1.4 Brownout Reset (BOR)
An internal BOR circuit monitors the VDDIO rail for dips in voltage which result in the supply voltage dropping out
of operational range. When the VDDIO voltage drops below the BOR threshold, the device is forced into reset,
and XRSn is pulled low. XRSn will remain in reset until the voltage returns to the operational range. The BOR is
enabled by default. To disable the BOR, set the BORLVMONDIS bit in the VMONCTL register. The internal BOR
circuit monitors only the VDDIO rail. See Section 7.6 for BOR characteristics. External supply voltage supervisor
(SVS) devices can be used to monitor the voltage on the 3.3-V rail and to drive XRSn low if supplies fall outside
operational specifications.
58
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7.11.2 Reset Timing
XRSn is the device reset pin. It functions as an input and open-drain output. The device has a built-in power-on
reset (POR). During power up, the POR circuit drives the XRSn pin low. A watchdog or NMI watchdog reset will
also drive the pin low. An external open-drain circuit may drive the pin to assert a device reset.
A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRSn and VDDIO. A capacitor should be
placed between XRSn and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the
watchdog to properly drive the XRSn pin to VOL within 512 OSCCLK cycles when the watchdog reset is
asserted. Figure 7-7 shows the recommended reset circuit.
VDDIO
2.2 kW to 10 kW
Optional open-drain
Reset source
XRSn
£100 nF
Figure 7-7. Reset Circuit
7.11.2.1 Reset Sources
Table 7-1 summarizes the various reset signals and their effect on the device.
Table 7-1. Reset Signals
RESET SOURCE
CPU CORE
RESET
(C28x, FPU, VCU)
PERIPHERALS
RESET
JTAG/
DEBUG LOGIC
RESET
I/Os
XRSn OUTPUT
Yes
Yes
Yes
Hi-Z
Yes
POR
XRSn Pin
Yes
Yes
No
Hi-Z
–
WDRS
Yes
Yes
No
Hi-Z
Yes
NMIWDRS
Yes
Yes
No
Hi-Z
Yes
SYSRS (Debugger Reset)
Yes
Yes
No
Hi-Z
No
SCCRESET
Yes
Yes
No
Hi-Z
No
The parameter th(boot-mode) must account for a reset initiated from any of these sources.
See the Resets section of the System Control chapter in the TMS320F28002x Real-Time Microcontrollers
Technical Reference Manual.
CAUTION
Some reset sources are internally driven by the device. Some of these sources will drive XRSn low,
use this to disable any other devices driving the boot pins. The SCCRESET and debugger reset
sources do not drive XRSn; therefore, the pins used for boot mode should not be actively driven by
other devices in the system. The boot configuration has a provision for changing the boot pins in
OTP; for more details, see the TMS320F28002x Real-Time Microcontrollers Technical Reference
Manual.
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7.11.2.2 Reset Electrical Data and Timing
Section 7.11.2.2.1 lists the reset (XRSn) timing requirements. Section 7.11.2.2.2 lists the reset (XRSn) switching
characteristics. Figure 7-8 shows the power-on reset. Figure 7-9 shows the warm reset.
7.11.2.2.1 Reset (XRSn) Timing Requirements
MIN
th(boot-mode)
Hold time for boot-mode pins
1.5
All cases
Pulse duration, XRSn low on
Low-power
modes used in
warm reset
application and SYSCLKDIV > 16
3.2
tw(RSL2)
MAX
UNIT
ms
µs
3.2 * (SYSCLKDIV/16)
7.11.2.2.2 Reset (XRSn) Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
tw(RSL1)
Pulse duration, XRSn driven low by device after supplies are
stable
tw(WDRS)
Pulse duration, reset pulse generated by watchdog
tboot-flash
Boot-ROM execution time to first instruction fetch in flash
TYP
MAX
100
UNIT
µs
512tc(OSCCLK)
cycles
900
µs
7.11.2.2.3 Reset Timing Diagrams
VDDIO VDDA
(3.3V)
VDD (1.2V)
tw(RSL1)
XRSn(A)
tboot-flash
Boot ROM
CPU
Execution
Phase
User code
th(boot-mode)(B)
Boot-Mode
Pins
User code dependent
GPIO pins as input
Peripheral/GPIO function
Based on boot code
Boot-ROM execution starts
GPIO pins as input (pullups are disabled)
I/O Pins
User code dependent
A. The XRSn pin can be driven externally by a supervisor or an external pullup resistor, see Table 6-1. On-chip POR logic will hold this pin
low until the supplies are in a valid range.
B. After reset from any source (see Section 7.11.2.1), the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode
pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in
debugger environment), the boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based on user
environment and could be with or without PLL enabled.
Figure 7-8. Power-on Reset
60
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tw(RSL2)
XRSn
User code
CPU
Execution
Phase
Boot ROM
User code
Boot ROM execution starts
(initiated by any reset source)
Boot-Mode
Pins
Peripheral/GPIO function
GPIO Pins as Input
th(boot-mode)(A)
Peripheral/GPIO function
User-Code Execution Starts
I/O Pins
User-Code Dependent
GPIO Pins as Input (Pullups are Disabled)
User-Code Dependent
A. After reset from any source (see Section 7.11.2.1), the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot
Mode pin, the boot code branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in
debugger environment), the Boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based on user
environment and could be with or without PLL enabled.
Figure 7-9. Warm Reset
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7.11.3 Clock Specifications
7.11.3.1 Clock Sources
Table 7-2 lists clock sources. Figure 7-10 shows the clocking system. Figure 7-11 shows the PLL.
Table 7-2. Possible Reference Clock Sources
CLOCK SOURCE
DESCRIPTION
INTOSC1
Internal oscillator 1.
Zero-pin overhead 10-MHz internal oscillator.
INTOSC2(1)
Internal oscillator 2.
Zero-pin overhead 10-MHz internal oscillator.
X1 (XTAL)
External crystal or resonator connected between the X1 and X2 pins or single-ended clock connected to the X1
pin.
(1)
62
On reset, internal oscillator 2 (INTOSC2) is the default clock source for the PLL (OSCCLK).
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SYSCLKDIVSEL
Watchdog
Timer
SYSPLL
INTOSC1
INTOSC2
OSCCLK
PLLSYSCLK
NMIWD
SYS
Divider
PLLRAWCLK
FPU
TMU
Flash
CPUCLK
SYSPLLCLKEN
X1 (XTAL)
OSCCLKSRCSEL
CPU
SYSCLK
SYSCLK
One per SYSCLK peripheral
PCLKCRx
PERx.SYSCLK
ePIE
GPIO
Mx RAMs
Lx RAMs
GSx RAMs
Boot ROM
DCSM
System Control
WD
XINT
CPUTIMERs
CLB
ECAP
EQEP
EPWM
HRCAL
PMBUS
LIN
FSI
I2C
ADC
CMPSS
CAN
HIC
DCC
HWBIST
BGCRC
ERAD
One per LSPCLK peripheral
LOSPCP
PCLKCRx
LSP
Divider
LSPCLK
PERx.LSPCLK
SCI
SPI
CLKSRCCTL2.CANxBCLKSEL
CAN Bit Clock
Figure 7-10. Clocking System
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SYSPLL
OSCCLK
÷
(REFDIV+1)
INTCLK
VCOCLK
VCO
÷
(ODIV+1)
PLLRAWCLK
÷
IMULT
Figure 7-11. System PLL
In Figure 7-11,
f PLLRAWCLK
64
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f OSCCLK
REFDIV 1
u
IMULT
ODIV 1
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7.11.3.2 Clock Frequencies, Requirements, and Characteristics
This section provides the frequencies and timing requirements of the input clocks, PLL lock times, frequencies of
the internal clocks, and the frequency and switching characteristics of the output clock.
7.11.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
Section 7.11.3.2.1.1 lists the frequency requirements for the input clocks. Section 7.11.3.2.1.2 lists the XTAL
oscillator characteristics. Section 7.11.3.2.1.3 lists the X1 timing requirements. Section 7.11.3.2.1.4 lists the
APLL characteristics. Section 7.11.3.2.1.5 lists the switching characteristics of the output clock, XCLKOUT.
Section 7.11.3.2.1.6 provides the clock frequencies for the internal clocks.
7.11.3.2.1.1 Input Clock Frequency
MIN
MAX
UNIT
f(XTAL)
Frequency, X1/X2, from external crystal or resonator
10
20
MHz
f(X1)
Frequency, X1, from external oscillator
10
25
MHz
7.11.3.2.1.2 XTAL Oscillator Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
X1 VIL
Valid low-level input voltage
X1 VIH
Valid high-level input voltage
TYP
MAX
UNIT
–0.3
0.3 * VDDIO
V
0.7 * VDDIO
VDDIO + 0.3
V
7.11.3.2.1.3 X1 Timing Requirements
MIN
tf(X1)
Fall time, X1
MAX
UNIT
6
ns
6
ns
tr(X1)
Rise time, X1
tw(X1L)
Pulse duration, X1 low as a percentage of tc(X1)
45%
55%
tw(X1H)
Pulse duration, X1 high as a percentage of tc(X1)
45%
55%
7.11.3.2.1.4 APLL Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
PLL Lock time
SYS PLL Lock Time(1)
(1)
5µs + (1024 * (REFDIV + 1) * tc(OSCCLK))
us
The PLL lock time here defines the typical time that takes for the PLL to lock once PLL is enabled (SYSPLLCTL1[PLLENA]=1).
Additional time to verify the PLL clock using Dual Clock Comparator (DCC) is not accounted here. TI recommends using the latest
example software from C2000Ware for initializing the PLLs. For the system PLL, see InitSysPll() or SysCtl_setClock().
7.11.3.2.1.5 XCLKOUT Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER(1)
MIN
MAX
UNIT
tf(XCO)
Fall time, XCLKOUT
5
ns
tr(XCO)
Rise time, XCLKOUT
5
ns
tw(XCOL)
Pulse duration, XCLKOUT low
H – 2(2)
H + 2(2)
ns
tw(XCOH)
Pulse duration, XCLKOUT high
H – 2(2)
H + 2(2)
ns
f(XCO)
Frequency, XCLKOUT
(1)
(2)
50
MHz
A load of 40 pF is assumed for these parameters.
H = 0.5tc(XCO)
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7.11.3.2.1.6 Internal Clock Frequencies
MIN
NOM
MAX
UNIT
f(SYSCLK)
Frequency, device (system) clock
2
100
MHz
tc(SYSCLK)
Period, device (system) clock
10
500
ns
f(INTCLK)
Frequency, system PLL going into VCO (after
REFDIV)
10
20
MHz
f(VCOCLK)
Frequency, system PLL VCO (before ODIV)
220
600
MHz
f(PLLRAWCLK)
Frequency, system PLL output (before SYSCLK
divider)
6
200
MHz
f(PLL)
Frequency, PLLSYSCLK
2
f(PLL_LIMP)
Frequency, PLL Limp Frequency (1)
f(LSP)
Frequency, LSPCLK
tc(LSPCLK)
Period, LSPCLK
f(OSCCLK)
Frequency, OSCCLK (INTOSC1 or INTOSC2 or
XTAL or X1)
f(EPWM)
Frequency, EPWMCLK
f(HRPWM)
Frequency, HRPWMCLK
(1)
66
100
45/(ODIV+1)
MHz
MHz
2
100
MHz
10
500
ns
See respective clock
60
MHz
100
MHz
100
MHz
PLL output frequency when OSCCLK is dead (Loss of OSCCLK causes PLL to Limp).
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7.11.3.3 Input Clocks and PLLs
In addition to the internal 0-pin oscillators, three types of external clock sources are supported:
• A single-ended 3.3-V external clock. The clock signal should be connected to X1, as shown in Figure 7-12,
with the XTALCR.SE bit set to 1.
• An external crystal. The crystal should be connected across X1 and X2 with its load capacitors connected to
VSS as shown in Figure 7-13.
• An external resonator. The resonator should be connected across X1 and X2 with its ground connected to
VSS as shown in Figure 7-14.
Microcontroller
VSS
Microcontroller
GPIO19
GPIO18*
X1
X2
GPIO19
GPIO18
X1
X2
* Available as a
GPIO when X1 is
used as a clock
+3.3 V
VDD
VSS
Out
3.3-V Oscillator
Gnd
Figure 7-13. External Crystal
Figure 7-12. Single-ended 3.3-V External Clock
Microcontroller
VSS
GPIO19
GPIO18
X1
X2
Figure 7-14. External Resonator
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7.11.3.4 Crystal Oscillator
When using a quartz crystal, it may be necessary to include a damping resistor (RD) in the crystal circuit to
prevent overdriving the crystal (drive level can be found in the crystal data sheet). In higher-frequency
applications (10 MHz or greater), RD is generally not required. If a damping resistor is required, RD should be as
small as possible because the size of the resistance affects start-up time (smaller RD = faster start-up time). TI
recommends that the crystal manufacturer characterize the crystal with the application board. Section 7.11.3.4.1
lists the crystal oscillator parameters. Table 7-3 lists the crystal equivalent series resistance (ESR) requirements.
Section 7.11.3.4.2 lists the crystal oscillator electrical characteristics.
7.11.3.4.1 Crystal Oscillator Parameters
CL1, CL2
Load capacitance
C0
Crystal shunt capacitance
MIN
MAX
12
24
UNIT
pF
7
pF
For Table 7-3:
1. Crystal shunt capacitance (C0) should be less than or equal to 7 pF.
2. ESR = Negative Resistance/3
Table 7-3. Crystal Equivalent Series Resistance (ESR) Requirements
CRYSTAL FREQUENCY (MHz)
MAXIMUM ESR (Ω)
(CL1 = CL2 = 12 pF)
MAXIMUM ESR (Ω)
(CL1 = CL2 = 24 pF)
10
55
110
12
50
95
14
50
90
16
45
75
18
45
65
20
45
50
7.11.3.4.2 Crystal Oscillator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
f = 20 MHz
ESR MAX = 50 Ω
CL1 = CL2 = 24 pF
C0 = 7 pF
Start-up time(1)
MIN
TYP
MAX
2
Crystal drive level (DL)
(1)
68
UNIT
ms
1
mW
Start-up time is dependent on the crystal and tank circuit components. TI recommends that the crystal vendor characterize the
application with the chosen crystal.
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7.11.3.5 Internal Oscillators
To reduce production board costs and application development time, all F28002x devices contain two
independent internal oscillators, referred to as INTOSC1 and INTOSC2. By default, INTOSC2 is set as the
source for the system reference clock (OSCCLK) and INTOSC1 is set as the backup clock source.
Applications requiring tighter clock tolerance can use the SCI baud tuning example available in C2000Ware
(C2000Ware_3_03_00_00\driverlib\f28002x\examples\sci\baud_tune_via_uart) to enable baud matching better
than 1% accuracy.
Section 7.11.3.5.1 provides the electrical characteristics of the internal oscillators.
7.11.3.5.1 INTOSC Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
fINTOSC
Frequency, INTOSC1 and
INTOSC2
fINTOSC-STABILITY Frequency stability
tINT0SC-ST
Start-up and settling time
Copyright © 2020 Texas Instruments Incorporated
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
-40°C to 125°C
9.8 (–2.0%)
10
10.15 (1.5%)
MHz
-30°C to 90°C
9.85 (–1.5%)
10
10.15 (1.5%)
MHz
30°C, Nominal
VDDIO
±0.1
%
20
µs
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7.11.4 Flash Parameters
Table 7-4 lists the minimum required Flash wait states with different clock sources and frequencies. Wait state is
the value set in register FRDCNTL[RWAIT].
Table 7-4. Minimum Required Flash Wait States with Different Clock Sources and Frequencies
EXTERNAL OSCILLATOR OR CRYSTAL
CPUCLK (MHz)
NORMAL OPERATION
97 < CPUCLK ≤ 100
80 < CPUCLK ≤ 97
77 < CPUCLK ≤ 80
60 < CPUCLK ≤ 77
58 < CPUCLK ≤ 60
40 < CPUCLK ≤ 58
38 < CPUCLK ≤ 40
20 < CPUCLK ≤ 38
19 < CPUCLK ≤ 20
CPUCLK ≤ 19
(1)
INTOSC1 OR INTOSC2
BANK OR PUMP
SLEEP(1)
BANK OR PUMP
SLEEP(1)
NORMAL OPERATION
4
4
3
3
2
2
1
1
0
0
5
4
4
3
3
2
2
1
1
0
Flash SLEEP operations require an extra wait state when using INTOSC as the clock source for the frequency ranges indicated. Any
wait state FRDCNTL[RWAIT] change must be made before beginning a SLEEP mode operation. This setting impacts both flash banks.
The F28002x devices have an improved 128-bit prefetch buffer that provides high flash code execution efficiency
across wait states. Figure 7-15 and Figure 7-16 illustrate typical efficiency across wait-state settings compared to
previous-generation devices with a 64-bit prefetch buffer. Wait-state execution efficiency with a prefetch buffer
will depend on how many branches are present in application software. Two examples of linear code and if-thenelse code are provided.
100%
100%
95%
90%
Efficiency (%)
Efficiency (%)
90%
80%
70%
60%
Flash with 64-Bit Prefetch
Flash with 128-Bit Prefetch
50%
80%
75%
Flash with 64-Bit Prefetch
Flash with 128-Bit Prefetch
70%
65%
40%
60%
30%
55%
0
1
2
3
Wait State
4
5
D005
Figure 7-15. Application Code With Heavy 32-Bit
Floating-Point Math Instructions
70
85%
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1
2
3
Wait State
4
5
D006
Figure 7-16. Application Code With 16-Bit If-Else
Instructions
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Table 7-5 lists the Flash parameters.
Table 7-5. Flash Parameters
PARAMETER
MIN
128 data bits + 16 ECC bits
Program Time(1)
8KB sector
TYP
MAX
UNIT
150
300
µs
50
100
ms
EraseTime(2) (3) at < 25 cycles
8KB sector
15
100
ms
EraseTime(2) (3) at 1000 cycles
8KB sector
25
350
ms
EraseTime(2) (3)
8KB sector
30
600
ms
8KB sector
120
4000
ms
20000
cycles
100000
cycles
at 2000 cycles
EraseTime(2) (3) at 20K cycles
Nwec Write/Erase Cycles per sector
Nwec Write/Erase Cycles for entire Flash (combined all
sectors)
tretention Data retention duration at TJ = 85oC
(1)
(2)
(3)
20
years
Program time is at the maximum device frequency. Program time includes overhead of the flash state machine but does not include
the time to transfer the following into RAM:
• Code that uses flash API to program the flash
• Flash API itself
• Flash data to be programmed
In other words, the time indicated in this table is applicable after all the required code/data is available in the device RAM, ready for
programming. The transfer time will significantly vary depending on the speed of the JTAG debug probe used.
Program time calculation is based on programming 144 bits at a time at the specified operating frequency. Program time includes
Program verify by the CPU. The program time does not degrade with write/erase (W/E) cycling, but the erase time does.
Erase time includes Erase verify by the CPU and does not involve any data transfer.
Erase time includes Erase verify by the CPU.
The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
Note
The Main Array flash programming must be aligned to 64-bit address boundaries and each 64-bit
word may only be programmed once per write/erase cycle.
The DCSM OTP programming must be aligned to 128-bit address boundaries and each 128-bit word
may only be programmed once. The exceptions are:
1. The DCSM Zx-LINKPOINTER1 and Zx-LINKPOINTER2 values in the DCSM OTP should be
programmed together, and may be programmed 1 bit at a time as required by the DCSM operation.
2. The DCSM Zx-LINKPOINTER3 values in the DCSM OTP may be programmed 1 bit at a time on a
64-bit boundary to separate it from Zx-PSWDLOCK, which must only be programmed once.
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7.11.5 Emulation/JTAG
The JTAG (IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture) port has
four dedicated pins: TMS, TDI, TDO, and TCK. The cJTAG (IEEE Standard 1149.7-2009 for Reduced-Pin and
Enhanced-Functionality Test Access Port and Boundary-Scan Architecture) port is a compact JTAG interface
requiring only two pins (TMS and TCK), which allows other device functionality to be muxed to the traditional
GPIO35 (TDI) and GPIO37 (TDO) pins.
Typically, no buffers are needed on the JTAG signals when the distance between the MCU target and the JTAG
header is smaller than 6 inches (15.24 cm), and no other devices are present on the JTAG chain. Otherwise,
each signal should be buffered. Additionally, for most JTAG debug probe operations at 10 MHz, no series
resistors are needed on the JTAG signals. However, if high emulation speeds are expected (35 MHz or so), 22-Ω
resistors should be placed in series on each JTAG signal.
The PD (Power Detect) terminal of the JTAG debug probe header should be connected to the board's 3.3-V
supply. Header GND terminals should be connected to board ground. TDIS (Cable Disconnect Sense) should
also be connected to board ground. The JTAG clock should be looped from the header TCK output terminal back
to the RTCK input terminal of the header (to sense clock continuity by the JTAG debug probe). This MCU does
not support the EMU0 and EMU1 signals that are present on 14-pin and 20-pin emulation headers. These
signals should always be pulled up at the emulation header through a pair of board pullup resistors ranging from
2.2 kΩ to 4.7 kΩ (depending on the drive strength of the debugger ports). Typically, a 2.2-kΩ value is used.
Header terminal RESET is an open-drain output from the JTAG debug probe header that enables board
components to be reset through JTAG debug probe commands (available only through the 20-pin header).
Figure 7-17 shows how the 14-pin JTAG header connects to the MCU’s JTAG port signals. Figure 7-18 shows
how to connect to the 20-pin JTAG header. The 20-pin JTAG header terminals EMU2, EMU3, and EMU4 are not
used and should be grounded.
For more information about hardware breakpoints and watchpoints, see Hardware Breakpoints and Watchpoints
for C28x in CCS.
For more information about JTAG emulation, see the XDS Target Connection Guide.
Note
JTAG Test Data Input (TDI) is the default mux selection for the pin. The internal pullup is disabled by
default. If this pin is used as JTAG TDI, the internal pullup should be enabled or an external pullup
added on the board to avoid a floating input. In the cJTAG option, this pin can be used as GPIO.
JTAG Test Data Output (TDO) is the default mux selection for the pin. The internal pullup is disabled
by default. The TDO function will be in a tri-state condition when there is no JTAG activity, leaving this
pin floating. The internal pullup should be enabled or an external pullup added on the board to avoid a
floating GPIO input. In the cJTAG option, this pin can be used as GPIO.
72
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Distance between the header and the target
should be less than 6 inches (15.24 cm).
3.3 V
4.7 kΩ
1
TMS
TMS
TRST
TDI
TDIS
PD
KEY
2
3.3 V
10 kΩ
3
(A)
TDI
MCU
3.3 V
100 Ω
3.3 V
5
4
GND
6
10 kΩ
(A)
TDO
7
TDO
GND
9
RTCK
GND 10
TCK
GND 12
11
TCK
4.7 kΩ
3.3 V
8
4.7 kΩ
13
EMU0
EMU1
14
3.3 V
A. TDI and TDO connections are not required for cJTAG option and these pins can be used as GPIOs instead.
Figure 7-17. Connecting to the 14-Pin JTAG Header
Distance between the header and the target
should be less than 6 inches (15.24 cm).
3.3 V
4.7 kΩ
1
TMS
3.3 V
10 kΩ
3
(A)
MCU
TDI
3.3 V
100 Ω
3.3V
10 kΩ
5
7
(A)
TDO
9
11
TCK
4.7 kΩ
3.3 V
13
15
Open
Drain
17
19
A low pulse from the JTAG debug probe
can be tied with other reset sources
to reset the board.
GND
TMS
TRST
TDI
TDIS
PD
KEY
TDO
GND
RTCK
GND
TCK
GND
EMU0
EMU1
RESET
GND
EMU2
EMU3
EMU4
GND
2
4
GND
6
8
10
12
4.7 kΩ
14
3.3 V
16
18
20
GND
A. TDI and TDO connections are not required for cJTAG option and these pins can be used as GPIOs instead.
Figure 7-18. Connecting to the 20-Pin JTAG Header
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7.11.5.1 JTAG Electrical Data and Timing
Section 7.11.5.1.1 lists the JTAG timing requirements. Section 7.11.5.1.2 lists the JTAG switching characteristics.
Figure 7-19 shows the JTAG timing.
7.11.5.1.1 JTAG Timing Requirements
NO.
MIN
MAX
UNIT
1
tc(TCK)
Cycle time, TCK
66.66
ns
1a
tw(TCKH)
Pulse duration, TCK high (40% of tc)
26.66
ns
26.66
ns
1b
3
4
tw(TCKL)
Pulse duration, TCK low (40% of tc)
tsu(TDI-TCKH)
Input setup time, TDI valid to TCK high
13
tsu(TMS-TCKH)
Input setup time, TMS valid to TCK high
13
th(TCKH-TDI)
Input hold time, TDI valid from TCK high
7
th(TCKH-TMS)
Input hold time, TMS valid from TCK high
7
ns
ns
7.11.5.1.2 JTAG Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
2
PARAMETER
td(TCKL-TDO)
Delay time, TCK low to TDO valid
MIN
MAX
6
25
UNIT
ns
7.11.5.1.3 JTAG Timing Diagram
1
1a
1b
TCK
2
TDO
3
4
TDI/TMS
Figure 7-19. JTAG Timing
74
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7.11.5.2 cJTAG Electrical Data and Timing
Section 7.11.5.2.1 lists the cJTAG timing requirements. Section 7.11.5.2.2 lists the cJTAG switching
characteristics. Figure 7-20 shows the cJTAG timing.
7.11.5.2.1 cJTAG Timing Requirements
NO.
MIN
MAX
UNIT
1
tc(TCK)
Cycle time, TCK
100
ns
1a
tw(TCKH)
Pulse duration, TCK high (40% of tc)
40
ns
1b
3
4
tw(TCKL)
Pulse duration, TCK low (40% of tc)
40
ns
tsu(TMS-TCKH)
Input setup time, TMS valid to TCK high
15
ns
tsu(TMS-TCKL)
Input setup time, TMS valid to TCK low
15
ns
th(TCKH-TMS)
Input hold time, TMS valid from TCK high
2
ns
th(TCKL-TMS)
Input hold time, TMS valid from TCK low
2
ns
7.11.5.2.2 cJTAG Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
2
td(TCKL-TMS)
Delay time, TCK low to TMS valid
5
tdis(TCKH-TMS)
Delay time, TCK high to TMS disable
MIN
MAX
6
UNIT
20
ns
20
ns
7.11.5.2.3 cJTAG Timing Diagram
1
1a
TCK
TMS
1b
3
4
TMS Input
3
4
TMS Input
2
5
TMS Output
Figure 7-20. cJTAG Timing
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7.11.6 GPIO Electrical Data and Timing
The peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. On reset, GPIO pins
are configured as inputs. For specific inputs, the user can also select the number of input qualification cycles to
filter unwanted noise glitches.
The GPIO module contains an Output X-BAR which allows an assortment of internal signals to be routed to a
GPIO in the GPIO mux positions denoted as OUTPUTXBARx. The GPIO module also contains an Input X-BAR
which is used to route signals from any GPIO input to different IP blocks such as the ADCs, eCAPs, ePWMs,
and external interrupts. For more details, see the X-BAR chapter in the TMS320F28002x Real-Time
Microcontrollers Technical Reference Manual.
7.11.6.1 GPIO – Output Timing
Section 7.11.6.1.1 lists the general-purpose output switching characteristics. Figure 7-21 shows the generalpurpose output timing.
7.11.6.1.1 General-Purpose Output Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
tr(GPIO)
Rise time, GPIO switching low to high
All GPIOs
8(1)
tf(GPIO)
Fall time, GPIO switching high to low
All GPIOs
8(1)
ns
fGPIO
Toggling frequency, all GPIOs
25
MHz
(1)
ns
Rise time and fall time vary with load. These values assume a 40-pF load.
GPIO
tr(GPIO)
tf(GPIO)
Figure 7-21. General-Purpose Output Timing
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7.11.6.2 GPIO – Input Timing
Section 7.11.6.2.1 lists the general-purpose input timing requirements. Figure 7-22 shows the sampling mode.
7.11.6.2.1 General-Purpose Input Timing Requirements
MIN
tw(SP)
Sampling period
tw(IQSW)
Input qualifier sampling window
tw(GPI) (2)
Pulse duration, GPIO low/high
(1)
(2)
QUALPRD = 0
1tc(SYSCLK)
QUALPRD ≠ 0
2tc(SYSCLK) * QUALPRD
MAX
UNIT
cycles
tw(SP) * (n(1) – 1)
Synchronous mode
cycles
2tc(SYSCLK)
With input qualifier
cycles
tw(IQSW) + tw(SP) + 1tc(SYSCLK)
"n" represents the number of qualification samples as defined by GPxQSELn register.
For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
7.11.6.2.2 Sampling Mode
(A)
GPIO Signal
GPxQSELn = 1,0 (6 samples)
1
1
0
0
0
0
0
0
0
1
tw(SP)
0
0
0
1
1
1
1
Sampling Window
1
1
1
1
Sampling Period determined
by GPxCTRL[QUALPRD]
tw(IQSW)
1
(SYSCLK cycle * 2 * QUALPRD) * 5
(B)
(C)
SYSCLK
QUALPRD = 1
(SYSCLK/2)
(D)
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to
0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLK cycle. For any other value "n", the qualification sampling period in 2n
SYSCLK cycles (that is, at every 2n SYSCLK cycles, the GPIO pin will be sampled).
B. The qualification period selected through the GPxCTRL register applies to groups of eight GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLK cycles or greater. In other words,
the inputs should be stable for (5 × QUALPRD × 2) SYSCLK cycles. This would ensure 5 sampling periods for detection to occur.
Because external signals are driven asynchronously, an 13-SYSCLK-wide pulse ensures reliable recognition.
Figure 7-22. Sampling Mode
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7.11.6.3 Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLK.
Sampling frequency = SYSCLK/(2 × QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLK, if QUALPRD = 0
Sampling period = SYSCLK cycle × 2 × QUALPRD, if QUALPRD ≠ 0
In the previous equations, SYSCLK cycle indicates the time period of SYSCLK.
Sampling period = SYSCLK cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the
signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 5, if QUALPRD = 0
Figure 7-23 shows the general-purpose input timing.
SYSCLK
GPIOxn
tw(GPI)
Figure 7-23. General-Purpose Input Timing
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7.11.7 Interrupts
The C28x CPU has fourteen peripheral interrupt lines. Two of them (INT13 and INT14) are connected directly to
CPU timers 1 and 2, respectively. The remaining twelve are connected to peripheral interrupt signals through the
enhanced Peripheral Interrupt Expansion (ePIE) module. The ePIE multiplexes up to sixteen peripheral
interrupts into each CPU interrupt line. It also expands the vector table to allow each interrupt to have its own
ISR. This allows the CPU to support a large number of peripherals.
An interrupt path is divided into three stages—the peripheral, the ePIE, and the CPU. Each stage has its own
enable and flag registers. This system allows the CPU to handle one interrupt while others are pending,
implement and prioritize nested interrupts in software, and disable interrupts during certain critical tasks.
Figure 7-24 shows the interrupt architecture for this device.
TIMER0
LPM Logic
WD
LPMINT
WDINT
TINT0
WAKEINT
NMI module
ERAD
GPIO0
to
GPIOx
INPUTXBAR4
INPUTXBAR5
Input
INPUTXBAR6
X-BAR
INPUTXBAR13
INPUTXBAR14
XINT1 Control
XINT2 Control
XINT3 Control
XINT4 Control
XINT5 Control
Peripherals
See ePIE Table
NMI
RTOSINT
CPU
ePIE
INT1
to
INT12
TIMER1
INT13
TIMER2
INT14
Figure 7-24. Device Interrupt Architecture
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7.11.7.1 External Interrupt (XINT) Electrical Data and Timing
Section 7.11.7.1.1 lists the external interrupt timing requirements. Section 7.11.7.1.2 lists the external interrupt
switching characteristics. Figure 7-25 shows the external interrupt timing. For an explanation of the input qualifier
parameters, see Section 7.11.6.2.1.
7.11.7.1.1 External Interrupt Timing Requirements
MIN
tw(INT)
Pulse duration, INT input low/high
Synchronous
2tc(SYSCLK)
With qualifier
tw(IQSW) + tw(SP) + 1tc(SYSCLK)
MAX
UNIT
cycles
7.11.7.1.2 External Interrupt Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
td(INT) Delay time, INT low/high to interrupt-vector fetch(1)
(1)
MIN
MAX
UNIT
tw(IQSW) + 14tc(SYSCLK)
tw(IQSW) + tw(SP) + 14tc(SYSCLK)
cycles
This assumes that the ISR is in a single-cycle memory.
7.11.7.1.3 External Interrupt Timing
tw(INT)
XINT1, XINT2, XINT3,
XINT4, XINT5
td(INT)
Address bus
(internal)
Interrupt Vector
Figure 7-25. External Interrupt Timing
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7.11.8 Low-Power Modes
This device has HALT, IDLE and STANDBY as clock-gating low-power modes.
Further details, as well as the entry and exit procedure, for all of the low-power modes can be found in the Low
Power Modes section of the TMS320F28002x Real-Time Microcontrollers Technical Reference Manual.
7.11.8.1 Clock-Gating Low-Power Modes
IDLE and HALT modes on this device are similar to those on other C28x devices. Table 7-6 describes the effect
on the system when any of the clock-gating low-power modes are entered.
Table 7-6. Effect of Clock-Gating Low-Power Modes on the Device
MODULES/
CLOCK DOMAIN
IDLE
STANDBY
HALT
SYSCLK
Active
Gated
Gated
CPUCLK
Gated
Gated
Gated
Clock to modules connected
to PERx.SYSCLK
Active
Gated
Gated
WDCLK
Active
Active
Gated if CLKSRCCTL1.WDHALTI = 0
PLL
Powered
Powered
Software must power down PLL before entering HALT.
INTOSC1
Powered
Powered
Powered down if CLKSRCCTL1.WDHALTI = 0
INTOSC2
Powered
Powered
Powered down if CLKSRCCTL1.WDHALTI = 0
Flash(1)
Powered
Powered
Powered
XTAL(2)
Powered
Powered
Powered
(1)
(2)
The Flash module is not powered down by hardware in any LPM. It may be powered down using software if required by the
application. For more information, see the Flash and OTP Memory section of the System Control chapter in the TMS320F28002x RealTime Microcontrollers Technical Reference Manual.
The XTAL is not powered down by hardware in any LPM. It may be powered down by software setting the XTALCR.OSCOFF bit to 1.
This can be done at any time during the application if the XTAL is not required.
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7.11.8.2 Low-Power Mode Wake-up Timing
Section 7.11.8.2.1 lists the IDLE mode timing requirements, Section 7.11.8.2.2 lists the IDLE mode switching
characteristics, and Figure 7-26 shows the timing diagram for IDLE mode. For an explanation of the input
qualifier parameters, see Section 7.11.6.2.1.
7.11.8.2.1 IDLE Mode Timing Requirements
MIN
tw(WAKE)
Pulse duration, external wake-up signal
Without input qualifier
With input qualifier
MAX
2tc(SYSCLK)
UNIT
cycles
2tc(SYSCLK) + tw(IQSW)
7.11.8.2.2 IDLE Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
From Flash (active
state)
td(WAKE-IDLE)
Delay time, external wake signal to
program execution resume(1)
From Flash (sleep
state)
From RAM
(1)
(2)
Without input qualifier
With input qualifier
MIN
MAX UNIT
40tc(SYSCLK) cycles
40tc(SYSCLK) + tw(WAKE) cycles
Without input qualifier
6700tc(SYSCLK) (2) cycles
6700tc(SYSCLK) (2) +
cycles
tw(WAKE)
With input qualifier
Without input qualifier
With input qualifier
25tc(SYSCLK) cycles
25tc(SYSCLK) + tw(WAKE) cycles
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and FPAC1[PSLEEP] is 0x860.
7.11.8.2.3 IDLE Entry and Exit Timing Diagram
td(WAKE-IDLE)
Address/Data
(internal)
XCLKOUT
tw(WAKE)
WAKE
(A)
A. WAKE can be any enabled interrupt, WDINT or XRSn. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum)
is needed before the wake-up signal could be asserted.
Figure 7-26. IDLE Entry and Exit Timing Diagram
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Section 7.11.8.2.4 lists the STANDBY mode timing requirements, Section 7.11.8.2.5 lists the STANDBY mode
switching characteristics, and Figure 7-27 shows the timing diagram for STANDBY mode.
7.11.8.2.4 STANDBY Mode Timing Requirements
MIN
tw(WAKE-INT)
(1)
Pulse duration, external
wake-up signal
QUALSTDBY = 0 | 2tc(OSCCLK)
MAX
UNIT
3tc(OSCCLK)
QUALSTDBY > 0 |
(2 + QUALSTDBY)tc(OSCCLK) (1)
cycles
(2 + QUALSTDBY) * tc(OSCCLK)
QUALSTDBY is a 6-bit field in the LPMCR register.
7.11.8.2.5 STANDBY Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
td(IDLE-XCOS)
TEST CONDITIONS
(2)
UNIT
16tc(INTOSC1) cycles
Delay time, external wake signal to program
execution resume(1)
td(WAKE-STBY)
(1)
MAX
Delay time, IDLE instruction executed to
XCLKOUT stop
td(WAKE-STBY)
td(WAKE-STBY)
MIN
Wakeup from flash
(Flash module in
active state)
175tc(SYSCLK) + tw(WAKE-INT) cycles
Wakeup from flash
(Flash module in
sleep state)
6700tc(SYSCLK) (2) + tw(WAKE-INT) cycles
Wakeup from RAM
3tc(OSC) + 15tc(SYSCLK) + tw(WAKE-INT) cycles
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and FPAC1[PSLEEP] is 0x860.
7.11.8.2.6 STANDBY Entry and Exit Timing Diagram
(C)
(A)
(B)
Device
Status
(F)
(D)(E)
STANDBY
STANDBY
(G)
Normal Execution
Flushing Pipeline
Wake-up
Signal
tw(WAKE-INT)
td(WAKE-STBY)
OSCCLK
XCLKOUT
td(IDLE-XCOS)
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The LPM block responds to the STANDBY signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off.
This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode. After
the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.
D. The external wake-up signal is driven active.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of the device will not be deterministic and the device
may not exit low-power mode for subsequent wakeup pulses.
F. After a latency period, the STANDBY mode is exited.
G. Normal execution resumes. The device will respond to the interrupt (if enabled).
Figure 7-27. STANDBY Entry and Exit Timing Diagram
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Section 7.11.8.2.7 lists the HALT mode timing requirements, Section 7.11.8.2.8 lists the HALT mode switching
characteristics, and Figure 7-28 shows the timing diagram for HALT mode.
7.11.8.2.7 HALT Mode Timing Requirements
MIN
signal(1)
tw(WAKE-GPIO)
Pulse duration, GPIO wake-up
tw(WAKE-XRS)
Pulse duration, XRS wake-up signal(1)
(1)
MAX
UNIT
toscst + 2tc(OSCCLK)
cycles
toscst + 8tc(OSCCLK)
cycles
For applications using X1/X2 for OSCCLK, the user must characterize their specific oscillator start-up time as it is dependent on circuit/
layout external to the device. See Crystal Oscillator Electrical Characteristics table for more information. For applications using
INTOSC1 or INTOSC2 for OSCCLK, see Internal Oscillators section for toscst. Oscillator start-up time does not apply to applications
using a single-ended crystal on the X1 pin, as it is powered externally to the device.
7.11.8.2.8 HALT Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
td(IDLE-XCOS)
MAX
UNIT
16tc(INTOSC1)
cycles
Wakeup from Flash - Flash module in active state
75tc(OSCCLK)
cycles
Wakeup from Flash - Flash module in sleep state
17500tc(OSCCLK) (1)
Delay time, IDLE instruction executed to XCLKOUT
stop
MIN
Delay time, external wake signal end to CPU1 program
execution resume
td(WAKE-HALT)
Wakeup from RAM
(1)
84
75tc(OSCCLK)
This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and FPAC1[PSLEEP] is 0x860.
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7.11.8.2.9 HALT Entry and Exit Timing Diagram
(C)
(A)
(B)
Device
Status
(F)
(D)(E)
HALT
(G)
HALT
Flushing Pipeline
Normal
Execution
GPIOn
td(WAKE-HALT)
tw(WAKE-GPIO)
OSCCLK
Oscillator Start-up Time
XCLKOUT
td(IDLE-XCOS)
A. IDLE instruction is executed to put the device into HALT mode.
B. The LPM block responds to the HALT signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off. This
delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source,
the internal oscillator is shut down as well. The device is now in HALT mode and consumes very little power. It is possible to keep the
zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in HALT MODE. This is done by writing 1 to
CLKSRCCTL1.WDHALTI. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wakeup signal could be asserted.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up sequence
is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal
during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wake-up procedure, care should be
taken to maintain a low noise environment before entering and during HALT mode.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the device
may not exit low-power mode for subsequent wake-up pulses.
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after some latency. The HALT mode is now
exited.
G. Normal operation resumes.
H. The user must relock the PLL upon HALT wakeup to ensure a stable PLL lock.
Figure 7-28. HALT Entry and Exit Timing Diagram
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7.12 Analog Peripherals
The analog subsystem module is described in this section.
The analog modules on this device include the ADC, temperature sensor, and CMPSS.
The analog subsystem has the following features:
• Flexible voltage references
– The ADCs are referenced to VREFHI and VSSA pins
• VREFHI pin voltage can be driven in externally or can be generated by an internal bandgap voltage
reference
• The internal voltage reference range can be selected to be 0V to 3.3V or 0V to 2.5V
– The comparator DACs are referenced to VDDA and VSSA
• Alternately, these DACs can be referenced to the VDAC pin and VSSA
• Flexible pin usage
– Comparator subsystem inputs and digital inputs are multiplexed with ADC inputs
– Internal connection to VREFLO on all ADCs for offset self-calibration
Figure 7-29 shows the Analog Subsystem Block Diagram for the 80-pin PN and 64-pin PM LQFPs.
Figure 7-30 shows the Analog Subsystem Block Diagram for the 48-pin PT LQFP.
Table 7-7 lists the analog pins and internal connections. Table 7-8 lists descriptions of analog signals.Figure 7-31
shows the analog group connections.
Figure 7-29. Analog Subsystem Block Diagram (80-Pin PN and 64-Pin PM LQFPs)
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TMS320F280025, TMS320F280025-Q1
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Figure 7-30. Analog Subsystem Block Diagram (48-Pin PT LQFP)
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CMPSSx Input MUX
CMPxHPMX
CMPx_HP0
CMPx_HP1
CMPx_HP2
CMPx_HP3
CMPx_HP4
0
1
2
3
CMPx_HP
4
CMPxHNMX
0
CMPx_HN1
1
CMPx_LN0
0
CMPx_LN1
1
CMPx_HN
CMPxLNMX
To CMPSSx
CMPx_HN0
CMPx_LN
CMPxLPMX
CMPx_LP0
CMPx_LP1
CMPx_LP2
CMPx_LP3
CMPx_LP4
0
1
2
3
CMPx_LP
4
Gx_ADCA
Gx_ADCA
AIO
To ADCs
Gx_ADCC
Gx_ADCC
AIO
Figure 7-31. Analog Group Connections
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Analog Pins and Internal Connections
Table 7-7. Analog Pins and Internal Connections
Package Pin
Pin Name
ADC
80 QFP
64 QFP
48 QFN
VREFHI
20
16
12
VREFLO
21
17
13
Comparator Subsystem (MUX)
A
C
A13
C13
High
Positive
High
Negative
Analog Group 1
Low
Positive
Low
Negative
AIO Input
CMP1
A6
10
6
4(3)
A6
-
CMP1 (HPMXSEL=2)
CMP1 (LPMXSEL=2)
AIO228
A2/C9
13
9
6
A2
C9
CMP1 (HPMXSEL=0)
CMP1 (LPMXSEL=0)
AIO224
A15/C7
14
10
7
A15
C7
CMP1 (HPMXSEL=3)
CMP1 (HNMXSEL=0)
CMP1 (LPMXSEL=3)
CMP1 (LNMXSEL=0)
AIO233
A11/C0
16
12
8
A11
C0
CMP1 (HPMXSEL=1)
CMP1 (HNMXSEL=1)
CMP1 (LPMXSEL=1)
CMP1 (LNMXSEL=1)
AIO237
A1
18
14
10
A1
-
CMP1 (HPMXSEL=4)
CMP1 (LPMXSEL=4)
Analog Group 2
A10/C10
29
25
21
A10
C10
CMP2 (HPMXSEL=3)
CMP2 (HNMXSEL=0)
Analog Group 3
CMP2 (LPMXSEL=3)
CMP2 (LNMXSEL=0)
AIO230
CMP3 (LNMXSEL=0)
AIO242
CMP3 (LNMXSEL=1)
AIO244
CMP3
C6
11
7
4(3)
-
C6
CMP3 (HPMXSEL=0)
A3/C5/VDAC(1)
12
8
5
A3
C5
CMP3 (HPMXSEL=3)
A14/C4
15
11
-
A14
C4
CMP3 (HPMXSEL=4)
A5/C2
17
13
9
A5
C2
CMP3 (HPMXSEL=1)
A0/C15
19
15
11
A0
C15
CMP3 (HPMXSEL=2)
CMP3 (LPMXSEL=0)
CMP3 (HNMXSEL=0)
CMP3 (LPMXSEL=3)
CMP3 (HNMXSEL=1)
CMP3 (LPMXSEL=1)
AIO226
CMP3 (LPMXSEL=4)
AIO239
CMP3 (LPMXSEL=2)
Analog Group 4
A7/C3
AIO232
CMP2
AIO231
CMP4
23
19
15
A7
C3
CMP4 (HPMXSEL=1)
CMP4 (HNMXSEL=1)
Combined Analog Group 2/4
CMP4 (LPMXSEL=1)
CMP4 (LNMXSEL=1)
AIO245
CMP2 (LNMXSEL=1)
AIO238
CMP2/4
A12/C1
22
18
14
A12
C1
CMP2 (HPMXSEL=1)
CMP4 (HPMXSEL=2)
A8/C11
24
20
16
A8
C11
CMP2 (HPMXSEL=4)
CMP4 (HPMXSEL=4)
A4/C14
27
23
19
A4
C14
CMP2 (HPMXSEL=0)
CMP4 (HPMXSEL=3)
A9/C8
28
24
20
A9
C8
CMP2 (HPMXSEL=2)
CMP4 (HPMXSEL=0)
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CMP2 (HNMXSEL=1)
CMP2 (LPMXSEL=1)
CMP4 (LPMXSEL=2)
CMP2 (LPMXSEL=4)
CMP4 (LPMXSEL=4)
CMP4 (HNMXSEL=0)
CMP2 (LPMXSEL=0)
CMP4 (LPMXSEL=3)
AIO241
CMP4 (LNMXSEL=0)
CMP2 (LPMXSEL=2)
CMP4 (LPMXSEL=0)
AIO225
AIO227
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Table 7-7. Analog Pins and Internal Connections (continued)
Package Pin
Pin Name
ADC
Comparator Subsystem (MUX)
80 QFP
64 QFP
48 QFN
A
C
-
-
-
-
C12
High
Positive
High
Negative
Low
Positive
Low
Negative
AIO Input
Other Analog
TempSensor(2)
(1)
(2)
(3)
90
Optional external reference voltage for on-chip COMPDACs. There is an internal capacitance to VSSA on this pin whether used for ADC input or COMPDAC reference. If used as a
VDAC reference, place at least a 1-µF capacitor on this pin.
Internal connection only; does not come to a device pin.
A6 and C6 is double bonded as pin # 4.
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Analog Signal Descriptions
Table 7-8. Analog Signal Descriptions
SIGNAL NAME
DESCRIPTION
AIOx
Digital input on ADC pin
Ax
ADC A Input
Cx
ADC C Input
CMPx_HNy
Comparator subsystem high comparator negative input
CMPx_HPy
Comparator subsystem high comparator positive input
CMPx_LNy
Comparator subsystem low comparator negative input
CMPx_LPy
Comparator subsystem low comparator positive input
TempSensor
Internal temperature sensor
VDAC
Optional external reference voltage for on-chip COMPDACs. There is an internal capacitance to VSSA on this
pin whether used for ADC input or COMPDAC reference which cannot be disabled. If this pin is being used as
a reference for the on-chip COMPDACs, place at least a 1-uF capacitor on this pin.
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7.12.1 Analog-to-Digital Converter (ADC)
The ADC module described here is a successive approximation (SAR) style ADC with resolution of 12 bits. This
section refers to the analog circuits of the converter as the “core,” and includes the channel-select MUX, the
sample-and-hold (S/H) circuit, the successive approximation circuits, voltage reference circuits, and other analog
support circuits. The digital circuits of the converter are referred to as the “wrapper” and include logic for
programmable conversions, result registers, interfaces to analog circuits, interfaces to the peripheral buses,
post-processing circuits, and interfaces to other on-chip modules.
Each ADC module consists of a single sample-and-hold (S/H) circuit. The ADC module is designed to be
duplicated multiple times on the same chip, allowing simultaneous sampling or independent operation of multiple
ADCs. The ADC wrapper is start-of-conversion (SOC)-based (see the SOC Principle of Operation section of the
Analog-to-Digital Converter (ADC) chapter in the TMS320F28002x Real-Time Microcontrollers Technical
Reference Manual).
Each ADC has the following features:
• Resolution of 12 bits
• Ratiometric external reference set by VREFHI/VREFLO
• Selectable internal reference of 2.5 V or 3.3 V
• Single-ended signaling
• Input multiplexer with up to 16 channels
• 16 configurable SOCs
• 16 individually addressable result registers
• Multiple trigger sources
– S/W: software immediate start
– All ePWMs: ADCSOC A or B
– GPIO XINT2
– CPU Timers 0/1/2
– ADCINT1/2
• Four flexible PIE interrupts
• Burst-mode triggering option
• Four post-processing blocks, each with:
– Saturating offset calibration
– Error from setpoint calculation
– High, low, and zero-crossing compare, with interrupt and ePWM trip capability
– Trigger-to-sample delay capture
Note
Not every channel may be pinned out from all ADCs. See Section 6 to determine which channels are
available.
92
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The block diagram for the ADC core and ADC wrapper are shown in Figure 7-32.
Analog-to-Digital Wrapper Logic
Input Circuit
SOC Arbitration
& Control
ADCSOC
[15:0]
ACQPS
u
DOUT1
xV
2
IN-
SOCxSTART[15:0]
xV
1
IN+
EOCx[15:0]
[15:0]
CHSEL
ADCCOUNTER
TRIGGER[15:0]
SOC Delay
Timestamp
Converter
S/H Circuit
...
RESULT
Trigger
Timestamp
-
+
ADCRESULT
0±15 Regs
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[15:0]
...
ADCIN0
ADCIN1
ADCIN2
ADCIN3
ADCIN4
ADCIN5
ADCIN6
ADCIN7
ADCIN8
ADCIN9
ADCIN10
ADCIN11
ADCIN12
ADCIN13
ADCIN14
ADCIN15
TRIGSEL
SOCx (0-15)
CHSEL
Triggers
Analog-to-Digital Core
ADCPPBxOFFCAL
saturate
ADCPPBxOFFREF
+
ADCPPBxRESULT
ADCEVT
VREFHI
CONFIG
Bandgap
Reference Circuit
1.65-V Output
(3.3-V Range)
or
2.5-V Output
(2.5-V Range)
1
Event
Logic
ADCEVTINT
Post Processing Block (1-4)
0
Interrupt Block (1-4)
ADCINT1-4
VREFLO
Analog System Control
ANAREFSEL
ANAREFx2PSSEL
Reference Voltage Levels
Figure 7-32. ADC Module Block Diagram
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7.12.1.1 ADC Configurability
Some ADC configurations are individually controlled by the SOCs, while others are globally controlled per ADC
module. Table 7-9 summarizes the basic ADC options and their level of configurability.
Table 7-9. ADC Options and Configuration Levels
OPTIONS
CONFIGURABILITY
Clock
Per module(1)
Resolution
Not configurable (12-bit resolution only)
Signal mode
Not configurable (single-ended signal mode only)
Reference voltage source
Common for both ADC modules
Trigger source
Per SOC(1)
Converted channel
Per SOC
Acquisition window duration
Per SOC(1)
EOC location
Per module
Burst mode
Per module(1)
(1)
Writing these values differently to different ADC modules could cause the ADCs to operate
asynchronously. For guidance on when the ADCs are operating synchronously or asynchronously,
see the Ensuring Synchronous Operation section of the Analog-to-Digital Converter (ADC) chapter
in the TMS320F28002x Real-Time Microcontrollers Technical Reference Manual.
7.12.1.1.1 Signal Mode
The ADC supports single-ended signaling. The input voltage to the converter is sampled through a single pin
(ADCINx), referenced to VREFLO. Figure 7-33 shows the single-ended signaling mode.
Pin Voltage
VREFHI
VREFHI
ADCINx
ADCINx
ADC
VREFHI/2
VREFLO
VREFLO
(VSSA)
Digital Output
2n - 1
ADC Vin
0
Figure 7-33. Single-ended Signaling Mode
94
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7.12.1.2 ADC Electrical Data and Timing
Section 7.12.1.2.1 lists the ADC operating conditions. Section 7.12.1.2.2 lists the ADC electrical characteristics.
Note
The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input exceeds this
level, the VREF internal to the device may be disturbed, which can impact results for other ADC inputs
using the same VREF.
Note
The VREFHI pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the
VREFHI pin exceeds this level, a blocking circuit may activate, and the internal value of VREFHI may
float to 0 V internally, giving improper ADC conversion.
7.12.1.2.1 ADC Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ADCCLK (derived from PERx.SYSCLK)
MIN
100-MHz SYSCLK
Sample window duration (set by ACQPS and
PERx.SYSCLK)(1)
With 50 Ω or less Rs
75
VREFHI
External Reference
2.4
VREFHI - VREFLO
Internal Reference = 3.3 V Range
Internal Reference = 2.5 V Range
External Reference
(1)
(2)
UNIT
MHz
MSPS
ns
2.5 or 3.0
VDDA
1.65
Internal Reference = 2.5V Range
VREFLO
50
3.45
Internal Reference = 3.3V Range
Conversion range
MAX
5
Sample rate
VREFHI(2)
TYP
V
V
2.5
V
VSSA
VSSA
V
2.4
VDDA
V
0
3.3
V
0
2.5
V
VREFLO
VREFHI
V
The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.
In internal reference mode, the reference voltage is driven out of the VREFHI pin by the device. The user should not drive a voltage
into the pin in this mode.
7.12.1.2.2 ADC Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
General
ADCCLK Conversion Cycles
Power Up Time
100-MHz SYSCLK
10.1
11 ADCCLKs
External Reference mode
500
µs
Internal Reference mode
5000
µs
Internal Reference mode, when switching between
2.5-V range and 3.3-V range.
5000
µs
VREFHI input current(1)
130
µA
Internal Reference Capacitor
Value(2)
2.2
µF
External Reference Capacitor
Value(2)
2.2
µF
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7.12.1.2.2 ADC Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC Characteristics
Gain Error
Internal reference
–45
External reference
–5
±3
5
–5
±2
5
Offset Error
Channel-to-Channel Gain
Error(4)
Channel-to-Channel Offset
Error(4)
ADC-to-ADC Gain Error(5)
ADC-to-ADC Offset
Error(5)
Identical VREFHI and VREFLO for all ADCs
Identical VREFHI and VREFLO for all ADCs
DNL Error
INL Error
ADC-to-ADC Isolation
VREFHI = 2.5 V, synchronous ADCs
45
LSB
LSB
2
LSB
2
LSB
4
LSB
2
LSB
>–1
±0.5
1
–2
±1.0
2
LSB
1
LSBs
–1
LSB
AC Characteristics
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1
68.8
SNR(3)
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
INTOSC
60.1
THD(3)
VREFHI = 2.5 V, fin = 100 kHz
–80.6
dB
SFDR(3)
VREFHI = 2.5 V, fin = 100 kHz
79.2
dB
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1
68.5
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
INTOSC
60.0
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
X1, Single ADC
11.0
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
X1, synchronous ADCs
11.0
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
X1, asynchronous ADCs
Not
Supported
SINAD(3)
ENOB(3)
PSRR
(1)
(2)
(3)
(4)
(5)
96
VDD = 1.2-V DC + 100mV
DC up to Sine at 1 kHz
60
VDD = 1.2-V DC + 100 mV
DC up to Sine at 300 kHz
57
VDDA = 3.3-V DC + 200 mV
DC up to Sine at 1 kHz
60
VDDA = 3.3-V DC + 200 mV
Sine at 900 kHz
57
dB
dB
bits
dB
Load current on VREFHI increases when ADC input is greater than VDDA. This causes inaccurate conversions.
A ceramic capacitor with package size of 0805 or smaller is preferred. Up to ±20% tolerance is acceptable.
IO activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and
crosstalk.
Variation across all channels belonging to the same ADC module.
Worst case variation compared to other ADC modules.
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7.12.1.2.3 ADC Input Model
The ADC input characteristics are given by Table 7-10 and Figure 7-34.
Table 7-10. Input Model Parameters
DESCRIPTION
Cp
Ron
REFERENCE MODE
VALUE
Parasitic input capacitance
All
Sampling switch resistance
External Reference, 2.5-V Internal
Reference
500 Ω
3.3-V Internal Reference
860 Ω
Ch
Sampling capacitor
Rs
Nominal source impedance
See Table 7-11
External Reference, 2.5-V Internal
Reference
12.5 pF
3.3-V Internal Reference
7.5 pF
All
50 Ω
ADC
Rs
ADCINx
Switch
AC
Ron
Cp
Ch
VREFLO
Figure 7-34. Input Model
This input model should be used with actual signal source impedance to determine the acquisition window
duration. For more information, see the Choosing an Acquisition Window Duration section of the Analog-toDigital Converter (ADC) chapter in the TMS320F28002x Real-Time Microcontrollers Technical Reference
Manual.
Table 7-11 lists the parasitic capacitance on each channel.
Table 7-11. Per-Channel Parasitic Capacitance
ADC CHANNEL
(1)
Cp (pF)
COMPARATOR DISABLED
COMPARATOR ENABLED
ADCINA0/ADCINC15
3.3
15.8
ADCINA1
2.4
4.9
ADCINA2/ADCINC9
2.9
5.4
ADCINA3/ADCINC5(1)
71.4
73.9
ADCINA4/ADCINC14
4.5
7
ADCINA5/ADCINC2
2.7
5.2
ADCINA6
2.6
5.1
ADCINA7/ADCINC3
4.2
6.7
ADCINA8/ADCINC11
4.5
7
ADCINA9/ADCINC8
3.4
5.9
ADCINA10/ADCINC10
2.9
5.4
ADCINA11/ADCINC0
2.9
5.4
ADCINA12/ADCINC1
4.7
7.2
ADCINA14/ADCINC4
2.5
5
ADCINA15/ADCINC7
3.3
5.8
ADCINC6
2.9
5.4
Pin also used to supply reference voltage for COMPDAC and includes an internal decoupling
capacitor.
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7.12.1.2.4 ADC Timing Diagrams
Figure 7-35 shows the ADC conversion timings for two SOCs given the following assumptions:
• SOC0 and SOC1 are configured to use the same trigger.
• No other SOCs are converting or pending when the trigger occurs.
• The round-robin pointer is in a state that causes SOC0 to convert first.
• ADCINTSEL is configured to set an ADCINT flag upon end of conversion for SOC0 (whether this flag
propagates through to the CPU to cause an interrupt is determined by the configurations in the PIE module).
Table 7-12 lists the descriptions of the ADC timing parameters. Table 7-13 lists the ADC timings.
Sample n
Input on SOC0.CHSEL
Input on SOC1.CHSEL
Sample n+1
ADC S+H
SOC0
SOC1
SYSCLK
ADCCLK
ADCTRIG
ADCSOCFLG.SOC0
ADCSOCFLG.SOC1
ADCRESULT0
(old data)
ADCRESULT1
(old data)
Sample n
Sample n+1
ADCINTFLG.ADCINTx
tSH
tLAT
tEOC
tINT
Figure 7-35. ADC Timings
98
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Table 7-12. ADC Timing Parameters
PARAMETER
DESCRIPTION
The duration of the S+H window.
At the end of this window, the value on the S+H capacitor becomes the voltage to be converted into a digital
value. The duration is given by (ACQPS + 1) SYSCLK cycles. ACQPS can be configured individually for each
SOC, so tSH will not necessarily be the same for different SOCs.
tSH
Note: The value on the S+H capacitor will be captured approximately 5 ns before the end of the S+H window
regardless of device clock settings.
The time from the end of the S+H window until the ADC results latch in the ADCRESULTx register.
tLAT
If the ADCRESULTx register is read before this time, the previous conversion results will be returned.
The time from the end of the S+H window until the S+H window for the next ADC conversion can begin. The
subsequent sample can start before the conversion results are latched.
tEOC
The time from the end of the S+H window until an ADCINT flag is set (if configured).
If the INTPULSEPOS bit in the ADCCTL1 register is set, tINT will coincide with the conversion results being
latched into the result register.
If the INTPULSEPOS bit is 0, tINT will coincide with the end of the S+H window. If tINT triggers a read of the
ADC result register (directly through DMA or indirectly by triggering an ISR that reads the result), care must be
taken to ensure the read occurs after the results latch (otherwise, the previous results will be read).
tINT
If the INTPULSEPOS bit is 0, and the OFFSET field in the ADCINTCYCLE register is not 0, then there will be a
delay of OFFSET SYSCLK cycles before the ADCINT flag is set. This delay can be used to enter the ISR or
trigger the DMA at exactly the time the sample is ready.
Table 7-13. ADC Timings
ADCCLK PRESCALE
SYSCLK CYCLES
ADCCLK CYCLES
ADCCTL2 [PRESCALE]
RATIO
ADCCLK:SYSCLK
tEOC
0
1
11
13
1
11
11
2
2
21
23
1
21
10.5
4
3
31
34
1
31
10.3
6
4
41
44
1
41
10.3
8
5
51
55
1
51
10.2
10
6
61
65
1
61
10.2
12
7
71
76
1
71
10.1
14
8
81
86
1
81
10.1
(1)
(2)
tLAT
(1)
tINT(EARLY)
(2)
tINT(LATE)
tEOC
Refer to the "ADC: DMA Read of Stale Result" advisory in the TMS320F28002x Real-Time MCUs Silicon Errata.
By default, tINT occurs one SYSCLK cycle after the S+H window if INTPULSEPOS is 0. This can be changed by writing to the OFFSET
field in the ADCINTCYCLE register.
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7.12.2 Temperature Sensor
7.12.2.1 Temperature Sensor Electrical Data and Timing
The temperature sensor can be used to measure the device junction temperature. The temperature sensor is
sampled through an internal connection to the ADC and translated into a temperature through TI-provided
software. When sampling the temperature sensor, the ADC must meet the acquisition time in Section 7.12.2.1.1.
7.12.2.1.1 Temperature Sensor Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
Tacc
Temperature Accuracy
tstartup
Start-up time
(TSNSCTL[ENABLE] to
sampling temperature sensor)
tacq
ADC acquisition time
100
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TEST CONDITIONS
MIN
External reference
TYP
MAX
UNIT
±15
°C
500
µs
450
ns
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TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
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7.12.3 Comparator Subsystem (CMPSS)
Each CMPSS contains two comparators, two reference 12-bit DACs, two digital filters, and one ramp generator.
Comparators are denoted "H" or "L" within each module, where “H” and “L” represent high and low, respectively.
Each comparator generates a digital output that indicates whether the voltage on the positive input is greater
than the voltage on the negative input. The positive input of the comparator can be driven from an external pin or
by the PGA . The negative input can be driven by an external pin or by the programmable reference 12-bit DAC.
Each comparator output passes through a programmable digital filter that can remove spurious trip signals. An
unfiltered output is also available if filtering is not required. A ramp generator circuit is optionally available to
control the reference 12-bit DAC value for the high comparator in the subsystem. There are two outputs from
each CMPSS module. These two outputs pass through the digital filters and crossbar before connecting to the
ePWM modules or GPIO pin. Figure 7-36 shows the CMPSS connectivity.
CMP1_ HP
CMP1_HN
Comparator Subsystem 1
VDDA or VDAC
CTRIP1H
Digital
Filter
CTRIP1H
CTRIPOUT1H
Digital
Filter
CTRIP1L
CTRIPOUT1L
DAC12
CMP1_LN
CMP1_LP
CMP2_HP
CMP2_HN
Comparator Subsystem 2
Digital
Filter
VDDA or VDAC
DAC12
CTRIP2L
ePWM X- BAR
ePWMs
Output X- BAR
GPIO Mux
CTRIP2H
CTRIPOUT2H
DAC12
CMP2_LN
CMP2_LP
CTRIP1L
CTRIP2H
DAC12
CTRIP4H
Digital
Filter
CTRIP2L
CTRIPOUT2L
CTRIP4L
CTRIPOUT1H
CTRIPOUT1L
CTRIPOUT2H
CMP4_ HP
CMP4_ HN
Comparator Subsystem 4
VDDA or VDAC
Digital
Filter
CTRIP4H
CTRIPOUT4H
Digital
Filter
CTRIP4L
CTRIPOUT4L
CTRIPOUT2L
DAC12
DAC12
CMP4_LN
CMP4_ LP
CTRIPOUT4H
CTRIPOUT4L
Figure 7-36. CMPSS Connectivity
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7.12.3.1 CMPSS Electrical Data and Timing
Section 7.12.3.1.1 lists the comparator electrical characteristics. Figure 7-37 shows the CMPSS comparator
input referred offset. Figure 7-38 shows the CMPSS comparator hysteresis.
7.12.3.1.1 Comparator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TPU
TEST CONDITIONS
MIN
TYP
Power-up time
Comparator input (CMPINxx) range
Low common mode, inverting
input set to 50mV
Input referred offset error
Hysteresis(1)
MAX
UNIT
500
µs
0
VDDA
V
–20
20
1x
12
2x
24
3x
36
4x
48
Step response
21
mV
LSB
60
Response time (delay from CMPINx input
change to output on ePWM X-BAR or Output Ramp response (1.65V/µs)
X-BAR)
Ramp response (8.25mV/µs)
30
ns
PSRR
Power Supply Rejection Ratio Up to 250 kHz
46
dB
CMRR
Common Mode Rejection
Ratio
(1)
26
40
ns
dB
The CMPSS DAC is used as the reference to determine how much hysteresis to apply. Therefore, hysteresis will scale with the
CMPSS DAC reference voltage. Hysteresis is available for all comparator input source configurations.
CMPSS Comparator Input Referred Offset and Hysteresis
Note
The CMPSS inputs must be kept below VDDA + 0.3 V to ensure proper functional operation. If a
CMPSS input exceeds this level, an internal blocking circuit isolates the internal comparator from the
external pin until the external pin voltage returns below VDDA + 0.3 V. During this time, the internal
comparator input is floating and can decay below VDDA within approximately 0.5 µs. After this time,
the comparator could begin to output an incorrect result depending on the value of the other
comparator input.
Input Referred Offset
CTRIPx
Logic Level
CTRIPx = 1
CTRIPx = 0
0
CMPINxN or
DACxVAL
COMPINxP
Voltage
Figure 7-37. CMPSS Comparator Input Referred Offset
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Hysteresis
CTRIPx
Logic Level
CTRIPx = 1
CTRIPx = 0
0
CMPINxN or
DACxVAL
COMPINxP
Voltage
Figure 7-38. CMPSS Comparator Hysteresis
Section 7.12.3.1.2 lists the CMPSS DAC static electrical characteristics.
7.12.3.1.2 CMPSS DAC Static Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
CMPSS DAC output range
TEST CONDITIONS
TYP
MAX
UNIT
0
VDDA
External reference
0
VDAC(4)
–25
25
mV
Static offset error(1)
Static gain
MIN
Internal reference
error(1)
V
–2
2
% of FSR
Static DNL
Endpoint corrected
>–1
4
LSB
Static INL
Endpoint corrected
–16
16
LSB
Settling time
Settling to 1LSB after full-scale output
change
1
µs
Resolution
12
CMPSS DAC output disturbance(2)
Error induced by comparator trip or
CMPSS DAC code change within the
same CMPSS module
–100
CMPSS DAC disturbance time(2)
VDAC reference voltage
VDAC
(1)
(2)
(3)
(4)
load(3)
bits
100
LSB
200
ns
When VDAC is reference
2.4
2.5 or 3.0
VDDA
V
When VDAC is reference
6
8
10
kΩ
Includes comparator input referred errors.
Disturbance error may be present on the CMPSS DAC output for a certain amount of time after a comparator trip.
Per active CMPSS module.
The maximum output voltage is VDDA when VDAC > VDDA.
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7.12.3.1.3 CMPSS Illustrative Graphs
Figure 7-39 shows the CMPSS DAC static offset. Figure 7-40 shows the CMPSS DAC static gain. Figure 7-41
shows the CMPSS DAC static linearity.
Offset Error
Figure 7-39. CMPSS DAC Static Offset
Ideal Gain
Actual Gain
Actual Linear Range
Figure 7-40. CMPSS DAC Static Gain
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TMS320F280025, TMS320F280025-Q1
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Linearity Error
Figure 7-41. CMPSS DAC Static Linearity
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7.13 Control Peripherals
7.13.1 Enhanced Pulse Width Modulator (ePWM)
The ePWM peripheral is a key element in controlling many of the power electronic systems found in both
commercial and industrial equipment. The ePWM type-4 module is able to generate complex pulse width
waveforms with minimal CPU overhead by building the peripheral up from smaller modules with separate
resources that can operate together to form a system. Some of the highlights of the ePWM type-4 module
include complex waveform generation, dead-band generation, a flexible synchronization scheme, advanced tripzone functionality, and global register reload capabilities.
Figure 7-42 shows the ePWM module. Figure 7-43 shows the ePWM trip input connectivity.
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TMS320F280025, TMS320F280025-Q1
TMS320F280025C, TMS320F280025C-Q1, TMS320F280023, TMS320F280023-Q1
TMS320F280023C, TMS320F280021, TMS320F280021-Q1
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Time-Base (TB)
TBPRD Shadow (24)
ePWM
SYNC
Scheme
EXTSYNCIN
TBPRDHR (8)
TBPRD Active (24)
EXTSYNCOUT
CTR=PRD
EPWMxSYNCI
TBCTL[PHSEN]
TBCTL[SWFSYNC]
Counter
Up/Down
(16 bit)
DCAEVT1/sync(A)
DCBEVT1/sync(A)
CTR=ZERO
TBCTR
Active (16)
CTR=PRD
CTR=ZERO
CTR_Dir
TBPHSHR (8)
16
Phase
Control
Event
Trigger
And
Interrupt
(ET)
CTR=CMPD
CTR_Dir
Counter Compare (CC)
CTR=CMPA
EPWMxSOCA
CTR=PRD or ZERO
CTR=CMPA
CTR=CMPB
CTR=CMPC
8
TBPHS Active (24)
EPWMx_INT
Action
Qualifier
(AQ)
EPWMxSOCB
On-chip
ADC
ADCSOCOUTSELECT
DCAEVT1.soc(A)
DCBEVT1.soc(A)
Select and pulse stretch
for external ADC
CMPAHR (8)
16
HiRes PWM (HRPWM)
CMPAHR (8)
ADCSOCAO
ADCSOCBO
CMPA Active (24)
CMPA Shadow (24)
EPWMA
ePWMxA
Dead
Band
(DB)
CTR=CMPB
CMPBHR (8)
PWM
Chopper
(DB)
Trip
Zone
(TZ)
16
CMPB Active (16)
EPWMB
ePWMxB
CMPB Shadow (16)
CMPBHR (8)
TBCNT (16)
CTR=CMPC
CTR=ZERO
DCAEVT1.inter
CMPC[15-0]
DCBEVT1.inter
16
DCAEVT2.inter
CMPC Active (16)
DCBEVT2.inter
CMPC Shadow (16)
EPWMx_TZ_INT
TZ1 to TZ3
EMUSTOP
CLOCKFAIL
EQEPxERR
DCAEVT1.force(A)
DCBEVT1.force(A)
TBCNT (16)
CTR=CMPD
DCAEVT2.force(A)
DCBEVT2.force(A)
CMPD[15-0]
16
CMPD Active (16)
CMPD Shadow (16)
A. These events are generated by the ePWM digital compare (DC) submodule based on the levels of the TRIPIN inputs.
Figure 7-42. ePWM Submodules and Critical Internal Signal Interconnects
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GPIO0
Async/
Sync/
Sync+Filter
GPIOx
Input X-Bar
INPUT7
INPUT8
INPUT9
INPUT10
INPUT11
INPUT12
INPUT13
INPUT14
INPUT15
INPUT16
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
Other Sources
16:127
eCAPx
INPUT[1:16]
0:15
XINT1
XINT2
ADC
XINT3
Wrapper(s)
ePWM
eCAP
Sync Mux
XINT4
INPUT[1:14]
CMPSSx.TRIPH
CMPSSx.TRIPHORL
CMPSSx.TRIPL
ADCx.EVT1-4
ECAPx.OUT
PIE
XINT5
EXTSYNCIN1
EXTSYNCIN2
ePWM
X-Bar
TZ1
TZ2
TZ3
TRIP1
TRIP2
TRIP3
TRIP6
TRIP4
TRIP5
TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12
EPWMINT
TZINT
EPWMx.EPWMCLK
PCLKCR2[EPWMx]
TBCLKSYNC
PCLKCR0[TBCLKSYNC]
All
ePWM
Modules
ADCSOCAO Select
ADCSOCBO Select
EXTSYNCOUT
ADCSOCx
SOCA
Reserved
ECCERR
PIEVECTERROR
EQEPERR
CLKFAIL
EMUSTOP
TRIP13
TRIP14
TRIP15
TZ4
TZ5
TZ6
SOCB
EPWMSYNCPER
Blanking Window
ADC
Wrapper(s)
CMPSS
Figure 7-43. ePWM Trip Input Connectivity
108
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7.13.1.1 Control Peripherals Synchronization
The ePWM and eCAP synchronization scheme on the device provides flexibility in partitioning the ePWM and
eCAP modules and allows localized synchronization within the modules. Like the other peripherals, the
partitioning of the ePWM and eCAP modules needs to be done using the CPUSELx registers. Figure 7-44 shows
the synchronization scheme.
CTR=CMPD
CLR
One Shot
Latch
DCAEVT1.sync
DCBEVT1.sync
0
EPWMSYNCOUTEN
TBCTL2[OSHTSYNCMODE]
CTR=CMPC
TBCTL3[OSSFRCEN]
CTR=ZERO
CTR=CMPB
:ULWH ³1´ WR
TBCTL2[OSHTSYNC]
:ULWH ³1´ WR
GLDCTL2[OSHTLD]
TBCTL
SWFSYNC
Set
Q
1
SWEN
ZEROEN
0
CMPBEN
1
OR
CMPCEN
0
EPWMxSYNCOUT
1
0
CMPDEN
DCARVT1EN
TBCTL2[SELFCLRTRREM]
DCBEVT1EN
Clear
Register
Disable
0
EPWM1SYNCOUT
|
|
|
EPWMxSYNCOUT
EPWMxSYNCIN
ECAP1SYNCOUT
HRPCTL[PWMSYNCSELX]
CTR=CMPC UP
|
|
|
CTR=CMPC DOWN
ECAPySYNCOUT
CTR=CMPD UP
Other Sources
CTR=CMPD DOWN
HRPCTL[PWMSYNCSEL]
EPWMSYNCINSEL
EPWMxSYNCPER
CMPSS
DAC
CTR=PRD
CTR=ZERO
Note: SYNCO and SYNCOUT are used interchangeably
Figure 7-44. Synchronization Chain Architecture
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7.13.1.2 ePWM Electrical Data and Timing
Section 7.13.1.2.1 lists the ePWM timing requirements and Section 7.13.1.2.2 lists the ePWM switching
characteristics. For an explanation of the input qualifier parameters, see Section 7.11.6.2.1.
7.13.1.2.1 ePWM Timing Requirements
MIN
tw(SYNCIN)
Sync input pulse width
Asynchronous
2tc(EPWMCLK)
Synchronous
2tc(EPWMCLK)
With input qualifier
MAX
UNIT
cycles
1tc(EPWMCLK) + tw(IQSW)
7.13.1.2.2 ePWM Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
tw(PWM)
Pulse duration, PWMx output high/low
tw(SYNCOUT)
Sync output pulse width
td(TZ-PWM)
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
Delay time, trip input active to PWM Hi-Z
MIN
MAX
20
UNIT
ns
8tc(SYSCLK)
cycles
25
ns
7.13.1.2.3 Trip-Zone Input Timing
Section 7.13.1.2.3.1 lists the trip-zone input timing requirements. Figure 7-45 shows the PWM Hi-Z
characteristics. For an explanation of the input qualifier parameters, see Section 7.11.6.2.1.
7.13.1.2.3.1 Trip-Zone Input Timing Requirements
MIN
Asynchronous
tw(TZ)
Pulse duration, TZx input low
1tc(EPWMCLK)
Synchronous
With input qualifier
MAX
UNIT
cycles
2tc(EPWMCLK)
cycles
1tc(EPWMCLK) + tw(IQSW)
cycles
EPWMCLK
tw(TZ)
(A)
TZ
td(TZ-PWM)
(B)
PWM
A. TZ: TZ1, TZ2, TZ3, TRIP1–TRIP12
B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software.
Figure 7-45. PWM Hi-Z Characteristics
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7.13.1.3 External ADC Start-of-Conversion Electrical Data and Timing
Section 7.13.1.3.1 lists the external ADC start-of-conversion switching characteristics. Figure 7-46 shows the
ADCSOCAO or ADCSOCBO timing.
7.13.1.3.1 External ADC Start-of-Conversion Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
tw(ADCSOCL)
MIN
Pulse duration, ADCSOCxO low
MAX
32tc(SYSCLK)
UNIT
cycles
tw(ADCSOCL)
ADCSOCAO
or
ADCSOCBO
Figure 7-46. ADCSOCAO or ADCSOCBO Timing
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7.13.2 High-Resolution Pulse Width Modulator (HRPWM)
The HRPWM combines multiple delay lines in a single module and a simplified calibration system by using a
dedicated calibration delay line. For each ePWM module, there are two HR outputs:
• HR Duty and Deadband control on Channel A
• HR Duty and Deadband control on Channel B
The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be
achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
• Significantly extends the time resolution capabilities of conventionally derived digital PWM
• This capability can be used in both single edge (duty cycle and phase-shift control) as well as dual edge
control for frequency/period modulation.
• Finer time granularity control or edge positioning is controlled through extensions to the Compare A, B,
phase, period and deadband registers of the ePWM module.
Note
The minimum HRPWMCLK frequency allowed for HRPWM is 60 MHz.
7.13.2.1 HRPWM Electrical Data and Timing
Section 7.13.2.1.1 lists the high-resolution PWM switching characteristics.
7.13.2.1.1 High-Resolution PWM Characteristics
PARAMETER
Micro Edge Positioning (MEP) step size(1)
(1)
MIN
TYP
150
MAX UNIT
310
ps
The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher
temperature and lower voltage and decrease with lower temperature and higher voltage.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO functions in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLK period dynamically while the HRPWM is in operation.
7.13.3 Enhanced Capture and High-Resolution Capture (eCAP, HRCAP)
The eCAP module can be used in systems where accurate timing of external events is important. eCAP/HRCAP
on this device is Type-2.
Applications for eCAP include:
• Speed measurements of rotating machinery (for example, toothed sprockets sensed through Hall sensors)
• Elapsed time measurements between position sensor pulses
• Period and duty cycle measurements of pulse train signals
• Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors
The eCAP module includes the following features:
• 4-event time-stamp registers (each 32 bits)
• Edge-polarity selection for up to four sequenced time-stamp capture events
• Interrupt on either of the four events
• Single shot capture of up to four event timestamps
• Continuous mode capture of timestamps in a four-deep circular buffer
• Absolute time-stamp capture
• Difference (Delta) mode time-stamp capture
• All of the above resources dedicated to a single input pin
• When not used in capture mode, the eCAP module can be configured as a single-channel PWM output
(APWM).
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The capture functionality of the Type-1 eCAP is enhanced from the Type-0 eCAP with the following added
features:
•
•
•
•
•
Event filter reset bit
– Writing a 1 to ECCTL2[CTRFILTRESET] will clear the event filter, the modulo counter, and any pending
interrupts flags. Resetting the bit is useful for initialization and debug.
Modulo counter status bits
– The modulo counter (ECCTL2 [MODCTRSTS]) indicates which capture register will be loaded next. In the
Type-0 eCAP, it was not possible to know current state of modulo counter.
DMA trigger source
– eCAPxDMA is added as a DMA trigger. CEVT[1–4] can be configured as the source for eCAPxDMA.
Input multiplexer
– ECCTL0 [INPUTSEL] selects one of 128 input signals.
EALLOW protection
– EALLOW protection is added to critical registers. To maintain software compatibility with the Type-0 eCAP,
configure DEV_CFG_REGS.ECAPTYPE to make these registers unprotected.
The capture functionality of the Type-2 eCAP is enhanced from the Type-1 eCAP with the following added
features:
•
ECAPxSYNCINSEL register
– The ECAPSxYNCINSEL register is added for each eCAP to select an external SYNCIN. Every eCAP can
have a separate SYNCIN signal.
The eCAP inputs connect to any GPIO input through the Input X-BAR. The APWM outputs connect to GPIO pins
through the Output X-BAR to OUTPUTx positions in the GPIO mux. See Section 6.4.3 and Section 6.4.4.
The eCAP module is clocked by PERx.SYSCLK.
The clock enable bits (ECAP1–ECAP3) in the PCLKCR3 register turn off the eCAP module individually (for lowpower operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off.
7.13.3.1 High-Resolution Capture (HRCAP)
The eCAP3 module can be configured as high-resolution capture (HRCAP) submodules. The HRCAP
submodule measures the difference, in time, between pulses asynchronously to the system clock. This
submodule is new to the eCAP Type 1 module, and features many enhancements over the Type 0 HRCAP
module.
Applications for the HRCAP include:
• Capacitive touch applications
• High-resolution period and duty-cycle measurements of pulse train cycles
• Instantaneous speed measurements
• Instantaneous frequency measurements
• Voltage measurements across an isolation boundary
• Distance/sonar measurement and scanning
• Flow measurements
The HRCAP submodule includes the following features:
• Pulse-width capture in either non-high-resolution or high-resolution modes
• Absolute mode pulse-width capture
• Continuous or "one-shot" capture
• Capture on either falling or rising edge
• Continuous mode capture of pulse widths in 4-deep buffer
• Hardware calibration logic for precision high-resolution capture
• All of the resources in this list are available on any pin using the Input X-BAR.
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The HRCAP submodule includes one high-resolution capture channel in addition to a calibration block. The
calibration block allows the HRCAP submodule to be continually recalibrated, at a set interval, with no “down
time”. Because the HRCAP submodule now uses the same hardware as its respective eCAP, if the HRCAP is
used, the corresponding eCAP will be unavailable.
Each high-resolution-capable channel has the following independent key resources.
• All hardware of the respective eCAP
• High-resolution calibration logic
• Dedicated calibration interrupt
eCAP and HRCAP Block Diagram
Figure 7-47 shows the eCAP and HRCAP block diagram.
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ECCTL2 [ SYNCI_EN, SYNCOSEL, SWSYNC]
ECCTL2[CAP/APWM]
SYNC
CTRPHS
(phase register−32 bit)
ECAPxSYNCIN
APWM Mode
OVF
TSCTR
(counter−32 bit)
ECAPxSYNCOUT
RST
CTR_OVF
CTR [0−31]
Delta−Mode
PRD [0−31]
PWM
Compare
Logic
Output
X-Bar
CMP [0−31]
32
CTR=PRD
CTR [0−31]
CTR=CMP
32
PRD [0−31]
ECCTL1 [ CAPLDEN, CTRRSTx]
HRCTRL[HRE]
32
32
APRD
shadow
HRCTRL[HRE]
LD1
CAP1
(APRD Active)
Polarity
Select
LD
32
CMP [0−31]
32
HRCTRL[HRE]
32
32
CAP2
(ACMP Active)
32
Polarity
Select
LD2
LD
Other
Sources
[127:16]
Event
qualifier
ACMP
shadow
HRCTRL[HRE]
Event
Prescale
16
ECCTL1[PRESCALE]
[15:0]
Input
X-Bar
32
32
Polarity
Select
LD3
CAP3
(APRD Shadow)
LD
CAP4
(ACMP Shadow)
LD
HRCTRL[HRE]
32
32
LD4
Polarity
Select
4
Capture Events
4
Edge Polarity Select
ECCTL1[CAPxPOL]
CEVT[1:4]
ECAPxDMA_INT
ECCTL2[CTRFILTRESET]
ECCTL2[DMAEVTSEL]
ECAPx
(to ePIE)
Interrupt
Trigger
and
Flag
Control
Continuous /
Oneshot
Capture Control
CTR_OVF
MODCNTRSTS
CTR=PRD
CTR=CMP
ECCTL2 [ REARM, CONT_ONESHT, STOP_WRAP]
Registers: ECEINT, ECFLG, ECCLR, ECFRC
Capture Pulse
SYSCLK
HRCLK
HR Submodule
(A)
HR Input
ECAPx_HRCAL
(to ePIE)
Copyright © 2018, Texas Instruments Incorporated
A. The HRCAP submodule is not available on all eCAP modules; in this case, the high-resolution muxes and hardware are not
implemented.
Figure 7-47. eCAP and HRCAP Block Diagram
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7.13.3.2 eCAP/HRCAP Synchronization
The eCAP modules can be synchronized with each other by selecting a common SYNCIN source. SYNCIN
source for eCAP can be either software sync-in or external sync-in. The external sync-in signal can come from
EPWM, eCAP, or X-Bar. The SYNC signal is defined by the selection in the ECAPxSYNCINSEL[SEL] bit for
ECAPx as shown in Figure 7-48.
ECAPx
Disable
EPWM[1..7]SYNCOUT
0x0
0x1
ECAP[1..3]SYNCOUT
INPUT5 (Input X-Bar)
INPUT6 (Input X-Bar)
ECAPxSYNCIN
ECCTL2[SWSYNC]
CTR=PRD
Disable
Disable
EPWMxSYNCOUT
EXTSYNCOUT
ECAPxSYNCOUT
SYNCSELECT[SYNCOUT]
0x19
ECCTL2[SYNCOSEL]
ECAPSYNCINSEL[SEL]
Figure 7-48. eCAPSynchronization Scheme
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7.13.3.3 eCAP Electrical Data and Timing
Section 7.13.3.3.1 lists the eCAP timing requirements and Section 7.13.3.3.2 lists the eCAP switching
characteristics.
7.13.3.3.1 eCAP Timing Requirements
MIN
tw(CAP)
Capture input pulse width
Asynchronous
2tc(SYSCLK)
Synchronous
2tc(SYSCLK)
With input qualifier
NOM
MAX
UNIT
ns
1tc(SYSCLK) + tw_(IQSW)
7.13.3.3.2 eCAP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
tw(APWM)
MIN
Pulse duration, APWMx output high/low
TYP
MAX
UNIT
20
ns
7.13.3.4 HRCAP Electrical Data and Timing
Section 7.13.3.4.1 lists the HRCAP switching characteristics. Figure 7-49 shows the HRCAP accuracy precision
and resolution. Figure 7-50 shows the HRCAP standard deviation characteristics.
7.13.3.4.1 HRCAP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Input pulse width
Measurement length ≤ 5 µs
Measurement length > 5 µs
Standard deviation
Resolution
(4)
TYP
MAX
±390
540
ps
±450
1450
ps
110
Accuracy(1) (2) (3) (4)
(1)
(2)
(3)
MIN
UNIT
ns
See HRCAP
Standard
Deviation
Characteristics
figure
300
ps
Value obtained using an oscillator of 100 PPM, oscillator accuracy directly affects the HRCAP accuracy.
Measurement is completed using rising-rising or falling-falling edges
Opposite polarity edges will have an additional inaccuracy due to the difference between VIH and VIL. This effect is dependent on the
signal’s slew rate.
Accuracy only applies to time-converted measurements.
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HRCAP Figure and Graph
HRCAP’s Mean
HRCAP Result
Probability
Accuracy
Resolution
(Step Size)
Precision
(Standard Deviation)
Actual
Input Signal
A. The HRCAP has some variation in performance, this results in a probability distribution which is described using the following terms:
• Accuracy: The time difference between the input signal and the mean of the HRCAP’s distribution.
• Precision: The width of the HRCAP’s distribution, this is given as a standard deviation.
• Resolution: The minimum measurable increment.
Figure 7-49. HRCAP Accuracy Precision and Resolution
2
7.4
1.8
6.66
1.6
5.92
1.4
5.18
1.2
4.44
1
3.7
0.8
2.96
0.6
2.22
0.4
1.48
0.2
0
1000
2000
3000
4000
5000
6000
Time Between Edges(nS)
7000
8000
9000
Standard Deviation (Steps)
Standard Deviation (nS)
Typical Core Conditions
Noisy Core Supply
0.74
10000
A. Typical core conditions: All peripheral clocks are enabled.
B. Noisy core supply: All core clocks are enabled and disabled with a regular period during the measurement.
C. Fluctuations in current and voltage on the 1.2-V rail cause the standard deviation of the HRCAP to rise. Care should be taken to ensure
that the 1.2-V supply is clean, and that noisy internal events, such as enabling and disabling clock trees, have been minimized while
using the HRCAP.
Figure 7-50. HRCAP Standard Deviation Characteristics
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7.13.4 Enhanced Quadrature Encoder Pulse (eQEP)
The eQEP module on this device is Type-2. The eQEP interfaces directly with linear or rotary incremental
encoders to obtain position, direction, and speed information from rotating machines used in high-performance
motion and position control systems.
The eQEP peripheral contains the following major functional units (see Figure 7-51):
• Programmable input qualification for each pin (part of the GPIO MUX)
• Quadrature decoder unit (QDU)
• Position counter and control unit for position measurement (PCCU)
• Quadrature edge-capture unit for low-speed measurement (QCAP)
• Unit time base for speed/frequency measurement (UTIME)
• Watchdog timer for detecting stalls (QWDOG)
• Quadrature Mode Adapter (QMA)
System
control registers
To CPU
EQEPxENCLK
Data bus
SYSCLK
QCPRD
QCTMR
QCAPCTL
16
Enhanced QEP (eQEP) peripheral
16
16
Quadrature
capture unit
(QCAP)
QCTMRLAT
QCPRDLAT
QUTMR
QUPRD
Registers
used by
multiple units
QWDTMR
QWDPRD
32
QEPCTL
QEPSTS
QFLG
UTIME
16
UTOUT
QDECCTL
16
QWDOG
WDTOUT
PIE
QCLK
QDIR
QI
QS
PHE
EQEPxINT
32
Position counter/
control unit
(PCCU)
QPOSLAT
QPOSSLAT
QPOSILAT
QMA
Quadrature
decoder
(QDU)
QPOSCNT
QPOSINIT
QPOSMAX
32
QPOSCMP
EQEPx_A
EQEPxBIN
EQEPx_B
EQEPxIIN
EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE
PCSOUT
32
EQEPxAIN
16
GPIO
MUX
EQEPx_INDEX
EQEPx_STROBE
QEINT
QFRC
QCLR
QPOSCTL
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Figure 7-51. eQEP Block Diagram
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7.13.4.1 eQEP Electrical Data and Timing
Section 7.13.4.1.1 lists the eQEP timing requirements and Section 7.13.4.1.2 lists the eQEP switching
characteristics. For an explanation of the input qualifier parameters, see Section 7.11.6.2.1.
7.13.4.1.1 eQEP Timing Requirements
MIN
Synchronous(1)
tw(QEPP)
QEP input period
tw(INDEXH)
QEP Index Input High time
tw(INDEXL)
QEP Index Input Low time
tw(STROBH)
QEP Strobe High time
tw(STROBL)
QEP Strobe Input Low time
(1)
Synchronous with input qualifier
2tc(SYSCLK)
2tc(SYSCLK)
Synchronous with input qualifier
2tc(SYSCLK)
2tc(SYSCLK)
cycles
2tc(SYSCLK) + tw(IQSW)
Synchronous(1)
Synchronous with input qualifier
cycles
2tc(SYSCLK) + tw(IQSW)
Synchronous(1)
Synchronous with input qualifier
cycles
2tc(SYSCLK) + tw(IQSW)
Synchronous(1)
UNIT
cycles
2[1tc(SYSCLK) + tw(IQSW)]
Synchronous(1)
Synchronous with input qualifier
MAX
2tc(SYSCLK)
cycles
2tc(SYSCLK) + tw(IQSW)
The GPIO GPxQSELn Asynchronous mode should not be used for eQEP module input pins.
7.13.4.1.2 eQEP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
MAX
UNIT
td(CNTR)xin
Delay time, external clock to counter increment
PARAMETER
5tc(SYSCLK)
cycles
td(PCS-OUT)QEP
Delay time, QEP input edge to position compare sync output
7tc(SYSCLK)
cycles
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7.14 Communications Peripherals
7.14.1 Controller Area Network (CAN)
Note
The CAN module uses the IP known as DCAN. This document uses the names CAN and DCAN
interchangeably to reference this peripheral.
The CAN module implements the following features:
• Complies with ISO11898-1 ( Bosch® CAN protocol specification 2.0 A and B)
• Bit rates up to 1 Mbps
• Multiple clock sources
• 32 message objects (mailboxes), each with the following properties:
– Configurable as receive or transmit
– Configurable with standard (11-bit) or extended (29-bit) identifier
– Supports programmable identifier receive mask
– Supports data and remote frames
– Holds 0 to 8 bytes of data
– Parity-checked configuration and data RAM
• Individual identifier mask for each message object
• Programmable FIFO mode for message objects
• Programmable loopback modes for self-test operation
• Suspend mode for debug support
• Software module reset
• Automatic bus on after bus-off state by a programmable 32-bit timer
• Two interrupt lines
• DMA support
Note
For a CAN bit clock of 100 MHz, the smallest bit rate possible is 3.90625 kbps.
Note
The accuracy of the on-chip zero-pin oscillator is in Section 7.11.3.5.1. Depending on parameters
such as the CAN bit timing settings, bit rate, bus length, and propagation delay, the accuracy of this
oscillator may not meet the requirements of the CAN protocol. In this situation, an external clock
source must be used.
Figure 7-52 shows the CAN block diagram.
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CAN_H
CAN Bus
CAN_L
External connections
Device
3.3V CAN Transceiver
CANx RX pin
CANx TX pin
CAN
CAN Core
Message RAM
Message Handler
Message
RAM
Interface
32
Message
Objects
(Mailboxes)
Register and Message
Object Access (IFx)
Test Modes
Only
Module Interface
CANINT0
CANINT1
DMA
CPU Bus
Figure 7-52. CAN Block Diagram
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7.14.2 Inter-Integrated Circuit (I2C)
The I2C module has the following features:
• Compliance with the NXP Semiconductors I2C-bus specification (version 2.1):
– Support for 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit/receive and receive/transmit mode
– Data transfer rate from 10 kbps up to 400 kbps (Fast-mode)
• One 16-byte receive FIFO and one 16-byte transmit FIFO
• Supports two ePIE interrupts
– I2Cx interrupt – Any of the below conditions can be configured to generate an I2Cx interrupt:
• Transmit Ready
• Receive Ready
• Register-Access Ready
• No-Acknowledgment
• Arbitration-Lost
• Stop Condition Detected
• Addressed-as-Slave
– I2Cx_FIFO interrupts:
• Transmit FIFO interrupt
• Receive FIFO interrupt
• Module enable and disable capability
• Free data format mode
Figure 7-53 shows how the I2C peripheral module interfaces within the device.
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I2C module
I2CXSR
I2CDXR
TX FIFO
FIFO Interrupt
to CPU/PIE
SDA
RX FIFO
Peripheral bus
I2CRSR
SCL
Clock
synchronizer
I2CDRR
Control/status
registers
CPU
Prescaler
Noise filters
Interrupt to
CPU/PIE
I2C INT
Arbitrator
Figure 7-53. I2C Peripheral Module Interfaces
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7.14.2.1 I2C Electrical Data and Timing
Section 7.14.2.1.1 lists the I2C timing requirements. Section 7.14.2.1.2 lists the I2C switching characteristics.
Figure 7-54 shows the I2C timing diagram.
Note
To meet all of the I2C protocol timing specifications, the I2C module clock must be configured in the
range from 7 MHz to 12 MHz.
7.14.2.1.1 I2C Timing Requirements
NO.
MIN
MAX
UNIT
7
12
MHz
Standard mode
T0
fmod
I2C module frequency
T1
th(SDA-SCL)START
Hold time, START condition, SCL fall delay after
SDA fall
4.0
µs
T2
tsu(SCL-SDA)START
Setup time, Repeated START, SCL rise before SDA
fall delay
4.7
µs
0
µs
250
ns
T3
th(SCL-DAT)
Hold time, data after SCL fall
T4
tsu(DAT-SCL)
Setup time, data before SCL rise
T5
tr(SDA)
Rise time, SDA
1000
ns
T6
tr(SCL)
Rise time, SCL
1000
ns
T7
tf(SDA)
Fall time, SDA
300
ns
T8
tf(SCL)
Fall time, SCL
300
ns
T9
tsu(SCL-SDA)STOP
Setup time, STOP condition, SCL rise before SDA
rise delay
4.0
T10
tw(SP)
Pulse duration of spikes that will be suppressed by
filter
0
T11
Cb
capacitance load on each bus line
T0
fmod
I2C module frequency
T1
th(SDA-SCL)START
Hold time, START condition, SCL fall delay after
SDA fall
0.6
µs
T2
tsu(SCL-SDA)START
Setup time, Repeated START, SCL rise before SDA
fall delay
0.6
µs
0
µs
100
ns
µs
50
ns
400
pF
12
MHz
Fast mode
7
T3
th(SCL-DAT)
Hold time, data after SCL fall
T4
tsu(DAT-SCL)
Setup time, data before SCL rise
T5
tr(SDA)
Rise time, SDA
20
300
ns
T6
tr(SCL)
Rise time, SCL
20
300
ns
T7
tf(SDA)
Fall time, SDA
11.4
300
ns
T8
tf(SCL)
Fall time, SCL
11.4
300
ns
T9
tsu(SCL-SDA)STOP
Setup time, STOP condition, SCL rise before SDA
rise delay
0.6
T10
tw(SP)
Pulse duration of spikes that will be suppressed by
filter
0
T11
Cb
capacitance load on each bus line
Copyright © 2020 Texas Instruments Incorporated
µs
50
ns
400
pF
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7.14.2.1.2 I2C Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
0
100
kHz
Standard mode
S1
fSCL
SCL clock frequency
S2
TSCL
SCL clock period
S3
tw(SCLL)
Pulse duration, SCL clock low
4.7
µs
S4
tw(SCLH)
Pulse duration, SCL clock high
4.0
µs
S5
tBUF
Bus free time between STOP and START
conditions
4.7
µs
10
µs
S6
tv(SCL-DAT)
Valid time, data after SCL fall
3.45
µs
S7
tv(SCL-ACK)
Valid time, Acknowledge after SCL fall
3.45
µs
S8
II
Input current on pins
–10
10
µA
0
400
kHz
0.1 Vbus < Vi < 0.9 Vbus
Fast mode
S1
fSCL
SCL clock frequency
S2
TSCL
SCL clock period
S3
tw(SCLL)
Pulse duration, SCL clock low
1.3
µs
S4
tw(SCLH)
Pulse duration, SCL clock high
0.6
µs
S5
tBUF
Bus free time between STOP and START
conditions
1.3
µs
S6
tv(SCL-DAT)
Valid time, data after SCL fall
0.9
µs
S7
tv(SCL-ACK)
Valid time, Acknowledge after SCL fall
0.9
µs
S8
II
Input current on pins
10
µA
2.5
0.1 Vbus < Vi < 0.9 Vbus
µs
–10
7.14.2.1.3 I2C Timing Diagram
STOP
START
SDA
ACK
T5
S6
T7
Contd...
S7
T10
S3
Contd...
S4
SCL
T6
Repeated
START
SDA
9th
clock
T8
S2
STOP
S5
ACK
T2
T9
T1
SCL
9th
clock
Figure 7-54. I2C Timing Diagram
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
7.14.3 Power Management Bus (PMBus) Interface
The PMBus module has the following features:
• Compliance with the SMI Forum PMBus Specification (Part I v1.0 and Part II v1.1)
• Support for master and slave modes
• Support for I2C mode
• Support for two speeds:
– Standard Mode: Up to 100 kHz
– Fast Mode: 400 kHz
• Packet error checking
• CONTROL and ALERT signals
• Clock high and low time-outs
• Four-byte transmit and receive buffers
• One maskable interrupt, which can be generated by several conditions:
– Receive data ready
– Transmit buffer empty
– Slave address received
– End of message
– ALERT input asserted
– Clock low time-out
– Clock high time-out
– Bus free
Figure 7-55 shows the PMBus block diagram.
PCLKCR20
SYSCLK
Div
PMBCTRL
ALERT
DMA
Bit clock
Other registers
CTL
GPIO Mux
CPU
PMBTXBUF
SCL
Shift register
PMBRXBUF
SDA
PMBUSA_INT
PIE
PMBus Module
Figure 7-55. PMBus Block Diagram
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7.14.3.1 PMBus Electrical Data and Timing
Section 7.14.3.1.1 lists the PMBus electrical characteristics. Section 7.14.3.1.2 lists the PMBUS fast mode
switching characteristics. Section 7.14.3.1.3 lists the PMBUS standard mode switching characteristics.
7.14.3.1.1 PMBus Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIL
Valid low-level input voltage
VIH
Valid high-level input voltage
VOL
Low-level output voltage
At Ipullup = 4 mA
IOL
Low-level output current
VOL ≤ 0.4 V
tSP
Pulse width of spikes that must be
suppressed by the input filter
Ii
Input leakage current on each pin
Ci
Capacitance on each pin
MIN
TYP
2.1
0.1 Vbus < Vi < 0.9 Vbus
MAX
UNIT
0.8
V
VDDIO
V
0.4
V
4
mA
0
50
ns
–10
10
µA
10
pF
7.14.3.1.2 PMBus Fast Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
400
kHz
fSCL
SCL clock frequency
10
tBUF
Bus free time between STOP and
START conditions
1.3
µs
tHD;STA
START condition hold time -- SDA fall
to SCL fall delay
0.6
µs
tSU;STA
Repeated START setup time -- SCL
rise to SDA fall delay
0.6
µs
tSU;STO
STOP condition setup time -- SCL rise
to SDA rise delay
0.6
µs
tHD;DAT
Data hold time after SCL fall
300
ns
tSU;DAT
Data setup time before SCL rise
100
ns
tTimeout
Clock low time-out
25
tLOW
Low period of the SCL clock
1.3
tHIGH
High period of the SCL clock
0.6
tLOW;SEXT
Cumulative clock low extend time
(slave device)
tLOW;MEXT
35
ms
µs
50
µs
From START to STOP
25
ms
Cumulative clock low extend time
(master device)
Within each byte
10
ms
tr
Rise time of SDA and SCL
5% to 95%
20
300
ns
tf
Fall time of SDA and SCL
95% to 5%
20
300
ns
128
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7.14.3.1.3 PMBus Standard Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
100
kHz
fSCL
SCL clock frequency
10
tBUF
Bus free time between STOP and
START conditions
4.7
µs
tHD;STA
START condition hold time -- SDA fall
to SCL fall delay
4
µs
tSU;STA
Repeated START setup time -- SCL
rise to SDA fall delay
4.7
µs
tSU;STO
STOP condition setup time -- SCL rise
to SDA rise delay
4
µs
tHD;DAT
Data hold time after SCL fall
300
ns
tSU;DAT
Data setup time before SCL rise
250
ns
tTimeout
Clock low time-out
25
tLOW
Low period of the SCL clock
4.7
tHIGH
High period of the SCL clock
4
tLOW;SEXT
Cumulative clock low extend time
(slave device)
tLOW;MEXT
Cumulative clock low extend time
(master device)
tr
tf
35
ms
50
µs
From START to STOP
25
ms
Within each byte
10
ms
Rise time of SDA and SCL
1000
ns
Fall time of SDA and SCL
300
ns
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
7.14.4 Serial Communications Interface (SCI)
The SCI is a 2-wire asynchronous serial port, commonly known as a UART. The SCI module supports digital
communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero
(NRZ) format
The SCI receiver and transmitter each have a 16-level-deep FIFO for reducing servicing overhead, and each has
its own separate enable and interrupt bits. Both can be operated independently for half-duplex communication,
or simultaneously for full-duplex communication. To specify data integrity, the SCI checks received data for break
detection, parity, overrun, and framing errors. The bit rate is programmable to different speeds through a 16-bit
baud-select register.
Features of the SCI module include:
• Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
– Baud rate programmable to 64K different rates
• Data-word format
– 1 start bit
– Data-word length programmable from 1 to 8 bits
– Optional even/odd/no parity bit
– 1 or 2 stop bits
• Four error-detection flags: parity, overrun, framing, and break detection
• Two wake-up multiprocessor modes: idle-line and address bit
• Half- or full-duplex operation
• Double-buffered receive and transmit functions
• Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY
flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
• Separate enable bits for transmitter and receiver interrupts (except BRKDT)
• NRZ format
• Auto baud-detect hardware logic
• 16-level transmit and receive FIFO
Note
All registers in this module are 8-bit registers. When a register is accessed, the register data is in the
lower byte (bits 7–0), and the upper byte (bits 15–8) is read as zeros. Writing to the upper byte has no
effect.
Figure 7-56 shows the SCI block diagram.
130
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TXENA
SCICTL1.1
TXSHF
Register
Frame
Format and Mode
SCITXD
8
Parity
Even/Odd
0
TXEMPTY
1
SCICCR.6
SCICTL2.6
8
Enable
TX FIFO_0
SCICCR.5
88
TX FIFO_1
TX Interrupt
Logic
TX FIFO Interrupts
TXINT
To CPU
TX FIFO_N
TXINTENA
8
0
TXWAKE
SCICTL2.0
TXRDY
1
SCICTL2.7
SCICTL1.3
SCI TX Interrupt Select Logic
8
WUT
Transmit Data
Buffer Register
SCITXBUF.7-0
Auto Baud Detect Logic
RXENA
LSPCLK
Baud Rate
MSB/LSB
Registers
SCICTL1.0
RXSHF
Register
SCIHBAUD.15-8
SCIRXD
RXWAKE
8
SCILBAUD.7-0
SCIRXST.1
0
1
8
SCIFFENA
RX FIFO_0
SCIFFTX.14
8
RX FIFO_1
RX FIFO Interrupts
RX Interrupt
Logic
RXINT
To CPU
RX FIFO_N
RXFFOVF
8
0
SCIFFRX.15
1
RXBKINTENA
SCICTL2.1
RXRDY
SCIRXST.6
RXENA
BRKDT
SCICTL1.0
RXERRINTENA
SCIRXST.5
8
SCICTL1.6
SCI RX Interrupt Select Logic
SCIRXST.5-2
Receive Data
Buffer Register
SCIRXBUF.7-0
BRKDT
FE OE PE
RXERROR
SCIRXST.7
Figure 7-56. SCI Block Diagram
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7.14.5 Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) is a high-speed synchronous serial input and output (I/O) port that allows a
serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a programmed bittransfer rate. The SPI is normally used for communications between the MCU controller and external peripherals
or another controller. Typical applications include external I/O or peripheral expansion through devices such as
shift registers, display drivers, and analog-to-digital converters (ADCs). Multidevice communications are
supported by the master or slave operation of the SPI. The port supports a 16-level, receive and transmit FIFO
for reducing CPU servicing overhead.
The SPI module features include:
• SPISOMI: SPI slave-output/master-input pin
• SPISIMO: SPI slave-input/master-output pin
• SPISTE: SPI slave transmit-enable pin
• SPICLK: SPI serial-clock pin
• Two operational modes: Master and Slave
• Baud rate: 125 different programmable rates. The maximum baud rate that can be employed is limited by the
maximum speed of the I/O buffers used on the SPI pins.
• Data word length: 1 to 16 data bits
• Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling
edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising
edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
• Simultaneous receive and transmit operation (transmit function can be disabled in software)
• Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithm
• 16-level transmit/receive FIFO
• DMA support
• High-speed mode
• Delayed transmit control
• 3-wire SPI mode
• SPISTE inversion for digital audio interface receive mode on devices with two SPI modules
Figure 7-57 shows the SPI CPU interfaces.
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PCLKCR8
LSPCLK
Low-Speed
Prescaler
SYSCLK
CPU
Bit Clock
Peripheral Bus
SYSRS
SPISIMO
SPISOMI
SPI
GPIO MUX
SPICLK
SPIINT
SPITXINT
PIE
SPISTE
SPIRXDMA
SPITXDMA
DMA
Figure 7-57. SPI CPU Interface
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7.14.5.1 SPI Master Mode Timings
The following section contains the SPI Master Mode Timings. For more information about the SPI in High-Speed
mode, see the Serial Peripheral Interface (SPI) chapter of the TMS320F28002x Real-Time Microcontrollers
Technical Reference Manual.
Section 7.14.5.1.1 lists the SPI master mode timing requirements.
Section 7.14.5.1.2 lists the SPI master mode switching characteristics where the clock phase = 0. Figure 7-58
shows the SPI master mode external timing where the clock phase = 0.
Section 7.14.5.1.3 lists the SPI master mode switching characteristics where the clock phase = 1. Figure 7-59
shows the SPI master mode external timing where the clock phase = 1.
Note
All timing parameters for SPI High-Speed Mode assume a load capacitance of 5 pF on SPICLK,
SPISIMO, and SPISOMI.
7.14.5.1.1 SPI Master Mode Timing Requirements
(BRR + 1) (1)
NO.
MIN
MAX
UNIT
High-Speed Mode
8
tsu(SOMI)M
Setup time, SPISOMI valid before SPICLK
Even, Odd
1
ns
9
th(SOMI)M
Hold time, SPISOMI valid after SPICLK
Even, Odd
5
ns
Normal Mode
8
tsu(SOMI)M
Setup time, SPISOMI valid before SPICLK
Even, Odd
15
ns
9
th(SOMI)M
Hold time, SPISOMI valid after SPICLK
Even, Odd
0
ns
(1)
134
The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
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7.14.5.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 0)
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
(BRR + 1)(1)
MIN
MAX
UNIT
Even
4tc(LSPCLK)
128tc(LSPCLK)
Odd
5tc(LSPCLK)
127tc(LSPCLK)
0.5tc(SPC)M – 1
0.5tc(SPC)M + 1
0.5tc(SPC)M + 0.5tc(LSPCLK) – 1
0.5tc(SPC)M +
0.5tc(LSPCLK) + 1
0.5tc(SPC)M – 1
0.5tc(SPC)M + 1
0.5tc(SPC)M – 0.5tc(LSPCLK) – 1
0.5tc(SPC)M –
0.5tc(LSPCLK) + 1
Even
1.5tc(SPC)M – 3tc(SYSCLK) – 3
1.5tc(SPC)M –
3tc(SYSCLK) + 3
Odd
1.5tc(SPC)M – 4tc(SYSCLK) – 3
1.5tc(SPC)M –
4tc(SYSCLK) + 3
0.5tc(SPC)M – 3
0.5tc(SPC)M + 3
0.5tc(SPC)M – 0.5tc(LSPCLK) – 3
0.5tc(SPC)M –
0.5tc(LSPCLK) + 3
ns
1
ns
General
1
tc(SPC)M
Cycle time, SPICLK
2
tw(SPC1)M
Pulse duration, SPICLK, first pulse
3
tw(SPC2)M
Pulse duration, SPICLK, second pulse
Even
Odd
Even
23
td(SPC)M
Odd
Delay time, SPISTE active to SPICLK
Even
24
tv(STE)M
Valid time, SPICLK to SPISTE inactive
Odd
ns
ns
ns
ns
High-Speed Mode
4
td(SIMO)M
Delay time, SPICLK to SPISIMO valid
Even, Odd
5
tv(SIMO)M
Valid time, SPISIMO valid after
SPICLK
Even
Odd
0.5tc(SPC)M – 3
ns
0.5tc(SPC)M – 0.5tc(LSPCLK) – 3
Normal Mode
4
td(SIMO)M
Delay time, SPICLK to SPISIMO valid
Even, Odd
5
tv(SIMO)M
Valid time, SPISIMO valid after
SPICLK
Even
(1)
Odd
1
0.5tc(SPC)M – 3
0.5tc(SPC)M – 0.5tc(LSPCLK) – 3
ns
ns
The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
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7.14.5.1.3 SPI Master Mode Switching Characteristics (Clock Phase = 1)
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
(BRR + 1)
MIN
MAX
UNIT
General
1
tc(SPC)M
Cycle time, SPICLK
2
tw(SPCH)M
Pulse duration, SPICLK, first pulse
3
tw(SPC2)M
Pulse duration, SPICLK, second pulse
23
td(SPC)M
Delay time, SPISTE valid to SPICLK
24
td(STE)M
Delay time, SPICLK to SPISTE invalid
Even
4tc(LSPCLK)
128tc(LSPCLK)
Odd
5tc(LSPCLK)
127tc(LSPCLK)
0.5tc(SPC)M – 1
0.5tc(SPC)M + 1
0.5tc(SPC)M – 0.5tc(LSPCLK) – 1
0.5tc(SPC)M –
0.5tc(LSPCLK) + 1
0.5tc(SPC)M – 1
0.5tc(SPC)M + 1
0.5tc(SPC)M + 0.5tc(LSPCLK) – 1
0.5tc(SPC)M +
0.5tc(LSPCLK) + 1
2tc(SPC)M – 3tc(SYSCLK) – 3
2tc(SPC)M –
3tc(SYSCLK) + 2
Even
–3
2
Odd
–3
2
Even
Odd
Even
Odd
Even, Odd
ns
ns
ns
ns
ns
High-Speed Mode
4
td(SIMO)M
Delay time, SPISIMO valid to SPICLK
5
tv(SIMO)M
Valid time, SPISIMO valid after
SPICLK
Even
Odd
Even
Odd
0.5tc(SPC)M – 2
0.5tc(SPC)M + 0.5tc(LSPCLK) – 2
0.5tc(SPC)M – 3
0.5tc(SPC)M – 0.5tc(LSPCLK) – 3
ns
ns
Normal Mode
4
td(SIMO)M
Delay time, SPISIMO valid to SPICLK
5
tv(SIMO)M
Valid time, SPISIMO valid after
SPICLK
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Even
Odd
Even
Odd
0.5tc(SPC)M – 2
0.5tc(SPC)M + 0.5tc(LSPCLK) – 2
0.5tc(SPC)M – 3
0.5tc(SPC)M – 0.5tc(LSPCLK) – 3
ns
ns
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7.14.5.1.4 SPI Master Mode Timing Diagrams
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
SPISOMI
24
23
(A)
SPISTE
A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 7-58. SPI Master Mode External Timing (Clock Phase = 0)
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
Master Out Data Is Valid
SPISIMO
8
9
Master In Data Must
Be Valid
SPISOMI
(A)
24
23
SPISTE
A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 7-59. SPI Master Mode External Timing (Clock Phase = 1)
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7.14.5.2 SPI Slave Mode Timings
The following section contains the SPI Slave Mode Timings. For more information about the SPI in High-Speed
mode, see the Serial Peripheral Interface (SPI) chapter of the TMS320F28002x Real-Time Microcontrollers
Technical Reference Manual.
Section 7.14.5.2.1 lists the SPI slave mode timing requirements. Section 7.14.5.2.2 lists the SPI slave mode
switching characteristics.
Figure 7-60 shows the SPI slave mode external timing where the clock phase = 0. Figure 7-61 shows the SPI
slave mode external timing where the clock phase = 1.
7.14.5.2.1 SPI Slave Mode Timing Requirements
NO.
MIN
MAX
UNIT
12
tc(SPC)S
Cycle time, SPICLK
4tc(SYSCLK)
ns
13
tw(SPC1)S
Pulse duration, SPICLK, first pulse
2tc(SYSCLK) – 1
ns
14
tw(SPC2)S
Pulse duration, SPICLK, second pulse
2tc(SYSCLK) – 1
ns
19
tsu(SIMO)S
Setup time, SPISIMO valid before SPICLK
1.5tc(SYSCLK)
ns
20
th(SIMO)S
Hold time, SPISIMO valid after SPICLK
25
26
tsu(STE)S
th(STE)S
1.5tc(SYSCLK)
ns
Setup time, SPISTE valid before SPICLK
(Clock Phase = 0)
2tc(SYSCLK) + 3
ns
Setup time, SPISTE valid before SPICLK
(Clock Phase = 1)
2tc(SYSCLK) + 23
ns
1.5tc(SYSCLK)
ns
Hold time, SPISTE invalid after SPICLK
7.14.5.2.2 SPI Slave Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
15
td(SOMI)S
Delay time, SPICLK to SPISOMI valid
16
tv(SOMI)S
Valid time, SPISOMI valid after SPICLK
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MIN
MAX
12
0
UNIT
ns
ns
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7.14.5.2.3 SPI Slave Mode Timing Diagrams
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
SPISOMI
16
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
SPISIMO
25
26
SPISTE
Figure 7-60. SPI Slave Mode External Timing (Clock Phase = 0)
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
SPISOMI
Data Valid
SPISOMI Data Is Valid
Data Valid
16
19
20
SPISIMO Data
Must Be Valid
SPISIMO
26
25
SPISTE
Figure 7-61. SPI Slave Mode External Timing (Clock Phase = 1)
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7.14.6 Local Interconnect Network (LIN)
This device contains one Local Interconnect Network (LIN) module. The LIN module adheres to the LIN 2.1
standard as defined by the LIN Specification Package Revision 2.1. The LIN is a low-cost serial interface
designed for applications where the CAN protocol may be too expensive to implement, such as small
subnetworks for cabin comfort functions like interior lighting or window control in an automotive application.
The LIN standard is based on the SCI (UART) serial data link format. The communication concept is singlemaster and multiple-slave with a message identification for multicast transmission between any network nodes.
The LIN module can be programmed to work either as an SCI or as a LIN as the core of the module is an SCI.
The hardware features of the SCI are augmented to achieve LIN compatibility. The SCI module is a universal
asynchronous receiver-transmitter (UART) that implements the standard non-return-to-zero format.
Though the registers are common for LIN and SCI, the register descriptions have notes to identify the register/bit
usage in different modes. Because of this, code written for this module cannot be directly ported to the standalone SCI module and vice versa.
The LIN module has the following features:
• Compatibility with LIN 1.3, 2.0 and 2.1 protocols
• Configurable baud rate up to 20 kbps (as per LIN 2.1 protocol)
• Two external pins: LINRX and LINTX
• Multibuffered receive and transmit units
• Identification masks for message filtering
• Automatic master header generation
– Programmable synchronization break field
– Synchronization field
– Identifier field
• Slave automatic synchronization
– Synchronization break detection
– Optional baud rate update
– Synchronization validation
• 231 programmable transmission rates with 7 fractional bits
• Wakeup on LINRX dominant level from transceiver
• Automatic wakeup support
– Wakeup signal generation
– Expiration times on wakeup signals
• Automatic bus idle detection
• Error detection
– Bit error
– Bus error
– No-response error
– Checksum error
– Synchronization field error
– Parity error
• Capability to use direct memory access (DMA) for transmit and receive data
• Two interrupt lines with priority encoding for:
– Receive
– Transmit
– ID, error, and status
• Support for LIN 2.0 checksum
• Enhanced synchronizer finite state machine (FSM) support for frame processing
• Enhanced handling of extended frames
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•
•
SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Enhanced baud rate generator
Update wakeup/go to sleep
Figure 7-62 shows the LIN block diagram.
READ DATA BUS
WRITE DATA BUS
ADDRESS BUS
CHECKSUM
CALCULATOR
INTERFACE
ID PARTY
CHECKER
BIT
MONITOR
TXRX ERROR
DETECTOR (TED)
TIME-OUT
CONTROL
COUNTER
LINRX/
SCIRX
COMPARE
LINTX/
SCITX
FSM
MASK
FILTER
SYNCHRONIZER
8 RECEIVE
BUFFERS
DMA
CONTROL
8 TRANSMIT
BUFFERS
Figure 7-62. LIN Block Diagram
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7.14.7 Fast Serial Interface (FSI)
The Fast Serial Interface (FSI) module is a serial communication peripheral capable of reliable and robust highspeed communications. The FSI is designed to ensure data robustness across many system conditions such as
chip-to-chip as well as board-to-board across an isolation barrier. Payload integrity checks such as CRC, startand end-of-frame patterns, and user-defined tags, are encoded before transmit and then verified after receipt
without additional CPU interaction. Line breaks can be detected using periodic transmissions, all managed and
monitored by hardware. The FSI is also tightly integrated with other control peripherals on the device. To ensure
that the latest sensor data or control parameters are available, frames can be transmitted on every control loop
period. An integrated skew-compensation block has been added on the receiver to handle skew that may occur
between the clock and data signals due to a variety of factors, including trace-length mismatch and skews
induced by an isolation chip. With embedded data robustness checks, data-link integrity checks, skew
compensation, and integration with control peripherals, the FSI can enable high-speed, robust communication in
any system. These and many other features of the FSI follow.
The FSI module includes the following features:
• Independent transmitter and receiver cores
• Source-synchronous transmission
• Dual data rate (DDR)
• One or two data lines
• Programmable data length
• Skew adjustment block to compensate for board and system delay mismatches
• Frame error detection
• Programmable frame tagging for message filtering
• Hardware ping to detect line breaks during communication (ping watchdog)
• Two interrupts per FSI core
• Externally triggered frame generation
• Hardware- or software-calculated CRC
• Embedded ECC computation module
• Register write protection
• DMA support
• SPI compatibility mode (limited features available)
Operating the FSI at maximum speed (50 MHz) at dual data rate (100 Mbps) may require the integrated skew
compensation block to be configured according to the specific operating conditions on a case-by-case basis.
The Fast Serial Interface (FSI) Skew Compensation Application Report provides example software on how to
configure and set up the integrated skew compensation block on the Fast Serial Interface.
The FSI consists of independent transmitter (FSITX) and receiver (FSIRX) cores. The FSITX and FSIRX cores
are configured and operated independently. The features available on the FSITX and FSIRX are described in
Section 7.14.7.1 and Section 7.14.7.2, respectively.
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7.14.7.1 FSI Transmitter
The FSI transmitter module handles the framing of data, CRC generation, signal generation of TXCLK, TXD0,
and TXD1, as well as interrupt generation. The operation of the transmitter core is controlled and configured
through programmable control registers. The transmitter control registers let the CPU program, control, and
monitor the operation of the FSI transmitter. The transmit data buffer is accessible by the CPU and the DMA.
The transmitter has the following features:
• Automated ping frame generation
• Externally triggered ping frames
• Externally triggered data frames
• Software-configurable frame lengths
• 16-word data buffer
• Data buffer underrun and overrun detection
• Hardware-generated CRC on data bits
• Software ECC calculation on select data
• DMA support
Figure 7-63 shows the FSITX CPU interface. Figure 7-64 shows the high-level block diagram of the FSITX. Not
all data paths and internal connections are shown. This diagram provides a high-level overview of the internal
modules present in the FSITX.
PLLRAWCLK
PCLKCR18
SYSCLK
SYSRSN
C28x
ePIE
FSITXyINT1
FSITXyINT2
FSITX
FSITXyD1
FSITXyDMA
Trigger Muxes(A)
32
FSITXyD0
GPIO MUX
Registers
Register Interface
DMA
FSITXyCLK
A. The signals connected to the trigger muxes are described in the External Frame Trigger Mux section of the Fast Serial Interface (FSI)
chapter in the TMS320F28002x Real-Time Microcontrollers Technical Reference Manual.
Figure 7-63. FSITX CPU Interface
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PLLRAWCLK
FSITX
SYSRSN
SYSCLK
Transmit Clock
Generator
TXCLKIN
Register Interface
FSI Mode:
TXCLK = TXCLKIN/2
SPI Signaling Mode:
TXCLK = TXCLKIN
Core Reset
FSITXINT1
FSITXINT2
Control Registers,
Interrupt Management
TXCLK
Ping Time-out Counter
FSITX_DMA_EVT
Transmitter Core
External Frame Triggers
TXD0
TXD1
Transmit Data
Buffer
ECC Logic
Figure 7-64. FSITX Block Diagram
7.14.7.1.1 FSITX Electrical Data and Timing
Section 7.14.7.1.1.1 lists the FSITX switching characteristics. Figure 7-65 shows the FSITX timings.
7.14.7.1.1.1 FSITX Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
NO.
PARAMETER
1
tc(TXCLK)
Cycle time, TXCLK
2
tw(TXCLK)
Pulse width, TXCLK low or TXCLK high
3
td(TXCLK–TXD)
Delay time, TXCLK rising or falling toTXD
valid
TDM1
tskew(TDM_CLK-TDM_Dx )
Delay skew introduced between TXCLKTDM_CLK delay and TXDx-TDM_Dx delays
MIN
MAX
20
UNIT
ns
(0.5tc(TXCLK)) – 1
(0.5tc(TXCLK)) + 1
ns
(0.25tc(TXCLK)) – 2
(0.25tc(TXCLK)) + 2
ns
-2
2
ns
7.14.7.1.1.2 FSITX Timings
1
2
FSITXCLK
FSITXD0
FSITXD1
3
Figure 7-65. FSITX Timings
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7.14.7.2 FSI Receiver
The receiver module interfaces to the FSI clock (RXCLK), and data lines (RXD0 and RXD1) after they pass
through an optional programmable delay line. The receiver core handles the data framing, CRC computation,
and frame-related error checking. The receiver bit clock and state machine are run by the RXCLK input, which is
asynchronous to the device system clock.
The receiver control registers let the CPU program, control, and monitor the operation of the FSIRX. The receive
data buffer is accessible by the CPU, HIC, and the DMA.
The receiver core has the following features:
• 16-word data buffer
• Multiple supported frame types
• Ping frame watchdog
• Frame watchdog
• CRC calculation and comparison in hardware
• ECC detection
• Programmable delay line control on incoming signals
• DMA support
• SPI compatibility mode
Figure 7-66 shows the FSIRX CPU interface. Figure 7-67 provides a high-level overview of the internal modules
present in the FSIRX. Not all data paths and internal connections are shown.
PCLKCR18
SYSCLK
SYSRSN
C28x
ePIE
FSIRXyINT1
FSIRXyINT2
FSIRX
FSIRXyD0
FSIRXyD1
GPIO MUX
Registers
Register Interface
DMA
FSIRXyCLK
FSIRXyDMA
Figure 7-66. FSIRX CPU Interface
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FSIRX
SYSRSn
SYSCLK
Frame Watchdog
Register Interface
Core Reset
FSIRXINT1
FSIRXINT2
Control Registers,
Interrupt Management
RXCLK
Ping Watchdog
FSIRX_DMA_EVT
Receiver Core
Skew
Control
RXD0
RXD1
Receive Data
Buffer
ECC Check
Logic
Figure 7-67. FSIRX Block Diagram
7.14.7.2.1 FSIRX Electrical Data and Timing
Section 7.14.7.2.1.1 lists the FSIRX timing requirements. Section 7.14.7.2.1.2 lists the FSIRX switching
characteristics. Figure 7-68 shows the FSIRX Timings.
7.14.7.2.1.1 FSIRX Timing Requirements
NO.
MIN
1
tc(RXCLK)
Cycle time, RXCLK
2
tw(RXCLK)
Pulse width, RXCLK low or RXCLK high.
3
tsu(RXCLK–RXD)
Setup time with respect to RXCLK, applies to
both edges of the clock
4
th(RXCLK–RXD)
Hold time with respect to RXCLK, applies to
both edges of the clock
MAX
20
0.35tc(RXCLK)
UNIT
ns
0.65tc(RXCLK)
ns
1.7
ns
2
ns
7.14.7.2.1.2 FSIRX Switching Characteristics
NO.
PARAMETER
MIN
MAX
UNIT
10
30
ns
1
td(RXCLK)
RXCLK delay compensation at
RX_DLYLINE_CTRL[RXCLK_DLY]=31
2
td(RXD0)
RXD0 delay compensation at
RX_DLYLINE_CTRL[RXD0_DLY]=31
10
30
ns
3
td(RXD1)
RXD1 delay compensation
at RX_DLYLINE_CTRL[RXD1_DLY]=31
10
30
ns
4
td(DELAY_ELEMENT)
Incremental delay of each delay line element
for RXCLK, RXD0, and RXD1
0.3
1
ns
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7.14.7.2.1.3 FSIRX Timings
1
2
FSIRXCLK
FSIRXD0
FSIRXD1
3
4
Figure 7-68. FSIRX Timings
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7.14.7.3 FSI SPI Compatibility Mode
The FSI supports a SPI compatibility mode to enable communication with programmable SPI devices. In this
mode, the FSI transmits its data in the same manner as a SPI in a single clock configuration mode. While the
FSI is able to physically interface with a SPI in this mode, the external device must be able to encode and
decode an FSI frame to communicate successfully. This is because the FSI transmits all SPI frame phases with
the exception of the preamble and postamble. The FSI provides the same data validation and frame checking as
if it was in standard FSI mode, allowing for more robust communication without consuming CPU cycles. The
external SPI is required to send all relevant information and can access standard FSI features such as the ping
frame watchdog on the FSIRX, frame tagging, or custom CRC values. The list of features of SPI compatibility
mode follows:
• Data will transmit on rising edge and receive on falling edge of the clock.
• Only 16-bit word size is supported.
• TXD1 will be driven like an active-low chip-select signal. The signal will be low for the duration of the full
frame transmission.
• No receiver chip-select input is required. RXD1 is not used. Data is shifted into the receiver on every active
clock edge.
• No preamble or postamble clocks will be transmitted. All signals return to the idle state after the frame phase
is finished.
• It is not possible to transmit in the SPI slave configuration because the FSI TXCLK cannot take an external
clock source.
7.14.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
Section 7.14.7.3.1.1 lists the FSITX SPI signaling mode switching characteristics. Figure 7-69 shows the FSITX
SPI signaling mode timings. Special timings are not required for the FSIRX in SPI signaling mode. FSIRX
timings listed in Section 7.14.7.2.1.1 are applicable in SPI compatibility mode. Setup and Hold times are only
valid on the falling edge of FSIRXCLK because this is the active edge in SPI signaling mode.
7.14.7.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
NO.
PARAMETER
MIN
MAX
20
UNIT
1
tc(TXCLK)
Cycle time, TXCLK
2
tw(TXCLK)
Pulse width, TXCLK low or TXCLK high
3
td(TXCLKH–TXD0)
Delay time, TXD0 valid after TXCLK high
4
td(TXD1-TXCLK)
Delay time, TXCLK high after TXD1 low
tw(TXCLK) – 3
ns
5
td(TXCLK-TXD1)
Delay time, TXD1 high after TXCLK low
tw(TXCLK)
ns
(0.5tc(TXCLK)) – 1
ns
(0.5tc(TXCLK)) + 1
ns
3
ns
7.14.7.3.1.2 FSITX SPI Signaling Mode Timings
1
2
FSITXCLK
3
FSITXD0
5
4
FSITXD1
Figure 7-69. FSITX SPI Signaling Mode Timings
148
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7.14.8 Host Interface Controller (HIC)
The HIC module allows an external host controller to directly access resources of the device by emulating the
ASRAM protocol. It has two modes of operation: direct access and mailbox access. In direct access mode,
device resources is written to and read from directly by the external host. In mailbox access mode, external host
and device write to and read from a buffer and notify each other when the buffer write/read is complete. For
security reasons, the HIC has to be enabled by the device before the external host can access it. Figure 7-70
shows the block diagram of the HIC.
Features of the HIC include:
•
•
•
•
•
•
•
•
Configurable I/O data lines of 8 bits and 16 bits
Direct and mailbox access modes
8 address lines and 8 configurable base addresses for a total of 2048 possible addressable regions
Two 64-byte buffers for external host and device when using mailbox access mode
Interrupt generation on buffer full/empty
High throughput
Trigger HIC activity from other peripherals
Error indicators to the system or interface
Legend
HIC Pins
HIC Registers
HIC
I/O Interface
A[7:0]
D[15:0]
A[31:0]
H2DINT to PIE
Memory Mapped HIC
Configuration Interface
nBE[1:0]
nCS
D2HINT to Pin
Host
To
Device
CTRL Regs
STATUS Regs
WDATA[31:0]
RDATA[31:0]
Device
To
Host
nWE
nOE
BASESEL[2:0]
Mailbox
Buffer
BASE_ADDR0
BASE_ADDR1
.
.
BASE_ADDRn
Mailbox
Buffer
nRDY
EVT_TRIGGER[15:0]
Figure 7-70. HIC Block Diagram
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7.14.8.1 HIC Electrical Data and Timing
Section 7.14.8.1.1 lists the HIC timing requirements. Section 7.14.8.1.2 lists the HIC switching characteristics.
Figure 7-71 shows the read/write operation with nOE and nWE pins. Figure 7-72 shows the read/write operation
with RnW pin.
7.14.8.1.1 HIC Timing Requirements
over operating free-air temperature range (unless otherwise noted)
REFID
MIN
MAX UNIT
Read/Write Parameters with nOE and nWE pins - Dual Read/Write pins
T1
tsu(ABBV-OEV)
Setup time, A/BASESEL/nBE before nOE active
0
ns
T2
tsu(ABBV-WEV)
Setup time, A/BASESEL/nBE before nWE active
0
ns
T3
tsu(CSV-OEV)
Setup time, nCS active before nOE active
0.5tc(SYSCLK)
ns
T4
tsu(CSV-WEV)
Setup time, nCS active before nWE active
0.5tc(SYSCLK)
ns
T5
th(ABBV-OEIV)
Hold time, A/BASESEL/nBE/nCS after nOE inactive
6
ns
T6
th(ABBV-WEIV)
Hold time, A/BASESEL/nBE/nCS after nWE inactive
6
ns
4tc(SYSCLK)
ns
4tc(SYSCLK)
ns
(Read)(1)
T7
tw(OEV)
Active pulse width of nOE
T8
tw(WEV)
Active pulse width of nWE (Write)
nCS(2)
T9
tw(CSIV)
Inactive pulse width of
3tc(SYSCLK)
ns
T10
tw(OEIV)
Inactive Read pulse width of nOE(2)
3tc(SYSCLK)
ns
T11
tw(WEIV)
Inactive Write pulse width of
nWE(2)
3tc(SYSCLK)
ns
T12
tsu(DV-WEV)
Setup time, D before nWE active
0
ns
T13
th(DV-WEIV)
Hold time, D after nWE inactive
6
ns
Read/Write Parameters with RnW pin - Single Read/Write pin
T14
tsu(ABBV-CSV)
Setup time, A/BASESEL/nBE before nCS active
T15
tsu(RNWV-CSV)
Setup time, RnW before nCS active
T16
th(ABBV-CSIV)
Hold time, A/BASESEL/nBE/RnW after nCS inactive
T17
tw(CSV_RD)
Active pulse width of nCS for read operation(1)
0
ns
0.5tc(SYSCLK)
ns
6
ns
4tc(SYSCLK)
ns
T18
tw(CSV_WR)
Active pulse width of nCS for write operation
4tc(SYSCLK)
ns
T19
tw(CSIV)
Inactive pulse width of nCS(2)
3tc(SYSCLK)
ns
RnW(2)
T20
tw(RNWIV)
Inactive pulse width of
3tc(SYSCLK)
ns
T21
tsu(DV-CSV)
Setup time, D before nCS active
0
ns
T22
th(DV-CSIV)
Hold time, D after nCS inactive
5
ns
(1)
(2)
150
For accesses to the device region, additional 2 SYSCLK cycles are required.
For accesses to the device region with nRDY pin, additional SYSCLK cycle is required.
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7.14.8.1.2 HIC Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
REFID
PARAMETER
MIN
MAX UNIT
Read/Write Parameters with nOE and nWE pins
S1
td(OEV-DV)
Output data delay time : nOE to D output valid (1)
3tc(SYSCLK)
4tc(SYSCLK) + 14
ns
S2
td(OEIV-DIV)
Output data hold time : nOE invalid to D output invalid (tri-state)
1tc(SYSCLK)
2tc(SYSCLK) + 14
ns
S3
td(OEV-RDYV)
Read Ready delay time : nOE to nRDY output valid
0
11
ns
S4
td(WEV-RDYV)
Write Ready delay time : nWE to nRDY output valid
0
11
ns
-3
3
S5
td(RDYV-DV)
Ready to Data delay time : nRDY output valid to D output valid
S6
tw(RDYACT)
Active pulse width of nRDY output
2tc(SYSCLK)
ns
ns
Read/Write Parameters with RnW pin
td(CSV-DV)
Output delay time : nCS active to D output valid (1)
3tc(SYSCLK)
4tc(SYSCLK) + 14
ns
S8
td(CSIV-DIV)
Output hold time : nCS inactive to D output invalid (tri-state)
1tc(SYSCLK)
2tc(SYSCLK) + 14
ns
S9
td(CSV-RDYV)
Output delay time : nCS to nRDY output valid
0
11
ns
-3
3
ns
S7
S10
td(RDYV-DV)
Ready to Data delay time : nRDY output valid to D output valid
S11
tw(RDYACT)
Active pulse width of nRDY output
(1)
2tc(SYSCLK)
ns
Applicable to mailbox accesses only. Direct memory map (Device) accesses are qualified with nRDY pin.
7.14.8.1.3 HIC Timing Diagrams
SETUP SIGNALS
T9
nCS
A[7:0]
BASESEL[2:0]
nBE[3:0]
READ SIGNALS
T1
T5
T3
T10
nOE
T7
S2
S1
D[15:0]
7
WRITE SIGNALS
T6
T2
T4
T11
nWE
T8
T12
T13
D[15:0]
S3
nRDY
READY/WAIT SIGNAL
S5
S6
S4
Figure 7-71. Read/Write Operation With nOE and nWE Pins
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SETUP SIGNALS
T19
nCS
T17 or T18
A[7:0]
BASESEL[2:0]
nBE[3:0]
T16
T14
READ SIGNALS
RnW
(Read)
T15
T20
S8
S7
D[15:0]
S10
WRITE SIGNALS
RnW
(Write)
T20
T15
T21
T22
D[15:0]
nRDY
READY/WAIT SIGNAL
S9
S11
Figure 7-72. Read/Write Operation With RnW Pin
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8 Detailed Description
8.1 Overview
C2000™ 32-bit microcontrollers are optimized for processing, sensing, and actuation to improve closed-loop
performance in real-time control applications such as industrial motor drives; solar inverters and digital power;
electrical vehicles and transportation; motor control; and sensing and signal processing.
The TMS320F28002x (F28002x) is a powerful 32-bit floating-point microcontroller unit (MCU) that lets designers
incorporate crucial control peripherals, differentiated analog, and nonvolatile memory on a single device.
The real-time control subsystem is based on TI’s 32-bit C28x CPU, which provides 100 MHz of signal processing
performance. The C28x CPU is further boosted by the new TMU extended instruction set, which enables fast
execution of algorithms with trigonometric operations commonly found in transforms and torque loop
calculations; and the VCRC extended instruction set, which reduces the latency for complex math operations
commonly found in encoded applications.
The F28002x supports up to 128KB (64KW) of flash memory in one bank. Up to 24KB (12KW) of on-chip SRAM
is also available in blocks of 4KB (2KW) for efficient system partitioning. Flash ECC, SRAM ECC/parity, and
dual-zone security are also supported.
High-performance analog blocks are integrated on the F28002x real-time MCU to further enable system
consolidation. Two separate 12-bit ADCs provide precise and efficient management of multiple analog signals,
which ultimately boosts system throughput. Four analog comparator modules provide continuous monitoring of
input voltage levels for trip conditions.
The TMS320C2000™ devices contain industry-leading control peripherals with frequency-independent ePWM/
HRPWM and eCAP allow for a best-in-class level of control to the system.
Connectivity is supported through various industry-standard communication ports (such as SPI, SCI, I2C,
PMBus, LIN, and CAN) and offers multiple muxing options for optimal signal placement in a variety of
applications. New to the C2000™ platform is Host Interface Controller (HIC), a high throughput interface that
allows an external host to access resources of the TMS320F28002x. Additionally, in an industry first, the FSI
enables high-speed, robust communication to complement the rich set of peripherals that are embedded in the
device.
A specially enabled device variant, TMS320F28002xC, allows access to the Configurable Logic Block (CLB) for
additional interfacing features and allows access to the secure ROM, which includes a library to enable
InstaSPIN-FOC™. See Table 5-1 for more information.
The Embedded Real-Time Analysis and Diagnostic (ERAD) module enhances the debug and system analysis
capabilities of the device by providing additional hardware breakpoints and counters for profiling.
To learn more about the C2000 real-time MCUs, visit the C2000™ real-time control MCUs page.
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8.2 Functional Block Diagram
Figure 8-1 shows the CPU system and associated peripherals.
Boot ROM
C28x CPU
Secure ROM
FPU32
FINTDIV
TMU
VCRC
Flash Bank0
16 Sectors
64 KW (128 KB)
Secure Memories
shown in Red
Bus Legend
CPU
DMA
HIC
BGCRC
CPU Timers
DCC
DCSM
ePIE
ERAD
M0-M1 RAM
2 KW (4 KB)
BGCRC
LS4-LS7 RAM
8 KW (16 KB)
Crystal Oscillator
INTOSC1, INTOSC2
PLL
HIC
GS0 RAM
2 KW (4 KB)
PF1
14x ePWM Chan.
(8 Hi-Res Capable)
14x ePWM Chan.
4x CMPSS
(8 Hi-Res Capable)
3x eCAP
3x eCAP
2x CLB
(1 HRCAP Capable) (1 HRCAP Capable)
2x eQEP
(CW/CCW Support)
PF3
Result
2x 12-Bit ADC
DMA
6 Channles
PF4
Data
PF2
PF7
PF8
PF9
1x PMBUS
1x CAN
2x LIN
1x SCI
39x GPIO
2x SPI
2x I2C
Input XBAR
1x FSI RX
Output XBAR
1x FSI TX
NMI
Watchdog
Windowed
Watchdog
ePWM XBAR
CLB XBAR
Figure 8-1. Functional Block Diagram
154
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8.3 Memory
8.3.1 Memory Map
The Memory Map table describes the memory map. See the Memory Controller Module section of the System
Control chapter in the TMS320F28002x Real-Time Microcontrollers Technical Reference Manual.
Table 8-1. Memory Map
SIZE
START
ADDRESS
END ADDRESS
HIC
ACCESS
DMA
ACCESS
ECC/
PARITY
ACCESS
PROTECTION
SECURITY
M0 RAM
1K x 16
0x0000 0000
0x0000 03FF
-
-
ECC
Yes
-
M1 RAM
1K x 16
0x0000 0400
0x0000 07FF
-
-
ECC
Yes
-
PieVectTable
512 x 16
0x0000 0D00
0x0000 0EFF
-
-
-
-
-
LS4 RAM
2K x 16
0x0000 A000
0x0000 A7FF
-
-
ECC
Yes
Yes
LS5 RAM
2K x 16
0x0000 A800
0x0000 AFFF
-
-
ECC
Yes
Yes
LS6 RAM
2K x 16
0x0000 B000
0x0000 B7FF
-
-
ECC
Yes
Yes
LS7 RAM
2K x 16
0x0000 B800
0x0000 BFFF
-
-
ECC
Yes
Yes
GS0 RAM
2K x 16
0x0000 C000
0x0000 C7FF
Yes
Yes
Parity
Yes
-
CAN A Message RAM
2K x 16
0x0004 9000
0x0004 97FF
-
-
Parity
-
-
TI OTP(1)
1K x 16
0x0007 0000
0x0007 03FF
-
-
ECC
-
-
User OTP
1K x 16
0x0007 8000
0x0007 83FF
-
-
ECC
-
Yes
Flash
64K x 16
0x0008 0000
0x0008 FFFF
-
-
ECC
-
Yes
Secure ROM
32K x 16
0x003E 8000
0x003E FFFF
-
-
Parity
-
Yes
Boot ROM
64K x 16
0x003F 0000
0x003F FFFF
-
-
Parity
-
-
Pie Vector Fetch Error
(part of Boot ROM)
1 x 16
0x003F FFBE
0x003F FFBF
-
-
Parity
-
-
Default Vectors
(part of Boot ROM)
64 x 16
0x003F FFC0
0x003F FFFF
-
-
Parity
-
-
MEMORY
(1)
TI OTP is for TI internal use only.
8.3.1.1 Dedicated RAM (Mx RAM)
The CPU subsystem has two dedicated ECC-capable RAM blocks: M0 and M1. These memories are small
nonsecure blocks that are tightly coupled with the CPU (that is, only the CPU has access to them).
8.3.1.2 Local Shared RAM (LSx RAM)
Local shared RAMs (LSx RAMs) are accessible to the CPU, HIC, and BGCRC. All LSx RAM blocks have ECC.
These memories are secure and have CPU access protection (CPU write/CPU fetch).
8.3.1.3 Global Shared RAM (GSx RAM)
Global shared RAMs (GSx RAMs) are accessible from the CPU, HIC, and DMA. The CPU, HIC, and DMA have
full read and write access to these memories. All GSx RAM blocks have parity. The GSx RAMs have access
protection (CPU write/CPU fetch/DMA write/HIC write).
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8.3.2 Flash Memory Map
On the F28002x devices one flash bank (128KB [64KW]) is available. Code to program the flash should be
executed out of RAM, there should not be any kind of access to the flash bank when an erase or program
operation is in progress. Table 8-2 lists the addresses of flash sectors available for each part number.
8.3.2.1 Addresses of Flash Sectors
Table 8-2. Addresses of Flash Sectors
PART NUMBER
SECTOR
ADDRESS
SIZE
ECC ADDRESS
START
END
SIZE
START
END
OTP Sectors
All F28002x
TI OTP
1K x 16
0x0007 0000
0x0007 03FF
128 x 16
0x0107 0000
0x0107 007F
DCSM OTP
1K x 16
0x0007 8000
0x0007 83FF
128 x 16
0x0107 1000
0x0107 107F
Sector 0
4K x 16
0x0008 0000
0x0008 0FFF
512 x 16
0x0108 0000
0x0108 01FF
Sector 1
4K x 16
0x0008 1000
0x0008 1FFF
512 x 16
0x0108 0200
0x0108 03FF
Sector 2
4K x 16
0x0008 2000
0x0008 2FFF
512 x 16
0x0108 0400
0x0108 05FF
Sector 3
4K x 16
0x0008 3000
0x0008 3FFF
512 x 16
0x0108 0600
0x0108 07FF
Sector 4
4K x 16
0x0008 4000
0x0008 4FFF
512 x 16
0x0108 0800
0x0108 09FF
Sector 5
4K x 16
0x0008 5000
0x0008 5FFF
512 x 16
0x0108 0A00
0x0108 0BFF
Sector 6
4K x 16
0x0008 6000
0x0008 6FFF
512 x 16
0x0108 0C00
0x0108 0DFF
Sector 7
4K x 16
0x0008 7000
0x0008 7FFF
512 x 16
0x0108 0E00
0x0108 0FFF
Sector 8
4K x 16
0x0008 8000
0x0008 8FFF
512 x 16
0x0108 1000
0x0108 11FF
Sector 9
4K x 16
0x0008 9000
0x0008 9FFF
512 x 16
0x0108 1200
0x0108 13FF
Sector 10
4K x 16
0x0008 A000
0x0008 AFFF
512 x 16
0x0108 1400
0x0108 15FF
Sector 11
4K x 16
0x0008 B000
0x0008 BFFF
512 x 16
0x0108 1600
0x0108 17FF
Sector 12
4K x 16
0x0008 C000
0x0008 CFFF
512 x 16
0x0108 1800
0x0108 19FF
Sector 13
4K x 16
0x0008 D000
0x0008 DFFF
512 x 16
0x0108 1A00
0x0108 1BFF
Sector 14
4K x 16
0x0008 E000
0x0008 EFFF
512 x 16
0x0108 1C00
0x0108 1DFF
Sector 15
4K x 16
0x0008 F000
0x0008 FFFF
512 x 16
0x0108 1E00
0x0108 1FFF
Bank 0 Sectors
All F28002x
F280025,
F280023
F280025
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TMS320F280025, TMS320F280025-Q1
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8.3.3 Peripheral Registers Memory Map
The Peripheral Registers Memory Map (C28x) table lists the peripheral registers.
Table 8-3. Peripheral Registers Memory Map (C28x)
Bit Field Name
Instance
Structure
DriverLib Name
Base Address
Pipeline
Protected
DMA
Access
HIC
Access
Peripheral Frame 0 (PF0)
AdcaResultRegs
ADC_RESULT_REGS
ADCARESULT_BASE
0x0000_0B00
-
YES
YES
AdccResultRegs
ADC_RESULT_REGS
ADCCRESULT_BASE
0x0000_0B40
-
YES
YES
CpuTimer0Regs
CPUTIMER_REGS
CPUTIMER0_BASE
0x0000_0C00
-
-
-
CpuTimer1Regs
CPUTIMER_REGS
CPUTIMER1_BASE
0x0000_0C08
-
-
-
CpuTimer2Regs
CPUTIMER_REGS
CPUTIMER2_BASE
0x0000_0C10
-
-
-
PieCtrlRegs
PIE_CTRL_REGS
PIECTRL_BASE
0x0000_0CE0
-
-
-
DmaRegs
DMA_REGS
DMA_BASE
0x0000_1000
-
-
-
Dmach1Regs
DMA_CH_REGS
DMA_CH1_BASE
0x0000_1020
-
-
-
Dmach2Regs
DMA_CH_REGS
DMA_CH2_BASE
0x0000_1040
-
-
-
Dmach3Regs
DMA_CH_REGS
DMA_CH3_BASE
0x0000_1060
-
-
-
Dmach4Regs
DMA_CH_REGS
DMA_CH4_BASE
0x0000_1080
-
-
-
Dmach5Regs
DMA_CH_REGS
DMA_CH5_BASE
0x0000_10A0
-
-
-
Dmach6Regs
DMA_CH_REGS
DMA_CH6_BASE
0x0000_10C0
-
-
-
YES
Peripheral Frame 1 (PF1)
Clb1LogicCfgRegs
CLB_LOGIC_CONFIG_REGS
CLB1_LOGICCFG_BASE
0x0000_3000
-
YES
Clb1LogicCtrlRegs
CLB_LOGIC_CONTROL_REGS
CLB1_LOGICCTRL_BASE
0x0000_3100
-
YES
YES
Clb1DataExchRegs
CLB_DATA_EXCHANGE_REGS
CLB1_DATAEXCH_BASE
0x0000_3180
-
YES
YES
Clb2LogicCfgRegs
CLB_LOGIC_CONFIG_REGS
CLB2_LOGICCFG_BASE
0x0000_3200
-
YES
YES
Clb1DataExchRegs
CLB_DATA_EXCHANGE_REGS
CLB1_DATAEXCH_BASE
0x0000_3300
-
YES
YES
Clb2LogicCfgRegs
CLB_LOGIC_CONFIG_REGS
CLB2_LOGICCFG_BASE
0x0000_3380
-
YES
YES
EPwm1Regs
EPWM_REGS
EPWM1_BASE
0x0000_4000
YES
YES
YES
EPwm2Regs
EPWM_REGS
EPWM2_BASE
0x0000_4100
YES
YES
YES
EPwm3Regs
EPWM_REGS
EPWM3_BASE
0x0000_4200
YES
YES
YES
EPwm4Regs
EPWM_REGS
EPWM4_BASE
0x0000_4300
YES
YES
YES
EPwm5Regs
EPWM_REGS
EPWM5_BASE
0x0000_4400
YES
YES
YES
EPwm6Regs
EPWM_REGS
EPWM6_BASE
0x0000_4500
YES
YES
YES
EPwm7Regs
EPWM_REGS
EPWM7_BASE
0x0000_4600
YES
YES
YES
EQep1Regs
EQEP_REGS
EQEP1_BASE
0x0000_5100
YES
YES
YES
EQep2Regs
EQEP_REGS
EQEP2_BASE
0x0000_5140
YES
YES
YES
ECap1Regs
ECAP_REGS
ECAP1_BASE
0x0000_5200
YES
YES
YES
ECap2Regs
ECAP_REGS
ECAP2_BASE
0x0000_5240
YES
YES
YES
ECap3Regs
ECAP_REGS
ECAP3_BASE
0x0000_5280
YES
YES
YES
Hrcap3Regs
HRCAP_REGS
HRCAP3_BASE
0x0000_52A0
YES
YES
YES
Cmpss1Regs
CMPSS_REGS
CMPSS1_BASE
0x0000_5C80
YES
YES
YES
Cmpss2Regs
CMPSS_REGS
CMPSS2_BASE
0x0000_5CA0
YES
YES
YES
Cmpss3Regs
CMPSS_REGS
CMPSS3_BASE
0x0000_5CC0
YES
YES
YES
Cmpss4Regs
CMPSS_REGS
CMPSS4_BASE
0x0000_5CE0
YES
YES
YES
Peripheral Frame 2 (PF2)
SpiaRegs
SPI_REGS
SPIA_BASE
0x0000_6100
YES
YES
YES
SpibRegs
SPI_REGS
SPIB_BASE
0x0000_6110
YES
YES
YES
BGCRC_REGS
BGCRC_CPU_BASE
0x0000_6340
YES
YES
YES
BgcrcCpuRegs
PmbusaRegs
PMBUS_REGS
PMBUSA_BASE
0x0000_6400
YES
YES
YES
HIC_CFG_REGS
HIC_BASE
0x0000_6500
YES
YES
YES
FsiTxaRegs
FSI_TX_REGS
FSITXA_BASE
0x0000_6600
YES
YES
YES
FsiRxaRegs
FSI_RX_REGS
FSIRXA_BASE
0x0000_6680
YES
YES
YES
HicRegs
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Table 8-3. Peripheral Registers Memory Map (C28x) (continued)
Bit Field Name
Instance
Structure
DriverLib Name
Base Address
Pipeline
Protected
DMA
Access
HIC
Access
Peripheral Frame 3 (PF3)
AdcaRegs
ADC_REGS
ADCA_BASE
0x0000_7400
YES
-
-
AdccRegs
ADC_REGS
ADCC_BASE
0x0000_7500
YES
-
-
-
Peripheral Frame 4 (PF4)
InputXbarRegs
INPUT_XBAR_REGS
INPUTXBAR_BASE
0x0000_7900
YES
-
XBAR_REGS
XBAR_BASE
0x0000_7920
YES
-
-
SYNC_SOC_REGS
SYNCSOC_BASE
0x0000_7940
YES
-
-
INPUT_XBAR_REGS
INPUTXBAR2_BASE
0x0000_7960
YES
-
-
DMA_CLA_SRC_SEL_REGS
DMACLASRCSEL_BASE
0x0000_7980
YES
-
-
EPWM_XBAR_REGS
EPWMXBAR_BASE
0x0000_7A00
YES
-
-
CLB_XBAR_REGS
CLBXBAR_BASE
0x0000_7A40
YES
-
-
OutputXbarRegs
OUTPUT_XBAR_REGS
OUTPUTXBAR_BASE
0x0000_7A80
YES
-
-
OutputXbar2Regs
OUTPUT_XBAR_REGS
OUTPUTXBAR2_BASE
0x0000_7BC0
YES
-
-
GPIO_CTRL_REGS
GPIOCTRL_BASE
0x0000_7C00
YES
-
-
GPIO_DATA_REGS
GPIODATA_BASE
0x0000_7F00
YES
-
-
GPIO_DATA_READ_REGS
GPIODATAREAD_BASE
0x0000_7F80
YES
-
YES
XbarRegs
SyncSocRegs
InputXbar2Regs
DmaClaSrcSelRegs
EPwmXbarRegs
ClbXbarRegs
GpioCtrlRegs
GpioDataRegs
GpioDataReadRegs
Peripheral Frame 5 (PF5)
DevCfgRegs
DEV_CFG_REGS
DEVCFG_BASE
0x0005_D000
YES
-
-
ClkCfgRegs
CLK_CFG_REGS
CLKCFG_BASE
0x0005_D200
YES
-
-
CpuSysRegs
CPU_SYS_REGS
CPUSYS_BASE
0x0005_D300
YES
-
-
PeriphAcRegs
PERIPH_AC_REGS
PERIPHAC_BASE
0x0005_D500
YES
-
-
AnalogSubsysRegs
ANALOG_SUBSYS_REGS
ANALOGSUBSYS_BASE
0x0005_D700
YES
-
-
DcsmBank0Z1Regs
DCSM_BANK0_Z1_REGS
DCSM_BANK0_Z1_BASE
0x0005_F000
YES
-
-
DcsmBank0Z2Regs
DCSM_BANK0_Z2_REGS
DCSM_BANK0_Z2_BASE
0x0005_F040
YES
-
-
DcsmCommonRegs
DCSM_COMMON_REGS
DCSMCOMMON_BASE
0x0005_F070
YES
-
-
DcsmCommon2Regs
DCSM_COMMON2_REGS
DCSMCOMMON2_BASE
0x0005_F080
YES
-
-
Peripheral Frame 6 (PF6)
MemCfgRegs
MEM_CFG_REGS
MEMCFG_BASE
0x0005_F400
YES
-
-
ACCESSPROTECTION_REGS
ACCESSPROTECTION_BASE
0x0005_F500
YES
-
-
MemoryErrorRegs
MEMORY_ERROR_REGS
MEMORYERROR_BASE
0x0005_F540
YES
-
-
RomWaitStateRegs
ROM_WAIT_STATE_REGS
ROMWAITSTATE_BASE
0x0005_F580
YES
-
-
RomPrefetchRegs
ROM_PREFETCH_REGS
ROMPREFETCH_BASE
0x0005_F588
YES
-
-
Flash0CtrlRegs
FLASH_CTRL_REGS
FLASH0CTRL_BASE
0x0005_F800
YES
-
-
Flash0EccRegs
FLASH_ECC_REGS
FLASH0ECCREGS_BASE
0x0005_FB00
YES
-
-
AccessProtectionRegs
Peripheral Frame 7 (PF7)
CanaRegs
CAN_REGS
CANA_BASE
0x0004_8000
YES
YES
YES
CanaMboxRegs
CAN_MBOX
CANAMBOX_BASE
0x0004_9000
YES
YES
YES
HwbistRegs
HWBIST_REGS
HWBIST_BASE
0x0005_E000
YES
-
-
MpostRegs
MPOST_REGS
MPOST_BASE
0x0005_E200
YES
-
-
Dcc0Regs
DCC_REGS
DCC0_BASE
0x0005_E700
YES
-
-
Dcc1Regs
DCC_REGS
DCC1_BASE
0x0005_E740
YES
-
-
ERAD_GLOBAL_REGS
ERADGLOBAL_BASE
0x0005_E800
YES
-
-
EradHWBP1Regs
ERAD_HWBP_REGS
ERADHWBP1_BASE
0x0005_E900
YES
-
-
EradHWBP2Regs
ERAD_HWBP_REGS
ERADHWBP2_BASE
0x0005_E908
YES
-
-
EradHWBP3Regs
ERAD_HWBP_REGS
ERADHWBP3_BASE
0x0005_E910
YES
-
-
EradHWBP4Regs
ERAD_HWBP_REGS
ERADHWBP4_BASE
0x0005_E918
YES
-
-
EradHWBP5Regs
ERAD_HWBP_REGS
ERADHWBP5_BASE
0x0005_E920
YES
-
-
EradHWBP6Regs
ERAD_HWBP_REGS
ERADHWBP6_BASE
0x0005_E928
YES
-
-
EradHWBP7Regs
ERAD_HWBP_REGS
ERADHWBP7_BASE
0x0005_E930
YES
-
-
EradGlobalRegs
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TMS320F280025, TMS320F280025-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
Table 8-3. Peripheral Registers Memory Map (C28x) (continued)
Bit Field Name
Instance
Structure
DriverLib Name
Base Address
Pipeline
Protected
DMA
Access
HIC
Access
EradHWBP8Regs
ERAD_HWBP_REGS
ERADHWBP8_BASE
0x0005_E938
YES
-
-
EradCounter1Regs
ERAD_COUNTER_REGS
ERADCOUNTER1_BASE
0x0005_E980
YES
-
-
EradCounter2Regs
ERAD_COUNTER_REGS
ERADCOUNTER2_BASE
0x0005_E990
YES
-
-
EradCounter3Regs
ERAD_COUNTER_REGS
ERADCOUNTER3_BASE
0x0005_E9A0
YES
-
-
EradCounter4Regs
ERAD_COUNTER_REGS
ERADCOUNTER4_BASE
0x0005_E9B0
YES
-
-
ERAD_CRC_GLOBAL_REGS
ERADCRCGLOBAL_BASE
0x0005_EA00
YES
-
-
EradCRC1Regs
ERAD_CRC_REGS
ERADCRC1_BASE
0x0005_EA10
YES
-
-
EradCRC2Regs
ERAD_CRC_REGS
ERADCRC2_BASE
0x0005_EA20
YES
-
-
EradCRC3Regs
ERAD_CRC_REGS
ERADCRC3_BASE
0x0005_EA30
YES
-
-
EradCRC4Regs
ERAD_CRC_REGS
ERADCRC4_BASE
0x0005_EA40
YES
-
-
EradCRC5Regs
ERAD_CRC_REGS
ERADCRC5_BASE
0x0005_EA50
YES
-
-
EradCRC6Regs
ERAD_CRC_REGS
ERADCRC6_BASE
0x0005_EA60
YES
-
-
EradCRC7Regs
ERAD_CRC_REGS
ERADCRC7_BASE
0x0005_EA70
YES
-
-
EradCRC8Regs
ERAD_CRC_REGS
ERADCRC8_BASE
0x0005_EA80
YES
-
-
EradCRCGlobalRegs
Peripheral Frame 8 (PF8)
LinaRegs
LIN_REGS
LINA_BASE
0x0000_6A00
YES
YES
YES
LinbRegs
LIN_REGS
LINB_BASE
0x0000_6B00
YES
YES
YES
WD_BASE
0x0000_7000
YES
-
YES
Peripheral Frame 9 (PF9)
WdRegs
NmiIntruptRegs
WD_REGS
NMI_INTRUPT_REGS
NMI_BASE
0x0000_7060
YES
-
YES
XintRegs
XINT_REGS
XINT_BASE
0x0000_7070
YES
-
YES
SciaRegs
SCI_REGS
SCIA_BASE
0x0000_7200
YES
-
YES
I2caRegs
I2C_REGS
I2CA_BASE
0x0000_7300
YES
-
YES
I2cbRegs
I2C_REGS
I2CB_BASE
0x0000_7340
YES
-
YES
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8.4 Identification
Table 8-4 lists the Device Identification Registers. Additional information on these device identification registers
can be found in the TMS320F28002x Real-Time Microcontrollers Technical Reference Manual.
Table 8-4. Device Identification Registers
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
Device part identification number
PARTIDH
0x0005 D00A
2
TMS320F280025
0x04FF 0500
TMS320F280025C
0x04FF 0500
TMS320F280023
0x04FD 0500
TMS320F280023C
0x04FD 0500
TMS320F280021
0x04FB 0500
Silicon revision number
REVID
UID_UNIQUE
160
0x0005 D00C
0x0007 01F4
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2
2
Revision 0
0x0000 0000
Revision A
0x0000 0001
Unique identification number. This number is different on each
individual device with the same PARTIDH. This unique number
can be used as a serial number in the application. This number
is present only on TMS devices.
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TMS320F280025, TMS320F280025-Q1
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
8.5 Bus Architecture – Peripheral Connectivity
The Peripheral Connectivity table lists a broad view of the peripheral and configuration register accessibility from
each bus master.
Table 8-5. Peripheral Connectivity
PERIPHERAL
C28
DMA
HIC
BGCRC
SYSTEM PERIPHERALS
CPU Timers
Y
ERAD
Y
GPIO Data
Y
GPIO Pin Mapping and Configuration
Y
XBAR Configuration
Y
System Configuration
Y
DCC
Y
Y
MEMORY
M0/M1
Y
Y
LSx
Y
Y
GS0
Y
ROM
Y
FLASH
Y
Y
Y
Y
Y
CONTROL PERIPHERALS
ePWM/HRPWM
Y
Y
Y
eCAP
Y
Y
Y
Y
Y
Y
CMPSS(1)
Y
Y
Y
ADC Configuration
Y
Y
Y
eQEP(1)
ANALOG PERIPHERALS
ADC Results(1)
Y
COMMUNICATION PERIPHERALS
CAN
Y
Y
Y
FSITX/FSIRX
Y
Y
Y
I2C
Y
LIN
Y
Y
Y
PMBus
Y
Y
Y
SCI
Y
SPI
Y
(1)
Y
Y
Y
Y
These modules are accessible from DMA but cannot trigger a DMA transfer.
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SPRSP45B – MARCH 2020 – REVISED DECEMBER 2020
8.6 C28x Processor
The CPU is a 32-bit fixed-point processor. This device draws from the best features of digital signal processing;
reduced instruction set computing (RISC); and microcontroller architectures, firmware, and tool sets.
The CPU features include a modified Harvard architecture and circular addressing. The RISC features are
single-cycle instruction execution, register-to-register operations, and modified Harvard architecture. The
microcontroller features include ease of use through an intuitive instruction set, byte packing and unpacking, and
bit manipulation. The modified Harvard architecture of the CPU enables instruction and data fetches to be
performed in parallel. The CPU can read instructions and data while it writes data simultaneously to maintain the
single-cycle instruction operation across the pipeline. The CPU does this over six separate address/data buses.
For more information on CPU architecture and instruction set, see the TMS320C28x CPU and Instruction Set
Reference Guide. For more information on the C28x Floating Point Unit (FPU), Trigonometric Math Unit, and
Cyclic Redundancy Check (VCRC) instruction sets, see the TMS320C28x Extended Instruction Sets Technical
Reference Manual. A brief overview of the FPU, TMU, and VCRC are provided here.
8.6.1 Floating-Point Unit (FPU)
The C28x plus floating-point (C28x+FPU) processor extends the capabilities of the C28x fixed-point CPU by
adding registers and instructions to support IEEE single-precision floating-point operations.
Devices with the C28x+FPU include the standard C28x register set plus an additional set of floating-point unit
registers. The additional floating-point unit registers are the following:
• Eight floating-point result registers, RnH (where n = 0–7)
• Floating-point Status Register (STF)
• Repeat Block Register (RB)
All of the floating-point registers, except the RB, are shadowed. This shadowing can be used in high-priority
interrupts for fast context save and restore of the floating-point registers.
8.6.2 Fast Integer Division Unit
The Fast Integer Division (FINTDIV) unit of the C28x CPU uniquely supports three types of integer division
(Truncated, Modulus, Euclidean) of varying data type sizes (16/16, 32/16, 32/32, 64/32, 64/64) in unsigned or
signed formats.
• Truncated integer division is naturally supported by C language (/, % operators).
• Modulus and Euclidean divisions are variants that are more efficient for control algorithms and are supported
by C intrinsics.
All three types of integer division produce both a quotient and remainder component, are interruptible, and
execute in a minimum number of deterministic cycles (10 cycles for a 32/32 division). In addition, the Fast
Division capabilities of the C28x CPU uniquely support fast execution of floating-point 32-bit (in 5 cycles) and 64bit (in 20 cycles) division.
For more information about fast integer division, see the Fast Integer Division – A Differentiated Offering From
C2000™ Product Family Application Report.
162
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8.6.3 Trigonometric Math Unit (TMU)
The TMU extends the capabilities of a C28x+FPU by adding instructions and leveraging existing FPU
instructions to speed up the execution of common trigonometric and arithmetic operations listed in Table 8-6.
Table 8-6. TMU Supported Instructions
INSTRUCTIONS
C EQUIVALENT OPERATION
PIPELINE CYCLES
MPY2PIF32 RaH,RbH
a = b * 2pi
2/3
DIV2PIF32 RaH,RbH
a = b / 2pi
2/3
DIVF32 RaH,RbH,RcH
a = b/c
5
SQRTF32 RaH,RbH
a = sqrt(b)
5
SINPUF32 RaH,RbH
a = sin(b*2pi)
4
COSPUF32 RaH,RbH
a = cos(b*2pi)
4
ATANPUF32 RaH,RbH
a = atan(b)/2pi
4
QUADF32 RaH,RbH,RcH,RdH
Operation to assist in calculating ATANPU2
5
No changes have been made to existing instructions, pipeline or memory bus architecture. All TMU instructions
use the existing FPU register set (R0H to R7H) to carry out their operations.
Exponent instruction IEXP2F32 and logarithmic instruction LOG2F32 have been added to support computation
of floating-point power function for the non-linear proportional integral derivative control (NLPID) component of
the C2000 Digital Control Library. These two added instructions reduce the power function calculations from a
typical of 300 cycles using library emulation to less than 10 cycles.
8.6.4 VCRC Unit
Cyclic redundancy check (CRC) algorithms provide a straightforward method for verifying data integrity over
large data blocks, communication packets, or code sections. The C28x+VCRC can perform 8-bit, 16-bit, 24-bit,
and 32-bit CRCs. For example, the VCRC can compute the CRC for a block length of 10 bytes in 10 cycles. A
CRC result register contains the current CRC, which is updated whenever a CRC instruction is executed.
The following are the CRC polynomials used by the CRC calculation logic of the VCRC:
• CRC8 polynomial = 0x07
• CRC16 polynomial 1 = 0x8005
• CRC16 polynomial 2 = 0x1021
• CRC24 polynomial = 0x5d6dcb
• CRC32 polynomial 1 = 0x04c11db7
• CRC32 polynomial 2 = 0x1edc6f41
This module can calculate CRCs for a byte of data in a single cycle. The CRC calculation for CRC8, CRC16,
CRC24, and CRC32 is done byte-wise (instead of computing on a complete 16-bit or 32-bit data read by the
C28x core) to match the byte-wise computation requirement mandated by various standards.
The VCRC Unit also allows the user to provide the size (1b-32b) and value of any polynomial to fit custom CRC
requirements. The CRC execution time increases to three cycles when using a custom polynomial.
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8.7 Embedded Real-Time Analysis and Diagnostic (ERAD)
The ERAD module enhances the debug and system-analysis capabilities of the device. The debug and systemanalysis enhancements provided by the ERAD module is done outside of the CPU. The ERAD module consists
of the Enhanced Bus Comparator units and the System Event Counter units. The Enhanced Bus Comparator
units are used to generate hardware breakpoints, hardware watch points, and other output events. The System
Event Counter units are used to analyze and profile the system. The ERAD module is accessible by the
debugger and by the application software, which significantly increases the debug capabilities of many real-time
systems, especially in situations where debuggers are not connected. In the TMS320F28002x devices, the
ERAD module contains eight Enhanced Bus Comparator units (which increases the number of Hardware
breakpoints from two to ten) and four Benchmark System Event Counter units.
8.8 Background CRC-32 (BGCRC)
The Background CRC (BGCRC) module computes a CRC-32 on a configurable block of memory. It
accomplishes this by fetching the specified block of memory during idle cycles (when the CPU, HIC, or DMA is
not accessing the memory block). The calculated CRC-32 value is compared against a golden CRC-32 value to
indicate a pass or fail. In essence, the BGCRC helps identify memory faults and corruption.
The BGCRC module has the following features:
• One cycle CRC-32 computation on 32 bits of data
• No CPU bandwidth impact for zero wait state memory
• Minimal CPU bandwidth impact for non-zero wait state memory
• Dual operation modes (CRC-32 mode and scrub mode)
• Watchdog timer to time CRC-32 completion
• Ability to pause and resume CRC-32 computation
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8.9 Direct Memory Access (DMA)
The DMA module provides a hardware method of transferring data between peripherals and/or memory without
intervention from the CPU, thereby freeing up bandwidth for other system functions. Additionally, the DMA has
the capability to orthogonally rearrange the data as it is transferred as well as “ping-pong” data between buffers.
These features are useful for structuring data into blocks for optimal CPU processing. Figure 8-2 shows a
device-level block diagram of the DMA.
DMA features include:
• Six channels with independent PIE interrupts
• Peripheral interrupt trigger sources
– ADC interrupts and EVT signals
– External Interrupts
– ePWM SOC signals
– CPU timers
– eCAP
– SPI transmit and receive
– CAN transmit and receive
– LIN transmit and receive
• Data sources and destinations:
– GSx RAM
– ADC result registers
– Control peripheral registers (ePWM, eQEP, eCAP)
– SPI, LIN, CAN, and PMBus registers
• Word Size: 16-bit or 32-bit (SPI limited to 16-bit)
• Throughput: Four cycles per word without arbitration
CAN
LIN
ADC
WRAPPER
ADC
RESULTS
XINT
TIMER
Global Shared
(GS0) RAM
C28x bus
CMPSS
eQEP
TINT(0-2)
XINT(1-5)
ADCx.INT(1-5), ADCx.EVT
CANxIF(1-3)
ECAP(1-3)DMA
EPWM(1-7).SOCA, EPWM(1-7.SOCB
SPITXDMA(A-B), SPIRXDMA(A-B)
FSITXADMA, FSIRXADMA
eCAP
EPWM
SPI
PMBUS
DMA Trigger
Source Selection
DMACHSRCSEL1.CHx
DMACHSRCSEL2.CHx
CHx.MODE.PERINTSEL
(x = 1 to 6)
DMA
DMA_CHx(1-6)
DMA bus
C28x
PIE
FSI
Figure 8-2. DMA Block Diagram
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8.10 Device Boot Modes
This section explains the default boot modes, as well as all the available boot modes supported on this device.
The boot ROM uses the boot mode select, general-purpose input/output (GPIO) pins to determine the boot
mode configuration.
Table 8-7 shows the boot mode options available for selection by the default boot mode select pins. Users have
the option to program the device to customize the boot modes selectable in the boot-up table as well as the boot
mode select pin GPIOs used.
All the peripheral boot modes that are supported use the first instance of the peripheral module (SCIA, SPIA,
I2CA, CANA, and so forth). Whenever these boot modes are referred to in this chapter, such as SCI boot, it is
actually referring to the first module instance, which means the SCI boot on the SCIA port. The same applies to
the other peripheral boots.
See Section 7.11.2.2.2 and Figure 7-8 for tboot-flash, the boot ROM execution time to first instruction fetch in flash.
Table 8-7. Device Default Boot Modes
BOOT MODE
GPIO24
(DEFAULT BOOT MODE SELECT PIN 1)
GPIO32
(DEFAULT BOOT MODE SELECT PIN 0)
Parallel IO
0
0
SCI / Wait
(1)
Boot(1)
0
1
CAN
1
0
Flash
1
1
SCI boot mode can be used as a wait boot mode as long as SCI continues to wait for an 'A' or 'a' during the SCI autobaud lock
process.
8.10.1 Device Boot Configurations
This section details what boot configurations are available and how to configure them. This device supports from
0 boot mode select pins up to 3 boot mode select pins as well as from 1 configured boot mode up to 8
configured boot modes.
To change and configure the device from the default settings to custom settings for your application, use the
following process:
1. Determine all the various ways you want application to be able to boot. (For example: Primary boot option of
Flash boot for your main application, secondary boot option of CAN boot for firmware updates, tertiary boot
option of SCI boot for debugging, etc)
2. Based on the number of boot modes needed, determine how many boot mode select pins (BMSPs) are
required to select between your selected boot modes. (For example: 2 BMSPs are required to select between
3 boot mode options)
3. Assign the required BMSPs to a physical GPIO pin. (For example, BMSP0 to GPIO10, BMSP1 to GPIO51,
and BMSP2 left as default which is disabled). Refer to Section 8.10.1.1 for all the details on performing these
configurations.
4. Assign the determined boot mode definitions to indexes in your custom boot table that correlate to the
decoded value of the BMSPs. For example, BOOTDEF0=Boot to Flash, BOOTDEF1=CAN Boot,
BOOTDEF2=SCI Boot; all other BOOTDEFx are left as default/nothing). Refer to Section 8.10.1.2 for all the
details on setting up and configuring the custom boot mode table.
Additionally, the Boot Mode Example Use Cases section of the TMS320F28002x Real-Time Microcontrollers
Technical Reference Manual provides some example use cases on how to configure the BMSPs and custom
boot tables.
Note
The CAN boot mode turns on the XTAL. Be sure an XTAL is installed in the application before using
CAN boot mode.
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8.10.1.1 Configuring Boot Mode Pins
This section explains how the boot mode select pins can be customized by the user, by programming the
BOOTPIN-CONFIG location (refer to Table 8-8) in the user-configurable dual-zone security module (DCSM)
OTP. The location in the DCSM OTP is Z1-OTP-BOOTPIN-CONFIG or Z2-OTP-BOOTPIN-CONFIG. When
debugging, EMU-BOOTPIN-CONFIG is the emulation equivalent of Z1-OTP-BOOTPIN-CONFIG/Z2-OTPBOOTPIN-CONFIG, and can be programmed to experiment with different boot modes without writing to OTP.
The device can be programmed to use 0, 1, 2, or 3 boot mode select pins as needed.
Note
When using Z2-OTP-BOOTPIN-CONFIG, the configurations programmed in this location will take
priority over the configurations in Z1-OTP-BOOTPIN-CONFIG. It is recommended to use Z1-OTPBOOTPIN-CONFIG first and then if OTP configurations need to be altered, switch to using Z2-OTPBOOTPIN-CONFIG.
Table 8-8. BOOTPIN-CONFIG Bit Fields
BIT
NAME
DESCRIPTION
31:24
Key
23:16
Boot Mode Select Pin 2 (BMSP2)
Refer to BMSP0 description except for BMSP2
15:8
Boot Mode Select Pin 1 (BMSP1)
Refer to BMSP0 description except for BMSP1
Boot Mode Select Pin 0 (BMSP0)
Set to the GPIO pin to be used during boot (up to 255):
- 0x0 = GPIO0
- 0x01 = GPIO1
- and so on
Writing 0xFF disables BMSP0 and this pin is no longer used to select
the boot mode.
7:0
Write 0x5A to these 8-bits to indicate the bits in this register are valid
The following GPIOs cannot be used as a BMSP. If selected for a particular BMSP, the boot ROM automatically
selects the factory default GPIO (the factory default for BMSP2 is 0xFF, which disables the BMSP).
• GPIO 20 and GPIO 21
• GPIO 36 and GPIO 38
• GPIO 47 to GPIO 60
• GPIO 63 to GPIO 223
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Table 8-9. Standalone Boot Mode Select Pin Decoding
BOOTPIN_CONFIG
KEY
BMSP0
BMSP1
BMSP2
!= 0x5A
Don’t Care
Don’t Care
Don’t Care
0xFF
0xFF
0xFF
Boot as defined in the boot table for boot mode
0
(All BMSPs disabled)
Valid GPIO
0xFF
0xFF
Boot as defined by the value of BMSP0
(BMSP1 and BMSP2 disabled)
0xFF
Valid GPIO
0xFF
Boot as defined by the value of BMSP1
(BMSP0 and BMSP2 disabled)
0xFF
0xFF
Valid GPIO
Boot as defined by the value of BMSP2
(BMSP0 and BMSP1 disabled)
Valid GPIO
Valid GPIO
0xFF
Boot as defined by the values of BMSP0 and
BMSP1
(BMSP2 disabled)
Valid GPIO
0xFF
Valid GPIO
Boot as defined by the values of BMSP0 and
BMSP2
(BMSP1 disabled)
0xFF
Valid GPIO
Valid GPIO
Boot as defined by the values of BMSP1 and
BMSP2
(BMSP0 disabled)
Valid GPIO
Valid GPIO
Valid GPIO
Boot as defined by the values of BMSP0,
BMSP1, and BMSP2
= 0x5A
REALIZED BOOT MODE
Boot as defined by the factory default BMSPs
Invalid GPIO
Valid GPIO
Valid GPIO
BMSP0 is reset to the factory default BMSP0
GPIO
Boot as defined by the values of BMSP0,
BMSP1, and BMSP2
Valid GPIO
Invalid GPIO
Valid GPIO
BMSP1 is reset to the factory default BMSP1
GPIO
Boot as defined by the values of BMSP0,
BMSP1, and BMSP2
Invalid GPIO
BMSP2 is reset to the factory default state,
which is disabled
Boot as defined by the values of BMSP0 and
BMSP1
Valid GPIO
Valid GPIO
Note
When decoding the boot mode, BMSP0 is the least-significant-bit and BMSP2 is the most-significantbit of the boot table index value. It is recommended when disabling BMSPs to start with disabling
BMSP2. For example, in an instance when only using BMSP2 (BMSP1 and BMSP0 are disabled),
then only the boot table indexes of 0 and 4 will be selectable. In the instance when using only BMSP0,
then the selectable boot table indexes are 0 and 1.
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8.10.1.2 Configuring Boot Mode Table Options
This section explains how to configure the boot definition table, BOOTDEF, for the device and the associated
boot options. The 64-bit location is located in user-configurable DCSM OTP in the Z1-OTP-BOOTDEF-LOW and
Z1-OTP-BOOTDEF-HIGH locations. When debugging, EMU-BOOTDEF-LOW and EMU-BOOTDEF-HIGH are
the emulation equivalents of Z1-OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH, and can be programmed
to experiment with different boot mode options without writing to OTP. The range of customization to the boot
definition table depends on how many boot mode select pins (BMSP) are being used. For example, 0 BMSPs
equals to 1 table entry, 1 BMSP equals to 2 table entries, 2 BMSPs equals to 4 table entries, and 3 BMSPs
equals to 8 table entries. Refer to the TMS320F28002x Real-Time Microcontrollers Technical Reference Manual
for examples on how to set up the BOOTPIN_CONFIG and BOOTDEF values.
Note
The locations Z2-OTP-BOOTDEF-LOW and Z2-OTP-BOOTDEF-HIGH will be used instead of Z1OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH locations when Z2-OTP-BOOTPIN-CONFIG is
configured. Refer to Configuring Boot Mode Pins for more details on BOOTPIN_CONFIG usage.
Table 8-10. BOOTDEF Bit Fields
BOOTDEF NAME
BYTE
POSITION
NAME
DESCRIPTION
Set the boot mode for index 0 of the boot table.
BOOT_DEF0
7:0
BOOT_DEF0 Mode/Options
Different boot modes and their options can include,
for example, a boot mode that uses different GPIOs
for a specific bootloader or a different flash entry
point address. Any unsupported boot mode will
cause the device to either go to wait boot or boot to
flash.
Refer to GPIO Assignments for valid BOOTDEF
values to set in the table.
BOOT_DEF1
15:8
BOOT_DEF1 Mode/Options
BOOT_DEF2
23:16
BOOT_DEF2 Mode/Options
BOOT_DEF3
31:24
BOOT_DEF3 Mode/Options
BOOT_DEF4
39:32
BOOT_DEF4 Mode/Options
BOOT_DEF5
47:40
BOOT_DEF5 Mode/Options
BOOT_DEF6
55:48
BOOT_DEF6 Mode/Options
BOOT_DEF7
63:56
BOOT_DEF7 Mode/Options
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8.10.2 GPIO Assignments
This section details the GPIOs and boot option values used for boot mode set in the BOOT_DEF memory
location located at Z1-OTP-BOOTDEF-LOW/ Z2-OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH/ Z2-OTPBOOTDEF-HIGH. Refer to Configuring Boot Mode Table Options on how to configure BOOT_DEF. When
selecting a boot mode option, make sure to verify that the necessary pins are available in the pin mux options for
the specific device package being used.
Table 8-11. SCI Boot Options
OPTION
BOOTDEF VALUE
SCITXDA GPIO
SCIRXDA GPIO
0 (default)
0x01
GPIO29
GPIO28
1
0x21
GPIO16
GPIO17
2
0x41
GPIO8
GPIO9
3
0x61
GPIO2
GPIO3
4
0x81
GPIO16
GPIO3
OPTION
BOOTDEF VALUE
CANTXA GPIO
CANRXA GPIO
0 (default)
0x02
GPIO4
GPIO5
1
0x22
GPIO32
GPIO33
2
0x42
GPIO2
GPIO3
OPTION
BOOTDEF VALUE
SDAA GPIO
SCLA GPIO
Table 8-12. CAN Boot Options
Table 8-13. I2C Boot Options
0
0x07
GPIO32
GPIO33
1
0x27
GPIO0
GPIO1
2
0x47
GPIO10
GPIO8
Table 8-14. RAM Boot Options
OPTION
BOOTDEF VALUE
RAM ENTRY POINT
(ADDRESS)
0
0x05
0x0000 0000
Table 8-15. Flash Boot Options
BOOTDEF VALUE
FLASH ENTRY POINT
(ADDRESS)
0 (default)
0x03
0x0008 0000
Bank0 Sector 0
1
0x23
0x0008 4000
Bank 0 Sector 4
2
0x43
0x0008 8000
Bank 0 Sector 8
3
0x63
0x0008 EFF0
Bank 0, End of Sector 14
OPTION
FLASH SECTOR
Table 8-16. Wait Boot Options
170
OPTION
BOOTDEF VALUE
0
0x04
Enabled
1
0x24
Disabled
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Table 8-17. SPI Boot Options
OPTION
BOOTDEF VALUE
SPISIMOA
SPISOMIA
SPICLKA
SPISTEA
0
0x06
GPIO2
GPIO1
GPIO3
GPIO5
1
0x26
GPIO16
GPIO1
GPIO3
GPIO0
2
0x46
GPIO8
GPIO10
GPIO9
GPIO11
3
0x66
GPIO8
GPIO17
GPIO9
GPIO11
Table 8-18. Parallel Boot Options
OPTION
BOOTDEF VALUE
D0-D7 GPIO
28x(DSP) CONTROL
GPIO
HOST CONTROL GPIO
0 (default)
0x00
D0 - GPIO28
GPIO16
GPIO29
GPIO16
GPIO11
D1 - GPIO1
D2 - GPIO2
D3 - GPIO3
D4 - GPIO4
D5 - GPIO5
D6 - GPIO6
D7 - GPIO7
1
0x20
D0 - GPIO0
D1 - GPIO1
D2 - GPIO2
D3 - GPIO3
D4 - GPIO4
D5 - GPIO5
D6 - GPIO6
D7 - GPIO7
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8.11 Dual Code Security Module
The dual code security module (DCSM) prevents access to on-chip secure memories. The term “secure” means
access to secure memories and resources is blocked. The term “unsecure” means access is allowed; for
example, through a debugging tool such as Code Composer Studio™ (CCS).
The code security mechanism offers protection for two zones, Zone 1 (Z1) and Zone 2 (Z2). The security
implementation for both the zones is identical. Each zone has its own dedicated secure resource (OTP memory
and secure ROM) and allocated secure resource (LSx RAM and flash sectors).
The security of each zone is ensured by its own 128-bit password (CSM password). The password for each zone
is stored in an OTP memory location based on a zone-specific link pointer. The link pointer value can be
changed to program a different set of security settings (including passwords) in OTP.
Code Security Module Disclaimer
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO
PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY AND IS
WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS
AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY
PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY
CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH
ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR
OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF
YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR
OTHER ECONOMIC LOSS.
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8.12 Watchdog
The watchdog module is the same as the one on previous TMS320C2000 devices, but with an optional lower
limit on the time between software resets of the counter. This windowed countdown is disabled by default, so the
watchdog is fully backward-compatible.
The watchdog generates either a reset or an interrupt. It is clocked from the internal oscillator with a selectable
frequency divider.
Figure 8-3 shows the various functional blocks within the watchdog module.
WDCR.WDPRECLKDIV
WDCR.WDPS
WDCR.WDDIS
WDCNTR
WDCLK
(INTOSC1)
Overflow
WDCLK
Divider
8-bit
Watchdog
Counter
Watchdog
Prescaler
1-count
delay
SYSRSn
Clear
Count
WDWCR.MIN
WDKEY (7:0)
WDCR(WDCHK(2:0))
Watchdog
Key Detector
55 + AA
Good Key
Out of Window
Watchdog
Window
Detector
Bad Key
WDRSTn
1
0
1
WDINTn
Generate
512-WDCLK
Output Pulse
Watchdog Time-out
SCSR.WDENINT
Figure 8-3. Windowed Watchdog
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8.13 C28x Timers
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The
timers have a 32-bit count-down register that generates an interrupt when the counter reaches zero. The counter
is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, it
is automatically reloaded with a 32-bit period value.
CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use and is
connected to INT13 of the CPU. CPU-Timer 2 is reserved for TI-RTOS. It is connected to INT14 of the CPU. If
TI-RTOS is not being used, CPU-Timer 2 is available for general use.
CPU-Timer 2 can be clocked by any one of the following:
• SYSCLK (default)
• Internal zero-pin oscillator 1 (INTOSC1)
• Internal zero-pin oscillator 2 (INTOSC2)
• X1 (XTAL)
8.14 Dual-Clock Comparator (DCC)
There are three Dual-Clock Comparators (DCC0 and DCC1) on the device. All three DCCs are only accessible
through CPU1. The DCC module is used for evaluating and monitoring the clock input based on a second clock,
which can be a more accurate and reliable version. This instrumentation is used to detect faults in clock source
or clock structures, thereby enhancing the system's safety metrics.
8.14.1 Features
The DCC has the following features:
• Allows the application to ensure that a fixed ratio is maintained between frequencies of two clock signals.
• Supports the definition of a programmable tolerance window in terms of the number of reference clock cycles.
• Supports continuous monitoring without requiring application intervention.
• Supports a single-sequence mode for spot measurements.
• Allows the selection of a clock source for each of the counters, resulting in several specific use cases.
8.14.2 Mapping of DCCx (DCC0 and DCC1) Clock Source Inputs
Table 8-19. DCCx Clock Source0 Table
DCCxCLKSRC0[3:0]
174
CLOCK NAME
0x0
XTAL/X1
0x1
INTOSC1
0x2
INTOSC2
0x5
CPU1.SYSCLK
0xC
INPUT XBAR (Output16 of input-xbar)
others
Reserved
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TMS320F280025, TMS320F280025-Q1
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Table 8-20. DCCx Clock Source1 Table
DCCxCLKSRC1[4:0]
CLOCK NAME
0x0
PLLRAWCLK
0x2
INTOSC1
0x3
INTOSC2
0x6
CPU1.SYSCLK
0x9
Input XBAR (Output15 of the input-xbar)
0xB
EPWMCLK
0xC
LSPCLK
0xD
ADCCLK
0xE
WDCLK
0xF
CAN0BITCLK
others
Reserved
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8.15 Configurable Logic Block (CLB)
The C2000 configurable logic block (CLB) is a collection of blocks that can be interconnected using software to
implement custom digital logic functions or enhance existing on-chip peripherals. The CLB is able to enhance
existing peripherals through a set of crossbar interconnections, which provide a high level of connectivity to
existing control peripherals such as enhanced pulse width modulators (ePWM), enhanced capture modules
(eCAP), and enhanced quadrature encoder pulse modules (eQEP). The crossbars also allow the CLB to be
connected to external GPIO pins. In this way, the CLB can be configured to interact with device peripherals to
perform small logical functions such as comparators, or to implement custom serial data exchange protocols.
Through the CLB, functions that would otherwise be accomplished using external logic devices can now be
implemented inside the MCU.
The CLB peripheral is configured through the CLB tool. For more information on the CLB tool, available
examples, application reports and users guide, please refer to the following location in your C2000Ware package
(C2000Ware_2_00_00_03 and higher):
C2000WARE_INSTALL_LOCATION\utilities\clb_tool\clb_syscfg\doc
CLB Tool User Guide
How to Design with the C2000™ CLB Application Report
How to Migrate Custom Logic From an FPGA/CPLD to C2000™ CLB Application Report
The CLB module and its interconnections are shown in Figure 8-4.
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Figure 8-4. CLB Overview
Absolute encoder protocol interfaces are now provided as Position Manager solutions in the C2000Ware
MotorControl SDK. Configuration files, application programmer interface (API), and use examples for such
solutions are provided with C2000Ware MotorControl SDK. In some solutions, the TI-configured CLB is used
with other on-chip resources, such as the SPI port or the C28x CPU, to perform more complex functionality.
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9 Applications, Implementation, and Layout
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 TI Reference Design
The TI Reference Design Library is a robust reference design library spanning analog, embedded processor,
and connectivity. Created by TI experts to help you jump start your system design, all reference designs include
schematic or block diagrams, BOMs, and design files to speed your time to market.
Check out our latest reference design based on F28002x, targeted for digital power applications: Two Phase
Interleaved LLC Resonant Converter Reference Design Using C2000™ MCUs.
Search and download other TI reference designs at Select TI reference designs.
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10 Device and Documentation Support
10.1 Getting Started and Next Steps
For a quick overview of the device, features, roadmap, comparisons to other devices, and package details, see
Texas Instruments C2000™ F28002x Real-Time Controller Series.
10.2 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320
MCU devices and support tools. Each TMS320™ MCU commercial family member has one of three prefixes:
TMX, TMP, or TMS (for example, TMS320F280025C). Texas Instruments recommends two of three possible
prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of
product development from engineering prototypes (with TMX for devices and TMDX for tools) through fully
qualified production devices and tools (with TMS for devices and TMDS for tools).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device's electrical specifications and
may not use production assembly flow.
TMP Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical
specifications.
TMS Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully-qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, PN) and temperature range (for example, S).
For device part numbers and further ordering information, see the TI website (www.ti.com) or contact your TI
sales representative.
For additional description of the device nomenclature markings on the die, see the TMS320F28002x Real-Time
MCUs Silicon Errata.
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320
F 280025C
(blank)
F 280025C
Generic Part Number: TMS
Orderable Part Number:
X
-Q1
PN
Q
R
(A)
PREFIX
TMX (X) = experimental device
TMS (blank) = qualified device
SHIPPING OPTIONS
(blank) = Tray
R = Tape and Reel
QUALIFICATION (in Generic Part Number)
blank = Non-Automotive
-Q1 = Q1 refers to Automotive AEC Q100 Grade 1 qualification.
DEVICE FAMILY
320 = TMS320 MCU Family
TEMPERATURE RANGE (in Orderable Part Number)
S = −40°C to 125°C (TJ)
Q = −40°C to 125°C (T )
TECHNOLOGY
F = Flash
A
PACKAGE TYPE
80-Pin PN Low-Profile Quad Flatpack (LQFP)
64-Pin PM LQFP
48-Pin PT LQFP
DEVICE
280025
280023
280021
280025C
280023C
A. Prefix X is used in orderable part numbers.
Figure 10-1. Device Nomenclature
10.3 Markings
Figure 10-2 and Figure 10-3 show the package symbolization. Table 10-1 lists the silicon revision codes.
F280025CPMS
$$#−YMLLLLS
G4
Package
Pin 1
F280025CPNS
$$#−YMLLLLS
G4
Package
Pin 1
YMLLLLS = Lot Trace Code
YM
LLLL
S
$$
#
=
=
=
=
=
2-Digit Year/Month Code
Assembly Lot
Assembly Site Code
Wafer Fab Code (one or two characters) as applicable
Silicon Revision Code
G4 = Green (Low Halogen and RoHS-compliant)
Figure 10-2. Package Symbolization for PM and PN Packages
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YMLLLLS = Lot Trace Code
980 PTS
F280025C
YMLLLLS
$$# G4
YM
LLLL
S
980
$$
#
=
=
=
=
=
=
2-Digit Year/Month Code
Assembly Lot
Assembly Site Code
TI E.I.A. Code
Wafer Fab Code (one or two characters) as applicable
Silicon Revision Code
G4 = Green (Low Halogen and RoHS-compliant)
Package
Pin 1
Figure 10-3. Package Symbolization for PT Package
Table 10-1. Revision Identification
SILICON REVISION CODE
SILICON REVISION
REVID(1)
ADDRESS: 0x5D00C
Blank
0
0x0000 0000
This silicon revision is available as TMX.
A
A
0x0000 0001
This silicon revision is available as TMX and
TMS.
(1)
COMMENTS
Silicon Revision ID
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10.4 Tools and Software
TI offers an extensive line of development tools. Some of the tools and software to evaluate the performance of
the device, generate code, and develop solutions follow. To view all available tools and software for C2000™
real-time control MCUs, visit the C2000 real-time control MCUs – Design & development page.
Development Tools
LAUNCHXL-F280025C
LAUNCHXL-F280025C is a low-cost development board for TI C2000™ Real-Time Controllers series of F28002x
devices. Ideal for initial evaluation and prototyping, it provides a standardized and easy-to-use platform to
develop your next application. This extended version LaunchPad™ development kit offers extra pins for
evaluation and supports the connection of two BoosterPack™ plug-in modules.
F280025 controlCARD
The F280025 controlCARD is an HSEC180 controlCARD based evaluation and development tool for the
C2000™ F28002x series of microcontroller products. controlCARDs are ideal to use for initial evaluation and
system prototyping. controlCARDs are complete board-level modules that utilize one of two standard form
factors (100-pin DIMM or 180-pin HSEC ) to provide a low-profile single-board controller solution. For first
evaluation controlCARDs are typically purchased bundled with a baseboard or bundled in an application kit.
TI Resource Explorer
To enhance your experience, be sure to check out the TI Resource Explorer to browse examples, libraries, and
documentation for your applications.
Software Tools
C2000Ware for C2000 MCUs
C2000Ware for C2000™ MCUs is a cohesive set of software and documentation created to minimize
development time. It includes device-specific drivers, libraries, and peripheral examples.
Digital Power SDK
Digital Power SDK is a cohesive set of software infrastructure, tools, and documentation designed to minimize
C2000 MCU-based digital power system development time targeted for various AC-DC, DC-DC and DC-AC
power supply applications. The software includes firmware that runs on C2000 digital power evaluation modules
(EVMs) and TI designs (TIDs), which are targeted for solar, telecom, server, electric vehicle chargers and
industrial power delivery applications. Digital Power SDK provides all the needed resources at every stage of
development and evaluation in a digital power applications.
Motor Control SDK
Motor Control SDK is a cohesive set of software infrastructure, tools, and documentation designed to minimize
C2000 MCU-based motor control system development time targeted for various three-phase motor control
applications. The software includes firmware that runs on C2000 motor control evaluation modules (EVMs) and
TI designs (TIDs), which are targeted for industrial drive and other motor control, Motor Control SDK provides all
the needed resources at every stage of development and evaluation for high-performance motor control
applications.
Code Composer Studio™ (CCS) Integrated Development Environment (IDE) for C2000 microcontrollers
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and
Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug
embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking the user
through each step of the application development flow. Familiar tools and interfaces allow users to get started
faster than ever before. Code Composer Studio combines the advantages of the Eclipse software framework
with advanced embedded debug capabilities from TI resulting in a compelling feature-rich development
environment for embedded developers.
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SysConfig System configuration tool
SysConfig is a comprehensive collection of graphical utilities for configuring pins, peripherals, radios,
subsystems, and other components. SysConfig helps you manage, expose and resolve conflicts visually so that
you have more time to create differentiated applications. The tool's output includes C header and code files that
can be used with software development kit (SDK) examples or used to configure custom software. The
SysConfig tool automatically selects the pinmux settings that satisfy the entered requirements. The SysConfig
tool is delivered integrated in CCS, as a standalone installer, or can be used via the dev.ti.com cloud tools portal.
For more information about the SysConfig system configuration tool, visit the System configuation tool page.
Models
Various models are available for download from the product Design & development pages. These models
include I/O Buffer Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL)
Models. To view all available models, visit the Design tools & simulation section of the Design & development
page for each device.
Training
To help assist design engineers in taking full advantage of the C2000 microcontroller features and performance,
TI has developed a variety of training resources. Utilizing the online training materials and downloadable handson workshops provides an easy means for gaining a complete working knowledge of the C2000 microcontroller
family. These training resources have been designed to decrease the learning curve, while reducing
development time, and accelerating product time to market. For more information on the various training
resources, visit the C2000™ real-time control MCUs – Support & training site.
The architecture and many of the peripherals of the F28002x are similar to those of the F28004x. The following
Workshop material and the Migration Between TMS320F28004x and TMS320F28002x Application Report will
cover the technical details of the TMS320F28004x architecture and highlight the device differences, which will be
helpful to users of the F28002x device.
Specific TMS320F28004x hands-on training resources can be found at C2000™ MCU Device Workshops.
Technical Introduction to the New C2000 TMS320F28004x Device Family
Many of the peripherals and architecture of the F28002x are similar to the F28004x. This presentation will cover
the technical details of the TMS320F28004x architecture and highlight the new improvements to various key
peripherals which will be helpful to users of the F28002x device.
10.5 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral
follows.
Errata
TMS320F28002x Real-Time MCUs Silicon Errata describes known advisories on silicon and provides
workarounds.
Technical Reference Manual
TMS320F28002x Real-Time Microcontrollers Technical Reference Manual details the integration, the
environment, the functional description, and the programming models for each peripheral and subsystem in the
F28002x real-time microcontrollers.
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CPU User's Guides
TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the
assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). This Reference
Guide also describes emulation features available on these DSPs.
TMS320C28x Extended Instruction Sets Technical Reference Manual describes the architecture, pipeline, and
instruction set of the TMU, VCU-II, and FPU accelerators.
Peripheral Guides
C2000 Real-Time Control Peripherals Reference Guide describes the peripheral reference guides of the 28x
DSPs.
Tools Guides
TMS320C28x Assembly Language Tools v20.8.0.STS User's Guide describes the assembly language tools
(assembler and other tools used to develop assembly language code), assembler directives, macros, common
object file format, and symbolic debugging directives for the TMS320C28x device.
TMS320C28x Optimizing C/C++ Compiler v20.8.0.STS User's Guide describes the TMS320C28x C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly
language source code for the TMS320C28x device.
Application Reports
The SMT & packaging application notes website lists documentation on TI’s surface mount technology (SMT)
and application notes on a variety of packaging-related topics.
Semiconductor Packing Methodology describes the packing methodologies employed to prepare semiconductor
devices for shipment to end users.
Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful lifetime
of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at general
engineers who wish to determine if the reliability of the TI EP meets the end system reliability requirement.
An Introduction to IBIS (I/O Buffer Information Specification) Modeling discusses various aspects of IBIS
including its history, advantages, compatibility, model generation flow, data requirements in modeling the input/
output structures, and future trends.
Serial Flash Programming of C2000™ Microcontrollers discusses using a flash kernel and ROM loaders for
serial programming a device.
Fast Integer Division – A Differentiated Offering From C2000™ Product Family provides an overview of the
different division and modulo (remainder) functions and its associated properties.
C2000™ Key Technology Guide provides a deeper look into the components that differentiate the C2000
Microcontroller Unit (MCU) as it pertains to Real-Time Control Systems.
Migration Between TMS320F28004x and TMS320F28002x describes the hardware and software differences to
be aware of when moving between F28004x and F28002x C2000™ MCUs.
TMS320F2802x/TMS320F2803x to TMS320F28002x Migration Overview describes the differences between the
Texas Instruments TMS320F2802x/TMS320F2803x and the TMS320F28002x microcontrollers for the purpose
of assisting with application migration.
10.6 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
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TMS320F280025, TMS320F280025-Q1
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10.7 Trademarks
C2000™, TMS320C2000™, InstaSPIN-FOC™, Code Composer Studio™, TMS320™, LaunchPad™,
BoosterPack™, TI E2E™ are trademarks of Texas Instruments.
Bosch® is a registered trademark of Robert Bosch GmbH Corporation.
All trademarks are the property of their respective owners.
10.8 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.9 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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11 Mechanical, Packaging, and Orderable Information
11.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
To learn more about TI packaging, visit the Packaging information website.
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Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TMS320F280025 TMS320F280025-Q1 TMS320F280025C TMS320F280025C-Q1
TMS320F280023 TMS320F280023-Q1 TMS320F280023C TMS320F280021 TMS320F280021-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
F280021PTQR
ACTIVE
LQFP
PT
48
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F280021
PTQ
F280021PTSR
ACTIVE
LQFP
PT
48
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F280021
PTS
F280023CPMSR
ACTIVE
LQFP
PM
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F280023CPMS
F280023CPNSR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F280023CPNS
F280023CPTSR
ACTIVE
LQFP
PT
48
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F280023C
PTS
F280023PMQR
ACTIVE
LQFP
PM
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F280023PMQ
F280023PMSR
ACTIVE
LQFP
PM
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F280023PMS
F280023PNQR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F280023PNQ
F280023PNSR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F280023PNS
F280023PTQR
ACTIVE
LQFP
PT
48
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F280023
PTQ
F280023PTSR
ACTIVE
LQFP
PT
48
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F280023
PTS
F280025CPMQR
ACTIVE
LQFP
PM
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F280025CPMQ
F280025CPMS
ACTIVE
LQFP
PM
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F280025CPMS
F280025CPMSR
ACTIVE
LQFP
PM
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F280025CPMS
F280025CPNQR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F280025CPNQ
F280025CPNSR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F280025CPNS
F280025CPTQR
ACTIVE
LQFP
PT
48
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F280025C
PTQ
F280025CPTSR
ACTIVE
LQFP
PT
48
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F280025C
PTS
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jan-2021
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
F280025PMQR
ACTIVE
LQFP
PM
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F280025PMQ
F280025PMS
ACTIVE
LQFP
PM
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F280025PMS
F280025PMSR
ACTIVE
LQFP
PM
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F280025PMS
F280025PNQR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F280025PNQ
F280025PNS
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F280025PNS
F280025PNSR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F280025PNS
F280025PTQR
ACTIVE
LQFP
PT
48
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F280025
PTQ
F280025PTS
ACTIVE
LQFP
PT
48
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F280025
PTS
F280025PTSR
ACTIVE
LQFP
PT
48
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F280025
PTS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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