F280039CSPZ

TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 TMS320F28003x Real-Time Microcontrollers 1 Features • • • • • • • TMS320C28x 32-bit DSP core at 120 MHz – IEEE 754 Floating-Point Unit (FPU) • Support for Fast Integer Division (FINTDIV) – Trigonometric Math Unit (TMU) • Support for Nonlinear Proportional Integral Derivative (NLPID) control – CRC Engine and Instructions (VCRC) – Ten hardware breakpoints (with ERAD) Programmable Control Law Accelerator (CLA) – 120 MHz – IEEE 754 single-precision floating-point instructions – Executes code independently of main CPU On-chip memory – 384KB (192KW) of flash (ECC-protected) across three independent banks – 69KB (34.5KW) of RAM (ECC-protected) – Dual-zone security – Secure Boot and JTAG Lock Clock and system control – Two internal 10-MHz oscillators – Crystal oscillator or external clock input – Windowed watchdog timer module – Missing clock detection circuitry – Dual-clock Comparator (DCC) 3.3-V I/O design – Internal VREG generation allows for singlesupply design – Brownout reset (BOR) circuit System peripherals – 6-channel Direct Memory Access (DMA) controller – 55 individually programmable multiplexed General-Purpose Input/Output (GPIO) pins – 23 digital inputs on analog pins – 2 digital inputs/outputs on analog pins (AGPIO) – Enhanced Peripheral Interrupt Expansion (ePIE) – Multiple low-power mode (LPM) support – Embedded Real-time Analysis and Diagnostic (ERAD) – Unique Identification (UID) number Communications peripherals – One Power-Management Bus (PMBus) interface – Two Inter-integrated Circuit (I2C) interfaces – One Controller Area Network (CAN/DCAN) bus port • • • • • • – One Controller Area Network with Flexible Data-Rate (CAN FD/MCAN) bus port – Two Serial Peripheral Interface (SPI) ports – Two UART-compatible Serial Communication Interface (SCI) – Two UART-compatible Local Interconnect Network (LIN) interfaces – Fast Serial Interface (FSI) with one transmitter and one receiver (up to 200Mbps) Analog system – Three 4-MSPS, 12-bit Analog-to-Digital Converters (ADCs) • Up to 23 external channels (includes the two gpdac outputs) • Four integrated Post-Processing Blocks (PPB) per ADC – Four windowed comparators (CMPSS) with 12-bit reference Digital-to-Analog Converters (DACs) • Digital glitch filters – Two 12-bit buffered DAC outputs Enhanced control peripherals – 16 ePWM channels with eight channels that have high-resolution capability (150-ps resolution) • Integrated dead-band support • Integrated hardware trip zones (TZs) – Three Enhanced Capture (eCAP) modules • High-resolution Capture (HRCAP) available on one of the three eCAP modules – Two Enhanced Quadrature Encoder Pulse (eQEP) modules with support for CW/CCW operation modes – Eight Sigma-Delta Filter Module (SDFM) input channels (two parallel filters per channel) • Standard SDFM data filtering • Comparator filter for fast action for overvalue or undervalue condition – Embedded Pattern Generator (EPG) Configurable Logic Block (CLB) – 4 tiles – Augments existing peripheral capability – Supports position manager solutions Host Interface Controller (HIC) – Access to internal memory from an external host Background CRC (BGCRC) – One cycle CRC computation on 32 bits of data Advanced Encryption Standard (AES) accelerator An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 • • • • • • Live Firmware Update (LFU) – Fast context switching from old to new firmware – Flash bank erase time improvements Diagnostic features – Memory Power On Self Test (MPOST) – Hardware Built-in Self Test (HWBIST) Functional Safety-Compliant targeted – Developed for functional safety applications – Documentation available to aid ISO 26262 and IEC 61508 system design – Systematic capability up to ASIL D and SIL 3 targeted – Hardware capability up to ASIL B and SIL 2 targeted Safety-related certification – ISO 26262 certification up to ASIL B and SIL 2 by TÜV SÜD planned Package options: – 100-pin Low-profile Quad Flatpack (LQFP) [PZ suffix] – 80-pin Low-profile Quad Flatpack (LQFP) [PN suffix] – 64-pin (LQFP) [PM suffix] – 48-pin (LQFP) [PT suffix] Temperature options: – Free-air (TA): –40°C to 125°C – Junction (TJ): –40°C to 150°C 2 Applications • • • • • • • • 2 Appliances – Air conditioner outdoor unit Building automation – Door operator drive control Industrial machine & machine tools – Automated sorting equipment – Textile machine AC inverter & VF drives – AC drive control module – AC drive position feedback – AC drive power stage module Linear motor transport systems – Linear motor power stage Single & multi axis servo drives – Servo drive position feedback – Servo drive power stage module Speed controlled BLDC drives – AC-input BLDC motor drive – DC-input BLDC motor drive Factory automation – Robot servo drive – Mobile robot motor control – Position sensor Submit Document Feedback • • • • • • • • • • • Industrial power – Industrial AC-DC UPS – Three phase UPS – Single phase online UPS Telecom & server power – Merchant DC/DC – Merchant network & server PSU – Merchant telecom rectifiers Hybrids, electric & powertrain systems – DC/DC converter – Inverter & motor control – On-board (OBC) & wireless charger – Virtual engine sound system (VESS) – Engine fan – eTurbo/charger – Pump – Electric power steering (EPS) Infotainment and cluster – Head-up display – Automotive head unit – Automotive external amplifier Body electronics & lighting – Automotive HVAC compressor module – DC/AC inverter – Headlight ADAS – Mechanically scanning LIDAR HEV/EV battery-management system (BMS) – 100-V battery pack-passive balancing – 12- & 24-V battery pack-passive balancing – 400-V battery pack-passive balancing – 48-V battery pack-passive balancing EV charging infrastructure – AC charging (pile) station – DC charging (pile) station – EV charging station power module – Wireless EV charging station Renewable energy storage – Energy storage power conversion system (PCS) Solar energy – Central inverter – Micro inverter – Solar power optimizer – Solar arc protection – Rapid shutdown – String inverter Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 3 Description The TMS320F28003x (F28003x) is a member of the C2000™ real-time microcontroller family of scalable, ultralow latency devices designed for efficiency in power electronics, including but not limited to: high power density, high switching frequencies, and supporting the use of GaN and SiC technologies. These include such applications as: • • • • • • • Motor drives Appliances Hybrid, electric & powertrain systems Solar & EV charging Digital power Body electronics & lighting Test & measurement The real-time control subsystem is based on TI’s 32-bit C28x DSP core, which provides 120 MHz of signalprocessing performance for floating- or fixed-point code running from either on-chip flash or SRAM. The C28x CPU is further boosted by the Floating-Point Unit (FPU), Trigonometric Math Unit (TMU), and VCRC (Cyclical Redundancy Check) extended instruction sets, speeding up common algorithms key to real-time control systems. The CLA allows significant offloading of common tasks from the main C28x CPU. The CLA is an independent 32-bit floating-point math accelerator that executes in parallel with the CPU. Additionally, the CLA has its own dedicated memory resources and it can directly access the key peripherals that are required in a typical control system. Support of a subset of ANSI C is standard, as are key features like hardware breakpoints and hardware task-switching. The F28003x supports up to 384KB (192KW) of flash memory divided into three 128KB (64KW) banks, which enable programming and execution in parallel. Up to 69KB (34.5KW) of on-chip SRAM is also available to supplement the flash memory. The Live Firmware Update hardware enhancements on F28003x allow fast context switching from the old firmware to the new firmware to minimize application downtime when updating the device firmware. High-performance analog blocks are integrated on the F28003x real-time microcontroller (MCU) and are closely coupled with the processing and PWM units to provide optimal real-time signal chain performance. Sixteen PWM channels, all supporting frequency-independent resolution modes, enable control of various power stages from a 3-phase inverter to power factor correction and advanced multilevel power topologies. The inclusion of the Configurable Logic Block (CLB) allows the user to add custom logic and potentially integrate FPGA-like functions into the C2000 real-time MCU. Interfacing is supported through various industry-standard communication ports (such as SPI, SCI, I2C, PMBus, LIN, CAN and CAN FD) and offers multiple pin-muxing options for optimal signal placement. The Fast Serial Interface (FSI) enables up to 200Mbps of robust communications across an isolation boundary. New to the C2000 platform is the Host Interface Controller (HIC), a high-throughput interface that allows an external host to access the resources of the TMS320F28003x directly. Want to learn more about features that make C2000 Real-Time MCUs the right choice for your real-time control system? Check out The Essential Guide for Developing With C2000™ Real-Time Microcontrollers and visit the C2000™ real-time control MCUs page. The Getting Started With C2000™ Real-Time Control Microcontrollers (MCUs) Getting Started Guide covers all aspects of development with C2000 devices from hardware to support resources. In addition to key reference documents, each section provides relevant links and resources to further expand on the information covered. Ready to get started? Check out the TMDSCNCD280039C evaluation board and download C2000Ware. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 3 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Device Information CONTROL LAW ACCELERATOR (CLA) CONFIGURABLE LOGIC BLOCK (CLB) TMS320F280039C-Q1 TMS320F280039C Yes 4 Tiles TMS320F280039-Q1(2) TMS320F280039(2) Yes – TMS320F280038C-Q1 Yes 4 Tiles TMS320F280038-Q1(2) Yes – TMS320F280037C-Q1 TMS320F280037C Yes 4 Tiles TMS320F280037-Q1(2) TMS320F280037 Yes – TMS320F280036C-Q1(2) Yes 4 Tiles TMS320F280036-Q1(2) Yes – TMS320F280034-Q1(2) TMS320F280034 Yes – 128KB TMS320F280033(2) No – 128KB PART (1) (2) 4 NUMBER(1) FLASH SIZE 384KB 256KB For more information on these devices, see the Device Comparison table. Preview information (not Production Data). Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 3.1 Functional Block Diagram The Functional Block Diagram shows the CPU system and associated peripherals. C28x CPU (120 MHz) FPU32 TMU VCRC FINTDIV CLA (120 MHz) CLA to CPU MSG RAM SYSTEM CONTROL CPU Timers XTAL INTOSC1, INTOSC2 PLL ePIE Windowed WD NMI WD Boot ROM CPU to CLA MSG RAM Secure ROM Flash Bank0 16 Sectors, 64Kw(128 KB) CLA Data ROM CLA Program ROM Flash Bank1 16 Sectors, 64Kw(128 KB) SECURITY DCSM JTAG Lock Secure Boot CLA to DMA MSG RAM Flash Bank2 16 Sectors, 64Kw(128 KB) DMA to CLA MSG RAM M0-M1 RAM 2Kw(4 KB) DIAGNOSTICS DCC MPOST HWBIST ERAD JTAG/cJTAG BGCRC Buses Legend LS0-LS7 RAM 16Kw(32 KB) CPU HIC DMA GS0-GS3 RAM 16Kw(32 KB) OTHERS EPG PF1 PF3 PF4 Result 16x ePWM (8 Hi-Res Capable) 4x CMPSS 3x eCAP (1 HRCAP Capable) 2x Buffered DAC 55x GPIO Input XBAR Output XBAR HIC DMA 6 Channels PF2 1x PMBUS Data 3x 12-Bit ADC CLU 2x SPI 1x FSI RX PF7 1x DCAN/ CAN PF7 PF8 2x LIN(A) 1x MCAN/ CAN FD PF9 2x SCI BGCRC PF10 PF11 PF12 4x CLB 1x AES LFU 2x I2C 1x FSI TX ePWM XBAR 2x eQEP (CW/CCW Support) CLB XBAR CLB Input XBAR CLB Output XBAR 8x SD Filters A. The LIN module can also work as an SCI. Figure 3-1. Functional Block Diagram Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 5 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 2 3 Description.......................................................................3 3.1 Functional Block Diagram........................................... 5 Revision History................................................................. 7 4 Device Comparison......................................................... 8 4.1 Related Products...................................................... 10 5 Pin Configuration and Functions................................. 11 5.1 Pin Diagrams.............................................................11 5.2 Pin Attributes.............................................................16 5.3 Signal Descriptions................................................... 36 5.4 Pin Multiplexing.........................................................48 5.5 Pins With Internal Pullup and Pulldown.................... 56 5.6 Connections for Unused Pins................................... 57 6 Specifications................................................................ 59 6.1 Absolute Maximum Ratings...................................... 59 6.2 ESD Ratings – Commercial...................................... 59 6.3 ESD Ratings – Automotive....................................... 60 6.4 Recommended Operating Conditions.......................60 6.5 Power Consumption Summary................................. 61 6.6 Electrical Characteristics...........................................67 6.7 Thermal Resistance Characteristics for PZ Package...................................................................... 68 6.8 Thermal Resistance Characteristics for PN Package...................................................................... 69 6.9 Thermal Resistance Characteristics for PM Package...................................................................... 70 6.10 Thermal Resistance Characteristics for PT Package...................................................................... 71 6.11 Thermal Design Considerations..............................71 6.12 System.................................................................... 72 6.13 Analog Peripherals................................................113 6.14 Control Peripherals............................................... 143 6 Submit Document Feedback 6.15 Communications Peripherals................................ 158 7 Detailed Description....................................................193 7.1 Overview................................................................. 193 7.2 Functional Block Diagram....................................... 194 7.3 Memory................................................................... 195 7.4 Identification............................................................203 7.5 Bus Architecture – Peripheral Connectivity.............204 7.6 C28x Processor...................................................... 205 7.7 Control Law Accelerator (CLA)............................... 207 7.8 Embedded Real-Time Analysis and Diagnostic (ERAD)...................................................................... 209 7.9 Background CRC-32 (BGCRC).............................. 209 7.10 Direct Memory Access (DMA)...............................210 7.11 Device Boot Modes............................................... 211 7.12 Dual Code Security Module.................................. 219 7.13 Watchdog.............................................................. 220 7.14 C28x Timers..........................................................221 7.15 Dual-Clock Comparator (DCC)............................. 221 7.16 Configurable Logic Block (CLB)............................223 8 Applications, Implementation, and Layout............... 225 8.1 TI Reference Design............................................... 225 9 Device and Documentation Support..........................226 9.1 Getting Started and Next Steps.............................. 226 9.2 Device Nomenclature..............................................226 9.3 Markings................................................................. 227 9.4 Tools and Software................................................. 229 9.5 Documentation Support.......................................... 231 9.6 Support Resources................................................. 232 9.7 Trademarks............................................................. 233 9.8 Electrostatic Discharge Caution..............................233 9.9 Glossary..................................................................233 10 Mechanical, Packaging, and Orderable Information.................................................................. 234 Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Revision History Changes from March 4, 2022 to November 29, 2022 Page • This Revision History lists the changes from SPRSP61A to SPRSP61B. ..................................................1 • Global: Changed document status from "PRODUCTION DATA" to "UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA". Information on the TMS320F280039, TMS320F280039-Q1, TMS320F280038-Q1, TMS320F280037-Q1, TMS320F280036C-Q1, TMS320F280036-Q1, TMS320F280034-Q1, and TMS320F280033 devices is Preview information (not Production Data).................1 • Global: Information on TMS320F280037 and TMS320F280034 is now Production Data.................................1 • Section 1, Features: Added "Functional Safety Compliant targeted" feature and "Safety-related certification" feature. Added "HEV/EV battery-management system (BMS)" feature............................................................. 1 • Device Information table: Added "Preview information (not Production Data)" footnote.................................... 3 • Table 4-1, Device Comparison: Added "Preview information (not Production Data)" footnote...........................8 • Table 5-1, Pin Attributes: Updated table............................................................................................................11 • Table 5-2, Analog Signals: Updated table.........................................................................................................36 • Table 5-3, Digital Signals: Updated table..........................................................................................................36 • Table 5-4, Power and Ground: Updated table.................................................................................................. 36 • Table 5-5, Test, JTAG, and Reset: Updated table.............................................................................................36 • Section 6, Specifications: Removed "Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device beyond the Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to VSS, unless otherwise noted" paragraph.................................................................................................................. 59 • Section 6.1, Absolute Maximum Ratings: Added "Operation outside the Absolute Maximum Ratings may cause permanent device damage ..." footnote. Added "All voltage values are with respect to VSS, unless otherwise noted" footnote................................................................................................................................. 59 • Section 6.4, Recommended Operating Conditions: Added "Device supply voltage, VDD".............................. 59 • Power Management Module Operating Conditions table: Updated MAX value of "VDDIO - VDD Delay" parameter..........................................................................................................................................................79 • ADC Input Model section: Added reference to the ADC Input Circuit Evaluation for C2000 MCUs Application Report............................................................................................................................................................. 127 • Section 7.11.2, GPIO Assignments: Removed Secure LFU Flash Boot Options table.................................. 216 • Table 7-18, LFU Flash Boot Options: Changed FLASH ENTRY POINT (ADDRESS) of OPTION 3 Bank2 from 0x0009 0000 to 0x000A 0000.........................................................................................................................216 • Section 8, Applications, Implementation, and Layout: Added reference to Hardware Design Guide for F2800x C2000™ Real-Time MCU Series Application Note........................................................................................ 225 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 7 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 4 Device Comparison Table 4-1 lists the features of the TMS320F28003x devices. Table 4-1. Device Comparison FEATURE(1) F280039C F280037C F280036CF280039C-Q1 F280038C-Q1 F280037C-Q1 F280034 Q1(2) (2) F280039(2) F280038-Q1(2) F280037 (2) F280034-Q1 F280036-Q1 F280039-Q1(2) F280037-Q1(2) F280033(2) Processor and Accelerators C28x Frequency (MHz) 120 FPU Yes (instructions for Fast Integer Division) VCRC Yes TMU CLA – Type 2 Yes – Type 1 (instructions supporting NLPID) Available Yes Frequency (MHz) 120 6-Channel DMA – Type 0 No – Yes External interrupts 5 Memory Flash Flash Banks RAM 384KB (192KW) 256KB (128KW) 128KB (64KW) 3 x 128KB 2 x 128KB 2 x 64KB Dedicated 4KB (2KW) Local Shared 32KB (16KW) Message 1KB (0.5KW) Global Shared 32KB (16KW) Total 69KB (34.5KW) Message RAM Types ECC 512B (256W) CPU-CLA 512B (256W) CLA-DMA – FLASH, Mx, LSx, GSx, Message RAM FLASH, Mx, LSx, GSx Parity ROM, CAN RAM Code security for on-chip flash and RAM Yes System Configurable Logic Block (CLB) Embedded Pattern Generator (EPG) 32-bit CPU timers – Yes 3 Advance Encryption Standard (AES) Background CRC (BGCRC) Live Firmware Update (LFU) Support 8 4 Tiles on C Variants Yes Yes Yes, with enhancements and flash bank erase time improvements Secure Boot Yes JTAG Lock Yes HWBIST Yes Nonmaskable Interrupt Watchdog (NMIWD) timers 1 Watchdog timers 1 Crystal oscillator/External clock input 1 Internal oscillator 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 4-1. Device Comparison (continued) FEATURE(1) F280039C F280037C F280036CF280039C-Q1 F280038C-Q1 F280037C-Q1 F280034 Q1(2) (2) (2) F280039 F280038-Q1 F280037 F280034-Q1(2) F280036-Q1(2) (2) (2) F280039-Q1 F280037-Q1 F280033(2) Pins and Power Supply Internal 3.3-V to 1.2-V Voltage Regulator VREG LDO Yes GPIO pins 100-pin PZ 51 – 51 – 51 80-pin PN 39 – 39 – 39 64-pin PM 26 25 26 25 26 48-pin PT – – 14 – 14 Additional GPIO AIO (analog with digital inputs) 4 (2 from cJTAG and 2 from X1/X2) 100-pin PZ 23 – 23 – 23 80-pin PN 16 – 16 – 16 64-pin PM 16 16 16 16 16 48-pin PT – – 14 – 14 AGPIO (analog with digital inputs and outputs) 100-pin PZ 2 – 2 – 2 80-pin PN 2 – 2 – 2 ADC 12-bit Number of ADCs – 23 Analog Peripherals 3 MSPS 4 Conversion Time (ns)(3) ADC channels (single-ended) (includes the two gpdac outputs) 250 100-pin PZ 23 – 23 80-pin PN 64-pin PM 18 – 18 – 18 16 16 16 16 48-pin PT 16 – – 14 – 14 Temperature sensor 1 Buffered DAC 2 CMPSS (each CMPSS has two comparators and two internal DACs) 4 Control Peripherals (4) eCAP/HRCAP modules – Type 2 ePWM/HRPWM channels – Type 4 3 (1 - eCAP3 with HRCAP capability) 16 (8 - ePWM1 to ePWM4 with HRPWM capability) eQEP modules – Type 2 2 SDFM channels – Type 2 8 Communication Peripherals (4) CAN (DCAN) – Type 0 CAN FD (MCAN) – Type 1 Fast Serial Interface (FSI) – Type 2 1 1 1 (1 RX and 1 TX) I2C – Type 1 2 LIN – Type 1 (UART-Compatible) 2 Host Interface Controller (HIC) – Type 1 1 PMBus – Type 0 1 SCI – Type 0 (UART-Compatible) 2 SPI – Type 2 2 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 9 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 4-1. Device Comparison (continued) FEATURE(1) F280039C F280037C F280036CF280039C-Q1 F280038C-Q1 F280037C-Q1 F280034 Q1(2) (2) (2) F280039 F280038-Q1 F280037 F280034-Q1(2) F280036-Q1(2) (2) (2) F280039-Q1 F280037-Q1 F280033(2) Package Options, Temperature, and Qualification Junction temperature (TJ) –40°C to 150°C Free-Air temperature (TA) Package Options Package Options with AECQ100 Qualification available (1) (2) (3) (4) –40°C to 125°C 100-pin PZ F280039C F280039 – F280037C F280037 – F280034 F280033 80-pin PN F280039C F280039 – F280037C F280037 – F280034 F280033 64-pin PM F280039C F280039 – F280037C F280037 – F280034 F280033 48-pin PT – – F280037C F280037 – F280034 F280033 100-pin PZ F280039C-Q1 F280039-Q1 – F280037C-Q1 F280037-Q1 – – – 64-pin PM – F280038C-Q1 F280038-Q1 – F280036C-Q1 F280036-Q1 – – 48-pin PT – – F280037C-Q1 F280037-Q1 – F280034-Q1 – A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the basic functionality of the module. Preview information (not Production Data). Time between start of sample-and-hold window to start of sample-and-hold window of the next conversion. For devices that are available in more than one package, the peripheral count listed in the smaller package is reduced because the smaller package has less device pins available. The number of peripherals internally present on the device is not reduced compared to the largest package offered within a part number. See Section 5 to identify which peripheral instances are accessible on pins in the smaller package. 4.1 Related Products TMS320F2803x Real-Time Microcontrollers The F2803x series increases the pin-count and memory size options. The F2803x series also introduces the parallel control law accelerator (CLA) option. TMS320F2807x Real-Time Microcontrollers The F2807x series offers the most performance, largest pin counts, flash memory sizes, and peripheral options. The F2807x series includes the latest generation of accelerators, ePWM peripherals, and analog technology. TMS320F28004x Real-Time Microcontrollers The F28004x series is a reduced version of the F2807x series with the latest generational enhancements. TMS320F28002x Real-Time Microcontrollers The F28002x series is a reduced version of the F28004x series with the latest generational enhancements. TMS320F2838x Real-Time Microcontrollers The F2838x series offers more performance, larger pin counts, flash memory sizes, peripheral and wide variety of connectivity options. The F2838x series includes the latest generation of accelerators, ePWM peripherals, and analog technology. 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 5 Pin Configuration and Functions 5.1 Pin Diagrams GPIO29 GPIO31 GPIO30 GPIO6 GPIO14 GPIO15 GPIO34 GPIO10 GPIO59 GPIO61 GPIO9 GPIO5 VDDIO VDD VSS GPIO44 GPIO7 GPIO22 GPIO41 GPIO23 GPIO40 GPIO0 GPIO1 GPIO2 GPIO3 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 Figure 5-1 shows the pin assignments on the 100-pin PZ low-profile quad flatpack; the Q and non-Q variant have the same pinout. Figure 5-2 shows the pin assignments on the 80-pin PN low-profile quad flatpack. Figure 5-3 shows the pin assignments on the 64-pin PM low-profile quad flatpack (Q temperature). Figure 5-4 shows the pin assignments on the 64-pin PM low-profile quad flatpack. Figure 5-5 shows the pin assignments on the 48-Pin PT low-profile quad flatpack; the Q and non-Q variant have the same pinout. GPIO28 1 75 GPIO4 XRSn 2 74 GPIO8 VDDIO 3 73 VREGENZ VDD 4 72 VSS VSS 5 71 VDD GPIO47 6 70 VDDIO GPIO48 7 69 GPIO19,X1 GPIO49 8 68 GPIO18,X2 GPIO50 9 67 GPIO58 GPIO51 10 66 GPIO57 GPIO52 11 65 GPIO56 GPIO53 12 64 GPIO32 GPIO54 13 63 GPIO35/TDI A6 14 62 TMS B2,C6 15 61 GPIO37/TDO B3,VDAC 16 60 TCK A2,B6,C9 17 59 GPIO27 50 GPIO13 49 B11,GPIO21 48 B5,GPIO20 VDD VDDIO VSS GPIO60 GPIO55 C14 B0,C11 A10,B1,C10 B4,C8 A9 A8 A4,B8 A5 VDDA B5 VSSA A7,C3 B11 C1 A12,C5 VREFLO VREFLO A. 47 GPIO12 46 51 45 25 44 GPIO11 VREFHI 43 GPIO33 52 42 53 24 41 23 VREFHI 40 A0,B15,C15,DACA_OUT 39 GPIO16 38 54 37 22 36 GPIO17 A1,B7,DACB_OUT 35 55 34 21 33 GPIO24 B12,C2 32 56 31 20 30 GPIO25 A11,B10,C0 29 GPIO26 57 28 58 19 27 18 26 A3,B9,C7 A14,B14,C4 Not to scale Only the GPIO function is shown on GPIO pins. See Section 5.2 for the complete, muxed signal name. Figure 5-1. 100-Pin PZ Low-Profile Quad Flatpack (Top View) Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 11 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com GPIO6 GPIO14 GPIO15 GPIO34 GPIO10 GPIO9 GPIO5 GPIO45 VDDIO VDD VSS GPIO44 GPIO7 GPIO22 GPIO41 GPIO23 GPIO40 GPIO0 GPIO1 GPIO2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 GPIO30 1 60 GPIO3 GPIO31 2 59 GPIO4 GPIO29 3 58 GPIO8 GPIO28 4 57 GPIO42 XRSn 5 56 GPIO39 GPIO46 6 55 VSS VDDIO 7 54 GPIO43 VDD 8 53 VDD VSS 9 52 VDDIO A6 10 51 GPIO19,X1 B2,C6 11 50 GPIO18,X2 A3,B3,C5,VDAC 12 49 GPIO32 A2,B6,C9 13 48 GPIO35/TDI A15,B9,C7 14 47 TMS A14,B14,C4 15 46 GPIO37/TDO A11,B10,C0 16 45 TCK A5,B12,C2 17 44 GPIO27 40 GPIO17 39 GPIO16 37 38 GPIO33 GPIO11 36 GPIO12 35 GPIO13 34 33 B5,GPIO20 B11,GPIO21 32 VDDIO 31 30 VSS VDD A10,B1,C10 A9,B4,C8 A4,B8,C14 VDDA VSSA A8,B0,C11 A7,C3 A12,C1 VREFLO A. 29 GPIO24 28 41 27 20 26 VREFHI 25 GPIO25 24 GPIO26 42 23 43 19 22 18 21 A1,B7,DACB_OUT A0,B15,C15,DACA_OUT Not to scale Only the GPIO function is shown on GPIO pins. See Section 5.2 for the complete, muxed signal name. Figure 5-2. 80-Pin PN Low-Profile Quad Flatpack (Top View) 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com GPIO6 GPIO10 GPIO9 GPIO5 VDDIO VDD VSS GPIO7 GPIO22 GPIO41 GPIO23 GPIO40 GPIO0 GPIO1 GPIO2 GPIO3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 VSS 5 44 VDD A6 6 43 VDDIO B2,C6 7 42 GPIO19,X1 A3,B3,C5,VDAC 8 41 GPIO18,X2 A2,B6,C9 9 40 GPIO32 A15,B9,C7 10 39 GPIO35/TDI A14,B14,C4 11 38 TMS A11,B10,C0 12 37 GPIO37/TDO A5,B12,C2 13 36 TCK A1,B7,DACB_OUT 14 35 GPIO24 A0,B15,C15,DACA_OUT 15 34 GPIO17 VREFHI 16 33 GPIO16 GPIO33 GPIO11 GPIO12 GPIO13 VDDIO VDD VSS A10,B1,C10 A9,B4,C8 A4,B8,C14 VDDA VSSA A8,B0,C11 A7,C3 A12,C1 VREFLO A. 32 VSS 31 45 30 4 29 VDD 28 VREGENZ 27 46 26 3 25 XRSn 24 GPIO8 23 47 22 2 21 GPIO28 20 GPIO4 19 48 18 1 17 GPIO29 Not to scale Only the GPIO function is shown on GPIO pins. See Section 5.2 for the complete, muxed signal name. Figure 5-3. 64-Pin PM Low-Profile Quad Flatpack - Q Temperature (Top View) Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 13 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com GPIO6 GPIO10 GPIO9 GPIO5 VDDIO VDD VSS GPIO7 GPIO22 GPIO41 GPIO23 GPIO40 GPIO0 GPIO1 GPIO2 GPIO3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 VSS 5 44 VDD A6 6 43 VDDIO B2,C6 7 42 GPIO19,X1 A3,B3,C5,VDAC 8 41 GPIO18,X2 A2,B6,C9 9 40 GPIO32 A15,B9,C7 10 39 GPIO35/TDI A14,B14,C4 11 38 TMS A11,B10,C0 12 37 GPIO37/TDO A5,B12,C2 13 36 TCK A1,B7,DACB_OUT 14 35 GPIO24 A0,B15,C15,DACA_OUT 15 34 GPIO17 VREFHI 16 33 GPIO16 GPIO33 GPIO11 GPIO12 GPIO13 VDDIO VDD VSS A10,B1,C10 A9,B4,C8 A4,B8,C14 VDDA VSSA A8,B0,C11 A7,C3 A12,C1 VREFLO A. 32 VSS 31 45 30 4 29 VDD 28 GPIO39 27 46 26 3 25 XRSn 24 GPIO8 23 47 22 2 21 GPIO28 20 GPIO4 19 48 18 1 17 GPIO29 Not to scale Only the GPIO function is shown on GPIO pins. See Section 5.2 for the complete, muxed signal name. Figure 5-4. 64-Pin PM Low-Profile Quad Flatpack (Top View) 14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com GPIO6 GPIO5 VDDIO VDD VSS GPIO7 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 VSS 48 47 46 45 44 43 42 41 40 39 38 37 SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 A6,B2,C6 4 33 GPIO18,X2 A3,B3,C5,VDAC 5 32 GPIO32 A2,B6,C9 6 31 GPIO35/TDI A15,B9,C7 7 30 TMS A11,B10,C0 8 29 GPIO37/TDO A5,B12,C2 9 28 TCK A1,B7,DACB_OUT 10 27 GPIO24 A0,B15,C15,DACA_OUT 11 26 GPIO16 VREFHI 12 25 GPIO33 Not to scale VDDIO VDD VSS A10,B1,C10 A9,B4,C8 A4,B8,C14 VDDA VSSA A8,B0,C11 A7,C3 A12,C1 VREFLO A. 24 GPIO19,X1 23 34 22 3 21 XRSn 20 VDDIO 19 35 18 2 17 GPIO28 16 VDD 15 36 14 1 13 GPIO29 Only the GPIO function is shown on GPIO pins. See Section 5.2 for the complete, muxed signal name. Figure 5-5. 48-Pin PT Low-Profile Quad Flatpack (Top View) Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 15 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 5.2 Pin Attributes Table 5-1. Pin Attributes SIGNAL NAME MUX POSITION 100 PZ 80 PN 64 PMQ 64 PM 48 PT PIN TYPE DESCRIPTION ANALOG A0 I ADC-A Input 0 B15 I ADC-B Input 15 C15 I ADC-C Input 15 CMP3_HP2 I CMPSS-3 High Comparator Positive Input 2 I CMPSS-3 Low Comparator Positive Input 2 O Buffered DAC-A Output. I Analog Pin Used For Digital Input 231 This pin also has digital mux functions which are described in the GPIO section of this table. A1 I ADC-A Input 1 B7 I ADC-B Input 7 CMP1_HP4 I CMPSS-1 High Comparator Positive Input 4 CMP1_LP4 I CMPSS-1 Low Comparator Positive Input 4 O Buffered DAC-B Output. I Analog Pin Used For Digital Input 232 This pin also has digital mux functions which are described in the GPIO section of this table. A2 I ADC-A Input 2 B6 I ADC-B Input 6 C9 I ADC-C Input 9 I CMPSS-1 High Comparator Positive Input 0 I CMPSS-1 Low Comparator Positive Input 0 I Analog Pin Used For Digital Input 224 This pin also has digital mux functions which are described in the GPIO section of this table. I ADC-A Input 3 I CMPSS-3 High Comparator Positive Input 5 I CMPSS-3 Low Comparator Positive Input 5 I Analog Pin Used For Digital Input 229 I ADC-A Input 3 I CMPSS-3 High Comparator Positive Input 5 CMP3_LP5 I CMPSS-3 Low Comparator Positive Input 5 A4 I ADC-A Input 4 B8 I ADC-B Input 8 I CMPSS-2 High Comparator Positive Input 0 I CMPSS-2 Low Comparator Positive Input 0 I Analog Pin Used For Digital Input 225 This pin also has digital mux functions which are described in the GPIO section of this table. A5 I ADC-A Input 5 CMP2_HP5 I CMPSS-2 High Comparator Positive Input 5 I CMPSS-2 Low Comparator Positive Input 5 I Analog Pin Used For Digital Input 249 I ADC-A Input 5 I CMPSS-2 High Comparator Positive Input 5 I CMPSS-2 Low Comparator Positive Input 5 23 CMP3_LP2 19 15 15 11 DACA_OUT AIO231 0, 4, 8, 12 22 18 14 14 10 DACB_OUT AIO232 0, 4, 8, 12 CMP1_HP0 17 13 9 9 6 CMP1_LP0 AIO224 0, 4, 8, 12 A3 CMP3_HP5 18 CMP3_LP5 AIO229 0, 4, 8, 12 A3 CMP3_HP5 12 8 8 5 CMP2_HP0 36 CMP2_LP0 AIO225 23 23 19 0, 4, 8, 12 35 CMP2_LP5 AIO249 27 0, 4, 8, 12 A5 CMP2_HP5 17 CMP2_LP5 16 Submit Document Feedback 13 13 9 Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-1. Pin Attributes (continued) SIGNAL NAME MUX POSITION 100 PZ 80 PN 64 PMQ 64 PM 48 PT PIN TYPE DESCRIPTION A6 I ADC-A Input 6 CMP1_HP2 I CMPSS-1 High Comparator Positive Input 2 CMP1_LP2 I CMPSS-1 Low Comparator Positive Input 2 I Analog Pin Used For Digital Input 228 This pin also has digital mux functions which are described in the GPIO section of this table. A8 I ADC-A Input 8 CMP4_HP4 I CMPSS-4 High Comparator Positive Input 4 I CMPSS-4 Low Comparator Positive Input 4 I Analog Pin Used For Digital Input 240 This pin also has digital mux functions which are described in the GPIO section of this table. A8 I ADC-A Input 8 CMP4_HP4 I CMPSS-4 High Comparator Positive Input 4 I CMPSS-4 Low Comparator Positive Input 4 I Analog Pin Used For Digital Input 241 This pin also has digital mux functions which are described in the GPIO section of this table. A9 I ADC-A Input 9 CMP2_HP2 I CMPSS-2 High Comparator Positive Input 2 CMP2_LP2 I CMPSS-2 Low Comparator Positive Input 2 I Analog Pin Used For Digital Input 227 This pin also has digital mux functions which are described in the GPIO section of this table. A10 I ADC-A Input 10 B1 I ADC-B Input 1 C10 I ADC-C Input 10 CMP2_HN0 I CMPSS-2 High Comparator Negative Input 0 CMP2_HP3 I CMPSS-2 High Comparator Positive Input 3 CMP2_LN0 I CMPSS-2 Low Comparator Negative Input 0 CMP2_LP3 I CMPSS-2 Low Comparator Positive Input 3 I Analog Pin Used For Digital Input 230 This pin also has digital mux functions which are described in the GPIO section of this table. A11 I ADC-A Input 11 B10 I ADC-B Input 10 C0 I ADC-C Input 0 CMP1_HN1 I CMPSS-1 High Comparator Negative Input 1 CMP1_HP1 I CMPSS-1 High Comparator Positive Input 1 CMP1_LN1 I CMPSS-1 Low Comparator Negative Input 1 CMP1_LP1 I CMPSS-1 Low Comparator Positive Input 1 I Analog Pin Used For Digital Input 237 This pin also has digital mux functions which are described in the GPIO section of this table. A12 I ADC-A Input 12 CMP2_HN1 I CMPSS-2 High Comparator Negative Input 1 CMP2_HP1 I CMPSS-2 High Comparator Positive Input 1 CMP2_LN1 I CMPSS-2 Low Comparator Negative Input 1 I CMPSS-2 Low Comparator Positive Input 1 I Analog Pin Used For Digital Input 238 This pin also has digital mux functions which are described in the GPIO section of this table. AIO228 14 AIO227 AIO230 AIO237 4 0, 4, 8, 12 24 20 20 16 0, 4, 8, 12 38 28 24 24 20 0, 4, 8, 12 40 29 25 25 21 0, 4, 8, 12 20 16 12 12 8 0, 4, 8, 12 28 CMP2_LP1 AIO238 6 37 CMP4_LP4 AIO241 6 0, 4, 8, 12 CMP4_LP4 AIO240 10 0, 4, 8, 12 Copyright © 2022 Texas Instruments Incorporated 22 18 18 14 Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 17 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-1. Pin Attributes (continued) SIGNAL NAME MUX POSITION 100 PZ 80 PN 64 PMQ 64 PM 48 PT PIN TYPE DESCRIPTION A14 I ADC-A Input 14 B14 I ADC-B Input 14 C4 I ADC-C Input 4 CMP3_HP4 I CMPSS-3 High Comparator Positive Input 4 I CMPSS-3 Low Comparator Positive Input 4 I Analog Pin Used For Digital Input 239 This pin also has digital mux functions which are described in the GPIO section of this table. A15 I ADC-A Input 15 CMP1_HN0 I CMPSS-1 High Comparator Negative Input 0 CMP1_HP3 I CMPSS-1 High Comparator Positive Input 3 CMP1_LN0 I CMPSS-1 Low Comparator Negative Input 0 I CMPSS-1 Low Comparator Positive Input 3 I Analog Pin Used For Digital Input 233 This pin also has digital mux functions which are described in the GPIO section of this table. B0 I ADC-B Input 0 C11 I ADC-C Input 11 I CMPSS-2 High Comparator Positive Input 4 I CMPSS-2 Low Comparator Positive Input 4 I Analog Pin Used For Digital Input 253 B0 I ADC-B Input 0 C11 I ADC-C Input 11 I CMPSS-2 High Comparator Positive Input 4 CMP2_LP4 I CMPSS-2 Low Comparator Positive Input 4 B2 I ADC-B Input 2 C6 I ADC-C Input 6 CMP3_HP0 I CMPSS-3 High Comparator Positive Input 0 I CMPSS-3 Low Comparator Positive Input 0 I Analog Pin Used For Digital Input 226 This pin also has digital mux functions which are described in the GPIO section of this table. B3 I ADC-B Input 3 CMP3_HN0 I CMPSS-3 High Comparator Negative Input 0 CMP3_HP3 I CMPSS-3 High Comparator Positive Input 3 CMP3_LN0 I CMPSS-3 Low Comparator Negative Input 0 I CMPSS-3 Low Comparator Positive Input 3 I Optional external reference voltage for on-chip DACs. I Analog Pin Used For Digital Input 242 This pin also has digital mux functions which are described in the GPIO section of this table. B4 I ADC-B Input 4 C8 I ADC-C Input 8 I CMPSS-4 High Comparator Positive Input 0 I CMPSS-4 Low Comparator Positive Input 0 I Analog Pin Used For Digital Input 236 B5 I ADC-B Input 5 CMP1_HP5 I CMPSS-1 High Comparator Positive Input 5 CMP1_LP5 I CMPSS-1 Low Comparator Positive Input 5 I Analog Pin Used For Digital Input 252 This pin also has digital mux functions which are described in the GPIO section of this table. 19 15 11 11 CMP3_LP4 AIO239 0, 4, 8, 12 14 10 10 7 CMP1_LP3 AIO233 0, 4, 8, 12 CMP2_HP4 41 CMP2_LP4 AIO253 0, 4, 8, 12 24 CMP2_HP4 15 CMP3_LP0 AIO226 11 20 7 20 7 16 4 0, 4, 8, 12 16 CMP3_LP3 12 8 8 5 VDAC AIO242 0, 4, 8, 12 CMP4_HP0 39 CMP4_LP0 AIO236 AIO252 18 0, 4, 8, 12 32 0, 4, 8, 12 Submit Document Feedback 28 24 24 20 Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-1. Pin Attributes (continued) SIGNAL NAME MUX POSITION 100 PZ 80 PN 64 PMQ 64 PM 48 PT PIN TYPE DESCRIPTION B5 I ADC-B Input 5 CMP1_HP5 I CMPSS-1 High Comparator Positive Input 5 CMP1_LP5 I CMPSS-1 Low Comparator Positive Input 5 48 33 GPIO20 I/O General-Purpose Input Output 20 This pin also has digital mux functions which are described in the GPIO section of this table. B11 I ADC-B Input 11 CMP4_HP5 I CMPSS-4 High Comparator Positive Input 5 I CMPSS-4 Low Comparator Positive Input 5 I Analog Pin Used For Digital Input 251 B11 I ADC-B Input 11 CMP4_HP5 I CMPSS-4 High Comparator Positive Input 5 CMP4_LP5 I CMPSS-4 Low Comparator Positive Input 5 30 CMP4_LP5 AIO251 0, 4, 8, 12 49 34 GPIO21 I/O General-Purpose Input Output 21 This pin also has digital mux functions which are described in the GPIO section of this table. C1 I ADC-C Input 1 CMP4_HP2 I CMPSS-4 High Comparator Positive Input 2 I CMPSS-4 Low Comparator Positive Input 2 I Analog Pin Used For Digital Input 248 I Analog Pin Used For Digital Input 248 B12 I ADC-B Input 12 C2 I ADC-C Input 2 CMP3_HN1 I CMPSS-3 High Comparator Negative Input 1 CMP3_HP1 I CMPSS-3 High Comparator Positive Input 1 I CMPSS-3 Low Comparator Negative Input 1 I CMPSS-3 Low Comparator Positive Input 1 I Analog Pin Used For Digital Input 244 This pin also has digital mux functions which are described in the GPIO section of this table. A7 I ADC-A Input 7 C3 I ADC-C Input 3 CMP4_HN1 I CMPSS-4 High Comparator Negative Input 1 CMP4_HP1 I CMPSS-4 High Comparator Positive Input 1 I CMPSS-4 Low Comparator Negative Input 1 I CMPSS-4 Low Comparator Positive Input 1 I Analog Pin Used For Digital Input 245 This pin also has digital mux functions which are described in the GPIO section of this table. I ADC-C Input 5 I ADC-B Input 9 I ADC-C Input 7 C14 I ADC-C Input 14 CMP4_HN0 I CMPSS-4 High Comparator Negative Input 0 CMP4_HP3 I CMPSS-4 High Comparator Positive Input 3 I CMPSS-4 Low Comparator Negative Input 0 I CMPSS-4 Low Comparator Positive Input 3 I Analog Pin Used For Digital Input 247 C14 I ADC-C Input 14 CMP4_HN0 I CMPSS-4 High Comparator Negative Input 0 I CMPSS-4 High Comparator Positive Input 3 CMP4_LN0 I CMPSS-4 Low Comparator Negative Input 0 CMP4_LP3 I CMPSS-4 Low Comparator Positive Input 3 29 CMP4_LP2 AIO248 22 18 18 14 0, 4, 8, 12 AIO248 29 21 CMP3_LN1 22 17 18 13 18 13 14 9 CMP3_LP1 AIO244 0, 4, 8, 12 31 CMP4_LN1 23 19 19 15 CMP4_LP1 AIO245 0, 4, 8, 12 C5 B9 C7 28 12 8 8 5 18 14 10 10 7 42 CMP4_LN0 CMP4_LP3 AIO247 0, 4, 8, 12 CMP4_HP3 27 Copyright © 2022 Texas Instruments Incorporated 23 23 19 Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 19 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-1. Pin Attributes (continued) SIGNAL NAME MUX POSITION 100 PZ 80 PN 64 PMQ 64 PM 48 PT VREFHI 24, 25 20 16 VREFLO 26, 27 21 17 PIN TYPE DESCRIPTION 16 12 I ADC High Reference. In external reference mode, externally drive the high reference voltage onto this pin. In internal reference mode, a voltage is driven onto this pin by the device. In either mode, place at least a 2.2-µF capacitor on this pin. This capacitor should be placed as close to the device as possible between the VREFHI and VREFLO pins. 17 13 I ADC Low Reference I Analog Pin Used For Digital Input 231 This pin also has analog functions which are described in the ANALOG section of this table. GPIO AIO231 0, 4, 8, 12 SD1_C1 2 I SDFM-1 Channel 1 Clock Input HIC_BASESEL1 15 I HIC Base address range select 1 AIO232 0, 4, 8, 12 I Analog Pin Used For Digital Input 232 This pin also has analog functions which are described in the ANALOG section of this table. SD1_D4 2 I SDFM-1 Channel 4 Data Input HIC_BASESEL0 15 I HIC Base address range select 0 AIO224 0, 4, 8, 12 I Analog Pin Used For Digital Input 224 This pin also has analog functions which are described in the ANALOG section of this table. SD2_D3 2 I SDFM-2 Channel 3 Data Input HIC_A3 15 I HIC Address 3 AIO225 0, 4, 8, 12 I Analog Pin Used For Digital Input 225 This pin also has analog functions which are described in the ANALOG section of this table. SD2_C2 2 I SDFM-2 Channel 2 Clock Input HIC_NWE 15 I HIC Data Write enable from host AIO228 0, 4, 8, 12 I Analog Pin Used For Digital Input 228 This pin also has analog functions which are described in the ANALOG section of this table. SD2_C1 2 I SDFM-2 Channel 1 Clock Input HIC_A0 15 I HIC Address 0 AIO240 0, 4, 8, 12 I Analog Pin Used For Digital Input 240 This pin also has analog functions which are described in the ANALOG section of this table. SD2_C1 2 I SDFM-2 Channel 1 Clock Input HIC_NBE1 15 I HIC Byte enable 1 AIO241 0, 4, 8, 12 I Analog Pin Used For Digital Input 241 This pin also has analog functions which are described in the ANALOG section of this table. SD2_C1 2 I SDFM-2 Channel 1 Clock Input HIC_NBE1 15 I HIC Byte enable 1 AIO227 0, 4, 8, 12 I Analog Pin Used For Digital Input 227 This pin also has analog functions which are described in the ANALOG section of this table. SD1_C3 2 I SDFM-1 Channel 3 Clock Input HIC_NBE0 15 I HIC Byte enable 0 AIO230 0, 4, 8, 12 I Analog Pin Used For Digital Input 230 This pin also has analog functions which are described in the ANALOG section of this table. SD1_C4 2 I SDFM-1 Channel 4 Clock Input HIC_BASESEL2 15 I HIC Base address range select 2 AIO237 0, 4, 8, 12 I Analog Pin Used For Digital Input 237 This pin also has analog functions which are described in the ANALOG section of this table. SD1_D2 2 I SDFM-1 Channel 2 Data Input HIC_A6 15 I HIC Address 6 23 22 17 36 14 19 18 13 27 10 15 14 9 23 6 15 14 9 23 6 11 10 6 19 4 37 24 38 40 20 20 Submit Document Feedback 28 29 16 20 24 25 12 20 24 25 12 16 20 21 8 Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-1. Pin Attributes (continued) SIGNAL NAME MUX POSITION 100 PZ 80 PN 64 PMQ 64 PM 48 PT PIN TYPE DESCRIPTION I Analog Pin Used For Digital Input 238 This pin also has analog functions which are described in the ANALOG section of this table. 2 I SDFM-2 Channel 3 Clock Input 15 I HIC Chip select input AIO239 0, 4, 8, 12 I Analog Pin Used For Digital Input 239 This pin also has analog functions which are described in the ANALOG section of this table. SD1_D1 2 I SDFM-1 Channel 1 Data Input HIC_A5 15 I HIC Address 5 AIO233 0, 4, 8, 12 I Analog Pin Used For Digital Input 233 This pin also has analog functions which are described in the ANALOG section of this table. SD2_D1 2 I SDFM-2 Channel 1 Data Input HIC_A4 15 I HIC Address 4 AIO226 0, 4, 8, 12 I Analog Pin Used For Digital Input 226 This pin also has analog functions which are described in the ANALOG section of this table. SD2_D4 2 I SDFM-2 Channel 4 Data Input HIC_A1 15 I HIC Address 1 AIO242 0, 4, 8, 12 I Analog Pin Used For Digital Input 242 This pin also has analog functions which are described in the ANALOG section of this table. SD2_D2 2 I SDFM-2 Channel 2 Data Input HIC_A2 15 I HIC Address 2 AIO252 0, 4, 8, 12 I Analog Pin Used For Digital Input 252 This pin also has analog functions which are described in the ANALOG section of this table. SD2_C4 2 I SDFM-2 Channel 4 Clock Input AIO244 0, 4, 8, 12 I Analog Pin Used For Digital Input 244 This pin also has analog functions which are described in the ANALOG section of this table. SD1_D3 2 I SDFM-1 Channel 3 Data Input HIC_A7 15 I HIC Address 7 AIO245 0, 4, 8, 12 I Analog Pin Used For Digital Input 245 This pin also has analog functions which are described in the ANALOG section of this table. SD1_C2 2 I SDFM-1 Channel 2 Clock Input HIC_NOE 15 O HIC Output enable for data bus AIO238 0, 4, 8, 12 SD2_C3 HIC_NCS 28 19 22 15 14 15 16 12 11 10 7 8 18 14 11 10 7 8 7 4 5 32 21 31 GPIO0 11 18 17 23 13 19 13 19 9 15 0, 4, 8, 12 I/O General-Purpose Input Output 0 EPWM1_A 1 O ePWM-1 Output A I2CA_SDA 6 I/OD I2C-A Open-Drain Bidirectional Data SPIA_STE 7 I/O SPI-A Slave Transmit Enable (STE) FSIRXA_CLK 9 I FSIRX-A Input Clock MCAN_RX 10 I CAN/CAN FD Receive CLB_OUTPUTXBAR8 11 O CLB Output X-BAR Output 8 EQEP1_INDEX 13 I/O eQEP-1 Index HIC_D7 14 I/O HIC Data 7 HIC_BASESEL1 15 I Copyright © 2022 Texas Instruments Incorporated 79 63 52 52 42 HIC Base address range select 1 Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 21 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-1. Pin Attributes (continued) SIGNAL NAME GPIO1 MUX POSITION 100 PZ 80 PN 64 PMQ 64 PM 48 PT PIN TYPE DESCRIPTION 0, 4, 8, 12 I/O General-Purpose Input Output 1 EPWM1_B 1 O ePWM-1 Output B I2CA_SCL 6 I/OD SPIA_SOMI 7 I/O SPI-A Slave Out, Master In (SOMI) MCAN_TX 10 O CAN/CAN FD Transmit CLB_OUTPUTXBAR7 11 O CLB Output X-BAR Output 7 HIC_A2 13 I HIC Address 2 FSITXA_TDM_D1 14 I FSITX-A Time Division Multiplexed Additional Data Input HIC_D10 78 62 51 51 41 I2C-A Open-Drain Bidirectional Clock 15 I/O HIC Data 10 0, 4, 8, 12 I/O General-Purpose Input Output 2 EPWM2_A 1 O ePWM-2 Output A OUTPUTXBAR1 5 O Output X-BAR Output 1 PMBUSA_SDA 6 I/OD SPIA_SIMO 7 I/O SPI-A Slave In, Master Out (SIMO) GPIO2 SCIA_TX 9 O SCI-A Transmit Data FSIRXA_D1 10 I FSIRX-A Optional Additional Data Input I2CB_SDA 11 I/OD HIC_A1 13 I HIC Address 1 CANA_TX 14 O CAN-A Transmit HIC_D9 15 I/O HIC Data 9 GPIO3 0, 4, 8, 12 I/O General-Purpose Input Output 3 1 O ePWM-2 Output B 2, 5 O Output X-BAR Output 2 PMBUSA_SCL 6 I/OD SPIA_CLK 7 I/O SCIA_RX 9 FSIRXA_D0 EPWM2_B OUTPUTXBAR2 77 76 61 60 50 49 50 49 40 PMBus-A Open-Drain Bidirectional Data 39 I2C-B Open-Drain Bidirectional Data PMBus-A Open-Drain Bidirectional Clock SPI-A Clock I SCI-A Receive Data 10 I FSIRX-A Primary Data Input I2CB_SCL 11 I/OD HIC_NOE 13 O HIC Output enable for data bus CANA_RX 14 I CAN-A Receive HIC_D4 15 I/O HIC Data 4 GPIO4 0, 4, 8, 12 I/O General-Purpose Input Output 4 EPWM3_A 1 O ePWM-3 Output A MCAN_TX 3 O CAN/CAN FD Transmit OUTPUTXBAR3 5 O Output X-BAR Output 3 CANA_TX 6 O CAN-A Transmit SPIB_CLK 7 I/O SPI-B Clock EQEP2_STROBE 9 I/O eQEP-2 Strobe FSIRXA_CLK 10 I FSIRX-A Input Clock CLB_OUTPUTXBAR6 11 O CLB Output X-BAR Output 6 HIC_BASESEL2 13 I HIC Base address range select 2 HIC_NWE 15 I HIC Data Write enable from host 22 Submit Document Feedback 75 59 48 48 38 I2C-B Open-Drain Bidirectional Clock Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-1. Pin Attributes (continued) SIGNAL NAME GPIO5 MUX POSITION 100 PZ 80 PN 64 PMQ 64 PM 48 PT PIN TYPE DESCRIPTION 0, 4, 8, 12 I/O General-Purpose Input Output 5 EPWM3_B 1 O ePWM-3 Output B OUTPUTXBAR3 3 O Output X-BAR Output 3 MCAN_RX 5 I CAN/CAN FD Receive CANA_RX 6 I CAN-A Receive SPIA_STE 7 89 74 61 61 47 I/O SPI-A Slave Transmit Enable (STE) FSITXA_D1 9 O FSITX-A Optional Additional Data Output CLB_OUTPUTXBAR5 10 O CLB Output X-BAR Output 5 HIC_A7 13 I HIC Address 7 HIC_D4 14 I/O HIC Data 4 HIC_D15 15 I/O HIC Data 15 0, 4, 8, 12 I/O General-Purpose Input Output 6 EPWM4_A 1 O ePWM-4 Output A OUTPUTXBAR4 2 O Output X-BAR Output 4 SYNCOUT 3 O External ePWM Synchronization Pulse EQEP1_A 5 I eQEP-1 Input A SPIB_SOMI 7 FSITXA_D0 GPIO6 I/O SPI-B Slave Out, Master In (SOMI) 9 O FSITX-A Primary Data Output FSITXA_D1 11 O FSITX-A Optional Additional Data Output HIC_NBE1 13 I HIC Byte enable 1 CLB_OUTPUTXBAR8 14 O CLB Output X-BAR Output 8 HIC_D14 15 I/O HIC Data 14 0, 4, 8, 12 I/O General-Purpose Input Output 7 EPWM4_B 1 O ePWM-4 Output B OUTPUTXBAR5 3 O Output X-BAR Output 5 EQEP1_B 5 I eQEP-1 Input B SPIB_SIMO 7 FSITXA_CLK GPIO7 97 SPI-B Slave In, Master Out (SIMO) FSITX-A Output Clock CLB_OUTPUTXBAR2 10 O CLB Output X-BAR Output 2 HIC_A6 13 I HIC Address 6 HIC_D14 15 I/O HIC Data 14 0, 4, 8, 12 I/O General-Purpose Input Output 8 EPWM5_A 1 O ePWM-5 Output A ADCSOCAO 3 O ADC Start of Conversion A for External ADC EQEP1_STROBE 5 I/O eQEP-1 Strobe SCIA_TX 6 O SCI-A Transmit Data SPIA_SIMO 7 I/O SPI-A Slave In, Master Out (SIMO) I2CA_SCL 9 FSITXA_D1 10 O FSITX-A Optional Additional Data Output CLB_OUTPUTXBAR5 11 O CLB Output X-BAR Output 5 HIC_A0 13 I HIC Address 0 FSITXA_TDM_CLK 14 I FSITX-A Time Division Multiplexed Clock Input HIC_D8 15 I/O Copyright © 2022 Texas Instruments Incorporated 47 57 48 O 58 57 64 9 74 68 64 I/O GPIO8 84 80 47 43 I/OD I2C-A Open-Drain Bidirectional Clock HIC Data 8 Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 23 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-1. Pin Attributes (continued) SIGNAL NAME GPIO9 MUX POSITION 100 PZ 80 PN 64 PMQ 64 PM 48 PT PIN TYPE DESCRIPTION 0, 4, 8, 12 I/O General-Purpose Input Output 9 EPWM5_B 1 O ePWM-5 Output B SCIB_TX 2 O SCI-B Transmit Data OUTPUTXBAR6 3 O Output X-BAR Output 6 EQEP1_INDEX 5 I/O eQEP-1 Index SCIA_RX 6 I 90 75 62 62 SCI-A Receive Data SPIA_CLK 7 I/O SPI-A Clock FSITXA_D0 10 O FSITX-A Primary Data Output LINB_RX 11 I LIN-B Receive HIC_BASESEL0 13 I HIC Base address range select 0 I2CB_SCL 14 I/OD HIC_NRDY 15 O HIC Ready from device to host 0, 4, 8, 12 I/O General-Purpose Input Output 10 EPWM6_A 1 O ePWM-6 Output A ADCSOCBO 3 O ADC Start of Conversion B for External ADC EQEP1_A 5 I eQEP-1 Input A SCIB_TX 6 O SCI-B Transmit Data SPIA_SOMI 7 I/O SPI-A Slave Out, Master In (SOMI) I2CA_SDA 9 FSITXA_CLK 10 O FSITX-A Output Clock LINB_TX 11 O LIN-B Transmit HIC_NWE 13 I HIC Data Write enable from host FSITXA_TDM_D0 14 I FSITX-A Time Division Multiplexed Data Input CLB_OUTPUTXBAR4 15 O CLB Output X-BAR Output 4 GPIO10 GPIO11 93 76 63 63 I/OD I2C-B Open-Drain Bidirectional Clock I2C-A Open-Drain Bidirectional Data 0, 4, 8, 12 I/O General-Purpose Input Output 11 EPWM6_B 1 O ePWM-6 Output B OUTPUTXBAR7 3 O Output X-BAR Output 7 EQEP1_B 5 I eQEP-1 Input B SCIB_RX 6 I SCI-B Receive Data SPIA_STE 7 I/O FSIRXA_D1 9 LINB_RX 52 37 31 31 SPI-A Slave Transmit Enable (STE) I FSIRX-A Optional Additional Data Input 10 I LIN-B Receive EQEP2_A 11 I eQEP-2 Input A SPIA_SIMO 13 I/O SPI-A Slave In, Master Out (SIMO) HIC_D6 14 I/O HIC Data 6 HIC_NBE0 15 I 0, 4, 8, 12 I/O General-Purpose Input Output 12 EPWM7_A 1 O ePWM-7 Output A MCAN_RX 3 I CAN/CAN FD Receive EQEP1_STROBE 5 I/O eQEP-1 Strobe SCIB_TX 6 O SCI-B Transmit Data PMBUSA_CTL 7 I/O PMBus-A Control Signal - Slave Input/Master Output FSIRXA_D0 9 LINB_TX GPIO12 51 36 30 30 HIC Byte enable 0 I FSIRX-A Primary Data Input 10 O LIN-B Transmit SPIA_CLK 11 I/O SPI-A Clock CANA_RX 13 I HIC_D13 14 I/O HIC Data 13 HIC_INT 15 O HIC Device interrupt to host 24 Submit Document Feedback CAN-A Receive Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-1. Pin Attributes (continued) SIGNAL NAME GPIO13 MUX POSITION 100 PZ 80 PN 64 PMQ 64 PM 48 PT PIN TYPE DESCRIPTION 0, 4, 8, 12 I/O General-Purpose Input Output 13 EPWM7_B 1 O ePWM-7 Output B MCAN_TX 3 O CAN/CAN FD Transmit EQEP1_INDEX 5 I/O eQEP-1 Index SCIB_RX 6 I PMBUSA_ALERT 7 I/OD 50 35 29 29 SCI-B Receive Data PMBus-A Open-Drain Bidirectional Alert Signal FSIRXA_CLK 9 I FSIRX-A Input Clock LINB_RX 10 I LIN-B Receive SPIA_SOMI 11 I/O SPI-A Slave Out, Master In (SOMI) CANA_TX 13 O CAN-A Transmit HIC_D11 14 I/O HIC Data 11 HIC_D5 15 I/O HIC Data 5 GPIO14 0, 4, 8, 12 I/O General-Purpose Input Output 14 EPWM8_A 1 O ePWM-8 Output A SCIB_TX 2 O SCI-B Transmit Data I2CB_SDA 5 I/OD OUTPUTXBAR3 6 O PMBUSA_SDA 7 I/OD SPIB_CLK 9 EQEP2_A 10 I eQEP-2 Input A LINB_TX 11 O LIN-B Transmit EPWM3_A 13 O ePWM-3 Output A CLB_OUTPUTXBAR7 14 O CLB Output X-BAR Output 7 HIC_D15 15 I/O HIC Data 15 GPIO15 96 79 I/O I2C-B Open-Drain Bidirectional Data Output X-BAR Output 3 PMBus-A Open-Drain Bidirectional Data SPI-B Clock 0, 4, 8, 12 I/O General-Purpose Input Output 15 EPWM8_B 1 O ePWM-8 Output B SCIB_RX 2 I SCI-B Receive Data I2CB_SCL 5 I/OD OUTPUTXBAR4 6 O PMBUSA_SCL 7 I/OD SPIB_STE 9 EQEP2_B 10 I eQEP-2 Input B LINB_RX 11 I LIN-B Receive EPWM3_B 13 O ePWM-3 Output B CLB_OUTPUTXBAR6 14 O CLB Output X-BAR Output 6 HIC_D12 15 I/O HIC Data 12 GPIO16 0, 4, 8, 12 I/O General-Purpose Input Output 16 SPIA_SIMO 1 I/O SPI-A Slave In, Master Out (SIMO) OUTPUTXBAR7 3 O Output X-BAR Output 7 EPWM5_A 5 O ePWM-5 Output A SCIA_TX 6 O SCI-A Transmit Data SD1_D1 7 I SDFM-1 Channel 1 Data Input EQEP1_STROBE 9 PMBUSA_SCL 10 I/OD XCLKOUT 11 O External Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device. EQEP2_B 13 I eQEP-2 Input B SPIB_SOMI 14 I/O SPI-B Slave Out, Master In (SOMI) HIC_D1 15 I/O HIC Data 1 Copyright © 2022 Texas Instruments Incorporated 95 54 78 39 I/O 33 33 26 I/O I2C-B Open-Drain Bidirectional Clock Output X-BAR Output 4 PMBus-A Open-Drain Bidirectional Clock SPI-B Slave Transmit Enable (STE) eQEP-1 Strobe PMBus-A Open-Drain Bidirectional Clock Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 25 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-1. Pin Attributes (continued) SIGNAL NAME GPIO17 MUX POSITION 100 PZ 80 PN 64 PMQ 64 PM 48 PT PIN TYPE DESCRIPTION 0, 4, 8, 12 I/O General-Purpose Input Output 17 SPIA_SOMI 1 I/O SPI-A Slave Out, Master In (SOMI) OUTPUTXBAR8 3 O Output X-BAR Output 8 EPWM5_B 5 O ePWM-5 Output B SCIA_RX 6 I SCI-A Receive Data SD1_C1 7 I SDFM-1 Channel 1 Clock Input 55 40 34 34 EQEP1_INDEX 9 I/O PMBUSA_SDA 10 I/OD CANA_TX 11 O CAN-A Transmit HIC_D2 15 I/O HIC Data 2 GPIO18 0, 4, 8, 12 I/O General-Purpose Input Output 18 SPIA_CLK 1 I/O SPI-A Clock SCIB_TX 2 O SCI-B Transmit Data CANA_RX 3 I CAN-A Receive EPWM6_A 5 O ePWM-6 Output A I2CA_SCL 6 I/OD SD1_D2 7 I SDFM-1 Channel 2 Data Input EQEP2_A 9 I eQEP-2 Input A PMBUSA_CTL 10 I/O PMBus-A Control Signal - Slave Input/Master Output XCLKOUT 11 O External Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device. LINB_TX 13 O LIN-B Transmit FSITXA_TDM_CLK 14 I FSITX-A Time Division Multiplexed Clock Input HIC_INT 15 O HIC Device interrupt to host ALT I/O Crystal oscillator output. X2 GPIO19 68 50 41 41 33 eQEP-1 Index PMBus-A Open-Drain Bidirectional Data I2C-A Open-Drain Bidirectional Clock 0, 4, 8, 12 I/O General-Purpose Input Output 19 SPIA_STE 1 I/O SPI-A Slave Transmit Enable (STE) SCIB_RX 2 I SCI-B Receive Data CANA_TX 3 O CAN-A Transmit EPWM6_B 5 O ePWM-6 Output B I2CA_SDA 6 I/OD SD1_C2 7 I SDFM-1 Channel 2 Clock Input EQEP2_B 9 I eQEP-2 Input B PMBUSA_ALERT 10 I/OD 69 51 42 42 34 I2C-A Open-Drain Bidirectional Data PMBus-A Open-Drain Bidirectional Alert Signal CLB_OUTPUTXBAR1 11 O CLB Output X-BAR Output 1 LINB_RX 13 I LIN-B Receive FSITXA_TDM_D0 14 I FSITX-A Time Division Multiplexed Data Input HIC_NBE0 15 I HIC Byte enable 0 X1 GPIO20 ALT I/O Crystal oscillator input or single-ended clock input. The device initialization software must configure this pin before the crystal oscillator is enabled. To use this oscillator, a quartz crystal circuit must be connected to X1 and X2. This pin can also be used to feed a single-ended 3.3-V level clock. See the XTAL section for usage details. 0, 4, 8, 12 I/O General-Purpose Input Output 20 This pin also has analog functions which are described in the ANALOG section of this table. EQEP1_A 1 SPIB_SIMO 6 I/O SD1_D3 7 I SDFM-1 Channel 3 Data Input MCAN_TX 9 O CAN/CAN FD Transmit 26 Submit Document Feedback 48 33 I eQEP-1 Input A SPI-B Slave In, Master Out (SIMO) Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-1. Pin Attributes (continued) SIGNAL NAME GPIO21 MUX POSITION 100 PZ 80 PN 64 PMQ 64 PM 48 PT 0, 4, 8, 12 PIN TYPE I/O General-Purpose Input Output 21 This pin also has analog functions which are described in the ANALOG section of this table. EQEP1_B 1 SPIB_SOMI 6 I/O SD1_C3 7 I SDFM-1 Channel 3 Clock Input CAN/CAN FD Receive MCAN_RX 49 I DESCRIPTION 34 eQEP-1 Input B SPI-B Slave Out, Master In (SOMI) 9 I 0, 4, 8, 12 I/O General-Purpose Input Output 22 EQEP1_STROBE 1 I/O eQEP-1 Strobe SCIB_TX 3 O SCI-B Transmit Data SPIB_CLK 6 I/O SPI-B Clock SD1_D4 7 I SDFM-1 Channel 4 Data Input LINA_TX 9 O LIN-A Transmit CLB_OUTPUTXBAR1 10 O CLB Output X-BAR Output 1 LINB_TX 11 O LIN-B Transmit HIC_A5 13 I HIC Address 5 EPWM4_A 14 O ePWM-4 Output A HIC_D13 15 I/O HIC Data 13 GPIO23 0, 4, 8, 12 I/O General-Purpose Input Output 23 EQEP1_INDEX 1 I/O eQEP-1 Index SCIB_RX 3 I SPIB_STE 6 I/O SD1_C4 7 I SDFM-1 Channel 4 Clock Input LINA_RX 9 I LIN-A Receive CLB_OUTPUTXBAR3 10 O CLB Output X-BAR Output 3 LINB_RX 11 I LIN-B Receive HIC_A3 13 I HIC Address 3 EPWM4_B 14 O ePWM-4 Output B HIC_D11 15 I/O HIC Data 11 GPIO24 0, 4, 8, 12 I/O General-Purpose Input Output 24 OUTPUTXBAR1 1 O Output X-BAR Output 1 EQEP2_A 2 I eQEP-2 Input A EPWM8_A 5 O ePWM-8 Output A SPIB_SIMO 6 I/O SPI-B Slave In, Master Out (SIMO) SD2_D1 7 I SDFM-2 Channel 1 Data Input LINB_TX 9 O LIN-B Transmit PMBUSA_SCL 10 I/OD SCIA_TX 11 O SCI-A Transmit Data ERRORSTS 13 O Error Status Output. This signal requires an external pulldown. HIC_D3 15 I/O HIC Data 3 GPIO25 0, 4, 8, 12 I/O General-Purpose Input Output 25 OUTPUTXBAR2 1 O Output X-BAR Output 2 EQEP2_B 2 I eQEP-2 Input B EQEP1_A 5 I eQEP-1 Input A SPIB_SOMI 6 I/O SD2_C1 7 FSITXA_D1 GPIO22 83 81 56 57 67 65 41 42 56 54 35 56 54 35 27 SCI-B Receive Data SPI-B Slave Transmit Enable (STE) PMBus-A Open-Drain Bidirectional Clock SPI-B Slave Out, Master In (SOMI) I SDFM-2 Channel 1 Clock Input 9 O FSITX-A Optional Additional Data Output PMBUSA_SDA 10 I/OD PMBus-A Open-Drain Bidirectional Data SCIA_RX 11 I SCI-A Receive Data HIC_BASESEL0 14 I HIC Base address range select 0 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 27 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-1. Pin Attributes (continued) SIGNAL NAME GPIO26 MUX POSITION 100 PZ 80 PN 64 PMQ 64 PM 48 PT PIN TYPE DESCRIPTION 0, 4, 8, 12 I/O General-Purpose Input Output 26 OUTPUTXBAR3 1, 5 O Output X-BAR Output 3 EQEP2_INDEX 2 I/O eQEP-2 Index SPIB_CLK 6 I/O SPI-B Clock SD2_D2 7 I SDFM-2 Channel 2 Data Input FSITXA_D0 9 O FSITX-A Primary Data Output PMBUSA_CTL 10 I/O PMBus-A Control Signal - Slave Input/Master Output I2CA_SDA 11 I/OD HIC_D0 14 I/O HIC_A1 15 I GPIO27 0, 4, 8, 12 I/O General-Purpose Input Output 27 1, 5 O Output X-BAR Output 4 EQEP2_STROBE 2 I/O eQEP-2 Strobe SPIB_STE 6 I/O SPI-B Slave Transmit Enable (STE) SD2_C2 7 I SDFM-2 Channel 2 Clock Input O FSITX-A Output Clock OUTPUTXBAR4 58 59 43 44 I2C-A Open-Drain Bidirectional Data HIC Data 0 HIC Address 1 FSITXA_CLK 9 PMBUSA_ALERT 10 I/OD PMBus-A Open-Drain Bidirectional Alert Signal I2CA_SCL 11 I/OD I2C-A Open-Drain Bidirectional Clock HIC_D1 14 I/O HIC_A4 15 I GPIO28 0, 4, 8, 12 I/O SCIA_RX 1 I SCI-A Receive Data EPWM7_A 3 O ePWM-7 Output A OUTPUTXBAR5 5 O Output X-BAR Output 5 EQEP1_A 6 I eQEP-1 Input A SD2_D3 7 I SDFM-2 Channel 3 Data Input EQEP2_STROBE 9 LINA_TX 1 4 2 2 2 HIC Data 1 HIC Address 4 General-Purpose Input Output 28 I/O eQEP-2 Strobe 10 O LIN-A Transmit SPIB_CLK 11 I/O SPI-B Clock ERRORSTS 13 O Error Status Output. This signal requires an external pulldown. I2CB_SDA 14 I/OD HIC_NOE 15 O HIC Output enable for data bus GPIO29 0, 4, 8, 12 I/O General-Purpose Input Output 29 SCIA_TX 1 O SCI-A Transmit Data EPWM7_B 3 O ePWM-7 Output B OUTPUTXBAR6 5 O Output X-BAR Output 6 EQEP1_B 6 I eQEP-1 Input B SD2_C3 7 I SDFM-2 Channel 3 Clock Input EQEP2_INDEX 9 I/O eQEP-2 Index LINA_RX 10 I LIN-A Receive SPIB_STE 11 I/O SPI-B Slave Transmit Enable (STE) ERRORSTS 13 O Error Status Output. This signal requires an external pulldown. I2CB_SCL 14 I/OD HIC_NCS 15 I HIC Chip select input ALT I Auxilary Clock Input AUXCLKIN 28 Submit Document Feedback 100 3 1 1 1 I2C-B Open-Drain Bidirectional Data I2C-B Open-Drain Bidirectional Clock Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-1. Pin Attributes (continued) SIGNAL NAME GPIO30 MUX POSITION 100 PZ 80 PN 64 PMQ 64 PM 48 PT PIN TYPE DESCRIPTION 0, 4, 8, 12 I/O CANA_RX 1 I SPIB_SIMO 3 I/O SPI-B Slave In, Master Out (SIMO) OUTPUTXBAR7 5 O Output X-BAR Output 7 EQEP1_STROBE 6 I/O eQEP-1 Strobe SD2_D4 7 98 1 General-Purpose Input Output 30 CAN-A Receive I SDFM-2 Channel 4 Data Input FSIRXA_CLK 9 I FSIRX-A Input Clock MCAN_RX 10 I CAN/CAN FD Receive EPWM1_A 11 O ePWM-1 Output A HIC_D8 14 I/O HIC Data 8 GPIO31 0, 4, 8, 12 I/O General-Purpose Input Output 31 CANA_TX 1 O CAN-A Transmit SPIB_SOMI 3 I/O SPI-B Slave Out, Master In (SOMI) OUTPUTXBAR8 5 O Output X-BAR Output 8 EQEP1_INDEX 6 I/O eQEP-1 Index SD2_C4 7 I SDFM-2 Channel 4 Clock Input FSIRXA_D1 9 I FSIRX-A Optional Additional Data Input MCAN_TX 10 O CAN/CAN FD Transmit EPWM1_B 11 O ePWM-1 Output B HIC_D10 14 I/O HIC Data 10 GPIO32 0, 4, 8, 12 I/O General-Purpose Input Output 32 I2CA_SDA 1 I/OD SPIB_CLK 3 I/O SPI-B Clock EPWM8_B 5 O ePWM-8 Output B LINA_TX 6 O LIN-A Transmit SD1_D2 7 I SDFM-1 Channel 2 Data Input FSIRXA_D0 9 I FSIRX-A Primary Data Input CANA_TX 10 O CAN-A Transmit PMBUSA_SDA 11 I/OD ADCSOCBO 13 O ADC Start of Conversion B for External ADC HIC_INT 15 O HIC Device interrupt to host GPIO33 0, 4, 8, 12 I/O General-Purpose Input Output 33 I2CA_SCL 1 I/OD SPIB_STE 3 I/O SPI-B Slave Transmit Enable (STE) OUTPUTXBAR4 5 O Output X-BAR Output 4 LINA_RX 6 I LIN-A Receive SD1_C2 7 I SDFM-1 Channel 2 Clock Input FSIRXA_CLK 9 I FSIRX-A Input Clock CANA_RX 10 I CAN-A Receive EQEP2_B 11 I eQEP-2 Input B ADCSOCAO 13 O ADC Start of Conversion A for External ADC SD1_C1 14 I SDFM-1 Channel 1 Clock Input HIC_D0 15 I/O HIC Data 0 GPIO34 99 64 53 2 49 38 40 32 40 32 32 25 I2C-A Open-Drain Bidirectional Data PMBus-A Open-Drain Bidirectional Data I2C-A Open-Drain Bidirectional Clock 0, 4, 8, 12 I/O General-Purpose Input Output 34 OUTPUTXBAR1 1 O Output X-BAR Output 1 PMBUSA_SDA 6 I/OD HIC_NBE1 13 I2CB_SDA 14 I/OD HIC_D9 15 I/O Copyright © 2022 Texas Instruments Incorporated 94 77 I PMBus-A Open-Drain Bidirectional Data HIC Byte enable 1 I2C-B Open-Drain Bidirectional Data HIC Data 9 Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 29 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-1. Pin Attributes (continued) SIGNAL NAME GPIO35 MUX POSITION 100 PZ 80 PN 64 PMQ 64 PM 48 PT PIN TYPE DESCRIPTION 0, 4, 8, 12 I/O SCIA_RX 1 I I2CA_SDA 3 I/OD CANA_RX 5 I PMBUSA_SCL 6 I/OD LINA_RX 7 I LIN-A Receive I eQEP-1 Input A EQEP1_A 9 PMBUSA_CTL 10 EPWM5_B 63 48 39 39 31 General-Purpose Input Output 35 SCI-A Receive Data I2C-A Open-Drain Bidirectional Data CAN-A Receive PMBus-A Open-Drain Bidirectional Clock I/O PMBus-A Control Signal - Slave Input/Master Output 11 O ePWM-5 Output B SD2_C1 13 I SDFM-2 Channel 1 Clock Input HIC_NWE 14 I HIC Data Write enable from host 15 I JTAG Test Data Input (TDI) - TDI is the default mux selection for the pin. The internal pullup is disabled by default. The internal pullup should be enabled or an external pullup added on the board if this pin is used as JTAG TDI to avoid a floating input. TDI GPIO37 0, 4, 8, 12 I/O General-Purpose Input Output 37 OUTPUTXBAR2 1 O Output X-BAR Output 2 I2CA_SCL 3 I/OD SCIA_TX 5 O SCI-A Transmit Data CANA_TX 6 O CAN-A Transmit LINA_TX 7 O LIN-A Transmit EQEP1_B 9 I eQEP-1 Input B PMBUSA_ALERT 10 HIC_NRDY 14 TDO GPIO39 61 46 37 37 29 I/OD I2C-A Open-Drain Bidirectional Clock PMBus-A Open-Drain Bidirectional Alert Signal O HIC Ready from device to host 15 O JTAG Test Data Output (TDO) - TDO is the default mux selection for the pin. The internal pullup is disabled by default. The TDO function will tristate when there is no JTAG activity, leaving this pin floating; the internal pullup should be enabled or an external pullup added on the board to avoid a floating GPIO input. General-Purpose Input Output 39 0, 4, 8, 12 I/O MCAN_RX 6 I CAN/CAN FD Receive FSIRXA_CLK 7 I FSIRX-A Input Clock EQEP2_INDEX 9 I/O eQEP-2 Index CLB_OUTPUTXBAR2 11 O CLB Output X-BAR Output 2 SYNCOUT 13 O External ePWM Synchronization Pulse EQEP1_INDEX 14 I/O eQEP-1 Index HIC_D7 15 I/O HIC Data 7 GPIO40 0, 4, 8, 12 I/O General-Purpose Input Output 40 SPIB_SIMO 1 I/O SPI-B Slave In, Master Out (SIMO) EPWM2_B 5 O ePWM-2 Output B PMBUSA_SDA 6 I/OD FSIRXA_D0 7 SCIB_TX 9 EQEP1_A 56 46 PMBus-A Open-Drain Bidirectional Data I FSIRX-A Primary Data Input O SCI-B Transmit Data 10 I eQEP-1 Input A LINB_TX 11 O LIN-B Transmit HIC_NBE1 14 I HIC Byte enable 1 HIC_D5 15 I/O 30 Submit Document Feedback 80 64 53 53 HIC Data 5 Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-1. Pin Attributes (continued) SIGNAL NAME GPIO41 MUX POSITION 100 PZ 80 PN 64 PMQ 64 PM 48 PT PIN TYPE DESCRIPTION 0, 4, 8, 12 I/O General-Purpose Input Output 41 EPWM2_A 5 O ePWM-2 Output A PMBUSA_SCL 6 I/OD FSIRXA_D1 7 I FSIRX-A Optional Additional Data Input SCIB_RX 9 I SCI-B Receive Data EQEP1_B 10 I eQEP-1 Input B 82 66 55 55 PMBus-A Open-Drain Bidirectional Clock LINB_RX 11 I LIN-B Receive HIC_A4 13 I HIC Address 4 SPIB_SOMI 14 I/O SPI-B Slave Out, Master In (SOMI) HIC_D12 15 I/O HIC Data 12 GPIO42 0, 4, 8, 12 I/O General-Purpose Input Output 42 LINA_RX 2 I LIN-A Receive OUTPUTXBAR5 3 O Output X-BAR Output 5 PMBUSA_CTL 5 I/O PMBus-A Control Signal - Slave Input/Master Output I2CA_SDA 6 EQEP1_STROBE 10 I/O eQEP-1 Strobe CLB_OUTPUTXBAR3 11 O CLB Output X-BAR Output 3 HIC_D2 14 I/O HIC Data 2 HIC_A6 15 I GPIO43 0, 4, 8, 12 I/O General-Purpose Input Output 43 OUTPUTXBAR6 3 O Output X-BAR Output 6 PMBUSA_ALERT 5, 9 I/OD PMBus-A Open-Drain Bidirectional Alert Signal I2CA_SCL 6 I/OD I2C-A Open-Drain Bidirectional Clock EQEP1_INDEX 10 57 54 I/OD I2C-A Open-Drain Bidirectional Data HIC Address 6 I/O eQEP-1 Index CLB_OUTPUTXBAR4 11 O CLB Output X-BAR Output 4 SD2_D3 13 I SDFM-2 Channel 3 Data Input HIC_D3 14 I/O HIC_A7 15 I GPIO44 0, 4, 8, 12 I/O General-Purpose Input Output 44 OUTPUTXBAR7 3 O Output X-BAR Output 7 EQEP1_A 5 I eQEP-1 Input A PMBUSA_SDA 6 I/OD FSITXA_CLK 7 O FSITX-A Output Clock PMBUSA_CTL 9 I/O PMBus-A Control Signal - Slave Input/Master Output CLB_OUTPUTXBAR3 10 O CLB Output X-BAR Output 3 FSIRXA_D0 11 I FSIRX-A Primary Data Input HIC_D7 13 I/O HIC Data 7 LINB_TX 14 O LIN-B Transmit HIC_D5 15 I/O HIC Data 5 GPIO45 0, 4, 8, 12 I/O General-Purpose Input Output 45 OUTPUTXBAR8 3 O Output X-BAR Output 8 FSITXA_D0 7 O FSITX-A Primary Data Output PMBUSA_ALERT 9 CLB_OUTPUTXBAR4 10 O CLB Output X-BAR Output 4 SD2_C3 13 I SDFM-2 Channel 3 Clock Input HIC_D6 15 I/O Copyright © 2022 Texas Instruments Incorporated 85 69 73 I/OD HIC Data 3 HIC Address 7 PMBus-A Open-Drain Bidirectional Data PMBus-A Open-Drain Bidirectional Alert Signal HIC Data 6 Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 31 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-1. Pin Attributes (continued) SIGNAL NAME MUX POSITION 100 PZ 80 PN 64 PMQ 64 PM 48 PT PIN TYPE DESCRIPTION GPIO46 0, 4, 8, 12 I/O General-Purpose Input Output 46 LINA_TX 3 O LIN-A Transmit MCAN_TX 5 O CAN/CAN FD Transmit FSITXA_D1 7 O FSITX-A Optional Additional Data Output PMBUSA_SDA 9 I/OD PMBus-A Open-Drain Bidirectional Data SD2_C4 13 I SDFM-2 Channel 4 Clock Input HIC_NWE 6 15 I HIC Data Write enable from host GPIO47 0, 4, 8, 12 I/O General-Purpose Input Output 47 LINA_RX 3 I LIN-A Receive MCAN_RX 5 I CAN/CAN FD Receive CLB_OUTPUTXBAR2 7 O CLB Output X-BAR Output 2 PMBUSA_SCL 9 SD2_D4 13 I SDFM-2 Channel 4 Data Input FSITXA_TDM_CLK 14 I FSITX-A Time Division Multiplexed Clock Input HIC_A6 15 I HIC Address 6 GPIO48 6 I/OD PMBus-A Open-Drain Bidirectional Clock 0, 4, 8, 12 I/O General-Purpose Input Output 48 OUTPUTXBAR3 1 O Output X-BAR Output 3 CANA_TX 3 O CAN-A Transmit SCIA_TX 6 O SCI-A Transmit Data SD1_D1 7 I SDFM-1 Channel 1 Data Input PMBUSA_SDA 9 I/OD HIC_A7 15 I GPIO49 0, 4, 8, 12 I/O General-Purpose Input Output 49 OUTPUTXBAR4 1 O Output X-BAR Output 4 CANA_RX 3 I CAN-A Receive SCIA_RX 6 I SCI-A Receive Data SD1_C1 7 I SDFM-1 Channel 1 Clock Input LINA_RX 9 I LIN-A Receive SD2_D1 13 I SDFM-2 Channel 1 Data Input FSITXA_D0 14 O FSITX-A Primary Data Output HIC_D2 15 I/O HIC Data 2 GPIO50 0, 4, 8, 12 I/O General-Purpose Input Output 50 EQEP1_A 1 I eQEP-1 Input A MCAN_TX 5 O CAN/CAN FD Transmit SPIB_SIMO 6 I/O SPI-B Slave In, Master Out (SIMO) SD1_D2 7 I2CB_SDA 9 I/OD SD2_D2 13 I SDFM-2 Channel 2 Data Input FSITXA_D1 14 O FSITX-A Optional Additional Data Output HIC_D3 15 I/O HIC Data 3 GPIO51 0, 4, 8, 12 I/O General-Purpose Input Output 51 EQEP1_B 1 I eQEP-1 Input B MCAN_RX 5 I CAN/CAN FD Receive SPIB_SOMI 6 I/O SD1_C2 7 I2CB_SCL 9 I/OD SD2_D3 13 I SDFM-2 Channel 3 Data Input FSITXA_CLK 14 O FSITX-A Output Clock HIC_D6 15 I/O HIC Data 6 32 Submit Document Feedback 7 8 9 10 I I PMBus-A Open-Drain Bidirectional Data HIC Address 7 SDFM-1 Channel 2 Data Input I2C-B Open-Drain Bidirectional Data SPI-B Slave Out, Master In (SOMI) SDFM-1 Channel 2 Clock Input I2C-B Open-Drain Bidirectional Clock Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-1. Pin Attributes (continued) SIGNAL NAME GPIO52 MUX POSITION 100 PZ 80 PN 64 PMQ 64 PM 48 PT PIN TYPE DESCRIPTION 0, 4, 8, 12 I/O General-Purpose Input Output 52 EQEP1_STROBE 1 I/O eQEP-1 Strobe CLB_OUTPUTXBAR5 5 O CLB Output X-BAR Output 5 SPIB_CLK 6 I/O SPI-B Clock SD1_D3 7 SYNCOUT I SDFM-1 Channel 3 Data Input 9 O External ePWM Synchronization Pulse SD2_D4 13 I SDFM-2 Channel 4 Data Input FSIRXA_D0 14 I FSIRX-A Primary Data Input HIC_NWE 15 I HIC Data Write enable from host 0, 4, 8, 12 I/O General-Purpose Input Output 53 EQEP1_INDEX 1 I/O eQEP-1 Index CLB_OUTPUTXBAR6 5 O CLB Output X-BAR Output 6 SPIB_STE 6 I/O SPI-B Slave Transmit Enable (STE) SD1_C3 7 ADCSOCAO GPIO53 11 I SDFM-1 Channel 3 Clock Input 9 O ADC Start of Conversion A for External ADC CANA_RX 10 I CAN-A Receive SD1_C1 13 I SDFM-1 Channel 1 Clock Input FSIRXA_D1 14 I FSIRX-A Optional Additional Data Input 0, 4, 8, 12 I/O General-Purpose Input Output 54 SPIA_SIMO 1 I/O SPI-A Slave In, Master Out (SIMO) EQEP2_A 5 I eQEP-2 Input A OUTPUTXBAR2 6 O Output X-BAR Output 2 SD1_D4 7 I SDFM-1 Channel 4 Data Input ADCSOCBO 9 O ADC Start of Conversion B for External ADC LINB_TX 10 O LIN-B Transmit SD1_C2 13 I SDFM-1 Channel 2 Clock Input FSIRXA_CLK 14 I FSIRX-A Input Clock FSITXA_TDM_D1 15 I FSITX-A Time Division Multiplexed Additional Data Input GPIO54 GPIO55 12 13 0, 4, 8, 12 I/O General-Purpose Input Output 55 SPIA_SOMI 1 I/O SPI-A Slave Out, Master In (SOMI) EQEP2_B 5 I eQEP-2 Input B OUTPUTXBAR3 6 O Output X-BAR Output 3 SD1_C4 7 I SDFM-1 Channel 4 Clock Input ERRORSTS 9 O Error Status Output. This signal requires an external pulldown. LINB_RX 10 I LIN-B Receive SD1_C3 13 I SDFM-1 Channel 3 Clock Input HIC_A0 15 I HIC Address 0 Copyright © 2022 Texas Instruments Incorporated 43 Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 33 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-1. Pin Attributes (continued) SIGNAL NAME GPIO56 MUX POSITION 100 PZ 80 PN 64 PMQ 64 PM 48 PT PIN TYPE DESCRIPTION 0, 4, 8, 12 I/O General-Purpose Input Output 56 SPIA_CLK 1 I/O SPI-A Clock CLB_OUTPUTXBAR7 2 O CLB Output X-BAR Output 7 MCAN_TX 3 O CAN/CAN FD Transmit EQEP2_STROBE 5 I/O eQEP-2 Strobe SCIB_TX 6 O SCI-B Transmit Data SD2_D1 7 I SDFM-2 Channel 1 Data Input SPIB_SIMO 9 I/O I2CA_SDA 10 I/OD EQEP1_A 11 I eQEP-1 Input A SD1_C4 13 I SDFM-1 Channel 4 Clock Input FSIRXA_D1 14 I FSIRX-A Optional Additional Data Input HIC_D6 15 I/O HIC Data 6 GPIO57 0, 4, 8, 12 I/O General-Purpose Input Output 57 SPIA_STE 1 I/O SPI-A Slave Transmit Enable (STE) CLB_OUTPUTXBAR8 2 O CLB Output X-BAR Output 8 MCAN_RX 3 I CAN/CAN FD Receive EQEP2_INDEX 5 I/O SCIB_RX 6 I SCI-B Receive Data SD2_C1 7 I SDFM-2 Channel 1 Clock Input SPIB_SOMI 9 I/O I2CA_SCL 10 I/OD EQEP1_B 11 I eQEP-1 Input B FSIRXA_CLK 14 I FSIRX-A Input Clock HIC_D4 15 I/O HIC Data 4 GPIO58 65 66 SPI-B Slave In, Master Out (SIMO) I2C-A Open-Drain Bidirectional Data eQEP-2 Index SPI-B Slave Out, Master In (SOMI) I2C-A Open-Drain Bidirectional Clock 0, 4, 8, 12 I/O General-Purpose Input Output 58 OUTPUTXBAR1 5 O Output X-BAR Output 1 SPIB_CLK 6 I/O SPI-B Clock SD2_D2 7 I SDFM-2 Channel 2 Data Input LINA_TX 9 O LIN-A Transmit CANA_TX 10 O CAN-A Transmit EQEP1_STROBE 11 I/O eQEP-1 Strobe SD2_C2 13 I SDFM-2 Channel 2 Clock Input FSIRXA_D0 14 I FSIRX-A Primary Data Input HIC_NRDY 67 15 O HIC Ready from device to host 0, 4, 8, 12 I/O General-Purpose Input Output 59 OUTPUTXBAR2 5 O Output X-BAR Output 2 SPIB_STE 6 I/O SPI-B Slave Transmit Enable (STE) SD2_C2 7 I SDFM-2 Channel 2 Clock Input LINA_RX 9 I LIN-A Receive CANA_RX 10 I CAN-A Receive EQEP1_INDEX 11 I/O SD2_C3 13 I SDFM-2 Channel 3 Clock Input FSITXA_TDM_D1 14 I FSITX-A Time Division Multiplexed Additional Data Input GPIO59 34 Submit Document Feedback 92 eQEP-1 Index Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-1. Pin Attributes (continued) SIGNAL NAME GPIO60 MUX POSITION 100 PZ 80 PN 64 PMQ 64 PM 48 PT PIN TYPE DESCRIPTION 0, 4, 8, 12 I/O General-Purpose Input Output 60 MCAN_TX 3 O CAN/CAN FD Transmit OUTPUTXBAR3 5 O Output X-BAR Output 3 SPIB_SIMO 6 I/O SPI-B Slave In, Master Out (SIMO) SD2_D3 7 I SDFM-2 Channel 3 Data Input SD2_C4 13 I SDFM-2 Channel 4 Clock Input HIC Address 0 44 HIC_A0 15 I GPIO61 0, 4, 8, 12 I/O MCAN_RX 3 I CAN/CAN FD Receive OUTPUTXBAR4 5 O Output X-BAR Output 4 SPIB_SOMI 6 I/O SPI-B Slave Out, Master In (SOMI) SD2_C3 7 I SDFM-2 Channel 3 Clock Input CANA_RX 14 I CAN-A Receive I JTAG test clock with internal pullup. 91 General-Purpose Input Output 61 TEST, JTAG, AND RESET TCK 60 TMS 62 XRSn 2 45 47 5 36 38 3 36 38 3 28 30 3 I/O JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. This device does not have a TRSTn pin. An external pullup resistor (recommended 2.2 kΩ) on the TMS pin to VDDIO should be placed on the board to keep JTAG in reset during normal operation. I/OD Device Reset (in) and Watchdog Reset (out). During a power-on condition, this pin is driven low by the device. An external circuit may also drive this pin to assert a device reset. This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRSn pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. A resistor between 2.2 kΩ and 10 kΩ should be placed between XRSn and VDDIO. If a capacitor is placed between XRSn and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRSn pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. This pin is an open-drain output with an internal pullup. If this pin is driven by an external device, it should be done using an open-drain device. POWER AND GROUND 4, 46, 8, 31, 71, 87 53, 71 VDD VDDA 34 26 3, 47, 7, 32, 70, 88 52, 72 VDDIO VREGENZ 73 VSSA 33 Copyright © 2022 Texas Instruments Incorporated 22 28, 43, 60 4, 27, 23, 36, 44, 59 45 22 25 5, 26, 45, 58 21 1.2-V Digital Logic Power Pins. See the Power Management Module (PMM) section for usage details. 3.3-V Analog Power Pins. Place a minimum 2.2-µF decoupling capacitor on each pin. See the Power Management Module (PMM) section for usage details. 18 28, 43, 24, 35, 60 46 46 5, 45, 9, 30, 72, 86 55, 70 VSS 4, 27, 44, 59 3.3-V Digital I/O Power Pins. See the Power Management Module (PMM) section for usage details. I 5, 26, 22, 37, 45, 58 44 21 17 Internal voltage regulator disable with internal pulldown. Tie low to VSS to enable internal VREG. Tie high to VDDIO to use an external supply. See the Power Management Module (PMM) section for usage details. Digital Ground Analog Ground Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 35 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 5.3 Signal Descriptions 5.3.1 Analog Signals Table 5-2. Analog Signals 36 SIGNAL NAME PIN TYPE A0 I A1 A2 DESCRIPTION 100 PZ 80 PN 64 PMQ 64 PM 48 PT ADC-A Input 0 23 19 15 15 11 I ADC-A Input 1 22 18 14 14 10 I ADC-A Input 2 17 13 9 9 6 A3 I ADC-A Input 3 18 12 8 8 5 A4 I ADC-A Input 4 36 27 23 23 19 A5 I ADC-A Input 5 35 17 13 13 9 A6 I ADC-A Input 6 14 10 6 6 4 A7 I ADC-A Input 7 31 23 19 19 15 A8 I ADC-A Input 8 37 24 20 20 16 A9 I ADC-A Input 9 38 28 24 24 20 A10 I ADC-A Input 10 40 29 25 25 21 A11 I ADC-A Input 11 20 16 12 12 8 A12 I ADC-A Input 12 28 22 18 18 14 A14 I ADC-A Input 14 19 15 11 11 A15 I ADC-A Input 15 14 10 10 7 AIO224 I Analog Pin Used For Digital Input 224 17 13 9 9 6 AIO225 I Analog Pin Used For Digital Input 225 36 27 23 23 19 AIO226 I Analog Pin Used For Digital Input 226 15 11 7 7 4 AIO227 I Analog Pin Used For Digital Input 227 38 28 24 24 20 AIO228 I Analog Pin Used For Digital Input 228 14 10 6 6 4 AIO229 I Analog Pin Used For Digital Input 229 18 AIO230 I Analog Pin Used For Digital Input 230 40 29 25 25 21 AIO231 I Analog Pin Used For Digital Input 231 23 19 15 15 11 AIO232 I Analog Pin Used For Digital Input 232 22 18 14 14 10 AIO233 I Analog Pin Used For Digital Input 233 14 10 10 7 AIO236 I Analog Pin Used For Digital Input 236 39 28 24 24 20 AIO237 I Analog Pin Used For Digital Input 237 20 16 12 12 8 AIO238 I Analog Pin Used For Digital Input 238 28 22 18 18 14 AIO239 I Analog Pin Used For Digital Input 239 19 15 11 11 AIO240 I Analog Pin Used For Digital Input 240 37 AIO241 I Analog Pin Used For Digital Input 241 24 20 20 16 AIO242 I Analog Pin Used For Digital Input 242 16 12 8 8 5 AIO244 I Analog Pin Used For Digital Input 244 21 17 13 13 9 AIO245 I Analog Pin Used For Digital Input 245 31 23 19 19 15 AIO247 I Analog Pin Used For Digital Input 247 42 AIO248 I Analog Pin Used For Digital Input 248 29 22 18 18 14 AIO249 I Analog Pin Used For Digital Input 249 35 AIO251 I Analog Pin Used For Digital Input 251 30 AIO252 I Analog Pin Used For Digital Input 252 32 AIO253 I Analog Pin Used For Digital Input 253 41 B0 I ADC-B Input 0 41 24 20 20 16 B1 I ADC-B Input 1 40 29 25 25 21 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-2. Analog Signals (continued) SIGNAL NAME PIN TYPE B2 I ADC-B Input 2 B3 I ADC-B Input 3 B4 I B5 I B6 B7 DESCRIPTION 80 PN 64 PMQ 64 PM 48 PT 15 11 7 7 4 16 12 8 8 5 ADC-B Input 4 39 28 24 24 20 ADC-B Input 5 32, 48 33 I ADC-B Input 6 17 13 9 9 6 I ADC-B Input 7 22 18 14 14 10 B8 I ADC-B Input 8 36 27 23 23 19 B9 I ADC-B Input 9 18 14 10 10 7 B10 I ADC-B Input 10 20 16 12 12 8 B11 I ADC-B Input 11 30, 49 34 B12 I ADC-B Input 12 21 17 13 13 9 B14 I ADC-B Input 14 19 15 11 11 B15 I ADC-B Input 15 23 19 15 15 11 C0 I ADC-C Input 0 20 16 12 12 8 C1 I ADC-C Input 1 29 22 18 18 14 C2 I ADC-C Input 2 21 17 13 13 9 C3 I ADC-C Input 3 31 23 19 19 15 C4 I ADC-C Input 4 19 15 11 11 C5 I ADC-C Input 5 28 12 8 8 5 C6 I ADC-C Input 6 15 11 7 7 4 C7 I ADC-C Input 7 18 14 10 10 7 C8 I ADC-C Input 8 39 28 24 24 20 C9 I ADC-C Input 9 17 13 9 9 6 C10 I ADC-C Input 10 40 29 25 25 21 C11 I ADC-C Input 11 41 24 20 20 16 C14 I ADC-C Input 14 42 27 23 23 19 C15 I ADC-C Input 15 23 19 15 15 11 CMP1_HN0 I CMPSS-1 High Comparator Negative Input 0 14 10 10 7 CMP1_HN1 I CMPSS-1 High Comparator Negative Input 1 20 16 12 12 8 CMP1_HP0 I CMPSS-1 High Comparator Positive Input 0 17 13 9 9 6 CMP1_HP1 I CMPSS-1 High Comparator Positive Input 1 20 16 12 12 8 CMP1_HP2 I CMPSS-1 High Comparator Positive Input 2 14 10 6 6 4 CMP1_HP3 I CMPSS-1 High Comparator Positive Input 3 14 10 10 7 CMP1_HP4 I CMPSS-1 High Comparator Positive Input 4 22 18 14 14 10 CMP1_HP5 I CMPSS-1 High Comparator Positive Input 5 32, 48 33 CMP1_LN0 I CMPSS-1 Low Comparator Negative Input 0 14 10 10 7 CMP1_LN1 I CMPSS-1 Low Comparator Negative Input 1 16 12 12 8 Copyright © 2022 Texas Instruments Incorporated 100 PZ 20 Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 37 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-2. Analog Signals (continued) 38 SIGNAL NAME PIN TYPE CMP1_LP0 I CMP1_LP1 DESCRIPTION 100 PZ 80 PN 64 PMQ 64 PM 48 PT CMPSS-1 Low Comparator Positive Input 0 17 13 9 9 6 I CMPSS-1 Low Comparator Positive Input 1 20 16 12 12 8 CMP1_LP2 I CMPSS-1 Low Comparator Positive Input 2 14 10 6 6 4 CMP1_LP3 I CMPSS-1 Low Comparator Positive Input 3 14 10 10 7 CMP1_LP4 I CMPSS-1 Low Comparator Positive Input 4 22 18 14 14 10 CMP1_LP5 I CMPSS-1 Low Comparator Positive Input 5 32, 48 33 CMP2_HN0 I CMPSS-2 High Comparator Negative Input 0 40 29 25 25 21 CMP2_HN1 I CMPSS-2 High Comparator Negative Input 1 28 22 18 18 14 CMP2_HP0 I CMPSS-2 High Comparator Positive Input 0 36 27 23 23 19 CMP2_HP1 I CMPSS-2 High Comparator Positive Input 1 28 22 18 18 14 CMP2_HP2 I CMPSS-2 High Comparator Positive Input 2 38 28 24 24 20 CMP2_HP3 I CMPSS-2 High Comparator Positive Input 3 40 29 25 25 21 CMP2_HP4 I CMPSS-2 High Comparator Positive Input 4 41 24 20 20 16 CMP2_HP5 I CMPSS-2 High Comparator Positive Input 5 35 17 13 13 9 CMP2_LN0 I CMPSS-2 Low Comparator Negative Input 0 40 29 25 25 21 CMP2_LN1 I CMPSS-2 Low Comparator Negative Input 1 28 22 18 18 14 CMP2_LP0 I CMPSS-2 Low Comparator Positive Input 0 36 27 23 23 19 CMP2_LP1 I CMPSS-2 Low Comparator Positive Input 1 28 22 18 18 14 CMP2_LP2 I CMPSS-2 Low Comparator Positive Input 2 38 28 24 24 20 CMP2_LP3 I CMPSS-2 Low Comparator Positive Input 3 40 29 25 25 21 CMP2_LP4 I CMPSS-2 Low Comparator Positive Input 4 41 24 20 20 16 CMP2_LP5 I CMPSS-2 Low Comparator Positive Input 5 35 17 13 13 9 CMP3_HN0 I CMPSS-3 High Comparator Negative Input 0 16 12 8 8 5 CMP3_HN1 I CMPSS-3 High Comparator Negative Input 1 21 17 13 13 9 CMP3_HP0 I CMPSS-3 High Comparator Positive Input 0 15 11 7 7 4 CMP3_HP1 I CMPSS-3 High Comparator Positive Input 1 21 17 13 13 9 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-2. Analog Signals (continued) SIGNAL NAME PIN TYPE CMP3_HP2 I CMP3_HP3 DESCRIPTION 100 PZ 80 PN 64 PMQ 64 PM 48 PT CMPSS-3 High Comparator Positive Input 2 23 19 15 15 11 I CMPSS-3 High Comparator Positive Input 3 16 12 8 8 5 CMP3_HP4 I CMPSS-3 High Comparator Positive Input 4 19 15 11 11 CMP3_HP5 I CMPSS-3 High Comparator Positive Input 5 18 12 8 8 5 CMP3_LN0 I CMPSS-3 Low Comparator Negative Input 0 16 12 8 8 5 CMP3_LN1 I CMPSS-3 Low Comparator Negative Input 1 21 17 13 13 9 CMP3_LP0 I CMPSS-3 Low Comparator Positive Input 0 15 11 7 7 4 CMP3_LP1 I CMPSS-3 Low Comparator Positive Input 1 21 17 13 13 9 CMP3_LP2 I CMPSS-3 Low Comparator Positive Input 2 23 19 15 15 11 CMP3_LP3 I CMPSS-3 Low Comparator Positive Input 3 16 12 8 8 5 CMP3_LP4 I CMPSS-3 Low Comparator Positive Input 4 19 15 11 11 CMP3_LP5 I CMPSS-3 Low Comparator Positive Input 5 18 12 8 8 5 CMP4_HN0 I CMPSS-4 High Comparator Negative Input 0 42 27 23 23 19 CMP4_HN1 I CMPSS-4 High Comparator Negative Input 1 31 23 19 19 15 CMP4_HP0 I CMPSS-4 High Comparator Positive Input 0 39 28 24 24 20 CMP4_HP1 I CMPSS-4 High Comparator Positive Input 1 31 23 19 19 15 CMP4_HP2 I CMPSS-4 High Comparator Positive Input 2 29 22 18 18 14 CMP4_HP3 I CMPSS-4 High Comparator Positive Input 3 42 27 23 23 19 CMP4_HP4 I CMPSS-4 High Comparator Positive Input 4 37 24 20 20 16 CMP4_HP5 I CMPSS-4 High Comparator Positive Input 5 30, 49 34 CMP4_LN0 I CMPSS-4 Low Comparator Negative Input 0 42 27 23 23 19 CMP4_LN1 I CMPSS-4 Low Comparator Negative Input 1 31 23 19 19 15 CMP4_LP0 I CMPSS-4 Low Comparator Positive Input 0 39 28 24 24 20 CMP4_LP1 I CMPSS-4 Low Comparator Positive Input 1 31 23 19 19 15 CMP4_LP2 I CMPSS-4 Low Comparator Positive Input 2 29 22 18 18 14 CMP4_LP3 I CMPSS-4 Low Comparator Positive Input 3 42 27 23 23 19 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 39 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-2. Analog Signals (continued) 40 SIGNAL NAME PIN TYPE CMP4_LP4 I CMP4_LP5 DESCRIPTION 100 PZ 80 PN 64 PMQ 64 PM 48 PT CMPSS-4 Low Comparator Positive Input 4 37 24 20 20 16 I CMPSS-4 Low Comparator Positive Input 5 30, 49 34 DACA_OUT O Buffered DAC-A Output. 23 19 15 15 11 DACB_OUT O Buffered DAC-B Output. 22 18 14 14 10 VDAC I Optional external reference voltage for on-chip DACs. 16 12 8 8 5 VREFHI I ADC High Reference. In external reference mode, externally drive the high reference voltage onto this pin. In internal reference mode, a voltage is driven onto this pin by the device. In either mode, place at least a 2.2µF capacitor on this pin. This capacitor should be placed as close to the device as possible between the VREFHI and VREFLO pins. 24, 25 20 16 16 12 VREFLO I ADC Low Reference 26, 27 21 17 17 13 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 5.3.2 Digital Signals Table 5-3. Digital Signals SIGNAL NAME PIN TYPE GPIO 100 PZ 80 PN 64 PMQ 64 PM 48 PT ADCSOCAO O ADC Start of Conversion A for External ADC 8, 33, 53 12, 53, 74 38, 58 32, 47 32, 47 25 ADCSOCBO O ADC Start of Conversion B for External ADC 10, 32, 54 13, 64, 93 49, 76 40, 63 40, 63 32 AUXCLKIN I Auxilary Clock Input 29 100 3 1 1 1 DESCRIPTION CANA_RX I CAN-A Receive 3, 5, 12, 18, 30, 8, 12, 51, 53, 63, 33, 35, 49, 53, 59, 68, 76, 89, 91, 92, 61 98 1, 36, 38, 48, 50, 60, 74 30, 32, 39, 41, 49, 61 30, 32, 39, 41, 49, 61 25, 31, 33, 39, 47 CANA_TX O CAN-A Transmit 2, 4, 13, 17, 19, 31, 32, 37, 48, 58 7, 50, 55, 61, 64, 67, 69, 75, 77, 99 2, 35, 40, 46, 49, 51, 59, 61 29, 34, 37, 40, 42, 48, 50 29, 34, 37, 40, 42, 48, 50 29, 32, 34, 38, 40 CLB_OUTPUTXBAR1 O CLB Output X-BAR Output 1 19, 22 69, 83 51, 67 42, 56 42, 56 34 CLB_OUTPUTXBAR2 O CLB Output X-BAR Output 2 7, 39, 47 6, 84 56, 68 57 46, 57 43 CLB_OUTPUTXBAR3 O CLB Output X-BAR Output 3 23, 42, 44 81, 85 57, 65, 69 54 54 CLB_OUTPUTXBAR4 O CLB Output X-BAR Output 4 10, 43, 45 93 54, 73, 76 63 63 CLB_OUTPUTXBAR5 O CLB Output X-BAR Output 5 5, 8, 52 11, 74, 89 58, 74 47, 61 47, 61 47 CLB_OUTPUTXBAR6 O CLB Output X-BAR Output 6 4, 15, 53 12, 75, 95 59, 78 48 48 38 CLB_OUTPUTXBAR7 O CLB Output X-BAR Output 7 1, 14, 56 65, 78, 96 62, 79 51 51 41 CLB_OUTPUTXBAR8 O CLB Output X-BAR Output 8 0, 6, 57 66, 79, 97 63, 80 52, 64 52, 64 42, 48 EPWM1_A O ePWM-1 Output A 0, 30 79, 98 1, 63 52 52 42 EPWM1_B O ePWM-1 Output B 1, 31 78, 99 2, 62 51 51 41 EPWM2_A O ePWM-2 Output A 2, 41 77, 82 61, 66 50, 55 50, 55 40 EPWM2_B O ePWM-2 Output B 3, 40 76, 80 60, 64 49, 53 49, 53 39 EPWM3_A O ePWM-3 Output A 4, 14 75, 96 59, 79 48 48 38 EPWM3_B O ePWM-3 Output B 5, 15 89, 95 74, 78 61 61 47 EPWM4_A O ePWM-4 Output A 6, 22 83, 97 67, 80 56, 64 56, 64 48 EPWM4_B O ePWM-4 Output B 7, 23 81, 84 65, 68 54, 57 54, 57 43 EPWM5_A O ePWM-5 Output A 8, 16 54, 74 39, 58 33, 47 33, 47 26 EPWM5_B O ePWM-5 Output B 9, 17, 35 55, 63, 90 40, 48, 75 34, 39, 62 34, 39, 62 31 EPWM6_A O ePWM-6 Output A 10, 18 68, 93 50, 76 41, 63 41, 63 33 EPWM6_B O ePWM-6 Output B 11, 19 52, 69 37, 51 31, 42 31, 42 34 EPWM7_A O ePWM-7 Output A 12, 28 1, 51 4, 36 2, 30 2, 30 2 EPWM7_B O ePWM-7 Output B 13, 29 50, 100 3, 35 1, 29 1, 29 1 EPWM8_A O ePWM-8 Output A 14, 24 56, 96 41, 79 35 35 27 EPWM8_B O ePWM-8 Output B 15, 32 64, 95 49, 78 40 40 32 1, 9, 48, 57, 63, 65, 80, 85, 93, 97 4, 33, 42, 48, 64, 69, 76, 80 2, 39, 53, 63, 64 2, 39, 53, 63, 64 2, 31, 48 EQEP1_A I eQEP-1 Input A 6, 10, 20, 25, 28, 35, 40, 44, 50, 56 EQEP1_B I eQEP-1 Input B 7, 11, 21, 29, 37, 41, 51, 57 10, 49, 52, 61, 66, 82, 84, 100 3, 34, 37, 46, 66, 68 1, 31, 37, 55, 57 1, 31, 37, 55, 57 1, 29, 43 EQEP1_INDEX I/O eQEP-1 Index 0, 9, 13, 17, 23, 31, 39, 43, 53, 59 12, 50, 55, 79, 81, 90, 92, 99 2, 35, 40, 54, 56, 63, 65, 75 29, 34, 52, 54, 62 29, 34, 46, 52, 54, 62 42 8, 12, 16, 22, 30, 42, 52, 58 11, 51, 54, 67, 74, 83, 98 1, 36, 39, 57, 58, 67 30, 33, 47, 56 30, 33, 47, 56 26 13, 52, 56, 68, 96 37, 41, 50, 79 31, 35, 41 31, 35, 41 27, 33 32, 33, 42 32, 33, 42 25, 26, 34 EQEP1_STROBE I/O eQEP-1 Strobe EQEP2_A I eQEP-2 Input A 11, 14, 18, 24, 54 eQEP-2 Input B 15, 16, 19, 25, 33, 43, 53, 54, 57, 69, 38, 39, 42, 51, 55 95 78 EQEP2_B I EQEP2_INDEX I/O eQEP-2 Index 26, 29, 39, 57 58, 66, 100 3, 43, 56 1 1, 46 1 EQEP2_STROBE I/O eQEP-2 Strobe 4, 27, 28, 56 1, 59, 65, 75 4, 44, 59 2, 48 2, 48 2, 38 ERRORSTS O Error Status Output. This signal requires an external pulldown. 24, 28, 29, 55 1, 43, 56, 100 3, 4, 41 1, 2, 35 1, 2, 35 1, 2, 27 FSIRXA_CLK I FSIRX-A Input Clock 0, 4, 13, 30, 33, 39, 54, 57 13, 50, 53, 66, 75, 79, 98 1, 35, 38, 56, 59, 63 29, 32, 48, 52 29, 32, 46, 48, 52 25, 38, 42 FSIRXA_D0 I FSIRX-A Primary Data Input 3, 12, 32, 40, 44, 52, 58 11, 51, 64, 67, 76, 80, 85 36, 49, 60, 64, 69 30, 40, 49, 53 30, 40, 49, 53 32, 39 12, 52, 65, 77, 82, 99 2, 37, 61, 66 31, 50, 55 31, 50, 55 40 FSIRXA_D1 I FSIRX-A Optional Additional Data Input 2, 11, 31, 41, 53, 56 FSITXA_CLK O FSITX-A Output Clock 7, 10, 27, 44, 51 10, 59, 84, 85, 93 44, 68, 69, 76 57, 63 57, 63 43 FSITXA_D0 O FSITX-A Primary Data Output 6, 9, 26, 45, 49 8, 58, 90, 97 43, 73, 75, 80 62, 64 62, 64 48 9, 57, 74, 89, 97 6, 42, 58, 74, 80 47, 61, 64 47, 61, 64 47, 48 FSITXA_D1 O FSITX-A Optional Additional Data Output Copyright © 2022 Texas Instruments Incorporated 5, 6, 8, 25, 46, 50 Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 41 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-3. Digital Signals (continued) 42 SIGNAL NAME PIN TYPE FSITXA_TDM_CLK I FSITXA_TDM_D0 I FSITXA_TDM_D1 I FSITX-A Time Division Multiplexed Additional Data Input GPIO0 I/O GPIO1 I/O GPIO2 DESCRIPTION GPIO 100 PZ 80 PN 64 PMQ 64 PM 48 PT FSITX-A Time Division Multiplexed Clock Input 8, 18, 47 6, 68, 74 50, 58 41, 47 41, 47 33 FSITX-A Time Division Multiplexed Data Input 10, 19 69, 93 51, 76 42, 63 42, 63 34 1, 54, 59 13, 78, 92 62 51 51 41 General-Purpose Input Output 0 0 79 63 52 52 42 General-Purpose Input Output 1 1 78 62 51 51 41 I/O General-Purpose Input Output 2 2 77 61 50 50 40 GPIO3 I/O General-Purpose Input Output 3 3 76 60 49 49 39 GPIO4 I/O General-Purpose Input Output 4 4 75 59 48 48 38 GPIO5 I/O General-Purpose Input Output 5 5 89 74 61 61 47 GPIO6 I/O General-Purpose Input Output 6 6 97 80 64 64 48 GPIO7 I/O General-Purpose Input Output 7 7 84 68 57 57 43 GPIO8 I/O General-Purpose Input Output 8 8 74 58 47 47 GPIO9 I/O General-Purpose Input Output 9 9 90 75 62 62 GPIO10 I/O General-Purpose Input Output 10 10 93 76 63 63 GPIO11 I/O General-Purpose Input Output 11 11 52 37 31 31 GPIO12 I/O General-Purpose Input Output 12 12 51 36 30 30 GPIO13 I/O General-Purpose Input Output 13 13 50 35 29 29 GPIO14 I/O General-Purpose Input Output 14 14 96 79 GPIO15 I/O General-Purpose Input Output 15 15 95 78 GPIO16 I/O General-Purpose Input Output 16 16 54 39 33 33 GPIO17 I/O General-Purpose Input Output 17 17 55 40 34 34 GPIO18 I/O General-Purpose Input Output 18 18 68 50 41 41 33 GPIO19 I/O General-Purpose Input Output 19 19 69 51 42 42 34 GPIO20 I/O General-Purpose Input Output 20 20 48 33 GPIO21 I/O General-Purpose Input Output 21 21 49 34 GPIO22 I/O General-Purpose Input Output 22 22 83 67 56 56 GPIO23 I/O General-Purpose Input Output 23 23 81 65 54 54 GPIO24 I/O General-Purpose Input Output 24 24 56 41 35 35 27 GPIO25 I/O General-Purpose Input Output 25 25 57 42 GPIO26 I/O General-Purpose Input Output 26 26 58 43 GPIO27 I/O General-Purpose Input Output 27 27 59 44 GPIO28 I/O General-Purpose Input Output 28 28 1 4 2 2 2 GPIO29 I/O General-Purpose Input Output 29 29 100 3 1 1 1 GPIO30 I/O General-Purpose Input Output 30 30 98 1 GPIO31 I/O General-Purpose Input Output 31 31 99 2 GPIO32 I/O General-Purpose Input Output 32 32 64 49 40 40 32 GPIO33 I/O General-Purpose Input Output 33 33 53 38 32 32 25 GPIO34 I/O General-Purpose Input Output 34 34 94 77 GPIO35 I/O General-Purpose Input Output 35 35 63 48 39 39 31 GPIO37 I/O General-Purpose Input Output 37 37 61 46 37 37 29 GPIO39 I/O General-Purpose Input Output 39 39 GPIO40 I/O General-Purpose Input Output 40 40 80 64 53 53 GPIO41 I/O General-Purpose Input Output 41 41 82 66 55 55 GPIO42 I/O General-Purpose Input Output 42 42 GPIO43 I/O General-Purpose Input Output 43 43 GPIO44 I/O General-Purpose Input Output 44 44 GPIO45 I/O General-Purpose Input Output 45 45 GPIO46 I/O General-Purpose Input Output 46 46 GPIO47 I/O General-Purpose Input Output 47 47 6 GPIO48 I/O General-Purpose Input Output 48 48 7 GPIO49 I/O General-Purpose Input Output 49 49 8 GPIO50 I/O General-Purpose Input Output 50 50 9 GPIO51 I/O General-Purpose Input Output 51 51 10 GPIO52 I/O General-Purpose Input Output 52 52 11 Submit Document Feedback 56 26 46 57 54 85 69 73 6 Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-3. Digital Signals (continued) SIGNAL NAME PIN TYPE GPIO53 I/O GPIO54 I/O GPIO55 DESCRIPTION GPIO 100 PZ 80 PN 64 PMQ 64 PM General-Purpose Input Output 53 53 12 General-Purpose Input Output 54 54 13 I/O General-Purpose Input Output 55 55 43 GPIO56 I/O General-Purpose Input Output 56 56 65 GPIO57 I/O General-Purpose Input Output 57 57 66 GPIO58 I/O General-Purpose Input Output 58 58 67 GPIO59 I/O General-Purpose Input Output 59 59 92 GPIO60 I/O General-Purpose Input Output 60 60 44 GPIO61 I/O General-Purpose Input Output 61 61 91 HIC_A0 I HIC Address 0 8, 55, 60 HIC_A1 I HIC Address 1 HIC_A2 I HIC_A3 I HIC_A4 48 PT 14, 43, 44, 74 10, 58 6, 47 6, 47 4 2, 26 15, 58, 77 11, 43, 61 7, 50 7, 50 4, 40 HIC Address 2 1 16, 78 12, 62 8, 51 8, 51 5, 41 HIC Address 3 23 17, 81 13, 65 9, 54 9, 54 6 I HIC Address 4 27, 41 59, 82 14, 44, 66 10, 55 10, 55 7 HIC_A5 I HIC Address 5 22 19, 83 15, 67 11, 56 11, 56 HIC_A6 I HIC Address 6 7, 42, 47 6, 20, 84 16, 57, 68 12, 57 12, 57 8, 43 HIC_A7 I HIC Address 7 5, 43, 48 7, 21, 89 17, 54, 74 13, 61 13, 61 9, 47 HIC_BASESEL0 I HIC Base address range select 0 9, 25 22, 57, 90 18, 42, 75 14, 62 14, 62 10 HIC_BASESEL1 I HIC Base address range select 1 0 23, 79 19, 63 15, 52 15, 52 11, 42 HIC_BASESEL2 I HIC Base address range select 2 4 40, 75 29, 59 25, 48 25, 48 21, 38 HIC_D0 I/O HIC Data 0 26, 33 53, 58 38, 43 32 32 25 HIC_D1 I/O HIC Data 1 16, 27 54, 59 39, 44 33 33 26 HIC_D2 I/O HIC Data 2 17, 42, 49 8, 55 40, 57 34 34 HIC_D3 I/O HIC Data 3 24, 43, 50 9, 56 41, 54 35 35 27 HIC_D4 I/O HIC Data 4 3, 5, 57 66, 76, 89 60, 74 49, 61 49, 61 39, 47 HIC_D5 I/O HIC Data 5 13, 40, 44 50, 80, 85 35, 64, 69 29, 53 29, 53 HIC_D6 I/O HIC Data 6 11, 45, 51, 56 10, 52, 65 37, 73 31 31 HIC_D7 I/O HIC Data 7 0, 39, 44 79, 85 56, 63, 69 52 46, 52 HIC_D8 I/O HIC Data 8 8, 30 74, 98 1, 58 47 47 42 HIC_D9 I/O HIC Data 9 2, 34 77, 94 61, 77 50 50 40 HIC_D10 I/O HIC Data 10 1, 31 78, 99 2, 62 51 51 41 HIC_D11 I/O HIC Data 11 13, 23 50, 81 35, 65 29, 54 29, 54 HIC_D12 I/O HIC Data 12 15, 41 82, 95 66, 78 55 55 HIC_D13 I/O HIC Data 13 12, 22 51, 83 36, 67 30, 56 30, 56 HIC_D14 I/O HIC Data 14 6, 7 84, 97 68, 80 57, 64 57, 64 HIC_D15 I/O HIC Data 15 5, 14 89, 96 74, 79 61 61 47 HIC_INT O HIC Device interrupt to host 12, 18, 32 51, 64, 68 36, 49, 50 30, 40, 41 30, 40, 41 32, 33 HIC_NBE0 I HIC Byte enable 0 11, 19 38, 52, 69 28, 37, 51 24, 31, 42 24, 31, 42 20, 34 HIC_NBE1 I HIC Byte enable 1 6, 34, 40 37, 80, 94, 97 24, 64, 77, 80 20, 53, 64 20, 53, 64 16, 48 HIC_NCS I HIC Chip select input 29 28, 100 3, 22 1, 18 1, 18 1, 14 2, 19, 49 2, 15, 39 43, 48 HIC_NOE O HIC Output enable for data bus 3, 28 1, 31, 76 4, 23, 60 2, 19, 49 HIC_NRDY O HIC Ready from device to host 9, 37, 58 61, 67, 90 46, 75 37, 62 37, 62 29 6, 27, 48, 59, 76 23, 39, 48, 63 23, 39, 48, 63 19, 31, 38 HIC_NWE I HIC Data Write enable from host 4, 10, 35, 46, 52 11, 36, 63, 75, 93 I2CA_SCL I/OD I2C-A Open-Drain Bidirectional Clock 1, 8, 18, 27, 33, 37, 43, 57 53, 59, 61, 66, 68, 38, 44, 46, 50, 74, 78 54, 58, 62 32, 37, 41, 47, 51 32, 37, 41, 47, 51 25, 29, 33, 41 I2CA_SDA I/OD I2C-A Open-Drain Bidirectional Data 0, 10, 19, 26, 32, 35, 42, 56 58, 63, 64, 65, 69, 43, 48, 49, 51, 79, 93 57, 63, 76 39, 40, 42, 52, 63 39, 40, 42, 52, 63 31, 32, 34, 42 I2CB_SCL I/OD I2C-B Open-Drain Bidirectional Clock 3, 9, 15, 29, 51 1, 49, 62 1, 49, 62 1, 39 I2CB_SDA I/OD I2C-B Open-Drain Bidirectional Data 3, 60, 75, 78 2, 14, 28, 34, 50 1, 9, 77, 94, 96 4, 61, 77, 79 2, 50 2, 50 2, 40 6, 8, 53, 63, 81, 92, 100 3, 38, 48, 57, 65 1, 32, 39, 54 1, 32, 39, 54 1, 25, 31 1, 61, 64, 67, 83 4, 6, 46, 49, 67 2, 37, 40, 56 2, 37, 40, 56 2, 29, 32 29, 31, 42, 54, 55, 62 29, 31, 42, 54, 55, 62 34 LINA_RX I LIN-A Receive 23, 29, 33, 35, 42, 47, 49, 59 LINA_TX O LIN-A Transmit 22, 28, 32, 37, 46, 58 LINB_RX I LIN-B Receive 9, 11, 13, 15, 19, 23, 41, 55 Copyright © 2022 Texas Instruments Incorporated 10, 76, 90, 95, 100 43, 50, 52, 69, 81, 35, 37, 51, 65, 82, 90, 95 66, 75, 78 Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 43 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-3. Digital Signals (continued) 44 SIGNAL NAME PIN TYPE LINB_TX O LIN-B Transmit MCAN_RX I DESCRIPTION GPIO 100 PZ 80 PN 64 PMQ 64 PM 48 PT 10, 12, 14, 18, 22, 13, 51, 56, 68, 80, 36, 41, 50, 64, 24, 40, 44, 54 83, 85, 93, 96 67, 69, 76, 79 30, 35, 41, 53, 56, 63 30, 35, 41, 53, 56, 63 27, 33 CAN/CAN FD Receive 0, 5, 12, 21, 30, 39, 47, 51, 57, 61 6, 10, 49, 51, 66, 79, 89, 91, 98 1, 34, 36, 56, 63, 74 30, 52, 61 30, 46, 52, 61 42, 47 1, 4, 13, 20, 31, 46, 50, 56, 60 9, 44, 48, 50, 65, 75, 78, 99 2, 6, 33, 35, 59, 62 29, 48, 51 29, 48, 51 38, 41 MCAN_TX O CAN/CAN FD Transmit OUTPUTXBAR1 O Output X-BAR Output 1 2, 24, 34, 58 56, 67, 77, 94 41, 61, 77 35, 50 35, 50 27, 40 OUTPUTXBAR2 O Output X-BAR Output 2 3, 25, 37, 54, 59 13, 57, 61, 76, 92 42, 46, 60 37, 49 37, 49 29, 39 7, 43, 44, 58, 75, 89, 96 43, 59, 74, 79 48, 61 48, 61 38, 47 OUTPUTXBAR3 O Output X-BAR Output 3 4, 5, 14, 26, 48, 55, 60 OUTPUTXBAR4 O Output X-BAR Output 4 6, 15, 27, 33, 49, 61 8, 53, 59, 91, 95, 97 38, 44, 78, 80 32, 64 32, 64 25, 48 OUTPUTXBAR5 O Output X-BAR Output 5 7, 28, 42 1, 84 4, 57, 68 2, 57 2, 57 2, 43 OUTPUTXBAR6 O Output X-BAR Output 6 9, 29, 43 90, 100 3, 54, 75 1, 62 1, 62 1 OUTPUTXBAR7 O Output X-BAR Output 7 11, 16, 30, 44 52, 54, 85, 98 1, 37, 39, 69 31, 33 31, 33 26 OUTPUTXBAR8 O Output X-BAR Output 8 17, 31, 45 55, 99 2, 40, 73 34 34 PMBus-A Open-Drain Bidirectional Alert Signal 13, 19, 27, 37, 43, 45 50, 59, 61, 69 35, 44, 46, 51, 54, 73 29, 37, 42 29, 37, 42 29, 34 PMBus-A Control Signal - Slave Input/Master Output 12, 18, 26, 35, 42, 44 51, 58, 63, 68, 85 36, 43, 48, 50, 57, 69 30, 39, 41 30, 39, 41 31, 33 PMBUSA_ALERT I/OD PMBUSA_CTL I/O PMBUSA_SCL I/OD PMBus-A Open-Drain Bidirectional Clock 3, 15, 16, 24, 35, 41, 47 6, 54, 56, 63, 76, 82, 95 39, 41, 48, 60, 66, 78 33, 35, 39, 49, 55 33, 35, 39, 49, 55 26, 27, 31, 39 PMBUSA_SDA I/OD PMBus-A Open-Drain Bidirectional Data 2, 14, 17, 25, 32, 34, 40, 44, 46, 48 7, 55, 57, 64, 77, 80, 85, 94, 96 6, 40, 42, 49, 61, 64, 69, 77, 79 34, 40, 50, 53 34, 40, 50, 53 32, 40 SCIA_RX I SCI-A Receive Data 3, 9, 17, 25, 28, 35, 49 1, 8, 55, 57, 63, 76, 90 4, 40, 42, 48, 60, 75 2, 34, 39, 49, 62 2, 34, 39, 49, 62 2, 31, 39 SCIA_TX O SCI-A Transmit Data 2, 8, 16, 24, 29, 37, 48 7, 54, 56, 61, 74, 77, 100 3, 39, 41, 46, 58, 61 1, 33, 35, 37, 47, 50 1, 33, 35, 37, 47, 50 1, 26, 27, 29, 40 SCIB_RX I SCI-B Receive Data 11, 13, 15, 19, 23, 50, 52, 66, 69, 81, 35, 37, 51, 65, 41, 57 82, 95 66, 78 29, 31, 42, 54, 55 29, 31, 42, 54, 55 34 SCIB_TX O SCI-B Transmit Data 9, 10, 12, 14, 18, 22, 40, 56 30, 41, 53, 56, 62, 63 30, 41, 53, 56, 62, 63 33 SD1_C1 I SDFM-1 Channel 1 Clock Input 15, 32, 34 15, 32, 34 11, 25 19, 32, 42 15, 25, 34 17, 33, 49, 53 51, 65, 68, 80, 83, 36, 50, 64, 67, 90, 93, 96 75, 76, 79 8, 12, 23, 53, 55 19, 38, 40 SD1_C2 I SDFM-1 Channel 2 Clock Input 19, 33, 51, 54 10, 13, 31, 53, 69 23, 38, 51 19, 32, 42 SD1_C3 I SDFM-1 Channel 3 Clock Input 21, 53, 55 12, 38, 43, 49 28, 34 24 24 20 SD1_C4 I SDFM-1 Channel 4 Clock Input 23, 55, 56 40, 43, 65, 81 29, 65 25, 54 25, 54 21 SD1_D1 I SDFM-1 Channel 1 Data Input 16, 48 7, 19, 54 15, 39 11, 33 11, 33 26 12, 40, 41 8, 32, 33 SD1_D2 I SDFM-1 Channel 2 Data Input 18, 32, 50 9, 20, 64, 68 16, 49, 50 12, 40, 41 SD1_D3 I SDFM-1 Channel 3 Data Input SD1_D4 I SDFM-1 Channel 4 Data Input 20, 52 11, 21, 48 17, 33 13 13 9 22, 54 13, 22, 83 18, 67 14, 56 14, 56 10 SD2_C1 I SDFM-2 Channel 1 Clock Input 25, 35, 57 14, 37, 57, 63, 66 10, 24, 42, 48 6, 20, 39 6, 20, 39 4, 16, 31 SD2_C2 I SDFM-2 Channel 2 Clock Input 27, 58, 59 36, 59, 67, 92 27, 44 23 23 19 SD2_C3 I SDFM-2 Channel 3 Clock Input 29, 45, 59, 61 28, 91, 92, 100 3, 22, 73 1, 18 1, 18 1, 14 SD2_C4 I SDFM-2 Channel 4 Clock Input 31, 46, 60 32, 44, 99 2, 6 SD2_D1 I SDFM-2 Channel 1 Data Input 24, 49, 56 8, 56, 65 14, 41 10, 35 10, 35 7, 27 SD2_D2 I SDFM-2 Channel 2 Data Input 26, 50, 58 9, 16, 58, 67 12, 43 8 8 5 SD2_D3 I SDFM-2 Channel 3 Data Input 28, 43, 51, 60 1, 10, 17, 44 4, 13, 54 2, 9 2, 9 2, 6 SDFM-2 Channel 4 Data Input SD2_D4 I 30, 47, 52 6, 11, 15, 98 1, 11 7 7 4 SPIA_CLK I/O SPI-A Clock 3, 9, 12, 18, 56 51, 65, 68, 76, 90 36, 50, 60, 75 30, 41, 49, 62 30, 41, 49, 62 33, 39 SPIA_SIMO I/O SPI-A Slave In, Master Out (SIMO) 2, 8, 11, 16, 54 13, 52, 54, 74, 77 37, 39, 58, 61 31, 33, 47, 50 31, 33, 47, 50 26, 40 SPIA_SOMI I/O SPI-A Slave Out, Master In (SOMI) 1, 10, 13, 17, 55 43, 50, 55, 78, 93 35, 40, 62, 76 29, 34, 51, 63 29, 34, 51, 63 41 SPIA_STE I/O SPI-A Slave Transmit Enable (STE) 0, 5, 11, 19, 57 52, 66, 69, 79, 89 37, 51, 63, 74 31, 42, 52, 61 31, 42, 52, 61 34, 42, 47 SPIB_CLK I/O SPI-B Clock 4, 14, 22, 26, 28, 32, 52, 58 1, 11, 58, 64, 67, 75, 83, 96 4, 43, 49, 59, 67, 79 2, 40, 48, 56 2, 40, 48, 56 2, 32, 38 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-3. Digital Signals (continued) SIGNAL NAME PIN TYPE SPIB_SIMO I/O SPIB_SOMI I/O DESCRIPTION GPIO 100 PZ 80 PN 64 PMQ 64 PM 48 PT SPI-B Slave In, Master Out (SIMO) 7, 20, 24, 30, 40, 50, 56, 60 9, 44, 48, 56, 65, 80, 84, 98 1, 33, 41, 64, 68 35, 53, 57 35, 53, 57 27, 43 SPI-B Slave Out, Master In (SOMI) 6, 16, 21, 25, 31, 41, 51, 57, 61 10, 49, 54, 57, 66, 82, 91, 97, 99 2, 34, 39, 42, 66, 80 33, 55, 64 33, 55, 64 26, 48 15, 23, 27, 29, 33, 12, 53, 59, 81, 92, 53, 59 95, 100 3, 38, 44, 65, 78 1, 32, 54 1, 32, 54 1, 25 SPIB_STE I/O SPI-B Slave Transmit Enable (STE) SYNCOUT O External ePWM Synchronization Pulse 6, 39, 52 11, 97 56, 80 64 46, 64 48 I JTAG Test Data Input (TDI) - TDI is the default mux selection for the pin. The internal pullup is disabled by default. The internal pullup should be enabled or an external pullup added on the board if this pin is used as JTAG TDI to avoid a floating input. 35 63 48 39 39 31 O JTAG Test Data Output (TDO) - TDO is the default mux selection for the pin. The internal pullup is disabled by default. The TDO function will tristate when there is no JTAG activity, leaving this pin floating; the internal pullup should be enabled or an external pullup added on the board to avoid a floating GPIO input. 37 61 46 37 37 29 X1 I/O Crystal oscillator input or single-ended clock input. The device initialization software must configure this pin before the crystal oscillator is enabled. To use this oscillator, a quartz crystal circuit must be connected to X1 and X2. This pin can also be used to feed a single-ended 3.3-V level clock. See the XTAL section for usage details. 19 69 51 42 42 34 X2 I/O Crystal oscillator output. 18 68 50 41 41 33 O External Clock Output. This pin outputs a divideddown version of a chosen clock signal from within the device. 16, 18 54, 68 39, 50 33, 41 33, 41 26, 33 TDI TDO XCLKOUT Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 45 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 5.3.3 Power and Ground Table 5-4. Power and Ground SIGNAL NAME PIN TYPE DESCRIPTION 100 PZ 80 PN 64 PMQ 64 PM 48 PT VDD 1.2-V Digital Logic Power Pins. See the Power Management Module (PMM) section for usage details. 4, 46, 71, 87 8, 31, 53, 71 4, 27, 44, 59 4, 27, 44, 59 23, 36, 45 VDDA 3.3-V Analog Power Pins. Place a minimum 2.2-µF decoupling capacitor on each pin. See the Power Management Module (PMM) section for usage details. 34 26 22 22 18 VDDIO 3.3-V Digital I/O Power Pins. See the Power Management Module (PMM) section for usage details. 3, 47, 70, 88 7, 32, 52, 72 28, 43, 60 28, 43, 60 24, 35, 46 VREGENZ Internal voltage regulator disable with internal pulldown. Tie low to VSS to enable internal VREG. Tie high to VDDIO to use an external supply. See the Power Management Module (PMM) section for usage details. 73 46 I 46 VSS Digital Ground 5, 45, 72, 86 9, 30, 55, 70 5, 26, 45, 58 5, 26, 45, 58 22, 37, 44 VSSA Analog Ground 33 25 21 21 17 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 5.3.4 Test, JTAG, and Reset Table 5-5. Test, JTAG, and Reset SIGNAL NAME PIN TYPE TCK I TMS XRSn DESCRIPTION 100 PZ 80 PN 64 PMQ 64 PM 48 PT JTAG test clock with internal pullup. 60 45 36 36 28 I/O JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. This device does not have a TRSTn pin. An external pullup resistor (recommended 2.2 kΩ) on the TMS pin to VDDIO should be placed on the board to keep JTAG in reset during normal operation. 62 47 38 38 30 I/OD Device Reset (in) and Watchdog Reset (out). During a power-on condition, this pin is driven low by the device. An external circuit may also drive this pin to assert a device reset. This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRSn pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. A resistor between 2.2 kΩ and 10 kΩ should be placed between XRSn and VDDIO. If a capacitor is placed between XRSn and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRSn pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. This pin is an open-drain output with an internal pullup. If this pin is driven by an external device, it should be done using an opendrain device. 2 5 3 3 3 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 47 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 5.4 Pin Multiplexing 5.4.1 GPIO Muxed Pins Table 5-6 lists the GPIO muxed pins. The default mode for each GPIO pin is the GPIO function, except GPIO35 and GPIO37, which default to TDI and TDO, respectively. Secondary functions can be selected by setting both the GPyGMUXn.GPIOz and GPyMUXn.GPIOz register bits. The GPyGMUXn register should be configured before the GPyMUXn to avoid transient pulses on GPIOs from alternate mux selections. Columns that are not shown and blank cells are reserved GPIO Mux settings. GPIO ALT functions cannot be configured with the GPyMUXn and GPyGMUXn registers. These are special functions that need to be configured from the module. Note GPIO36 and GPIO38 do not exist on this device. GPIO62 to GPIO63 exist but are not pinned out on any packages. Boot ROM enables pullups on GPIO62 to GPIO63. For more details, see Section 5.5. 48 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 5.4.1.1 GPIO Muxed Pins Table 5-6. GPIO Muxed Pins 0, 4, 8, 12 1 2 3 5 6 7 9 11 13 14 15 MCAN_RX CLB_OUTPUTXBA R8 EQEP1_INDE X HIC_D7 HIC_BASESEL1 MCAN_TX CLB_OUTPUTXBA R7 HIC_A2 FSITXA_TDM_D1 HIC_D10 HIC_D9 GPIO0 EPWM1_A I2CA_SDA SPIA_STE GPIO1 EPWM1_B I2CA_SCL SPIA_SOMI GPIO2 EPWM2_A OUTPUTXBAR1 PMBUSA_SDA SPIA_SIMO SCIA_TX FSIRXA_D1 I2CB_SDA HIC_A1 CANA_TX GPIO3 EPWM2_B OUTPUTXBAR2 PMBUSA_SCL SPIA_CLK SCIA_RX FSIRXA_D0 I2CB_SCL HIC_NOE CANA_RX GPIO4 EPWM3_A MCAN_TX OUTPUTXBAR3 CANA_TX SPIB_CLK EQEP2_STRO BE FSIRXA_CLK GPIO5 EPWM3_B OUTPUTXBA R3 MCAN_RX CANA_RX SPIA_STE FSITXA_D1 CLB_OUTPUTXBA R5 GPIO6 EPWM4_A SYNCOUT EQEP1_A SPIB_SOMI FSITXA_D0 GPIO7 EPWM4_B OUTPUTXBA R5 EQEP1_B SPIB_SIMO FSITXA_CLK CLB_OUTPUTXBA R2 GPIO8 EPWM5_A ADCSOCAO EQEP1_STROBE SCIA_TX SPIA_SIMO I2CA_SCL FSITXA_D1 CLB_OUTPUTXBA R5 HIC_A0 FSITXA_TDM_CL K HIC_D8 GPIO9 EPWM5_B OUTPUTXBA R6 EQEP1_INDEX SCIA_RX SPIA_CLK FSITXA_D0 LINB_RX HIC_BASESEL 0 I2CB_SCL HIC_NRDY GPIO10 EPWM6_A ADCSOCBO EQEP1_A SCIB_TX SPIA_SOMI I2CA_SDA FSITXA_CLK LINB_TX HIC_NWE FSITXA_TDM_D0 CLB_OUTPUTXBA R4 GPIO11 EPWM6_B OUTPUTXBA R7 EQEP1_B SCIB_RX SPIA_STE FSIRXA_D1 LINB_RX EQEP2_A SPIA_SIMO HIC_D6 HIC_NBE0 GPIO12 EPWM7_A MCAN_RX EQEP1_STROBE SCIB_TX PMBUSA_CTL FSIRXA_D0 LINB_TX SPIA_CLK CANA_RX HIC_D13 HIC_INT GPIO13 EPWM7_B MCAN_TX EQEP1_INDEX SCIB_RX PMBUSA_ALERT FSIRXA_CLK LINB_RX SPIA_SOMI CANA_TX HIC_D11 HIC_D5 I2CB_SDA OUTPUTXBAR 3 EPWM3_A CLB_OUTPUTXBA R7 HIC_D15 I2CB_SCL OUTPUTXBAR 4 PMBUSA_SCL SPIB_STE EQEP2_B LINB_RX EPWM3_B CLB_OUTPUTXBA R6 HIC_D12 EQEP2_B SPIB_SOMI HIC_D1 GPIO14 EPWM8_A OUTPUTXBAR2 OUTPUTXBAR4 SCIB_TX SCIB_TX SCIB_RX PMBUSA_SDA FSIRXA_CLK 10 SPIB_CLK CLB_OUTPUTXBA HIC_BASESEL R6 2 FSITXA_D1 EQEP2_A HIC_D4 HIC_NWE HIC_A7 HIC_D4 HIC_D15 HIC_NBE1 CLB_OUTPUTXBA R8 HIC_D14 HIC_A6 LINB_TX ALT HIC_D14 GPIO15 EPWM8_B GPIO16 SPIA_SIMO OUTPUTXBA R7 EPWM5_A SCIA_TX SD1_D1 EQEP1_STRO BE PMBUSA_SCL XCLKOUT GPIO17 SPIA_SOMI OUTPUTXBA R8 EPWM5_B SCIA_RX SD1_C1 EQEP1_INDE X PMBUSA_SDA CANA_TX GPIO18 SPIA_CLK SCIB_TX CANA_RX EPWM6_A I2CA_SCL SD1_D2 EQEP2_A PMBUSA_CTL XCLKOUT LINB_TX FSITXA_TDM_CL K HIC_INT X2 GPIO19 SPIA_STE SCIB_RX CANA_TX EPWM6_B I2CA_SDA SD1_C2 EQEP2_B PMBUSA_ALERT CLB_OUTPUTXBA R1 LINB_RX FSITXA_TDM_D0 HIC_NBE0 X1 GPIO20 EQEP1_A SPIB_SIMO SD1_D3 MCAN_TX GPIO21 EQEP1_B SPIB_SOMI SD1_C3 MCAN_RX GPIO22 EQEP1_STRO BE SPIB_CLK SD1_D4 LINA_TX CLB_OUTPUTXBA R1 LINB_TX HIC_A5 EPWM4_A HIC_D13 GPIO23 EQEP1_INDE X LINB_RX HIC_A3 EPWM4_B HIC_D11 GPIO24 OUTPUTXBAR 1 SCIA_TX ERRORSTS SCIB_TX SCIB_RX EQEP2_A Copyright © 2022 Texas Instruments Incorporated EPWM8_A SPIB_STE SD1_C4 LINA_RX CLB_OUTPUTXBA R3 SPIB_SIMO SD2_D1 LINB_TX PMBUSA_SCL HIC_D2 HIC_D3 Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 49 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-6. GPIO Muxed Pins (continued) 0, 4, 8, 12 1 2 GPIO25 OUTPUTXBAR 2 GPIO26 OUTPUTXBAR 3 OUTPUTXBAR GPIO27 4 3 5 6 7 9 10 11 13 14 15 EQEP2_B EQEP1_A SPIB_SOMI SD2_C1 FSITXA_D1 PMBUSA_SDA SCIA_RX HIC_BASESEL0 EQEP2_INDEX OUTPUTXBAR3 SPIB_CLK SD2_D2 FSITXA_D0 PMBUSA_CTL I2CA_SDA HIC_D0 HIC_A1 EQEP2_STROBE OUTPUTXBAR4 SPIB_STE SD2_C2 FSITXA_CLK PMBUSA_ALERT I2CA_SCL HIC_D1 HIC_A4 GPIO28 SCIA_RX EPWM7_A OUTPUTXBAR5 EQEP1_A SD2_D3 EQEP2_STRO BE LINA_TX SPIB_CLK ERRORSTS I2CB_SDA HIC_NOE GPIO29 SCIA_TX EPWM7_B OUTPUTXBAR6 EQEP1_B SD2_C3 EQEP2_INDE X LINA_RX SPIB_STE ERRORSTS I2CB_SCL HIC_NCS GPIO30 CANA_RX SPIB_SIMO OUTPUTXBAR7 EQEP1_STRO BE SD2_D4 FSIRXA_CLK MCAN_RX EPWM1_A HIC_D8 GPIO31 CANA_TX SPIB_SOMI OUTPUTXBAR8 EQEP1_INDE X SD2_C4 FSIRXA_D1 MCAN_TX EPWM1_B HIC_D10 GPIO32 I2CA_SDA SPIB_CLK EPWM8_B LINA_TX SD1_D2 FSIRXA_D0 CANA_TX PMBUSA_SDA ADCSOCBO GPIO33 I2CA_SCL SPIB_STE OUTPUTXBAR4 LINA_RX SD1_C2 FSIRXA_CLK CANA_RX EQEP2_B ADCSOCAO SD1_C1 HIC_D0 HIC_NBE1 I2CB_SDA HIC_D9 I2CA_SDA CANA_RX PMBUSA_SCL LINA_RX EQEP1_A PMBUSA_CTL EPWM5_B SD2_C1 HIC_NWE TDI I2CA_SCL SCIA_TX CANA_TX LINA_TX EQEP1_B PMBUSA_ALERT HIC_NRDY TDO MCAN_RX FSIRXA_CLK EQEP2_INDE X SYNCOUT EQEP1_INDEX HIC_D7 EPWM2_B PMBUSA_SDA FSIRXA_D0 SCIB_TX EQEP1_A LINB_TX HIC_NBE1 HIC_D5 EPWM2_A PMBUSA_SCL FSIRXA_D1 SCIB_RX EQEP1_B LINB_RX HIC_A4 SPIB_SOMI HIC_D12 OUTPUTXBA R5 PMBUSA_CTL I2CA_SDA EQEP1_STROBE CLB_OUTPUTXBA R3 HIC_D2 HIC_A6 GPIO43 OUTPUTXBA R6 PMBUSA_ALERT I2CA_SCL PMBUSA_ALE RT EQEP1_INDEX CLB_OUTPUTXBA R4 SD2_D3 HIC_D3 HIC_A7 GPIO44 OUTPUTXBA R7 EQEP1_A PMBUSA_SDA PMBUSA_CTL CLB_OUTPUTXBA R3 FSIRXA_D0 HIC_D7 LINB_TX HIC_D5 GPIO45 OUTPUTXBA R8 GPIO46 LINA_TX OUTPUTXBAR GPIO34 1 GPIO35 PMBUSA_SDA SCIA_RX OUTPUTXBAR GPIO37 2 GPIO39 GPIO40 SPIB_SIMO GPIO41 GPIO42 LINA_RX GPIO47 LINA_RX MCAN_TX FSITXA_CLK CLB_OUTPUTXBA R2 FSITXA_D0 PMBUSA_ALE CLB_OUTPUTXBA RT R4 SD2_C3 FSITXA_D1 PMBUSA_SDA SD2_C4 CLB_OUTPUTXBA PMBUSA_SCL R2 MCAN_RX SD2_D4 OUTPUTXBAR 3 CANA_TX SCIA_TX SD1_D1 PMBUSA_SDA OUTPUTXBAR GPIO49 4 CANA_RX SCIA_RX SD1_C1 LINA_RX SD2_D1 GPIO48 HIC_D6 HIC_NWE FSITXA_TDM_CL K HIC_A6 HIC_A7 FSITXA_D0 HIC_D2 EQEP1_A MCAN_TX SPIB_SIMO SD1_D2 I2CB_SDA SD2_D2 FSITXA_D1 HIC_D3 GPIO51 EQEP1_B MCAN_RX SPIB_SOMI SD1_C2 I2CB_SCL SD2_D3 FSITXA_CLK HIC_D6 EQEP1_STRO GPIO52 BE CLB_OUTPUTXBA R5 SPIB_CLK SD1_D3 SYNCOUT SD2_D4 FSIRXA_D0 HIC_NWE EQEP1_INDE X CLB_OUTPUTXBA R6 SPIB_STE SD1_C3 ADCSOCAO SD1_C1 FSIRXA_D1 50 Submit Document Feedback AUXCLKI N HIC_INT GPIO50 GPIO53 ALT CANA_RX Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-6. GPIO Muxed Pins (continued) 0, 4, 8, 12 1 GPIO54 GPIO55 2 5 6 7 9 10 SPIA_SIMO EQEP2_A OUTPUTXBAR 2 SD1_D4 ADCSOCBO SPIA_SOMI EQEP2_B OUTPUTXBAR 3 SD1_C4 GPIO56 SPIA_CLK CLB_OUTPUTXBA R7 GPIO57 SPIA_STE CLB_OUTPUTXBA R8 3 11 13 14 15 LINB_TX SD1_C2 FSIRXA_CLK FSITXA_TDM_D1 ERRORSTS LINB_RX SD1_C3 MCAN_TX EQEP2_STROBE SCIB_TX SD2_D1 SPIB_SIMO I2CA_SDA EQEP1_A MCAN_RX EQEP2_INDEX SCIB_RX SD2_C1 SPIB_SOMI I2CA_SCL EQEP1_B GPIO58 OUTPUTXBAR1 SPIB_CLK SD2_D2 LINA_TX CANA_TX EQEP1_STROBE GPIO59 OUTPUTXBAR2 SPIB_STE SD2_C2 LINA_RX CANA_RX EQEP1_INDEX GPIO60 MCAN_TX OUTPUTXBAR3 SPIB_SIMO SD2_D3 GPIO61 MCAN_RX OUTPUTXBAR4 SPIB_SOMI SD2_C3 SD1_C4 ALT HIC_A0 FSIRXA_D1 HIC_D6 FSIRXA_CLK HIC_D4 SD2_C2 FSIRXA_D0 HIC_NRDY SD2_C3 FSITXA_TDM_D1 SD2_C4 HIC_A0 CANA_RX AIO224 SD2_D3 HIC_A3 AIO225 SD2_C2 HIC_NWE AIO226 SD2_D4 HIC_A1 AIO227 SD1_C3 HIC_NBE0 AIO228 SD2_C1 HIC_A0 AIO230 SD1_C4 HIC_BASESEL2 AIO231 SD1_C1 HIC_BASESEL1 AIO232 SD1_D4 HIC_BASESEL0 AIO233 SD2_D1 HIC_A4 AIO229 AIO236 AIO237 SD1_D2 HIC_A6 AIO238 SD2_C3 HIC_NCS AIO239 SD1_D1 HIC_A5 AIO240 SD2_C1 HIC_NBE1 AIO241 SD2_C1 HIC_NBE1 AIO242 SD2_D2 HIC_A2 AIO244 SD1_D3 HIC_A7 AIO245 SD1_C2 HIC_NOE AIO247 AIO248 AIO249 AIO251 AIO252 SD2_C4 AIO253 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 51 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 5.4.2 Digital Inputs on ADC Pins (AIOs) GPIOs on port H (GPIO224–GPIO253) are multiplexed with analog pins. These are also referred to as AIOs. These pins can only function in input mode. By default, these pins will function as analog pins and the GPIOs are in a high-Z state. The GPHAMSEL register is used to configure these pins for digital or analog operation. Note If digital signals with sharp edges (high dv/dt) are connected to the AIOs, cross-talk can occur with adjacent analog signals. The user should therefore limit the edge rate of signals connected to AIOs if adjacent channels are being used for analog functions. 5.4.3 Digital Inputs and Outputs on ADC Pins (AGPIOs) Some GPIOs on this device are multiplexed with analog pins. These are also referred to as AGPIOs. Unlike AIOs, AGPIOs have full input and output capability. This device has two GPIOs (GPIO20, GPIO21) that offer this feature on the 100-Pin PZ and 80-Pin PN packages. 100-Pin PZ: On this package, there are dedicated pins for B5 (pin 32) and B11 (pin 30) which respectively also have AIO252 and AIO251 functionality. In addition, GPIO20 (pin 48) and GPIO21 (pin 49) are also available as B5 and B11 respectively. Since B5 and B11 are dedicated pins on this package, it is recommended to use them instead of the ones on GPIO20/21. 80-Pin PN: On this package, GPIO20 (pin 33) and GPIO21 (pin 34) are also available as B5 and B11 respectively. There are no dedicated pin for B5 and B11. By default the AGPIOs are not connected and have to be configured. Table 5-7 truth table shows how to configure the AGPIOs using B5 (pin 32) and GPIO20 (pin 48) on the 100-Pin PZ as an example. Table 5-7. AGPIO Configuration AGPIOCTRLA.bit.GPIO20 GPAAMSEL.bit.GPIO20 GPHAMSEL.bit.GPIO252 0 0 0 B5 CONNECTED TO GPIO20 CONNECTED TO ADC GPIO20 AIO252 ADC GPIO20 AIO252 1 Yes - - - Yes - 1 1 Yes - - - - - 1 0 1 Yes - - - Yes - 1 1 1 - - - Yes - - 0 0 0 Yes - Yes - Yes - 0 1 0 Yes - Yes - - - 1 0 0 Yes - Yes - Yes - 1 1 0 - - Yes Yes - - Note If digital signals with sharp edges (high dv/dt) are connected to the AGPIOs, cross-talk can occur with adjacent analog signals. The user should therefore limit the edge rate of signals connected to AGPIOs if adjacent channels are being used for analog functions. 5.4.4 GPIO Input X-BAR The Input X-BAR is used to route signals from a GPIO to many different IP blocks such as the ADCs, eCAPs, ePWMs, and external interrupts (see Figure 5-6). Table 5-8 lists the input X-BAR destinations. 52 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 GPIO0 Asynchronous Synchronous Sync. + Qual. GPIOx Input X-BAR Other Sources eCAP Modules 15:0 INPUT16 INPUT15 INPUT14 INPUT13 INPUT12 INPUT11 INPUT10 INPUT9 INPUT8 INPUT7 INPUT6 INPUT5 INPUT4 INPUT3 INPUT2 INPUT1 INPUT[16:1] 127:16 DCCx Clock Source-1 TZ1,TRIP1 TZ2,TRIP2 TZ3,TRIP3 TRIP6 DCCx Clock Source-0 XINT1 XINT2 XINT3 XINT4 XINT5 CPU PIE CLA TRIP4 TRIP5 ePWM Modules TRIP7 TRIP8 TRIP9 TRIP10 TRIP11 TRIP12 ePWM X-BAR Other Sources ADCEXTSOC ADC EXTSYNCIN1 ePWM and eCAP Sync Scheme EXTSYNCIN2 Other Sources INPUT[1:16] ERAD INPUT[13:16] EPG Output X-BAR Figure 5-6. Input X-BAR Table 5-8. Input X-BAR Destinations INPUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ECAP / HRCAP Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes EPWM X-BAR Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes CLB X-BAR Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes OUTPUT X-BAR Yes Yes Yes Yes Yes Yes XINT1 XINT2 XINT3 CPU XINT TZ1, TZ2, TZ3, TRIP1 TRIP2 TRIP3 EPWM TRIP XINT4 XINT5 TRIP6 ADC START OF CONVERSION ADCEX TSOC EPWM / ECAP SYNC EXTSY NCIN1 EXTSY NCIN2 CLK CLK 0 0 DCCx EPG1 EPG1 EPG1 EPG1 IN1 IN2 IN3 IN4 EPG ERAD CLK1 CLK0 Yes Yes Yes Copyright © 2022 Texas Instruments Incorporated Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 53 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 5.4.5 GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR The Output X-BAR has eight outputs that can be selected on the GPIO mux as OUTPUTXBARx. The CLB X-BAR has eight outputs that are connected to the CLB global mux as AUXSIGx. The CLB Output X-BAR has eight outputs that can be selected on the GPIO mux as CLB_OUTPUTXBARx. The ePWM X-BAR has eight outputs that are connected to the TRIPx inputs of the ePWM. The sources for the Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR are shown in Figure 5-7. 54 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 CMPSSx ePWM and eCAP Sync Chain CTRIPOUTH CTRIPOUTL (Output X-BAR only) CTRIPH CTRIPL (ePWM X-BAR only) EXTSYNCOUT ADCSOCA0 Select Circuit ADCSOCA0 ADCSOCB0 Select Circuit ADCSOCB0 eCAPx ECAPxOUT ADCx EVT1 EVT2 EVT3 EVT4 Input X-BAR CLAHALT CLB X-BAR CLB Global Mux TRIP4 TRIP5 EPWM X-BAR INPUT1-6 INPUT7-14 (ePWM X-BAR only) TRIP7 TRIP8 TRIP9 TRIP10 TRIP11 TRIP12 All ePWM Modules eQEPx CLAHALT FLT1.COMPH FLT1.COMPL SDFMx AUXSIG1 AUXSIG2 AUXSIG3 AUXSIG4 AUXSIG5 AUXSIG6 AUXSIG7 AUXSIG8 Output X-BAR FLT4.COMPH FLT4.COMPL OUTPUTXBAR1 OUTPUTXBAR2 OUTPUTXBAR3 OUTPUTXBAR4 OUTPUTXBAR5 OUTPUTXBAR6 OUTPUTXBAR7 OUTPUTXBAR8 GPIO Mux X-BAR Flags (shared) CLB Input X-BAR CLB TILEx CLB Output X-BAR CLB_OUTPUTXBAR1 CLB_OUTPUTXBAR2 CLB_OUTPUTXBAR3 CLB_OUTPUTXBAR4 CLB_OUTPUTXBAR5 CLB_OUTPUTXBAR6 CLB_OUTPUTXBAR7 CLB_OUTPUTXBAR8 Figure 5-7. Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR Sources Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 55 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 5.5 Pins With Internal Pullup and Pulldown Some pins on the device have internal pullups or pulldowns. Table 5-9 lists the pull direction and when it is active. The pullups on GPIO pins are disabled by default and can be enabled through software. To avoid any floating unbonded inputs, the Boot ROM will enable internal pullups on GPIO pins that are not bonded out in a particular package. Other pins noted in Table 5-9 with pullups and pulldowns are always on and cannot be disabled. Table 5-9. Pins With Internal Pullup and Pulldown PIN GPIOx RESET (XRSn = 0) DEVICE BOOT APPLICATION Pullup disabled Pullup disabled(1) Application defined GPIO35/TDI Pullup disabled GPIO37/TDO Application defined Pullup disabled AGPIOx Pullup disabled Application defined Pullup disabled TCK Pullup active TMS Pullup active XRSn Pullup active Other pins (including AIOs) (1) 56 Application defined No pullup or pulldown present Pins not bonded out in a given package will have the internal pullups enabled by the Boot ROM. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 5.6 Connections for Unused Pins For applications that do not need to use all functions of the device, Table 5-10 lists acceptable conditioning for any unused pins. When multiple options are listed in Table 5-10, any option is acceptable. Pins not listed in Table 5-10 must be connected according to Section 5. Table 5-10. Connections for Unused Pins SIGNAL NAME ACCEPTABLE PRACTICE ANALOG VREFHI Tie to VDDA (applies only if ADC is not used in the application) VREFLO Tie to VSSA Analog input pins with DACx_OUT • • No Connect Tie to VSSA through 4.7-kΩ or larger resistor Analog input pins (except DACx_OUT) • • • No Connect Tie to VSSA Tie to VSSA through resistor Analog input pins (shared with GPIOs)(1) • • • No connection (digital input mode with internal pullup enabled) No connection (digital output mode with internal pullup disabled) Pullup or pulldown resistor (any value resistor, digital input mode, and with internal pullup disabled) DIGITAL GPIOx • • • No connection (input mode with internal pullup enabled) No connection (output mode with internal pullup disabled) Pullup or pulldown resistor (any value resistor, input mode, and with internal pullup disabled) When TDI mux option is selected (default), the GPIO is in Input mode. GPIO35/TDI • • Internal pullup enabled External pullup resistor When TDO mux option is selected (default), the GPIO is in Output mode only during JTAG activity; otherwise, it is in a tri-state condition. The pin must be biased to avoid extra current on the input buffer. GPIO37/TDO • • Internal pullup enabled External pullup resistor TCK • • No Connect Pullup resistor TMS Pullup resistor Turn XTAL off and: GPIO19/X1 • • • Input mode with internal pullup enabled Input mode with external pullup or pulldown resistor Output mode with internal pullup disabled Turn XTAL off and: GPIO18/X2 • • • Input mode with internal pullup enabled Input mode with external pullup or pulldown resistor Output mode with internal pullup disabled POWER AND GROUND VDD All VDD pins must be connected per Section 5.3. Pins should not be used to bias any external circuits. VDDA If a dedicated analog supply is not used, tie to VDDIO. VDDIO All VDDIO pins must be connected per Section 5.3. VSS All VSS pins must be connected to board ground. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 57 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 5-10. Connections for Unused Pins (continued) SIGNAL NAME VSSA (1) 58 ACCEPTABLE PRACTICE If an analog ground is not used, tie to VSS. AGPIO pins share analog and digital functionality. The actions here only apply if these pins are also not being used for analog functions. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) (2) MIN MAX VDDIO with respect to VSS –0.3 4.6 VDDA with respect to VSSA –0.3 4.6 VDD with respect to VSS –0.3 1.5 Input voltage VIN (3.3 V) –0.3 4.6 V Output voltage VO –0.3 4.6 V Digital/analog input (per pin), IIK (VIN < VSS/VSSA or VIN > VDDIO/ VDDA)(4) –20 20 Total for all inputs, IIKTOTAL (VIN < VSS/VSSA or VIN > VDDIO/VDDA) –20 20 Output current Digital output (per pin), IOUT –20 20 mA Free-Air temperature TA –40 125 °C Operating junction temperature TJ –40 150 °C Storage temperature(3) Tstg –65 150 °C Supply voltage Input clamp current (1) (2) (3) (4) UNIT V mA Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. All voltage values are with respect to VSS, unless otherwise noted. Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device life. For additional information, see the Semiconductor and IC Package Thermal Metrics Application Report. Continuous clamp current per pin is ±2 mA. Do not operate in this condition continuously as VDDIO/VDDA voltage may internally rise and impact other electrical specifications. 6.2 ESD Ratings – Commercial VALUE UNIT F280039C, F280039, F280037C, F280037, F280034, F280033 in 100-pin PZ package V(ESD) Electrostatic discharge (ESD) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±500 V F280039C, F280039, F280037C, F280037, F280034, F280033 in 80-pin PN package V(ESD) Electrostatic discharge (ESD) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±500 V F280039C, F280039, F280037C, F280037, F280034, F280033 in 64-pin PM package V(ESD) Electrostatic discharge (ESD) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±500 V F280037C, F280037, F280034, F280033 in 48-pin PT package V(ESD) (1) (2) Electrostatic discharge (ESD) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 59 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 6.3 ESD Ratings – Automotive VALUE UNIT F280039C-Q1, F280039-Q1, F280037C-Q1, F280037-Q1 in 100-pin PZ package V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) All pins ±2000 Charged device model (CDM), per AEC Q100-011 All pins ±500 Corner pins on 100-pin PZ: 1, 25, 26, 50, 51, 75, 76, 100 ±750 Human body model (HBM), per AEC Q100-002(1) All pins ±2000 Charged device model (CDM), per AEC Q100-011 All pins ±500 Corner pins on 64-pin PM: 1, 16, 17, 32, 33, 48, 49, 64 ±750 Human body model (HBM), per AEC Q100-002(1) All pins ±2000 Charged device model (CDM), per AEC Q100-011 All pins ±500 Corner pins on 48-pin PT: 1, 12, 13, 24, 25, 36, 37, 48 ±750 V F280038C-Q1, F280038-Q1, F280036C-Q1, F280036-Q1 in 64-pin PM package V(ESD) Electrostatic discharge V F280037C-Q1, F280037-Q1, F280034-Q1 in 48-pin PT package V(ESD) (1) Electrostatic discharge V AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.4 Recommended Operating Conditions Device supply voltage, VDDIO and VDDA Internal BOR enabled(3) Internal BOR disabled Device supply voltage, VDD MIN NOM MAX VBOR-VDDIO(MAX) + VBOR-VDDIO-GB (2) 3.3 3.63 2.8 3.3 3.63 1.14 1.2 1.32 Device ground, VSS Analog ground, VSSA UNIT V V 0 V 0 V Supply ramp rate(4) SRSUPPLY Digital input voltage VSS – 0.3 VDDIO + 0.3 VSSA – 0.3 VDDA + 0.3 V Junction temperature, TJ (1) –40 150 °C Free-Air temperature, TA –40 125 °C VIN (1) (2) (3) (4) 60 Analog input voltage V Operation above TJ = 105°C for extended duration will reduce the lifetime of the device. See Calculating Useful Lifetimes of Embedded Processors for more information. See the Power Management Module (PMM) section. Internal BOR is enabled by default. See the Power Management Module Operating Conditions table. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 6.5 Power Consumption Summary Current values listed in this section are representative for the test conditions given and not the absolute maximum possible. The actual device currents in an application will vary with application code and pin configurations. Section 6.5.1 lists the system current consumption values. Section 6.5.2 lists the system current consumption with VREG disabled. 6.5.1 System Current Consumption over operating free-air temperature range (unless otherwise noted). TYP : Vnom, 30℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 80 108 mA 8 17.5 mA 30 58 mA 0.01 0.1 mA 16.5 41 mA 0.01 0.1 mA OPERATING MODE IDDIO VDDIO current consumption during operational usage IDDA VDDA current consumption during operational usage This is an estimation of current for a typical heavily loaded application. Actual currents will vary depending on system activity, I/O electrical loading and switching frequency. This includes Core supply current with Internal Vreg Enabled. - CPU is running from RAM - Flash is powered up - X1/X2 crystal is powered up - PLL is enabled, SYSCLK=Max Device frequency - Analog modules are powered up - Outputs are static without DC Load - Inputs are static high or low IDLE MODE IDDIO VDDIO current consumption while device is in Idle mode IDDA VDDA current consumption while device is in Idle mode - CPU is in IDLE mode - Flash is powered down - PLL is Enabled, SYSCLK=Max Device Frequency, CPUCLK is gated - X1/X2 crystal is powered up - Analog Modules are powered down - Outputs are static without DC Load - Inputs are static high or low STANDBY MODE IDDIO VDDIO current consumption while device is in Standby mode IDDA VDDA current consumption while device is in Standby mode Copyright © 2022 Texas Instruments Incorporated - CPU is in STANDBY mode - Flash is powered down - PLL is Enabled, SYSCLK & CPUCLK are gated - X1/X2 crystal is powered down - Analog Modules are powered down - Outputs are static without DC Load - Inputs are static high or low Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 61 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 6.5.1 System Current Consumption (continued) over operating free-air temperature range (unless otherwise noted). TYP : Vnom, 30℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 12.5 36 mA 0.01 0.1 mA 72 106 mA 0.1 2.5 mA HALT MODE IDDIO VDDIO current consumption while device is in Halt mode IDDA VDDA current consumption while device is in Halt mode - CPU is in HALT mode - Flash is powered down - PLL is Disabled, SYSCLK & CPUCLK are gated - X1/X2 crystal is powered down - Analog Modules are powered down - Outputs are static without DC Load - Inputs are static high or low FLASH ERASE/PROGRAM IDDIO VDDIO current consumption during Erase/Program cycle(1) IDDA VDDA current consumption during Erase/Program cycle - CPU is running from RAM - Flash going through continuous Program/Erase operation - PLL is enabled, SYSCLK at 120 MHz. - Peripheral clocks are turned OFF. - X1/X2 crystal is powered up - Analog is powered down - Outputs are static without DC Load - Inputs are static high or low RESET MODE IDDIO VDDIO current consumption while reset is active(2) 5.8 mA IDDA VDDA current consumption while reset is active(2) 0.1 mA (1) (2) 62 Brownout events during flash programming can corrupt flash data and permanently lock the device. Programming environments using alternate power sources (such as a USB programmer) must be capable of supplying the rated current for the device and other system components with sufficient margin to avoid supply brownout conditions. This is the current consumption while reset is active, that is XRSn is low. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 6.5.2 System Current Consumption - VREG Disable - External Supply over operating free-air temperature range (unless otherwise noted). TYP : Vnom, 30℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 73 103.5 mA 4 4.7 mA 8 17.5 mA 25 48 mA 1.7 2.2 mA 0.01 0.1 mA 11.6 35 mA 1.7 2.3 mA 0.01 0.1 mA 8.5 31 mA 0.8 1.2 mA 0.01 0.1 mA OPERATING MODE IDD VDD current consumption during operational usage IDDIO VDDIO current consumption during operational usage IDDA VDDA current consumption during operational usage This is an estimation of current for a typical heavily loaded application. Actual currents will vary depending on system activity, I/O electrical loading and switching frequency. - CPU is running from RAM - Flash is powered up - X1/X2 crystal is powered up - PLL is enabled, SYSCLK=Max Device frequency - Analog modules are powered up - Outputs are static without DC Load - Inputs are static high or low IDLE MODE VDD current consumption while device - CPU is in IDLE mode is in Idle mode - Flash is powered down - PLL is Enabled, SYSCLK=Max VDDIO current consumption while Device Frequency, CPUCLK is device is in Idle mode gated - X1/X2 crystal is powered up - Analog Modules are powered VDDA current consumption while down device is in Idle mode - Outputs are static without DC Load - Inputs are static high or low IDD IDDIO IDDA STANDBY MODE IDD IDDIO IDDA VDD current consumption while device - CPU is in STANDBY mode is in Standby mode - Flash is powered down - PLL is Enabled, SYSCLK & VDDIO current consumption while CPUCLK are gated device is in Standby mode - X1/X2 crystal is powered down - Analog Modules are powered down VDDA current consumption while - Outputs are static without DC device is in Standby mode Load - Inputs are static high or low HALT MODE IDD IDDIO IDDA VDD current consumption while device - CPU is in HALT mode is in Halt mode - Flash is powered down - PLL is Disabled, SYSCLK & VDDIO current consumption while CPUCLK are gated device is in Halt mode - X1/X2 crystal is powered down - Analog Modules are powered down VDDA current consumption while - Outputs are static without DC device is in Halt mode Load - Inputs are static high or low Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 63 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 6.5.2 System Current Consumption - VREG Disable - External Supply (continued) over operating free-air temperature range (unless otherwise noted). TYP : Vnom, 30℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 41 60.5 mA 31 45.5 mA 0.1 2.5 mA FLASH ERASE/PROGRAM IDD VDD Current consumption during Erase/Program cycle(1) IDDIO VDDIO Current consumption during Erase/Program cycle(1) IDDA VDDA Current consumption during Erase/Program cycle - CPU is running from RAM - Flash going through continuous Program/Erase operation - PLL is enabled, SYSCLK at 120 MHz. - Peripheral clocks are turned OFF. - X1/X2 crystal is powered up - Analog is powered down - Outputs are static without DC Load - Inputs are static high or low RESET MODE IDD VDD current consumption while reset is active(2) 3.3 mA IDDIO VDDIO current consumption while reset is active(2) 2.2 mA IDDA VDDA current consumption while reset is active(2) 0.1 mA (1) (2) 64 Brownout events during flash programming can corrupt flash data and permanently lock the device. Programming environments using alternate power sources (such as a USB programmer) must be capable of supplying the rated current for the device and other system components with sufficient margin to avoid supply brownout conditions. This is the current consumption while reset is active, that is XRSn is low. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 6.5.3 Operating Mode Test Description Section 6.5.1 and Section 6.5.4.1 list the current consumption values for the operational mode of the device. The operational mode provides an estimation of what an application might encounter. The test condition for these measurements has the following properties: • Code is executing from RAM. • FLASH is read and kept in active state. • No external components are driven by I/O pins. • All peripherals have clocks enabled. • The CPU is actively executing code. • All analog peripherals are powered up. ADCs and DACs are periodically converting. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 65 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 6.5.4 Reducing Current Consumption The F28003x devices provide some methods to reduce the device current consumption: • One of the two low-power modes—IDLE or STANDBY—could be entered during idle periods in the application. • The flash module may be powered down if the code is run from RAM. • Disable the pullups on pins that assume an output function. • Each peripheral has an individual clock-enable bit (PCLKCRx). Reduced current consumption may be achieved by turning off the clock to any peripheral that is not used in a given application. Section 6.5.4.1 lists the typical current reduction that may be achieved by disabling the clocks using the PCLKCRx register. • To realize the lowest VDDA current consumption in an LPM, see the Analog-to-Digital Converter (ADC) chapter of the TMS320F28003x Real-Time Microcontrollers Technical Reference Manual to ensure each module is powered down as well. 6.5.4.1 Typical Current Reduction per Disabled Peripheral PERIPHERAL IDD CURRENT REDUCTION (mA) ADC(1) 0.73 CLA 0.56 CLA BGCRC 0.42 CLB 1.41 CMPSS(1) 0.33 CPU BGCRC 0.25 CPU TIMER 0.04 GPDAC 0.12 DCAN 1.28 DCC 0.12 DMA 0.57 eCAP1 and eCAP2 0.08 eCAP3(2) 0.29 ePWM1 to ePWM4(3) 0.95 ePWM5 to ePWM8 0.78 ERAD 1.56 eQEP 0.1 FSI RX 0.34 FSI TX 0.27 HIC 0.17 I2C 0.26 LIN 0.35 MCAN (CAN FD) 1.01 PMBUS 0.28 SCI 0.16 SDFM 1.83 SPI 0.08 (1) (2) (3) 66 This current represents the current drawn by the digital portion of the each module. eCAP3 can also be configured as HRCAP. ePWM1 to ePWM4 can also be configured as HRPWM. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 6.6 Electrical Characteristics over recommended operating conditions (unless otherwise noted) TEST CONDITIONS PARAMETER MIN TYP MAX UNIT Digital and Analog IO IOH = IOH MIN VDDIO * 0.8 IOH = –100 μA VDDIO – 0.2 VOH High-level output voltage VOL Low-level output voltage IOH High-level output source current for all output pins IOL Low-level output sink current for all output pins ROH High-level output impedance for all output pins ROL Low-level output impedance for all output pins VIH High-level input voltage VIL Low-level input voltage VHYSTERESIS Input hysteresis IPULLDOWN Input current Pins with pulldown VDDIO = 3.3 V VIN = VDDIO 120 µA IPULLUP Input current Digital inputs with pullup VDDIO = 3.3 V enabled(1) VIN = 0 V 160 µA Pin leakage Input capacitance 0.4 IOL = 100 µA 0.2 –4 4 Ω 70 Ω V Digital inputs V mV Pullups and outputs disabled 0 V ≤ VIN ≤ VDDIO Analog drivers disabled 0 V ≤ VIN ≤ VDDA mA 70 0.8 Analog pins (except ADCINB3/VDAC) V mA 125 ADCINB3/VDAC CI IOL = IOL MAX 2.0 Digital inputs ILEAK V 0.1 µA 0.1 0.2 2 Analog pins(2) 4.4 pF VREG, POR and BOR VREG, POR, BOR(3) (1) (2) (3) See Pins With Internal Pullup and Pulldown table for a list of pins with a pullup or pulldown. The analog pins are specified separately; see the Per-Channel Parasitic Capacitance tables that are in the ADC Input Model section. See the Power Management Module (PMM) section. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 67 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 6.7 Thermal Resistance Characteristics for PZ Package °C/W(1) AIR FLOW (lfm)(2) RΘJC Junction-to-case thermal resistance 7.6 N/A RΘJB Junction-to-board thermal resistance 24.2 N/A RΘJA (High k PCB) Junction-to-free air thermal resistance 46.1 0 37.3 150 34.8 250 32.6 500 RΘJMA PsiJT PsiJB (1) (2) 68 Junction-to-moving air thermal resistance Junction-to-package top Junction-to-board 0.2 0 0.4 150 0.4 250 0.6 500 23.8 0 22.8 150 22.4 250 21.9 500 These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards: • JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air) • JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements lfm = linear feet per minute Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 6.8 Thermal Resistance Characteristics for PN Package °C/W(1) AIR FLOW (lfm)(2) RΘJC Junction-to-case thermal resistance 14.2 N/A RΘJB Junction-to-board thermal resistance 21.9 N/A RΘJA (High k PCB) PsiJT PsiJB (1) (2) Junction-to-free air thermal resistance Junction-to-package top Junction-to-board 49.9 0 38.3 150 36.7 250 34.4 500 0.8 0 1.18 150 1.34 250 1.62 500 21.6 0 20.7 150 20.5 250 20.1 500 These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards: • JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air) • JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements lfm = linear feet per minute Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 69 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 6.9 Thermal Resistance Characteristics for PM Package °C/W(1) AIR FLOW (lfm)(2) RΘJC Junction-to-case thermal resistance 12.4 N/A RΘJB Junction-to-board thermal resistance 25.6 N/A RΘJA (High k PCB) Junction-to-free air thermal resistance 51.8 0 42.2 150 39.4 250 36.5 500 RΘJMA PsiJT PsiJB (1) (2) 70 Junction-to-moving air thermal resistance Junction-to-package top Junction-to-board 0.5 0 0.9 150 1.1 250 1.4 500 25.1 0 23.8 150 23.4 250 22.7 500 These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards: • JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air) • JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements lfm = linear feet per minute Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 6.10 Thermal Resistance Characteristics for PT Package °C/W(1) AIR FLOW (lfm)(2) RΘJC Junction-to-case thermal resistance 16.2 N/A RΘJB Junction-to-board thermal resistance 22.3 N/A RΘJA (High k PCB) PsiJT PsiJB (1) (2) Junction-to-free air thermal resistance Junction-to-package top Junction-to-board 56.7 0 50.4 150 48.2 250 45 500 0.7 0 0.94 150 1.1 250 1.38 500 22 0 28.7 150 28.4 250 28 500 These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards: • JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air) • JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements lfm = linear feet per minute 6.11 Thermal Design Considerations Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems that exceed the recommended maximum power dissipation in the end product may require additional thermal enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the operating junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. The thermal application report Semiconductor and IC Package Thermal Metrics helps to understand the thermal metrics and definitions. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 71 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 6.12 System 6.12.1 Power Management Module (PMM) 6.12.1.1 Introduction The Power Management Module (PMM) handles all the power management functions required for device operation. 6.12.1.2 Overview The block diagram of the PMM is shown in Figure 6-1. As can be seen, the PMM comprises of various subcomponents, which are described in the subsequent sections. MCU To Rest of Chip PMM I/O POR CPU Reset Release RISE DELAY (45us) RISE DELAY (80us) I/O BOR Internal All Monitors Release Signal RISE DELAY (145us) RISE DELAY (40us) EN VMONCTL.bit.BORLVMONDIS CVDDIO XRSn VREGENZ Internal VSS 1.2v LDO VREG VDD VSS External VDDIO Internal VDD POR OUT IN EN External CVDD Figure 6-1. PMM Block Diagram 6.12.1.2.1 Power Rail Monitors The PMM has voltage monitors on the supply rails that release the XRSn signal high once the voltages cross the set threshold during power up. They also function to trip the XRSn signal low if any of the voltages drop below the programmed levels. The various voltage monitors are described in subsequent sections. Note Not all the voltage monitors are supported for device operation in an application after boot up. In the case where a voltage monitor is not supported, an external supervisor is recommended if the device needs supply voltage monitoring while the application is running. The three voltage monitors (I/O POR, I/O BOR, VDD POR) all have to release their respective outputs before the device begins operation (that is, XRSn goes high). However, if any of the voltage monitors trips, XRSn is driven low. The I/Os are held in high impedance when any of the voltage monitors trip. 72 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 6.12.1.2.1.1 I/O POR (Power-On Reset) Monitor The I/O POR monitor supervises the VDDIO rail. During power up, this is the first monitor to release (that is, first to untrip) on VDDIO. 6.12.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor The I/O BOR monitor also supervises the VDDIO rail. During power up, this is the second monitor to release (that is, second to untrip) on VDDIO. This monitor has a tighter tolerance compared to the I/O POR. Any drop in voltage below the recommended operating voltages will trip the I/O BOR and reset the device but this can be disabled by setting VMONCTL.bit.BORLVMONDIS to 1. The I/O BOR can only be disabled after the device has fully booted up. If the I/O BOR is disabled, the I/O POR will reset the device for voltage drops. Note The level at which the I/O POR trips is well below the minimum recommended voltage for VDDIO, and therefore should not be used for device supervision. Figure 6-2 shows the operating region of the I/O BOR. 3.63 V +10% 0% 3.3 V Recommended System Voltage Regulator Range VDDIO Operating Range 3.1 V –6.1% 3.0 V –9.1% VBOR-GB BOR Guard Band VBOR-VDDIO Internal BOR Threshold 2.81 V 2.80 V –14.8% –15.1% Figure 6-2. I/O BOR Operating Region 6.12.1.2.1.3 VDD POR (Power-On Reset) Monitor The VDD POR monitor supervises the VDD rail. During power up, this monitor releases (that is, untrips) once the voltage crosses the programmed trip level on VDD. Note VDD POR is programmed at a level below the minimum recommended voltage for VDD, and therefore it should not be relied upon for VDD supervision if that is required in the application. 6.12.1.2.2 External Supervisor Usage VDDIO Monitoring: The I/O BOR is supported for application use, so an external supervisor is not required to monitor the I/O rail. VDD Monitoring: The VDD POR is not supported for application use. If VDD monitoring is required by the application, an external supervisor should be used to monitor the VDD rail. Note The use of an external supervisor with the internal VREG is not supported. If VDD monitoring is required by the application, a package with a VREGENZ pin must be used to power VDD externally. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 73 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 6.12.1.2.3 Delay Blocks The delay blocks in the path of the voltage monitors work together to delay the release time between the voltage monitors and XRSn. These delays ensure that the voltages are stable when XRSn releases in external VREG mode. The delay blocks are only active during power up (that is, when VDDIO and VDD are ramping up). The delay blocks contribute to the minimum slew rates specified in Power Management Module Electrical Data and Timing for the power rails. Note The delay numbers specified in the block diagram are typical numbers. 6.12.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG) The internal VREG is supplied by the VDDIO rail and can generate the 1.2 V required to power the VDD pins. It is enabled by tying the VREGENZ pin low. Although the internal VREG eliminates the need to use an external supply for VDD, decoupling capacitors are still required on the VDD pins for VREG stability and transients. See VDD Decoupling for details. 6.12.1.2.5 VREGENZ The VREGENZ (VREG disable) pin controls the state of the internal VREG. To enable the internal VREG, the VREGENZ pin should be tied low. For applications supplying VDD externally (external VREG), the internal VREG should be disabled by tying the VREGENZ pin high. Note Not all device packages have VREGENZ pinned out. For packages without VREGENZ, external VREG mode is not supported. 6.12.1.3 External Components 6.12.1.3.1 Decoupling Capacitors VDDIO and VDD require decoupling capacitors for correct operation. The requirements are outlined in subsequent sections. 6.12.1.3.1.1 VDDIO Decoupling A minimum amount of decoupling capacitance should be placed on VDDIO. See the CVDDIO parameter in Power Management Module Electrical Data and Timing. The actual amount of decoupling capacitance to use is a requirement of the power supply driving VDDIO. Either of the configurations outlined below is acceptable: • Configuration 1: Place a decoupling capacitor on each VDDIO pin per the CVDDIO parameter. • Configuration 2: Install a single decoupling capacitor that is the equivalent of CVDDIO * VDDIO pins. Note It is critical to have the decoupling capacitor or capacitors close to the device pins. 6.12.1.3.1.2 VDD Decoupling A minimum amount of decoupling capacitance should be placed on VDD. See the CVDD TOTAL parameter in Power Management Module Electrical Data and Timing. In external VREG mode, the actual amount of decoupling capacitance to use is a requirement of the power supply driving VDD. Either of the configurations outlined below is acceptable: • Configuration 1: Divide CVDD TOTAL across the VDD pins. • Configuration 2: Install a single decoupling capacitor with value of CVDD TOTAL. 74 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Note It is critical to have the decoupling capacitor or capacitors close to the device pins. 6.12.1.4 Power Sequencing 6.12.1.4.1 Supply Pins Ganging It is strongly recommended that all 3.3-V rails be tied together and supplied from a single source. This list includes: • VDDIO • VDDA In addition, no power pin should be left unconnected. In external VREG mode, the VDD pins should be tied together and supplied from a single source. In internal VREG mode, tying the VDD pins together is optional as long as each VDD pin has a capacitor on it. See VDD Decoupling for VDD decoupling configurations. The analog modules on the device have fairly high PSRR; therefore, in most cases, noise on VDDA will have to exceed the recommended operating conditions of the supply rails before the analog modules see performance degradation. Therefore, supplying VDDA separately typically offers minimal benefits. Nevertheless, for the purposes of noise improvement, placing a pi filter between VDDIO and VDDA is acceptable. Note All the supply pins per rail are tied together internally. For example, all VDDIO pins are tied together internally, all VDD pins are tied together internally, and so forth. 6.12.1.4.2 Signal Pins Power Sequence Before powering the device, no voltage larger than 0.3 V above VDDIO or 0.3 V below VSS should be applied to any digital pin; and no voltage larger than 0.3 V above VDDA or 0.3 V below VSSA should be applied to any analog pin (including VREFHI and VDAC). Simply, the signal pins should only be driven after XRSn goes high, provided all the 3.3-V rails are tied together. This sequencing is still required even if VDDIO and VDDA are not tied together. CAUTION If the above sequence is violated, device malfunction and possibly damage can occur as current will flow through unintended parasitic paths in the device. 6.12.1.4.3 Supply Pins Power Sequence 6.12.1.4.3.1 External VREG/VDD Mode Sequence Figure 6-3 depicts the power sequencing requirements for external VREG mode. The values for all the parameters indicated can be found in Power Management Module Electrical Data and Timing. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 75 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 VDDIO VBOR-VDDIO-UP (A) SRVDDIO-UP VPOR-VDDIO SRVDD-UP VDD Internal All Monitors Release Signal(C) XRSn VDDIO VBOR-VDDIO-DN(B) VDD Internal All Monitors Release Signal(D) SRVDD-DN XRSn SRVDDIO-DN VPOR-VDD-DN(B) VPOR-VDD-UP(A) VPOR-VDDIO VDDIO - VDD Delay VDDIO-MON-TOT-DELAY A. B. C. D. VXRSn-PU-DELAY VXRSn-PD-DELAY This trip point is the trip point before XRSn releases. See the Power Management Module Characteristics table. This trip point is the trip point after XRSn releases. See the Power Management Module Characteristics table. During power up, the All Monitors Release Signal goes high after all POR and BOR monitors are released. See the PMM Block Diagram. During power down, the All Monitors Release Signal goes low if any of the POR or BOR monitors are tripped. See the PMM Block Diagram. Figure 6-3. External VREG Power Up Sequence • • For Power Up: 1. VDDIO (that is, the 3.3-V rail) should come up first with the minimum slew rate specified. 2. VDD (that is, the 1.2-V rail) should come up next with the minimum slew rate specified. 3. The time delta between the VDDIO rail coming up and when the VDD rail can come up is also specified. 4. After the times specified by VDDIO-MON-TOT-DELAY and VXRSN-PD-DELAY, XRSn will be released and the device starts the boot-up sequence. There is an additional delay between XRSn releasing (that is, going high) and the boot-up sequence starting. See Figure 6-1. 5. The I/O BOR monitor has different release points during power up and power down. 6. During power up, both VDDIO and VDD rails have to be up before XRSn releases. For Power Down: 1. There is no requirement between VDDIO and VDD on which should power down first; however, there is a minimum slew rate specification. 2. The I/O BOR monitor has different release points during power up and power down. 3. Any of the POR or BOR monitors that trips during power down will cause XRSn to go low after VXRSN-PD-DELAY. Note The All Monitors Release Signal is an internal signal. Note If there is an external circuit driving XRSn (for example, a supervisor), the boot-up sequence does not start until the XRSn pin is released by all internal and external sources. 6.12.1.4.3.2 Internal VREG/VDD Mode Sequence Figure 6-4 depicts the power sequencing requirements for internal VREG mode. The values for all the parameters indicated can be found in Power Management Module Electrical Data and Timing. 76 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 VDDIO VBOR-VDDIO-UP VDDIO (A) VBOR-VDDIO-DN(B) SRVDDIO-UP Internal All Monitors Release Signal(C) XRSn Internal All Monitors Release Signal(D) VPOR-VDDIO VPOR-VDDIO VDDIO-MON-TOT-DELAY A. B. C. D. XRSn SRVDDIO-DN VXRSn-PU-DELAY VXRSn-PD-DELAY This trip point is the trip point before XRSn releases. See the Power Management Module Characteristics table. This trip point is the trip point after XRSn releases. See the Power Management Module Characteristics table. During power up, the All Monitors Release Signal goes high after all POR and BOR monitors are released. See the PMM Block Diagram. During power down, the All Monitors Release Signal goes low if any of the POR or BOR monitors are tripped. See the PMM Block Diagram. Figure 6-4. Internal VREG Power Up Sequence • • For Power Up: 1. VDDIO (that is, the 3.3-V rail) should come up with the minimum slew rate specified. 2. The Internal VREG powers up after the I/O monitors (I/O POR and I/O BOR) are released. 3. After the times specified by VDDIO-MON-TOT-DELAY and VXRSN-PU-DELAY, XRSn will be released and the device starts the boot-up sequence. There is an additional delay between XRSn releasing (that is, going high) and the boot-up sequence starting. See Figure 6-1. 4. The I/O BOR monitor has different release points during power up and power down. For Power Down: 1. The only requirement on VDDIO during power down is the slew rate. 2. The I/O BOR monitor has different release points during power up and power down. 3. The I/O BOR tripping will cause XRSn to go low after VXRSN-PD-DELAY and also power down the Internal VREG. Note The All Monitors Release Signal is an internal signal. Note If there is an external circuit driving XRSn (for example, a supervisor), the boot-up sequence does not start until the XRSn pin is released by all internal and external sources. 6.12.1.4.3.3 Supply Sequencing Summary and Effects of Violations The acceptable power-up sequence for the rails is summarized below. "Power up" here means the rail in question has reached the minimum recommended operating voltage. CAUTION Non-acceptable sequences will lead to reliability concerns and possibly damage. For simplicity, it is recommended that all 3.3-V rails be tied together, and to follow the descriptions in Supply Pins Power Sequence. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 77 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 Table 6-1. External VREG Sequence Summary CASE RAILS POWER-UP ORDER ACCEPTABLE VDDIO VDDA VDD A 1 2 3 Yes B 1 3 2 Yes C 2 1 3 - D 2 3 1 - E 3 2 1 - F 3 1 2 - G 1 1 2 Yes H 2 2 1 - Table 6-2. Internal VREG Sequence Summary CASE RAILS POWER-UP ORDER ACCEPTABLE VDDIO VDDA A 1 2 Yes B 2 1 - C 1 1 Yes Note The analog modules on the device should only be powered after VDDA has reached the minimum recommended operating voltage. 6.12.1.4.3.4 Supply Slew Rate VDDIO has a minimum slew rate requirement. If the minimum slew rate is not met, XRSn might toggle a few times until VDDIO crosses the I/O BOR region. Note The toggling on XRSn has no adverse effect on the device as boot only starts once XRSn is steadily high. However if XRSn from the device is used to gate the reset signal of other ICs, then the slew rate requirement should be met to prevent this toggling. VDD has a minimum slew rate requirement in external VREG mode. If the minimum slew rate is not met, the device can release from reset and start booting before VDD has reached the minimum operating voltage, which can result in the device not functioning correctly. Note If the minimum slew rate cannot be met, a supervisor must be used on VDD to keep XRSn low until VDD crosses the minimum operating voltage to ensure correct device functionality. 78 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 6.12.1.5 Power Management Module Electrical Data and Timing 6.12.1.5.1 Power Management Module Operating Conditions over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT General CVDDIO (1) (2) VDDIO Capacitance Per Pin(7) 0.1 μF CVDDA (1) (2) VDDA Capacitance Per Pin(7) 2.2 μF SRVDDIO-UP (3) Supply Ramp Up Rate of 3.3V Rail (VDDIO) SRVDDIO-DN (3) Supply Ramp Down Rate of 3.3V Rail (VDDIO) 8 100 mV/μs 20 100 mV/μs VBOR-VDDIO-GB VDDIO Brown Out Reset (5) Voltage Guardband 0.1 V External VREG CVDD TOTAL(1) (4) Total VDD Capacitance(7) 10 SRVDD-UP (3) Supply Ramp Up Rate of 1.2V Rail (VDD) 3.5 100 mV/μs SRVDD-DN (3) Supply Ramp Down Rate of 1.2V Rail (VDD) 10 100 mV/μs VDDIO - VDD Delay(6) Ramp Delay Between VDDIO and VDD 0 No Restrictions μs 10 26.8 μF μF Internal VREG CVDD TOTAL(4) (1) (2) (3) (4) (5) (6) (7) Total VDD Capacitance(7) The exact value of the decoupling capacitance depends on the system voltage regulation solution that is supplying these pins. It is recommended to tie the 3.3V rails (VDDIO, VDDA) together and supply them from a single source. See the Supply Slew Rate section. Supply ramp rate faster than the maximum can trigger the on-chip ESD protection. See the Power Management Module (PMM) section on possible configurations for the total decoupling capacitance. TI recommends VBOR-VDDIO-GB to avoid BOR-VDDIO resets due to normal supply noise or load-transient events on the 3.3-V VDDIO system regulator. Good system regulator design and decoupling capacitance (following the system regulator specifications) are important to prevent activation of the BOR-VDDIO during normal device operation. The value of VBOR-VDDIO-GB is a system-level design consideration; the voltage listed here is typical for many applications. Delay between when the 3.3-V rail ramps up and when the 1.2-V rail ramps up. See the VREG Sequence Summary table for the allowable supply ramp sequences. Max capacitor tolerance should be 20%. 6.12.1.5.2 Power Management Module Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER VVREG Internal Voltage Regulator Output VVREG-PU Internal Voltage Regulator Power Up Time VVREG-INRUSH (5) Internal Voltage Regulator Inrush Current VPOR-VDDIO VDDIO Power on Reset Voltage TEST CONDITIONS MIN TYP MAX UNIT 1.14 1.2 1.32 V 350 µs 650 mA Before and After XRSn Release 2.3 V VBOR-VDDIO-UP VDDIO Brown Out Reset (1) Voltage on Ramp Up Before XRSn Release 2.7 V VBOR-VDDIO-DN VDDIO Brown Out Reset (1) Voltage on Ramp Down After XRSn Release Copyright © 2022 Texas Instruments Incorporated 2.81 3.0 V Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 79 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 6.12.1.5.2 Power Management Module Characteristics (continued) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VPOR-VDD-UP VDD Power on Reset Voltage Before XRSn Release on Ramp Up 1 V VPOR-VDD-DN VDD Power on Reset Voltage After XRSn Release on Ramp Down 1 V 40 μs 2 μs 145 μs 40 μs 140 μs 185 μs (2) (2) VXRSn-PUDELAY (3) VXRSn-PDDELAY (4) VDDIO-MONTOT-DELAY XRSn Release Delay after Supplies are Ramped Up During Power Up This is the final delay XRSn Trip Delay after Supplies are Ramped Down During Power Down Total Delays in Path of VDDIO Monitors (POR, BOR) XRSn Release Delay after a VDD POR Event VXRSn-MONRELEASE-DELAY XRSn Release Delay after a VDDIO BOR Supplies Within Operating Range XRSn Release Delay after a VDDIO POR Event (1) (2) (3) (4) (5) See the Supply Voltages figure. VPOR-VDD is not supported and it is set to trip at a level below the recommended operating conditions. If monitoring of VDD is needed, an external supervisor is required. Supplies are considered fully ramped up after they cross the minimum recommended operating conditions for the respective rail. All POR and BOR monitors need to be released before this delay takes effect. RC network delay will add to this. On power down, any of the POR or BOR monitors that trips will immediately trip XRSn. This delay is the time between any of the POR, BOR monitors tripping and XRSn going low. It is variable and depends on the ramp down rate of the supply. RC network delay will add to this. This is the transient current drawn on the VDDIO rail when the internal VREG turns on. Due to this, there might be some voltage drops on the VDDIO rail when the VREG turns on which could cause the VREG to ramp up in steps. There is no detriment to the device from this but the effect can be reduced if desired by using sufficient decoupling capacitors on VDDIO or picking an LDO/DC-DC that can supply this transient current. Supply Voltages 3.63 V 3.3 V +10% 0% Recommended System Voltage Regulator Range VDDIO Operating Range 3.1 V –6.1% 3.0 V –9.1% VBOR-GB BOR Guard Band VBOR-VDDIO Internal BOR Threshold 2.81 V 2.80 V –14.8% –15.1% Figure 6-5. Supply Voltages 80 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 6.12.2 Reset Timing XRSn is the device reset pin. It functions as an input and open-drain output. The device has a built-in power-on reset (POR) and brown-out reset (BOR) monitors. During power up, the monitor circuits keep the XRSn pin low. For more details, see the Power Management Module (PMM) section. A watchdog or NMI watchdog reset will also drive the pin low. An external open-drain circuit may drive the pin to assert a device reset. A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRSn and VDDIO. A capacitor should be placed between XRSn and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRSn pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. Figure 6-6 shows the recommended reset circuit. VDDIO 2.2 kW to 10 kW Optional open-drain Reset source XRSn £100 nF Figure 6-6. Reset Circuit 6.12.2.1 Reset Sources The Reset Signals table summarizes the various reset signals and their effect on the device. Table 6-3. Reset Signals Reset Source CPU Core Reset (C28x, FPU, TMU) Peripherals Reset JTAG / Debug Logic Reset IOs XRS Output POR Yes Yes Yes Hi-Z Yes BOR Yes Yes Yes Hi-Z Yes XRS Pin Yes Yes No Hi-Z - WDRS Yes Yes No Hi-Z Yes NMIWDRS Yes Yes No Hi-Z Yes SYSRS (Debugger Reset) Yes Yes No Hi-Z No SCCRESET Yes Yes No Hi-Z No SIMRESET. XRS Yes Yes No Hi-Z Yes SIMRESET. CPU1RS Yes Yes No Hi-Z No HWBISTRS Yes No No No No The parameter th(boot-mode) must account for a reset initiated from any of these sources. See the Resets section of the System Control chapter in the TMS320F28003x Real-Time Microcontrollers Technical Reference Manual. CAUTION Some reset sources are internally driven by the device. Some of these sources will drive XRSn low, use this to disable any other devices driving the boot pins. The SCCRESET and debugger reset sources do not drive XRSn; therefore, the pins used for boot mode should not be actively driven by other devices in the system. The boot configuration has a provision for changing the boot pins in OTP. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 81 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 6.12.2.2 Reset Electrical Data and Timing 6.12.2.2.1 Reset - XRSn - Timing Requirements MIN MAX UNIT th(boot-mode) Hold time for boot-mode pins 1.5 ms tw(RSL2) Pulse duration, XRSn low on warm reset 3.2 µs 6.12.2.2.2 Reset - XRSn - Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN tw(RSL1) Pulse duration, XRSn driven low by device after supplies are stable tw(WDRS) Pulse duration, reset pulse generated by watchdog tboot-flash Boot-ROM execution time to first instruction fetch in flash TYP MAX 100 UNIT µs 512tc(OSCCLK) cycles 1.2 ms 6.12.2.2.3 Reset Timing Diagrams VDDIO VDDA (3.3V) VDD (1.2V) tw(RSL1) XRSn(A) tboot-flash Boot ROM CPU Execution Phase User code th(boot-mode)(B) Boot-Mode Pins User code dependent GPIO pins as input Peripheral/GPIO function Based on boot code Boot-ROM execution starts GPIO pins as input (pullups are disabled) I/O Pins User code dependent A. B. The XRSn pin can be driven externally by a supervisor or an external pullup resistor, see the Pin Attributes table. On-chip monitors will hold this pin low until the supplies are in a valid range. After reset from any source (see the Reset Sources section), the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based on user environment and could be with or without PLL enabled. Figure 6-7. Power-on Reset 82 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 tw(RSL2) XRSn User code CPU Execution Phase Boot ROM User code Boot ROM execution starts (initiated by any reset source) Boot-Mode Pins Peripheral/GPIO function GPIO Pins as Input th(boot-mode)(A) Peripheral/GPIO function User-Code Execution Starts I/O Pins User-Code Dependent GPIO Pins as Input (Pullups are Disabled) User-Code Dependent A. After reset from any source (see the Reset Sources section), the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based on user environment and could be with or without PLL enabled. Figure 6-8. Warm Reset Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 83 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 6.12.3 Clock Specifications 6.12.3.1 Clock Sources Table 6-4. Possible Reference Clock Sources CLOCK SOURCE DESCRIPTION INTOSC1 Internal oscillator 1. Zero-pin overhead 10-MHz internal oscillator. INTOSC2(1) Internal oscillator 2. Zero-pin overhead 10-MHz internal oscillator. X1 (XTAL) External crystal or resonator connected between the X1 and X2 pins or single-ended clock connected to the X1 pin. (1) 84 On reset, internal oscillator 2 (INTOSC2) is the default clock source for the PLL (OSCCLK). Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 SYSCLKDIVSEL PLLSYSCLK NMIWD Watchdog Timer SYSPLL INTOSC1 INTOSC2 SYS Divider PLLRAWCLK FPU TMU Flash CPUCLK OSCCLK SYSPLLCLKEN X1 (XTAL) OSCCLKSRCSEL CPU SYSCLK SYSCLK One per SYSCLK peripheral PCLKCRx PERx.SYSCLK ePIE CLA GPIO Mx RAMs LSx RAMs GSx RAMs Boot ROM Message RAMs DCSM System Control WD XINT I2C ADC CMPSS GPDAC CAN MCAN HIC DCC HWBIST BGCRC ERAD CPUTIMERs CLB ECAP EQEP EPWM HRCAL PMBUS LIN FSI SDFM EPG AES One per LSPCLK peripheral LOSPCP PCLKCRx LSP Divider LSPCLK PERx.LSPCLK SCI SPI CLKSRCCTL2.CANxBCLKSEL AUXCLKIN (GPIO29) CAN Bit Clock PERx.SYSCLK CLKSRCCTL2.MCANxBCLKSEL CPUSYSCLK PLLRAWCLK / MCAN Bit Clock AUXCLKDIVSEL.MCANCLKDIV Figure 6-9. Clocking System Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 85 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 SYSPLL OSCCLK ÷ (REFDIV+1) INTCLK VCOCLK VCO ÷ (ODIV+1) PLLRAWCLK ÷ IMULT Figure 6-10. System PLL In Figure 6-10, f PLLRAWCLK 86 Submit Document Feedback f OSCCLK REFDIV 1 u IMULT ODIV 1 Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 6.12.3.2 Clock Frequencies, Requirements, and Characteristics This section provides the frequencies and timing requirements of the input clocks, PLL lock times, frequencies of the internal clocks, and the frequency and switching characteristics of the output clock. 6.12.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times 6.12.3.2.1.1 Input Clock Frequency MIN MAX UNIT f(XTAL) Frequency, X1/X2, from external crystal or resonator 10 20 MHz f(X1) Frequency, X1, from external oscillator 10 25 MHz f(AUXI) Frequency, AUXCLKIN, from external oscillator 10 60 MHz 6.12.3.2.1.2 XTAL Oscillator Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER X1 VIL Valid low-level input voltage (Comparator) X1 VIH Valid high-level input voltage (Comparator) MIN TYP MAX UNIT –0.3 0.3 * VDDIO V 0.7 * VDDIO VDDIO + 0.3 V 6.12.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source - Not a Crystal over recommended operating conditions (unless otherwise noted) PARAMETER X1 VIL Valid low-level input voltage (Buffer) X1 VIH Valid high-level input voltage (Buffer) MIN MAX UNIT –0.3 0.3 * VDDIO V 0.7 * VDDIO VDDIO + 0.3 V 6.12.3.2.1.4 X1 Timing Requirements MIN MAX tf(X1) Fall time, X1 tr(X1) Rise time, X1 tw(X1L) Pulse duration, X1 low as a percentage of tc(X1) 45% 55% tw(X1H) Pulse duration, X1 high as a percentage of tc(X1) 45% 55% MIN MAX UNIT 6 ns 6 ns 6.12.3.2.1.5 AUXCLKIN Timing Requirements UNIT tf(AUXI) Fall time, AUXCLKIN 6 ns tr(AUXI) Rise time, AUXCLKIN 6 ns tw(AUXL) Pulse duration, AUXCLKIN low as a percentage of tc(XCI) 45% 55% tw(AUXH) Pulse duration, AUXCLKIN high as a percentage of tc(XCI) 45% 55% 6.12.3.2.1.6 APLL Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER MIN TYP MAX UNIT PLL Lock time SYS PLL Lock Time(1) (1) 5µs + (1024 * (REFDIV + 1) * tc(OSCCLK)) μs The PLL lock time here defines the typical time that takes for the PLL to lock once PLL is enabled (SYSPLLCTL1[PLLENA]=1). Additional time to verify the PLL clock using Dual Clock Comparator (DCC) is not accounted here. TI recommends using the latest example software from C2000Ware for initializing the PLLs. For the system PLL, see InitSysPll() or SysCtl_setClock(). Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 87 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 6.12.3.2.1.7 XCLKOUT Switching Characteristics - PLL Bypassed or Enabled over recommended operating conditions (unless otherwise noted) PARAMETER(1) MIN MAX UNIT tf(XCO) Fall time, XCLKOUT 5 ns tr(XCO) Rise time, XCLKOUT 5 ns tw(XCOL) Pulse duration, XCLKOUT low H – 2(2) H + 2(2) ns 2(2) 2(2) ns 50 MHz tw(XCOH) Pulse duration, XCLKOUT high f(XCO) Frequency, XCLKOUT (1) (2) H– H+ A load of 40 pF is assumed for these parameters. H = 0.5tc(XCO) 6.12.3.2.1.8 Internal Clock Frequencies MIN f(SYSCLK) Frequency, device (system) clock tc(SYSCLK) Period, device (system) clock f(INTCLK) Frequency, system PLL going into VCO (after REFDIV) f(VCOCLK) Frequency, system PLL VCO (before ODIV) f(PLLRAWCLK) Frequency, system PLL output (before SYSCLK divider) f(PLL) Frequency, PLLSYSCLK Frequency, PLL Limp Frequency f(LSP) Frequency, LSPCLK tc(LSPCLK) Period, LSPCLK f(OSCCLK) Frequency, OSCCLK (INTOSC1 or INTOSC2 or XTAL or X1) f(EPWM) Frequency, EPWMCLK f(HRPWM) Frequency, HRPWMCLK 88 UNIT 120 MHz 8.33 500 ns 2 20 MHz 220 600 MHz 6 240 MHz 2 120 MHz (1) f(PLL_LIMP) (1) MAX 2 NOM 45/(ODIV+1) MHz 2 120 MHz 8.33 500 ns See respective clock 60 MHz 120 MHz 120 MHz PLL output frequency when OSCCLK is dead (Loss of OSCCLK causes PLL to Limp). Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 6.12.3.3 Input Clocks and PLLs In addition to the internal 0-pin oscillators, three types of external clock sources are supported: • A single-ended 3.3-V external clock. The clock signal should be connected to X1, as shown in Figure 6-11, with the XTALCR.SE bit set to 1. • An external crystal. The crystal should be connected across X1 and X2 with its load capacitors connected to VSS as shown in Figure 6-12. • An external resonator. The resonator should be connected across X1 and X2 with its ground connected to VSS as shown in Figure 6-13. Microcontroller Microcontroller VSS GPIO19 GPIO18* X1 X2 GPIO19 GPIO18 X1 X2 * Available as a GPIO when X1 is used as a clock +3.3 V VDD VSS Out 3.3-V Oscillator Gnd Figure 6-12. External Crystal Figure 6-11. Single-ended 3.3-V External Clock Microcontroller VSS GPIO19 GPIO18 X1 X2 Figure 6-13. External Resonator 6.12.3.4 XTAL Oscillator 6.12.3.4.1 Introduction The XTAL oscillator in this device is an embedded electrical oscillator that, when paired with a compatible crystal, can generate the system clock required by the device. 6.12.3.4.2 Overview The following sections describe the components of the electrical oscillator and crystal. 6.12.3.4.2.1 Electrical Oscillator The electrical oscillator in this device is a Pierce oscillator design. It is a positive feedback inverter circuit that requires a tuning circuit in order to oscillate. When this oscillator is paired with a compatible crystal, a tank circuit is formed. This tank circuit oscillates at the fundamental frequency of the crystal component. On this device, the oscillator is designed to operate in parallel resonance mode due to the shunt capacitor (C0) and required load capacitors (CL). Figure 6-14 illustrates the components of the electrical oscillator and the tank circuit. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 89 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 MCU To Rest of Chip XTAL Oscillator Buffer 0 Comp 1 XCLKOUT Circuit [XTAL On] Rbias XCLKOUT Pierce Inverter External Rd Crystal CL1 Internal GPIO External X2 X1 Internal CL2 GND GND Figure 6-14. Electrical Oscillator Block Diagram 6.12.3.4.2.1.1 Modes of Operation The electrical oscillator in this device has two modes of operation: crystal mode and single-ended mode. 6.12.3.4.2.1.1.1 Crystal Mode of Operation In the crystal mode of operation, a quartz crystal with load capacitors has to be connected to X1 and X2. This mode of operation is engaged when [XTAL On] = 1, which is achieved by setting XTALCR.OSCOFF = 0 and XTALCR.SE = 0. There is an internal bias resistor for the feedback loop so an external one should not be used. Adding an external bias resistor will create a parallel resistance with the internal Rbias, moving the bias point of operation and possibly leading to clipped waveforms, out-of-specification duty cycle, and reduction in the effective negative resistance. In this mode of operation, the resultant clock on X1 is passed through a comparator (Comp) to the rest of the chip. The clock on X1 needs to meet the VIH and VIL of the comparator. See the XTAL Oscillator Characteristics table for the VIH and VIL requirements of the comparator. 6.12.3.4.2.1.1.2 Single-Ended Mode of Operation In the single-ended mode of operation, a clock signal is connected to X1 with X2 left unconnected. A quartz crystal should not be used in this mode. This mode is enabled when [XTAL On] = 0, which can be achieved by setting XTALCR.OSCOFF = 1 and XTALCR.SE = 1. 90 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 In this mode of operation, the clock on X1 is passed through a buffer (Buffer) to the rest of the chip. See the X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal) table for the input requirements of the buffer. 6.12.3.4.2.1.2 XTAL Output on XCLKOUT The output of the electrical oscillator that is fed to the rest of the chip can be brought out on XCLKOUT for observation by configuring the CLKSRCCTL3.XCLKOUTSEL and XCLKOUTDIVSEL.XCLKOUTDIV registers. See the GPIO Muxed Pins table for a list of GPIOs that XCLKOUT comes out on. 6.12.3.4.2.2 Quartz Crystal Electrically, a quartz crystal can be represented by an LCR (Inductor-Capacitor-Resistor) circuit. However, unlike an LCR circuit, crystals have very high Q due to the low motional resistance and are also very underdamped. Components of the crystal are shown in Figure 6-15 and explained below. Quartz Crystal Internal External Cm Rm C0 CL Lm Figure 6-15. Crystal Electrical Representation Cm (Motional capacitance): Denotes the elasticity of the crystal. Rm (Motional resistance): Denotes the resistive losses within the crystal. This is not the ESR of the crystal but can be approximated as such depending on the values of the other crystal components. Lm (Motional inductance): Denotes the vibrating mass of the crystal. C0 (Shunt capacitance): The capacitance formed from the two crystal electrodes and stray package capacitance. CL (Load capacitance): This is the effective capacitance seen by the crystal at its electrodes. It is external to the crystal. The frequency ppm specified in the crystal data sheet is usually tied to the CL parameter. Note that most crystal manufacturers specify CL as the effective capacitance seen at the crystal pins, while some crystal manufacturers specify CL as the capacitance on just one of the crystal pins. Check with the crystal manufacturer for how the CL is specified in order to use the correct values in calculations. From Figure 6-14, CL1 and CL2 are in series; so, to find the equivalent total capacitance seen by the crystal, the capacitance series formula has to be applied which simply evaluates to [CL1]/2 if CL1 = CL2. It is recommended that a stray PCB capacitance be added to this value. 3 pF to 5 pF are reasonable estimates, but the actual value will depend on the PCB in question. Note that the load capacitance is a requirement of both the electrical oscillator and crystal. The value chosen has to satisfy both the electrical oscillator and the crystal. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 91 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 The effect of CL on the crystal is frequency-pulling. If the effective load capacitance is lower than the target, the crystal frequency will increase and vice-versa. However, the effect of frequency-pulling is usually very minimal and typically results in less than 10-ppm variation from the nominal frequency. 6.12.3.4.2.3 GPIO Modes of Operation On this device, X1 and X2 can be used as GPIO19 and GPIO18, respectively, depending on the operating mode of the XTAL. Refer to the External Oscillator (XTAL) section of the TMS320F28003x Real-Time Microcontrollers Technical Reference Manual. 6.12.3.4.3 Functional Operation 6.12.3.4.3.1 ESR – Effective Series Resistance Effective Series Resistance is the resistive load the crystal presents to the electrical oscillator at resonance. The higher the ESR, the lower the Q, and less likely the crystal will start up or maintain oscillation. The relationship between ESR and the crystal components is indicated below. ESR = Rm *  1 +   C0 CL 2 (1) Note that ESR is not the same as motional resistance of the crystal, but can be approximated as such if the effective load capacitance is much greater than the shunt capacitance. 6.12.3.4.3.2 Rneg – Negative Resistance Negative resistance is the impedance presented by the electrical oscillator to the crystal. It is the amount of energy the electrical oscillator must supply to the crystal to overcome the losses incurred during oscillation. Rneg depicts a circuit that provides rather than consume energy and can also be viewed as the overall gain of the circuit. The generally accepted practice is to have Rneg > 3x ESR to 5x ESR to ensure the crystal starts up under all conditions. Note that it takes slightly more energy to start up the crystal than it does to sustain oscillation; therefore, if it can be ensured that the negative resistance requirement is met at start-up, then oscillation sustenance will not be an issue. Figure 6-16 and Figure 6-17 show the variation between negative resistance and the crystal components for this device. As can be seen from the graphs, the crystal shunt capacitance (C0) and effective load capacitance (CL) greatly influence the negative resistance of the electrical oscillator. Note that these are typical graphs; so, refer to Table 6-5 for minimum and maximum values for design considerations. 6.12.3.4.3.3 Start-up Time Start-up time is an important consideration when selecting the components of the crystal circuit. As mentioned in the Rneg – Negative Resistance section, for reliable start-up across all conditions, it is recommended that the Rneg > 3x ESR to 5x ESR of the crystal. Crystal ESR and the dampening resistor (Rd) greatly affect the start-up time. The higher the two values, the longer the crystal takes to start up. Longer start-up times are usually a sign that the crystal and components are not a correct match. Refer to Crystal Oscillator Specifications for the typical start-up times. Note that the numbers specified here are typical numbers provided for guidance only. Actual start-up time depends heavily on the crystal in question and the external components. 6.12.3.4.3.3.1 X1/X2 Precondition On this device, the GPIO19/18 alternate functionality on X1/X2 can be used to speed up the start-up time of the crystal if needed. This functionality is achieved by preconditioning the load capacitors CL1 and CL2 to a known state before the XTAL is turned on. See the TMS320F28003x Real-Time Microcontrollers Technical Reference Manual for details. 92 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMS320F280039C TMS320F280039C-Q1 TMS320F280038C-Q1 TMS320F280037C TMS320F280037C-Q1 TMS320F280037 TMS320F280034 TMS320F280039C, TMS320F280039C-Q1, TMS320F280038C-Q1 TMS320F280037C, TMS320F280037C-Q1, TMS320F280037, TMS320F280034 www.ti.com SPRSP61B – OCTOBER 2021 – REVISED NOVEMBER 2022 6.12.3.4.3.4 DL – Drive Level Drive level refers to how much power is provided by the electrical oscillator and dissipated by the crystal. The maximum drive level specified in the crystal manufacturer’s data sheet is usually the maximum the crystal can dissipate without damage or significant reduction in operating life. On the other hand, the drive level specified by the electrical oscillator is the maximum power it can provide. The actual power provided by the electrical oscillator is not necessarily the maximum power and depends on the crystal and board components. For cases where the actual drive level from the electrical oscillator exceeds the maximum drive level specification of the crystal, a dampening resistor (Rd) should be installed to limit the current and reduce the power dissipated by the crystal. Note that Rd reduces the circuit gain; and therefore, the actual value to use should be evaluated to make sure all other conditions for start-up and sustained oscillation are met. 6.12.3.4.4 How to Choose a Crystal Using Crystal Oscillator Specifications as a reference: 1. Pick a crystal frequency (for example, 20 MHz). 2. Check that the ESR of the crystal = 1 mW. If this requirement is not met, a dampening resistor Rd can be used. Refer to DL – Drive Level on other points to consider when using Rd. 6.12.3.4.5 Testing It is recommended that the user have the crystal manufacturer completely characterize the crystal with their board to ensure the crystal always starts up and maintains oscillation. Below is a brief overview of some measurements that can be performed: Due to how sensitive the crystal circuit is to capacitance, it is recommended that scope probes not be connected to X1 and X2. If scope probes must be used to monitor X1/X2, an active probe with