TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
1 Features
•
•
•
•
•
•
•
TMS320C28x 32-bit DSP core at 120 MHz
– IEEE 754 Floating-Point Unit (FPU)
• Support for Fast Integer Division (FINTDIV)
– Trigonometric Math Unit (TMU)
• Support for Nonlinear Proportional Integral
Derivative (NLPID) control
– CRC Engine and Instructions (VCRC)
– Ten hardware breakpoints (with ERAD)
Programmable Control Law Accelerator (CLA)
– 120 MHz
– IEEE 754 single-precision floating-point
instructions
– Executes code independently of main CPU
On-chip memory
– 384KB (192KW) of flash (ECC-protected)
across three independent banks
– 69KB (34.5KW) of RAM (ECC-protected)
– Dual-zone security
– Secure Boot and JTAG Lock
Clock and system control
– Two internal 10-MHz oscillators
– Crystal oscillator or external clock input
– Windowed watchdog timer module
– Missing clock detection circuitry
– Dual-clock Comparator (DCC)
3.3-V I/O design
– Internal VREG generation allows for singlesupply design
– Brownout reset (BOR) circuit
System peripherals
– 6-channel Direct Memory Access (DMA)
controller
– 55 individually programmable multiplexed
General-Purpose Input/Output (GPIO) pins
– 23 digital inputs on analog pins
– 2 digital inputs/outputs on analog pins (AGPIO)
– Enhanced Peripheral Interrupt Expansion
(ePIE)
– Multiple low-power mode (LPM) support
– Embedded Real-time Analysis and Diagnostic
(ERAD)
– Unique Identification (UID) number
Communications peripherals
– One Power-Management Bus (PMBus)
interface
– Two Inter-integrated Circuit (I2C) interfaces
– One Controller Area Network (CAN/DCAN) bus
port
•
•
•
•
•
•
– One Controller Area Network with Flexible
Data-Rate (CAN FD/MCAN) bus port
– Two Serial Peripheral Interface (SPI) ports
– Two UART-compatible Serial Communication
Interface (SCI)
– Two UART-compatible Local Interconnect
Network (LIN) interfaces
– Fast Serial Interface (FSI) with one transmitter
and one receiver (up to 200Mbps)
Analog system
– Three 4-MSPS, 12-bit Analog-to-Digital
Converters (ADCs)
• Up to 23 external channels (includes the two
gpdac outputs)
• Four integrated Post-Processing Blocks
(PPB) per ADC
– Four windowed comparators (CMPSS) with
12-bit reference Digital-to-Analog Converters
(DACs)
• Digital glitch filters
– Two 12-bit buffered DAC outputs
Enhanced control peripherals
– 16 ePWM channels with eight channels
that have high-resolution capability (150-ps
resolution)
• Integrated dead-band support
• Integrated hardware trip zones (TZs)
– Three Enhanced Capture (eCAP) modules
• High-resolution Capture (HRCAP) available
on one of the three eCAP modules
– Two Enhanced Quadrature Encoder Pulse
(eQEP) modules with support for CW/CCW
operation modes
– Eight Sigma-Delta Filter Module (SDFM) input
channels (two parallel filters per channel)
• Standard SDFM data filtering
• Comparator filter for fast action for
overvalue or undervalue condition
– Embedded Pattern Generator (EPG)
Configurable Logic Block (CLB)
– 4 tiles
– Augments existing peripheral capability
– Supports position manager solutions
Host Interface Controller (HIC)
– Access to internal memory from an external
host
Background CRC (BGCRC)
– One cycle CRC computation on 32 bits of data
Advanced Encryption Standard (AES) accelerator
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
ADVANCE INFORMATION
TMS320F28003x Real-Time Microcontrollers
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
•
•
•
ADVANCE INFORMATION
•
Live Firmware Update (LFU)
– Fast context switching from old to new firmware
– Flash bank erase time improvements
Diagnostic features
– Memory Power On Self Test (MPOST)
– Hardware Built-in Self Test (HWBIST)
Package options:
– 100-pin Low-profile Quad Flatpack (LQFP)
[PZ suffix]
– 80-pin Low-profile Quad Flatpack (LQFP)
[PN suffix]
– 64-pin (LQFP) [PM suffix]
– 48-pin (LQFP) [PT suffix]
Temperature options:
– Free-air (TA): –40°C to 125°C
– Junction (TJ): –40°C to 150°C
•
•
•
•
2 Applications
•
•
•
•
•
•
•
•
Appliances
– Air conditioner outdoor unit
Building automation
– Door operator drive control
Industrial machine & machine tools
– Automated sorting equipment
– Textile machine
AC inverter & VF drives
– AC drive control module
– AC drive position feedback
– AC drive power stage module
Linear motor transport systems
– Linear motor power stage
Single & multi axis servo drives
– Servo drive position feedback
– Servo drive power stage module
Speed controlled BLDC drives
– AC-input BLDC motor drive
– DC-input BLDC motor drive
Factory automation
– Robot servo drive
– Mobile robot motor control
– Position sensor
•
•
•
•
•
•
Industrial power
– Industrial AC-DC
UPS
– Three phase UPS
– Single phase online UPS
Telecom & server power
– Merchant DC/DC
– Merchant network & server PSU
– Merchant telecom rectifiers
Hybrids, electric & powertrain systems
– DC/DC converter
– Inverter & motor control
– On-board (OBC) & wireless charger
– Virtual engine sound system (VESS)
– Engine fan
– eTurbo/charger
– Pump
– Electric power steering (EPS)
Infotainment and cluster
– Head-up display
– Automotive head unit
– Automotive external amplifier
Body electronics & lighting
– Automotive HVAC compressor module
– DC/AC inverter
– Headlight
ADAS
– Mechanically scanning LIDAR
EV charging infrastructure
– AC charging (pile) station
– DC charging (pile) station
– EV charging station power module
– Wireless EV charging station
Renewable energy storage
– Energy storage power conversion system
(PCS)
Solar energy
– Central inverter
– Micro inverter
– Solar power optimizer
– Solar arc protection
– Rapid shutdown
– String inverter
3 Description
The TMS320F28003x (F28003x) is a member of the C2000™ real-time microcontroller family of scalable, ultralow latency devices designed for efficiency in power electronics, including but not limited to: high power density,
high switching frequencies, and supporting the use of GaN and SiC technologies.
2
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These include such applications as:
•
•
•
•
•
•
Industrial motor drives
Motor control
Solar inverters
Digital power
Electrical vehicles and transportation
Sensing and signal processing
The real-time control subsystem is based on TI’s 32-bit C28x DSP core, which provides 120 MHz of signalprocessing performance for floating- or fixed-point code running from either on-chip flash or SRAM. The
C28x CPU is further boosted by the Floating-Point Unit (FPU), Trigonometric Math Unit (TMU), and VCRC
(Cyclical Redundancy Check) extended instruction sets, speeding up common algorithms key to real-time control
systems.
ADVANCE INFORMATION
The CLA allows significant offloading of common tasks from the main C28x CPU. The CLA is an independent
32-bit floating-point math accelerator that executes in parallel with the CPU. Additionally, the CLA has its own
dedicated memory resources and it can directly access the key peripherals that are required in a typical control
system. Support of a subset of ANSI C is standard, as are key features like hardware breakpoints and hardware
task-switching.
The F28003x supports up to 384KB (192KW) of flash memory divided into three 128KB (64KW) banks, which
enable programming and execution in parallel. Up to 69KB (34.5KW) of on-chip SRAM is also available to
supplement the flash memory.
The Live Firmware Update hardware enhancements on F28003x allow fast context switching from the old
firmware to the new firmware to minimize application downtime when updating the device firmware.
High-performance analog blocks are integrated on the F28003x real-time microcontroller (MCU) and are closely
coupled with the processing and PWM units to provide optimal real-time signal chain performance. Sixteen PWM
channels, all supporting frequency-independent resolution modes, enable control of various power stages from a
3-phase inverter to power factor correction and advanced multi-level power topologies.
The inclusion of the Configurable Logic Block (CLB) allows the user to add custom logic and potentially integrate
FPGA-like functions into the C2000 real-time MCU.
Interfacing is supported through various industry-standard communication ports (such as SPI, SCI, I2C, PMBus,
LIN, CAN and CAN FD) and offers multiple pin-muxing options for optimal signal placement. The Fast Serial
Interface (FSI) enables up to 200 Mbps of robust communications across an isolation boundary.
New to the C2000 platform is the Host Interface Controller (HIC), a high-throughput interface that allows an
external host to access the resources of the TMS320F28003x directly.
Want to learn more about features that make C2000 Real-Time MCUs the right choice for your real-time control
system? Check out The Essential Guide for Developing With C2000™ Real-Time Microcontrollers and visit the
C2000™ real-time control MCUs page.
The Getting Started With C2000™ Real-Time Control Microcontrollers (MCUs) Getting Started Guide covers all
aspects of development with C2000 devices from hardware to support resources. In addition to key reference
documents, each section provides relevant links and resources to further expand on the information covered.
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Ready to get started? Check out the F28003x evaluation board (coming soon) and download C2000Ware.
Device Information
CONTROL LAW
ACCELERATOR (CLA)
CONFIGURABLE
LOGIC BLOCK (CLB)
TMS320F280039C-Q1,
TMS320F280039C
Yes
4 Tiles
TMS320F280039-Q1,
TMS320F280039
Yes
–
TMS320F280038C-Q1
Yes
4 Tiles
TMS320F280038-Q1
Yes
–
TMS320F280037C-Q1,
TMS320F280037C
Yes
4 Tiles
PART NUMBER(1)
ADVANCE INFORMATION
TMS320F280037-Q1,
TMS320F280037
Yes
TMS320F280036C-Q1
Yes
4 Tiles
TMS320F280036-Q1
Yes
–
TMS320F280034-Q1,
TMS320F280034
Yes
TMS320F280033
No
(1)
4
FLASH SIZE
384KB
–
256KB
–
128KB
–
128KB
For more information on these devices, see the Device Comparison table.
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SPRSP61 – OCTOBER 2021
3.1 Functional Block Diagram
The Functional Block Diagram shows the CPU system and associated peripherals.
Buses Legend
CPU
CLA
DMA
HIC
BGCRC
C28x CPU
(120MHz)
FPU32
TMU
VCRC
FINTDIV
CLA
(120MHz)
SYSTEM CONTROL
CLA to CPU MSG RAM
CPU Timers
XTAL
INTOSC1, INTOSC2
PLL
ePIE
Windowed WD
NMI WD
Boot ROM
CPU to CLA MSG RAM
Flash Bank0
16 Sectors, 64Kw(128KB)
CLA Data ROM
CLA Program ROM
Flash Bank1
16 Sectors, 64Kw(128KB)
SECURITY
DCSM
JTAG Lock
Secure Boot
Flash Bank2
16 Sectors, 64Kw(128KB)
DIAGNOSTICS
M0-M1 RAM
2Kw(4KB)
DCC
MPOST
HWBIST
ERAD
JTAG/cJTAG
CLA to DMA MSG RAM
DMA to CLA MSG RAM
BGCRC
LS0-LS7 RAM
16Kw(32KB)
HIC
GS0-GS3 RAM
16Kw(32KB)
OTHERS
DMA
6 Channels
EPG
PF1
16x ePWM
(8 Hi-Res Capable)
3x eCAP
(1 HRCAP Capable)
PF3
4x CMPSS
Result
Data
3x 12-Bit ADC
55x GPIO
Input XBAR
Output XBAR
ePWM XBAR
CLB XBAR
CLB Input XBAR
CLB Output XBAR
2x Buered DAC
2x eQEP
(CW/CCW Support)
8x SD Filters
A.
PF4
ADVANCE INFORMATION
Secure ROM
PF2
1x PMBUS
2x SPI
1x FSI RX
1x FSI TX
PF7
1x
DCAN/
CAN
PF7
1x
MCAN/
CAN FD
PF8
2x LIN(A)
PF9
2x SCI
2x I2C
PF10
PF11
PF12
4x CLB
1x AES
LFU
The LIN module can also work as an SCI.
Figure 3-1. Functional Block Diagram
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Table of Contents
ADVANCE INFORMATION
1 Features............................................................................1
2 Applications..................................................................... 2
3 Description.......................................................................2
3.1 Functional Block Diagram........................................... 5
Revision History................................................................. 6
4 Device Comparison......................................................... 7
4.1 Related Products........................................................ 9
5 Pin Configuration and Functions.................................10
5.1 Pin Diagrams............................................................ 10
5.2 Pin Attributes.............................................................15
5.3 Signal Descriptions................................................... 37
5.4 Pin Multiplexing.........................................................61
5.5 Pins With Internal Pullup and Pulldown.................... 69
5.6 Connections for Unused Pins................................... 70
6 Specifications................................................................ 72
6.1 Absolute Maximum Ratings...................................... 72
6.2 ESD Ratings – Commercial...................................... 72
6.3 ESD Ratings – Automotive....................................... 73
6.4 Recommended Operating Conditions.......................73
6.5 Power Consumption Summary................................. 74
6.6 Electrical Characteristics...........................................80
6.7 Thermal Resistance Characteristics for PZ
Package...................................................................... 81
6.8 Thermal Resistance Characteristics for PN
Package...................................................................... 82
6.9 Thermal Resistance Characteristics for PM
Package...................................................................... 83
6.10 Thermal Resistance Characteristics for PT
Package...................................................................... 84
6.11 Thermal Design Considerations..............................84
6.12 System.................................................................... 85
6.13 Analog Peripherals................................................126
6.14 Control Peripherals............................................... 156
6.15 Communications Peripherals................................ 171
7 Detailed Description....................................................206
7.1 Overview................................................................. 206
7.2 Functional Block Diagram....................................... 207
7.3 Memory................................................................... 208
7.4 Identification............................................................216
7.5 Bus Architecture – Peripheral Connectivity.............217
7.6 C28x Processor...................................................... 218
7.7 Control Law Accelerator (CLA)............................... 220
7.8 Embedded Real-Time Analysis and Diagnostic
(ERAD)...................................................................... 222
7.9 Background CRC-32 (BGCRC).............................. 222
7.10 Direct Memory Access (DMA)...............................223
7.11 Device Boot Modes............................................... 224
7.12 Dual Code Security Module.................................. 232
7.13 Watchdog.............................................................. 233
7.14 C28x Timers..........................................................234
7.15 Dual-Clock Comparator (DCC)............................. 234
7.16 Configurable Logic Block (CLB)............................236
8 Applications, Implementation, and Layout............... 238
8.1 TI Reference Design............................................... 238
9 Device and Documentation Support..........................239
9.1 Getting Started and Next Steps.............................. 239
9.2 Device Nomenclature..............................................239
9.3 Markings................................................................. 240
9.4 Tools and Software................................................. 241
9.5 Documentation Support.......................................... 243
9.6 Support Resources................................................. 244
9.7 Trademarks............................................................. 245
9.8 Electrostatic Discharge Caution..............................245
9.9 Glossary..................................................................245
10 Mechanical, Packaging, and Orderable
Information.................................................................. 246
Revision History
DATE
October 2021
6
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REVISION
*
NOTES
Initial Release
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4 Device Comparison
Table 4-1 lists the features of the TMS320F28003x devices.
Table 4-1. Device Comparison
F280039C
F280039C-Q1
F280039
F280039-Q1
FEATURE(1)
F280038C-Q1
F280038-Q1
F280037C
F280037C-Q1
F280037
F280037-Q1
F280036C-Q1
F280036-Q1
F280034
F280034-Q1
F280033
Processor and Accelerators
Frequency (MHz)
120
FPU
Yes (instructions for Fast Integer Division)
VCRC
Yes
TMU
CLA – Type 2
Yes – Type 1 (instructions supporting NLPID)
Available
Yes
Frequency (MHz)
120
6-Channel DMA – Type 0
No
ADVANCE INFORMATION
C28x
–
Yes
External interrupts
5
Memory
Flash
Flash Banks
RAM
384KB (192KW)
256KB (128KW)
128KB (64KW)
3 x 128KB
2 x 128KB
2 x 64KB
Dedicated
4KB (2KW)
Local Shared
32KB (16KW)
Message
1KB (0.5KW)
Global Shared
32KB (16KW)
Total
69KB (34.5KW)
Message RAM Types
ECC
512B (256W) CPU-CLA
512B (256W) CLA-DMA
–
FLASH, Mx, LSx, GSx, Message RAM
FLASH, Mx,
LSx, GSx
Parity
ROM, CAN RAM
Code security for on-chip flash and RAM
Yes
System
Configurable Logic Block (CLB)
4 Tiles on C Variants
Embedded Pattern Generator (EPG)
–
Yes
32-bit CPU timers
3
Advance Encryption Standard (AES)
Yes
Background CRC (BGCRC)
Yes
Live Firmware Update (LFU) Support
Yes, with enhancements and flash bank erase time improvements
Secure Boot
Yes
JTAG Lock
Yes
HWBIST
Yes
Nonmaskable Interrupt Watchdog (NMIWD) timers
1
Watchdog timers
1
Crystal oscillator/External clock input
1
Internal oscillator
2
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Table 4-1. Device Comparison (continued)
F280039C
F280039C-Q1
F280039
F280039-Q1
FEATURE(1)
F280038C-Q1
F280038-Q1
F280037C
F280037C-Q1
F280037
F280037-Q1
F280036C-Q1
F280036-Q1
F280034
F280034-Q1
F280033
Pins and Power Supply
Internal 3.3-V to 1.2-V Voltage
Regulator
VREG LDO
Yes
GPIO pins
100-pin PZ
51
–
51
–
51
80-pin PN
39
–
39
–
39
64-pin PM
26
25
26
25
26
48-pin PT
–
–
14
–
14
Additional GPIO
AIO (analog with digital inputs)
4 (2 from cJTAG and 2 from X1/X2)
ADVANCE INFORMATION
100-pin PZ
23
–
23
–
23
80-pin PN
16
–
16
–
16
64-pin PM
16
16
16
16
16
48-pin PT
–
–
14
–
14
AGPIO (analog with digital
inputs and outputs)
100-pin PZ
2
–
2
–
2
80-pin PN
2
–
2
–
2
ADC 12-bit
Number of ADCs
–
23
Analog Peripherals
3
MSPS
4
Conversion Time (ns)(2)
ADC channels (single-ended)
(includes the two gpdac
outputs)
250
100-pin PZ
23
–
23
80-pin PN
64-pin PM
18
–
18
–
18
16
16
16
16
48-pin PT
16
–
–
14
–
14
Temperature sensor
1
Buffered DAC
2
CMPSS
(each CMPSS has two comparators and two internal DACs)
4
Control Peripherals (3)
eCAP/HRCAP modules – Type 2
ePWM/HRPWM channels – Type 4
8
3 (1 - eCAP3 with HRCAP capability)
16 (8 - ePWM1 to ePWM4 with HRPWM capability)
eQEP modules – Type 2
2
SDFM channels – Type 2
8
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Table 4-1. Device Comparison (continued)
F280039C
F280039C-Q1
F280039
F280039-Q1
FEATURE(1)
F280038C-Q1
F280038-Q1
F280037C
F280037C-Q1
F280037
F280037-Q1
F280036C-Q1
F280036-Q1
F280034
F280034-Q1
F280033
Communication Peripherals (3)
CAN (DCAN) – Type 0
1
CANFD (MCAN) – Type 1
1
1 (1 RX and 1 TX)
I2C – Type 1
2
LIN – Type 1 (UART-Compatible)
2
Host Interface Controller (HIC) – Type 1
1
PMBus – Type 0
1
SCI – Type 0 (UART-Compatible)
2
SPI – Type 2
ADVANCE INFORMATION
Fast Serial Interface (FSI) – Type 2
2
Package Options, Temperature, and Qualification
Junction temperature (TJ)
–40°C to 150°C
Free-Air temperature (TA)
–40°C to 125°C
Package Options
Package Options with AECQ100 Qualification available
(1)
(2)
(3)
100-pin PZ
F280039C
F280039
–
F280037C
F280037
–
F280034
F280033
80-pin PN
F280039C
F280039
–
F280037C
F280037
–
F280034
F280033
64-pin PM
F280039C
F280039
–
F280037C
F280037
–
F280034
F280033
48-pin PT
–
–
F280037C
F280037
–
F280034
F280033
100-pin PZ
F280039C-Q1
F280039-Q1
–
F280037C-Q1
F280037-Q1
–
–
–
64-pin PM
–
F280038C-Q1
F280038-Q1
–
F280036C-Q1
F280036-Q1
–
–
48-pin PT
–
–
F280037C-Q1
F280037-Q1
–
F280034-Q1
–
A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module.
Time between start of sample-and-hold window to start of sample-and-hold window of the next conversion.
For devices that are available in more than one package, the peripheral count listed in the smaller package is reduced because the
smaller package has less device pins available. The number of peripherals internally present on the device is not reduced compared
to the largest package offered within a part number. See Section 5 to identify which peripheral instances are accessible on pins in the
smaller package.
4.1 Related Products
TMS320F2803x Real-Time Microcontrollers
The F2803x series increases the pin-count and memory size options. The F2803x series also introduces the
parallel control law accelerator (CLA) option.
TMS320F2807x Real-Time Microcontrollers
The F2807x series offers the most performance, largest pin counts, flash memory sizes, and peripheral options.
The F2807x series includes the latest generation of accelerators, ePWM peripherals, and analog technology.
TMS320F28004x Real-Time Microcontrollers
The F28004x series is a reduced version of the F2807x series with the latest generational enhancements.
TMS320F28002x Real-Time Microcontrollers
The F28002x series is a reduced version of the F28004x series with the latest generational enhancements.
TMS320F2838x Real-Time Microcontrollers
The F2838x series offers more performance, larger pin counts, flash memory sizes, peripheral and wide variety
of connectivity options. The F2838x series includes the latest generation of accelerators, ePWM peripherals, and
analog technology.
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5 Pin Configuration and Functions
5.1 Pin Diagrams
GPIO29
GPIO31
GPIO30
GPIO6
GPIO14
GPIO15
GPIO34
GPIO10
GPIO59
GPIO61
GPIO9
GPIO5
VDDIO
VDD
VSS
GPIO44
GPIO7
GPIO22
GPIO41
GPIO23
GPIO40
GPIO0
GPIO1
GPIO2
GPIO3
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
Figure 5-1 shows the pin assignments on the 100-pin PZ low-profile quad flatpack; the Q and non-Q variant have
the same pinout. Figure 5-2 shows the pin assignments on the 80-pin PN low-profile quad flatpack. Figure 5-3
shows the pin assignments on the 64-pin PM low-profile quad flatpack (Q temperature). Figure 5-4 shows the pin
assignments on the 64-pin PM low-profile quad flatpack. Figure 5-5 shows the pin assignments on the 48-Pin PT
low-profile quad flatpack; the Q and non-Q variant have the same pinout.
ADVANCE INFORMATION
GPIO28
1
75
GPIO4
XRSn
2
74
GPIO8
VDDIO
3
73
VREGENZ
VDD
4
72
VSS
VSS
5
71
VDD
GPIO47
6
70
VDDIO
GPIO48
7
69
GPIO19,X1
GPIO49
8
68
GPIO18,X2
GPIO50
9
67
GPIO58
GPIO51
10
66
GPIO57
GPIO52
11
65
GPIO56
GPIO53
12
64
GPIO32
GPIO54
13
63
GPIO35/TDI
A6
14
62
TMS
B2,C6
15
61
GPIO37/TDO
B3,VDAC
16
60
TCK
A2,B6,C9
17
59
GPIO27
50
GPIO13
49
B11,GPIO21
48
B5,GPIO20
VDD
VDDIO
VSS
GPIO60
GPIO55
C14
B0,C11
A10,B1,C10
B4,C8
A9
A8
A4,B8
A5
VDDA
B5
VSSA
A7,C3
B11
C1
A12,C5
VREFLO
VREFLO
A.
47
GPIO12
46
51
45
25
44
GPIO11
VREFHI
43
GPIO33
52
42
53
24
41
23
VREFHI
40
A0,B15,C15,DACA_OUT
39
GPIO16
38
54
37
22
36
GPIO17
A1,B7,DACB_OUT
35
55
34
21
33
GPIO24
B12,C2
32
56
31
20
30
GPIO25
A11,B10,C0
29
GPIO26
57
28
58
19
27
18
26
A3,B9,C7
A14,B14,C4
Not to scale
Only the GPIO function is shown on GPIO pins. See Section 5.2 for the complete, muxed signal name.
Figure 5-1. 100-Pin PZ Low-Profile Quad Flatpack (Top View)
10
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GPIO14
GPIO15
GPIO34
GPIO10
GPIO9
GPIO5
GPIO45
VDDIO
VDD
VSS
GPIO44
GPIO7
GPIO22
GPIO41
GPIO23
GPIO40
GPIO0
GPIO1
GPIO2
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
GPIO30
1
60
GPIO3
GPIO31
2
59
GPIO4
GPIO29
3
58
GPIO8
GPIO28
4
57
GPIO42
XRSn
5
56
GPIO39
GPIO46
6
55
VSS
VDDIO
7
54
GPIO43
VDD
8
53
VDD
VSS
9
52
VDDIO
A6
10
51
GPIO19,X1
B2,C6
11
50
GPIO18,X2
A3,B3,C5,VDAC
12
49
GPIO32
A2,B6,C9
13
48
GPIO35/TDI
A15,B9,C7
14
47
TMS
A14,B14,C4
15
46
GPIO37/TDO
A11,B10,C0
16
45
TCK
A5,B12,C2
17
44
GPIO27
40
GPIO17
39
GPIO16
37
38
GPIO33
GPIO11
36
GPIO12
35
GPIO13
34
33
B5,GPIO20
B11,GPIO21
32
VDDIO
31
30
VSS
VDD
A10,B1,C10
A9,B4,C8
A4,B8,C14
VDDA
VSSA
A8,B0,C11
A7,C3
A12,C1
VREFLO
A.
29
GPIO24
28
41
27
20
26
VREFHI
25
GPIO25
24
GPIO26
42
23
43
19
22
18
21
A1,B7,DACB_OUT
A0,B15,C15,DACA_OUT
ADVANCE INFORMATION
GPIO6
80
SPRSP61 – OCTOBER 2021
Not to scale
Only the GPIO function is shown on GPIO pins. See Section 5.2 for the complete, muxed signal name.
Figure 5-2. 80-Pin PN Low-Profile Quad Flatpack (Top View)
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GPIO6
GPIO10
GPIO9
GPIO5
VDDIO
VDD
VSS
GPIO7
GPIO22
GPIO41
GPIO23
GPIO40
GPIO0
GPIO1
GPIO2
GPIO3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
SPRSP61 – OCTOBER 2021
5
44
VDD
A6
6
43
VDDIO
B2,C6
7
42
GPIO19,X1
A3,B3,C5,VDAC
8
41
GPIO18,X2
A2,B6,C9
9
40
GPIO32
A15,B9,C7
10
39
GPIO35/TDI
A14,B14,C4
11
38
TMS
A11,B10,C0
12
37
GPIO37/TDO
A5,B12,C2
13
36
TCK
A1,B7,DACB_OUT
14
35
GPIO24
A0,B15,C15,DACA_OUT
15
34
GPIO17
VREFHI
16
33
GPIO16
A.
GPIO33
GPIO11
GPIO12
GPIO13
VDDIO
VDD
VSS
A10,B1,C10
A9,B4,C8
A4,B8,C14
VDDA
VSSA
A8,B0,C11
A7,C3
A12,C1
32
VSS
31
VSS
30
45
29
4
28
VDD
27
VREGENZ
26
46
25
3
24
XRSn
23
GPIO8
22
47
21
2
20
GPIO28
19
GPIO4
18
48
17
1
VREFLO
ADVANCE INFORMATION
GPIO29
Not to scale
Only the GPIO function is shown on GPIO pins. See Section 5.2 for the complete, muxed signal name.
Figure 5-3. 64-Pin PM Low-Profile Quad Flatpack - Q Temperature (Top View)
12
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GPIO10
GPIO9
GPIO5
VDDIO
VDD
VSS
GPIO7
GPIO22
GPIO41
GPIO23
GPIO40
GPIO0
GPIO1
GPIO2
GPIO3
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VSS
5
44
VDD
A6
6
43
VDDIO
B2,C6
7
42
GPIO19,X1
A3,B3,C5,VDAC
8
41
GPIO18,X2
A2,B6,C9
9
40
GPIO32
A15,B9,C7
10
39
GPIO35/TDI
A14,B14,C4
11
38
TMS
A11,B10,C0
12
37
GPIO37/TDO
A5,B12,C2
13
36
TCK
A1,B7,DACB_OUT
14
35
GPIO24
A0,B15,C15,DACA_OUT
15
34
GPIO17
VREFHI
16
33
GPIO16
GPIO33
GPIO11
GPIO12
GPIO13
VDDIO
VDD
VSS
A10,B1,C10
A9,B4,C8
A4,B8,C14
VDDA
VSSA
A8,B0,C11
A7,C3
A12,C1
VREFLO
A.
32
VSS
31
45
30
4
29
VDD
28
GPIO39
27
46
26
3
25
XRSn
24
GPIO8
23
47
22
2
21
GPIO28
20
GPIO4
19
48
18
1
17
GPIO29
ADVANCE INFORMATION
GPIO6
64
SPRSP61 – OCTOBER 2021
Not to scale
Only the GPIO function is shown on GPIO pins. See Section 5.2 for the complete, muxed signal name.
Figure 5-4. 64-Pin PM Low-Profile Quad Flatpack (Top View)
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GPIO6
GPIO5
VDDIO
VDD
VSS
GPIO7
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
VSS
48
47
46
45
44
43
42
41
40
39
38
37
SPRSP61 – OCTOBER 2021
A6,B2,C6
4
33
GPIO18,X2
A3,B3,C5,VDAC
5
32
GPIO32
A2,B6,C9
6
31
GPIO35/TDI
A15,B9,C7
7
30
TMS
A11,B10,C0
8
29
GPIO37/TDO
A5,B12,C2
9
28
TCK
A1,B7,DACB_OUT
10
27
GPIO24
A0,B15,C15,DACA_OUT
11
26
GPIO16
VREFHI
12
25
GPIO33
VDDIO
VDD
VSS
A10,B1,C10
A9,B4,C8
A4,B8,C14
VDDA
VSSA
A8,B0,C11
A7,C3
A12,C1
VREFLO
A.
24
GPIO19,X1
23
34
22
3
21
XRSn
20
VDDIO
19
35
18
2
17
GPIO28
16
VDD
15
36
14
1
13
ADVANCE INFORMATION
GPIO29
Not to scale
Only the GPIO function is shown on GPIO pins. See Section 5.2 for the complete, muxed signal name.
Figure 5-5. 48-Pin PT Low-Profile Quad Flatpack (Top View)
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SPRSP61 – OCTOBER 2021
5.2 Pin Attributes
Table 5-1. Pin Attributes
SIGNAL NAME
MUX
100 PZ 80 PN
POSITION
64 PM
64
PMQ
48 PT
PIN
TYPE
DESCRIPTION
A0
I
ADC-A Input 0
B15
I
ADC-B Input 15
C15
I
ADC-C Input 15
DACA_OUT
O
Buffered DAC-A Output.
I
CMPSS-3 High Comparator Positive Input 2
CMP3_HP2
23
19
15
15
11
CMP3_LP2
I
CMPSS-3 Low Comparator Positive Input 2
0, 4, 8, 12
I
Analog Pin Used For Digital Input 231
SD1_C1
2
I
SDFM-1 Channel 1 Clock Input
HIC_BASESEL1
15
I
HIC Base address range select 1
I
ADC-A Input 1
B7
I
ADC-B Input 7
DACB_OUT
O
Buffered DAC-B Output.
I
CMPSS-1 High Comparator Positive Input 4
I
CMPSS-1 Low Comparator Positive Input 4
0, 4, 8, 12
I
Analog Pin Used For Digital Input 232
SD1_D4
2
I
SDFM-1 Channel 4 Data Input
HIC_BASESEL0
15
I
HIC Base address range select 0
A10
I
ADC-A Input 10
B1
I
ADC-B Input 1
C10
I
ADC-C Input 10
CMP2_HP3
I
CMPSS-2 High Comparator Positive Input 3
CMP2_HN0
I
CMPSS-2 High Comparator Negative Input 0
I
CMPSS-2 Low Comparator Positive Input 3
I
CMPSS-2 Low Comparator Negative Input 0
AIO231
A1
CMP1_HP4
22
CMP1_LP4
AIO232
40
CMP2_LP3
18
29
14
25
14
25
10
21
CMP2_LN0
AIO230
0, 4, 8, 12
I
Analog Pin Used For Digital Input 230
SD1_C4
2
I
SDFM-1 Channel 4 Clock Input
HIC_BASESEL2
15
I
HIC Base address range select 2
A11
I
ADC-A Input 11
B10
I
ADC-B Input 10
C0
I
ADC-C Input 0
CMP1_HP1
I
CMPSS-1 High Comparator Positive Input 1
CMP1_HN1
I
CMPSS-1 High Comparator Negative Input 1
I
CMPSS-1 Low Comparator Positive Input 1
I
CMPSS-1 Low Comparator Negative Input 1
20
CMP1_LP1
CMP1_LN1
16
12
12
8
AIO237
0, 4, 8, 12
I
Analog Pin Used For Digital Input 237
SD1_D2
2
I
SDFM-1 Channel 2 Data Input
HIC_A6
15
I
HIC Address 6
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ANALOG
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SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
SIGNAL NAME
MUX
100 PZ 80 PN
POSITION
64 PM
64
PMQ
48 PT
PIN
TYPE
DESCRIPTION
A12
I
ADC-A Input 12
CMP2_HP1
I
CMPSS-2 High Comparator Positive Input 1
CMP2_HN1
I
CMPSS-2 High Comparator Negative Input 1
CMP2_LP1
I
CMPSS-2 Low Comparator Positive Input 1
I
CMPSS-2 Low Comparator Negative Input 1
28
CMP2_LN1
22
18
18
14
AIO238
0, 4, 8, 12
I
Analog Pin Used For Digital Input 238
SD2_C3
2
I
SDFM-2 Channel 3 Clock Input
HIC_NCS
15
ADVANCE INFORMATION
I
HIC Chip select input
A14
I
ADC-A Input 14
B14
I
ADC-B Input 14
C4
I
ADC-C Input 4
CMP3_HP4
I
CMPSS-3 High Comparator Positive Input 4
19
CMP3_LP4
15
11
11
I
CMPSS-3 Low Comparator Positive Input 4
AIO239
0, 4, 8, 12
I
Analog Pin Used For Digital Input 239
SD1_D1
2
I
SDFM-1 Channel 1 Data Input
HIC_A5
15
I
HIC Address 5
A2
I
ADC-A Input 2
B6
I
ADC-B Input 6
C9
I
ADC-C Input 9
I
CMPSS-1 High Comparator Positive Input 0
I
CMPSS-1 Low Comparator Positive Input 0
0, 4, 8, 12
I
Analog Pin Used For Digital Input 224
SD2_D3
2
I
SDFM-2 Channel 3 Data Input
HIC_A3
15
I
HIC Address 3
A3
I
ADC-A Input 3
CMP3_HP5
I
CMPSS-3 High Comparator Positive Input 5
I
CMPSS-3 Low Comparator Positive Input 5
CMP1_HP0
17
CMP1_LP0
AIO224
9
9
6
18
CMP3_LP5
AIO229
13
I
Analog Pin Used For Digital Input 229
A4
0, 4, 8, 12
I
ADC-A Input 4
B8
I
ADC-B Input 8
CMP2_HP0
I
CMPSS-2 High Comparator Positive Input 0
CMP2_LP0
I
CMPSS-2 Low Comparator Positive Input 0
AIO225
0, 4, 8, 12
36
27
23
23
19
I
Analog Pin Used For Digital Input 225
SD2_C2
2
I
SDFM-2 Channel 2 Clock Input
HIC_NWE
15
I
HIC Data Write enable from host
I
ADC-A Input 5
I
CMPSS-2 High Comparator Positive Input 5
I
CMPSS-2 Low Comparator Positive Input 5
I
Analog Pin Used For Digital Input 249
A6
I
ADC-A Input 6
CMP1_HP2
I
CMPSS-1 High Comparator Positive Input 2
I
CMPSS-1 Low Comparator Positive Input 2
I
Analog Pin Used For Digital Input 228
A5
CMP2_HP5
35
CMP2_LP5
AIO249
0, 4, 8, 12
CMP1_LP2
14
10
6
6
4
AIO228
0, 4, 8, 12
SD2_C1
2
I
SDFM-2 Channel 1 Clock Input
HIC_A0
15
I
HIC Address 0
16
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SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
64 PM
64
PMQ
48 PT
PIN
TYPE
DESCRIPTION
A8
I
ADC-A Input 8
CMP4_HP4
I
CMPSS-4 High Comparator Positive Input 4
I
CMPSS-4 Low Comparator Positive Input 4
I
Analog Pin Used For Digital Input 240
CMP4_LP4
37
AIO240
0, 4, 8, 12
SD2_C1
2
I
SDFM-2 Channel 1 Clock Input
HIC_NBE1
15
I
HIC Byte enable 1
A9
I
ADC-A Input 9
CMP2_HP2
I
CMPSS-2 High Comparator Positive Input 2
CMP2_LP2
I
CMPSS-2 Low Comparator Positive Input 2
I
Analog Pin Used For Digital Input 227
AIO227
0, 4, 8, 12
38
28
24
24
20
SD1_C3
2
I
SDFM-1 Channel 3 Clock Input
HIC_NBE0
15
I
HIC Byte enable 0
B0
I
ADC-B Input 0
C11
I
ADC-C Input 11
I
CMPSS-2 High Comparator Positive Input 4
I
CMPSS-2 Low Comparator Positive Input 4
I
Analog Pin Used For Digital Input 253
B11
I
ADC-B Input 11
CMP4_HP5
I
CMPSS-4 High Comparator Positive Input 5
I
CMPSS-4 Low Comparator Positive Input 5
I
Analog Pin Used For Digital Input 251
B11
I
ADC-B Input 11
CMP4_HP5
I
CMPSS-4 High Comparator Positive Input 5
CMP4_LP5
I
CMPSS-4 Low Comparator Positive Input 5
CMP2_HP4
41
CMP2_LP4
AIO253
0, 4, 8, 12
30
CMP4_LP5
AIO251
GPIO21 (See GPIO
Section)
0, 4, 8, 12
49
34
0, 4, 8, 12
I/O
General-Purpose Input Output 21. This pin
also has digital mux functions which are
described in the DIGITAL section of this table.
B2
I
ADC-B Input 2
C6
I
ADC-C Input 6
I
CMPSS-3 High Comparator Positive Input 0
I
CMPSS-3 Low Comparator Positive Input 0
CMP3_HP0
CMP3_LP0
15
11
7
7
4
AIO226
0, 4, 8, 12
I
Analog Pin Used For Digital Input 226
SD2_D4
2
I
SDFM-2 Channel 4 Data Input
HIC_A1
15
I
HIC Address 1
B3
I
ADC-B Input 3
VDAC
I
Optional external reference voltage for on-chip
DACs.
CMP3_HP3
I
CMPSS-3 High Comparator Positive Input 3
CMP3_HN0
I
CMPSS-3 High Comparator Negative Input 0
I
CMPSS-3 Low Comparator Positive Input 3
I
CMPSS-3 Low Comparator Negative Input 0
16
CMP3_LP3
CMP3_LN0
12
8
8
5
ADVANCE INFORMATION
SIGNAL NAME
MUX
100 PZ 80 PN
POSITION
AIO242
0, 4, 8, 12
I
Analog Pin Used For Digital Input 242
SD2_D2
2
I
SDFM-2 Channel 2 Data Input
HIC_A2
15
I
HIC Address 2
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SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
SIGNAL NAME
MUX
100 PZ 80 PN
POSITION
64 PM
64
PMQ
48 PT
PIN
TYPE
DESCRIPTION
B4
I
ADC-B Input 4
C8
I
ADC-C Input 8
I
CMPSS-4 High Comparator Positive Input 0
I
CMPSS-4 Low Comparator Positive Input 0
I
Analog Pin Used For Digital Input 236
B5
I
ADC-B Input 5
CMP1_HP5
I
CMPSS-1 High Comparator Positive Input 5
CMP4_HP0
39
28
24
24
20
CMP4_LP0
AIO236
0, 4, 8, 12
CMP1_LP5
ADVANCE INFORMATION
I
CMPSS-1 Low Comparator Positive Input 5
AIO252
0, 4, 8, 12
32
I
Analog Pin Used For Digital Input 252
SD2_C4
2
I
SDFM-2 Channel 4 Clock Input
B5
I
ADC-B Input 5
CMP1_HP5
I
CMPSS-1 High Comparator Positive Input 5
I
CMPSS-1 Low Comparator Positive Input 5
CMP1_LP5
GPIO20 (See GPIO
Section)
48
33
0, 4, 8, 12
I/O
C1
CMP4_HP2
29
CMP4_LP2
AIO248
22
18
18
14
0, 4, 8, 12
General-Purpose Input Output 20. This pin
also has digital mux functions which are
described in the DIGITAL section of this table.
I
ADC-C Input 1
I
CMPSS-4 High Comparator Positive Input 2
I
CMPSS-4 Low Comparator Positive Input 2
I
Analog Pin Used For Digital Input 248
C14
I
ADC-C Input 14
CMP4_HP3
I
CMPSS-4 High Comparator Positive Input 3
CMP4_HN0
I
CMPSS-4 High Comparator Negative Input 0
I
CMPSS-4 Low Comparator Positive Input 3
I
CMPSS-4 Low Comparator Negative Input 0
I
Analog Pin Used For Digital Input 247
C2
I
ADC-C Input 2
B12
I
ADC-B Input 12
CMP3_HP1
I
CMPSS-3 High Comparator Positive Input 1
I
CMPSS-3 High Comparator Negative Input 1
I
CMPSS-3 Low Comparator Positive Input 1
42
CMP4_LP3
CMP4_LN0
AIO247
0, 4, 8, 12
CMP3_HN1
CMP3_LP1
21
17
13
13
9
CMP3_LN1
I
CMPSS-3 Low Comparator Negative Input 1
AIO244
0, 4, 8, 12
I
Analog Pin Used For Digital Input 244
SD1_D3
2
I
SDFM-1 Channel 3 Data Input
HIC_A7
15
I
HIC Address 7
C3
I
ADC-C Input 3
A7
I
ADC-A Input 7
CMP4_HP1
I
CMPSS-4 High Comparator Positive Input 1
CMP4_HN1
I
CMPSS-4 High Comparator Negative Input 1
I
CMPSS-4 Low Comparator Positive Input 1
I
CMPSS-4 Low Comparator Negative Input 1
31
CMP4_LP1
23
19
19
15
CMP4_LN1
AIO245
0, 4, 8, 12
I
Analog Pin Used For Digital Input 245
SD1_C2
2
I
SDFM-1 Channel 2 Clock Input
HIC_NOE
15
O
HIC Output enable for data bus
I
ADC-C Input 5
C5
18
28
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8
8
5
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SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
C7
18
B9
14
64 PM
64
PMQ
48 PT
10
10
7
PIN
TYPE
DESCRIPTION
I
ADC-C Input 7
I
ADC-B Input 9
VREFHI
25
20
16
16
12
I
ADC High Reference. In external reference
mode, externally drive the high reference
voltage onto this pin. In internal reference
mode, a voltage is driven onto this pin by the
device. In either mode, place at least a 2.2-µF
capacitor on this pin. This capacitor should
be placed as close to the device as possible
between the VREFHI and VREFLO pins.
VREFLO
27
21
17
17
13
I
ADC Low Reference
A15
I
ADC-A Input 15
CMP1_HP3
I
CMPSS-1 High Comparator Positive Input 3
CMP1_HN0
I
CMPSS-1 High Comparator Negative Input 0
I
CMPSS-1 Low Comparator Positive Input 3
I
CMPSS-1 Low Comparator Negative Input 0
0, 4, 8, 12
I
Analog Pin Used For Digital Input 233
SD2_D1
2
I
SDFM-2 Channel 1 Data Input
HIC_A4
15
I
HIC Address 4
I
ADC-A Input 3
I
CMPSS-3 High Comparator Positive Input 5
CMP3_LP5
I
CMPSS-3 Low Comparator Positive Input 5
A5
I
ADC-A Input 5
I
CMPSS-2 High Comparator Positive Input 5
CMP2_LP5
I
CMPSS-2 Low Comparator Positive Input 5
A8
I
ADC-A Input 8
CMP4_HP4
I
CMPSS-4 High Comparator Positive Input 4
CMP4_LP4
I
CMPSS-4 Low Comparator Positive Input 4
I
Analog Pin Used For Digital Input 241
CMP1_LP3
14
CMP1_LN0
AIO233
10
10
7
A3
12
CMP3_HP5
CMP2_HP5
AIO241
17
24
0, 4, 8, 12
8
13
20
8
13
20
5
9
16
SD2_C1
2
I
SDFM-2 Channel 1 Clock Input
HIC_NBE1
15
I
HIC Byte enable 1
B0
I
ADC-B Input 0
C11
I
ADC-C Input 11
24
CMP2_HP4
20
20
16
I
CMPSS-2 High Comparator Positive Input 4
CMP2_LP4
I
CMPSS-2 Low Comparator Positive Input 4
C14
I
ADC-C Input 14
I
CMPSS-4 High Comparator Positive Input 3
I
CMPSS-4 High Comparator Negative Input 0
CMP4_LP3
I
CMPSS-4 Low Comparator Positive Input 3
CMP4_LN0
I
CMPSS-4 Low Comparator Negative Input 0
CMP4_HP3
CMP4_HN0
27
23
23
19
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ADVANCE INFORMATION
SIGNAL NAME
MUX
100 PZ 80 PN
POSITION
19
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SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
SIGNAL NAME
MUX
100 PZ 80 PN
POSITION
64 PM
64
PMQ
48 PT
PIN
TYPE
DESCRIPTION
GPIO
GPIO0
0, 4, 8, 12
I/O
General-Purpose Input Output 0
ePWM-1 Output A
EPWM1_A
1
O
I2CA_SDA
6
I/OD
I2C-A Open-Drain Bidirectional Data
SPIA_STE
7
I/O
SPI-A Slave Transmit Enable (STE)
FSIRXA_CLK
9
MCAN_RX
10
79
63
52
52
42
I
FSIRX-A Input Clock
I
CAN/CAN FD Receive
ADVANCE INFORMATION
CLB_OUTPUTXBAR8
11
O
CLB Output X-BAR Output 8
EQEP1_INDEX
13
I/O
eQEP-1 Index
HIC_D7
14
I/O
HIC Data 7
HIC_BASESEL1
GPIO1
15
I
HIC Base address range select 1
0, 4, 8, 12
I/O
General-Purpose Input Output 1
ePWM-1 Output B
EPWM1_B
1
O
I2CA_SCL
6
I/OD
SPIA_SOMI
7
I/O
SPI-A Slave Out, Master In (SOMI)
MCAN_TX
10
O
CAN/CAN FD Transmit
CLB_OUTPUTXBAR7
11
O
CLB Output X-BAR Output 7
HIC_A2
13
I
HIC Address 2
FSITXA_TDM_D1
14
I
FSITX-A Time Division Multiplexed Additional
Data Input
HIC_D10
78
62
51
51
41
I2C-A Open-Drain Bidirectional Clock
15
I/O
HIC Data 10
0, 4, 8, 12
I/O
General-Purpose Input Output 2
EPWM2_A
1
O
ePWM-2 Output A
OUTPUTXBAR1
5
O
Output X-BAR Output 1
PMBUSA_SDA
6
I/OD
SPIA_SIMO
7
I/O
SPI-A Slave In, Master Out (SIMO)
SCIA_TX
9
O
SCI-A Transmit Data
FSIRXA_D1
10
I
FSIRX-A Optional Additional Data Input
I2CB_SDA
11
I/OD
HIC_A1
13
I
HIC Address 1
CANA_TX
14
O
CAN-A Transmit
HIC_D9
15
I/O
HIC Data 9
GPIO3
0, 4, 8, 12
I/O
General-Purpose Input Output 3
1
O
ePWM-2 Output B
Output X-BAR Output 2
GPIO2
EPWM2_B
OUTPUTXBAR2
77
61
50
50
40
2, 5
O
PMBUSA_SCL
6
I/OD
SPIA_CLK
7
SCIA_RX
9
FSIRXA_D0
I/O
49
49
39
PMBus-A Open-Drain Bidirectional Clock
SPI-A Clock
SCI-A Receive Data
10
I
FSIRX-A Primary Data Input
I2CB_SCL
11
I/OD
HIC_NOE
13
O
HIC Output enable for data bus
CANA_RX
14
I
CAN-A Receive
HIC_D4
15
I/O
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60
I2C-B Open-Drain Bidirectional Data
I
20
76
PMBus-A Open-Drain Bidirectional Data
I2C-B Open-Drain Bidirectional Clock
HIC Data 4
Copyright © 2021 Texas Instruments Incorporated
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SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
GPIO4
64 PM
64
PMQ
48 PT
PIN
TYPE
DESCRIPTION
0, 4, 8, 12
I/O
General-Purpose Input Output 4
EPWM3_A
1
O
ePWM-3 Output A
MCAN_TX
3
O
CAN/CAN FD Transmit
OUTPUTXBAR3
5
O
Output X-BAR Output 3
CANA_TX
6
O
CAN-A Transmit
SPIB_CLK
7
I/O
SPI-B Clock
EQEP2_STROBE
9
I/O
eQEP-2 Strobe
FSIRXA_CLK
10
I
FSIRX-A Input Clock
CLB_OUTPUTXBAR6
11
O
CLB Output X-BAR Output 6
HIC_BASESEL2
13
I
HIC Base address range select 2
HIC_NWE
75
59
48
48
38
15
I
HIC Data Write enable from host
0, 4, 8, 12
I/O
General-Purpose Input Output 5
EPWM3_B
1
O
ePWM-3 Output B
OUTPUTXBAR3
3
O
Output X-BAR Output 3
MCAN_RX
5
I
CAN/CAN FD Receive
CANA_RX
6
I
CAN-A Receive
SPIA_STE
7
GPIO5
89
74
61
61
47
I/O
SPI-A Slave Transmit Enable (STE)
FSITXA_D1
9
O
FSITX-A Optional Additional Data Output
CLB_OUTPUTXBAR5
10
O
CLB Output X-BAR Output 5
HIC_A7
13
I
HIC Address 7
HIC_D4
14
I/O
HIC Data 4
HIC_D15
15
I/O
HIC Data 15
GPIO6
0, 4, 8, 12
I/O
General-Purpose Input Output 6
EPWM4_A
1
O
ePWM-4 Output A
OUTPUTXBAR4
2
O
Output X-BAR Output 4
SYNCOUT
3
O
External ePWM Synchronization Pulse
EQEP1_A
5
I
eQEP-1 Input A
SPIB_SOMI
7
I/O
SPI-B Slave Out, Master In (SOMI)
FSITXA_D0
9
O
FSITX-A Primary Data Output
FSITXA_D1
11
O
FSITX-A Optional Additional Data Output
HIC_NBE1
13
I
HIC Byte enable 1
CLB_OUTPUTXBAR8
14
O
CLB Output X-BAR Output 8
HIC_D14
97
80
64
64
48
15
I/O
HIC Data 14
0, 4, 8, 12
I/O
General-Purpose Input Output 7
EPWM4_B
1
O
ePWM-4 Output B
OUTPUTXBAR5
3
O
Output X-BAR Output 5
EQEP1_B
5
I
eQEP-1 Input B
SPIB_SIMO
7
I/O
SPI-B Slave In, Master Out (SIMO)
FSITXA_CLK
9
O
FSITX-A Output Clock
CLB_OUTPUTXBAR2
10
O
CLB Output X-BAR Output 2
HIC_A6
13
I
HIC Address 6
HIC_D14
15
I/O
GPIO7
84
68
57
57
43
ADVANCE INFORMATION
SIGNAL NAME
MUX
100 PZ 80 PN
POSITION
HIC Data 14
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SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
SIGNAL NAME
GPIO8
MUX
100 PZ 80 PN
POSITION
64 PM
64
PMQ
48 PT
PIN
TYPE
DESCRIPTION
ADVANCE INFORMATION
0, 4, 8, 12
I/O
General-Purpose Input Output 8
EPWM5_A
1
O
ePWM-5 Output A
ADCSOCAO
3
O
ADC Start of Conversion A for External ADC
EQEP1_STROBE
5
I/O
eQEP-1 Strobe
SCIA_TX
6
O
SCI-A Transmit Data
SPIA_SIMO
7
I/O
SPI-A Slave In, Master Out (SIMO)
I2CA_SCL
9
FSITXA_D1
10
O
FSITX-A Optional Additional Data Output
CLB_OUTPUTXBAR5
11
O
CLB Output X-BAR Output 5
HIC_A0
13
I
HIC Address 0
FSITXA_TDM_CLK
14
I
FSITX-A Time Division Multiplexed Clock Input
HIC_D8
15
I/O
HIC Data 8
GPIO9
74
58
47
47
I/OD
I2C-A Open-Drain Bidirectional Clock
0, 4, 8, 12
I/O
General-Purpose Input Output 9
EPWM5_B
1
O
ePWM-5 Output B
SCIB_TX
2
O
SCI-B Transmit Data
OUTPUTXBAR6
3
O
Output X-BAR Output 6
EQEP1_INDEX
5
I/O
eQEP-1 Index
SCIA_RX
6
SPIA_CLK
7
FSITXA_D0
90
75
62
62
I
SCI-A Receive Data
I/O
SPI-A Clock
10
O
FSITX-A Primary Data Output
LINB_RX
11
I
LIN-B Receive
HIC_BASESEL0
13
I
HIC Base address range select 0
I2CB_SCL
14
I/OD
HIC_NRDY
15
O
HIC Ready from device to host
GPIO10
I2C-B Open-Drain Bidirectional Clock
0, 4, 8, 12
I/O
General-Purpose Input Output 10
EPWM6_A
1
O
ePWM-6 Output A
ADCSOCBO
3
O
ADC Start of Conversion B for External ADC
EQEP1_A
5
I
eQEP-1 Input A
SCIB_TX
6
O
SCI-B Transmit Data
SPIA_SOMI
7
I/O
SPI-A Slave Out, Master In (SOMI)
I2CA_SDA
9
FSITXA_CLK
10
O
FSITX-A Output Clock
LINB_TX
11
O
LIN-B Transmit
HIC_NWE
13
I
HIC Data Write enable from host
FSITXA_TDM_D0
14
I
FSITX-A Time Division Multiplexed Data Input
CLB_OUTPUTXBAR4
15
O
CLB Output X-BAR Output 4
22
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93
76
63
63
I/OD
I2C-A Open-Drain Bidirectional Data
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SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
GPIO11
64 PM
64
PMQ
48 PT
PIN
TYPE
DESCRIPTION
0, 4, 8, 12
I/O
General-Purpose Input Output 11
EPWM6_B
1
O
ePWM-6 Output B
OUTPUTXBAR7
3
O
Output X-BAR Output 7
EQEP1_B
5
I
eQEP-1 Input B
SCIB_RX
6
I
SCI-B Receive Data
SPIA_STE
7
FSIRXA_D1
9
LINB_RX
EQEP2_A
52
37
31
31
I/O
SPI-A Slave Transmit Enable (STE)
I
FSIRX-A Optional Additional Data Input
10
I
LIN-B Receive
11
I
eQEP-2 Input A
SPIA_SIMO
13
I/O
SPI-A Slave In, Master Out (SIMO)
HIC_D6
14
I/O
HIC Data 6
HIC_NBE0
15
I
GPIO12
HIC Byte enable 0
0, 4, 8, 12
I/O
General-Purpose Input Output 12
EPWM7_A
1
O
ePWM-7 Output A
MCAN_RX
3
I
CAN/CAN FD Receive
EQEP1_STROBE
5
I/O
eQEP-1 Strobe
SCIB_TX
6
O
SCI-B Transmit Data
PMBUSA_CTL
7
I/O
PMBus-A Control Signal - Slave Input/Master
Output
FSIRXA_D0
9
LINB_TX
SPIA_CLK
CANA_RX
13
I
HIC_D13
14
I/O
HIC Data 13
HIC_INT
15
O
HIC Device interrupt to host
GPIO13
51
36
30
30
I
FSIRX-A Primary Data Input
10
O
LIN-B Transmit
11
I/O
SPI-A Clock
CAN-A Receive
0, 4, 8, 12
I/O
General-Purpose Input Output 13
EPWM7_B
1
O
ePWM-7 Output B
MCAN_TX
3
O
CAN/CAN FD Transmit
EQEP1_INDEX
5
I/O
eQEP-1 Index
SCIB_RX
6
I
PMBUSA_ALERT
7
I/OD
FSIRXA_CLK
9
LINB_RX
SPIA_SOMI
CANA_TX
HIC_D11
HIC_D5
50
35
29
29
ADVANCE INFORMATION
SIGNAL NAME
MUX
100 PZ 80 PN
POSITION
SCI-B Receive Data
PMBus-A Open-Drain Bidirectional Alert Signal
I
FSIRX-A Input Clock
10
I
LIN-B Receive
11
I/O
SPI-A Slave Out, Master In (SOMI)
13
O
CAN-A Transmit
14
I/O
HIC Data 11
15
I/O
HIC Data 5
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SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
SIGNAL NAME
GPIO14
MUX
100 PZ 80 PN
POSITION
64 PM
64
PMQ
48 PT
PIN
TYPE
DESCRIPTION
ADVANCE INFORMATION
0, 4, 8, 12
I/O
General-Purpose Input Output 14
EPWM8_A
1
O
ePWM-8 Output A
SCIB_TX
2
O
SCI-B Transmit Data
I2CB_SDA
5
I/OD
OUTPUTXBAR3
6
O
PMBUSA_SDA
7
SPIB_CLK
9
EQEP2_A
10
I
eQEP-2 Input A
LINB_TX
11
O
LIN-B Transmit
EPWM3_A
13
O
ePWM-3 Output A
CLB_OUTPUTXBAR7
14
O
CLB Output X-BAR Output 7
HIC_D15
15
I/O
HIC Data 15
GPIO15
96
I/OD
79
I/O
I2C-B Open-Drain Bidirectional Data
Output X-BAR Output 3
PMBus-A Open-Drain Bidirectional Data
SPI-B Clock
0, 4, 8, 12
I/O
General-Purpose Input Output 15
EPWM8_B
1
O
ePWM-8 Output B
SCIB_RX
2
I
SCI-B Receive Data
I2CB_SCL
5
I/OD
OUTPUTXBAR4
6
O
PMBUSA_SCL
7
SPIB_STE
9
EQEP2_B
10
95
I/OD
78
I/O
I2C-B Open-Drain Bidirectional Clock
Output X-BAR Output 4
PMBus-A Open-Drain Bidirectional Clock
SPI-B Slave Transmit Enable (STE)
I
eQEP-2 Input B
LINB_RX
11
I
LIN-B Receive
EPWM3_B
13
O
ePWM-3 Output B
CLB_OUTPUTXBAR6
14
O
CLB Output X-BAR Output 6
HIC_D12
15
I/O
HIC Data 12
GPIO16
0, 4, 8, 12
I/O
General-Purpose Input Output 16
SPIA_SIMO
1
I/O
SPI-A Slave In, Master Out (SIMO)
OUTPUTXBAR7
3
O
Output X-BAR Output 7
EPWM5_A
5
O
ePWM-5 Output A
SCIA_TX
6
O
SCI-A Transmit Data
SD1_D1
7
I
SDFM-1 Channel 1 Data Input
EQEP1_STROBE
9
I/O
PMBUSA_SCL
10
I/OD
XCLKOUT
11
O
External Clock Output. This pin outputs a
divided-down version of a chosen clock signal
from within the device.
EQEP2_B
13
I
eQEP-2 Input B
SPIB_SOMI
14
I/O
SPI-B Slave Out, Master In (SOMI)
HIC_D1
15
I/O
HIC Data 1
24
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54
39
33
33
26
eQEP-1 Strobe
PMBus-A Open-Drain Bidirectional Clock
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SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
GPIO17
64 PM
64
PMQ
48 PT
PIN
TYPE
DESCRIPTION
0, 4, 8, 12
I/O
General-Purpose Input Output 17
SPIA_SOMI
1
I/O
SPI-A Slave Out, Master In (SOMI)
OUTPUTXBAR8
3
O
Output X-BAR Output 8
EPWM5_B
5
O
ePWM-5 Output B
SCIA_RX
6
I
SCI-A Receive Data
SD1_C1
7
I
SDFM-1 Channel 1 Clock Input
EQEP1_INDEX
9
I/O
PMBUSA_SDA
10
I/OD
CANA_TX
11
O
CAN-A Transmit
HIC_D2
15
I/O
HIC Data 2
GPIO18
55
40
34
34
eQEP-1 Index
PMBus-A Open-Drain Bidirectional Data
0, 4, 8, 12
I/O
General-Purpose Input Output 18
SPIA_CLK
1
I/O
SPI-A Clock
SCIB_TX
2
O
SCI-B Transmit Data
CANA_RX
3
I
CAN-A Receive
EPWM6_A
5
O
ePWM-6 Output A
I2CA_SCL
6
I/OD
SD1_D2
7
I
SDFM-1 Channel 2 Data Input
EQEP2_A
9
I
eQEP-2 Input A
PMBUSA_CTL
10
I/O
PMBus-A Control Signal - Slave Input/Master
Output
XCLKOUT
11
O
External Clock Output. This pin outputs a
divided-down version of a chosen clock signal
from within the device.
LINB_TX
13
O
LIN-B Transmit
FSITXA_TDM_CLK
14
I
FSITX-A Time Division Multiplexed Clock Input
HIC_INT
X2
GPIO19
68
50
41
41
33
I2C-A Open-Drain Bidirectional Clock
15
O
HIC Device interrupt to host
ALT
I/O
Crystal oscillator output.
0, 4, 8, 12
I/O
General-Purpose Input Output 19
SPIA_STE
1
I/O
SPI-A Slave Transmit Enable (STE)
SCIB_RX
2
I
SCI-B Receive Data
CANA_TX
3
O
CAN-A Transmit
EPWM6_B
5
O
ePWM-6 Output B
I2CA_SDA
6
I/OD
SD1_C2
7
I
SDFM-1 Channel 2 Clock Input
eQEP-2 Input B
EQEP2_B
9
I
PMBUSA_ALERT
10
I/OD
CLB_OUTPUTXBAR1
11
LINB_RX
FSITXA_TDM_D0
HIC_NBE0
X1
69
51
42
42
34
I2C-A Open-Drain Bidirectional Data
PMBus-A Open-Drain Bidirectional Alert Signal
O
CLB Output X-BAR Output 1
13
I
LIN-B Receive
14
I
FSITX-A Time Division Multiplexed Data Input
15
I
HIC Byte enable 0
ALT
I/O
ADVANCE INFORMATION
SIGNAL NAME
MUX
100 PZ 80 PN
POSITION
Crystal oscillator input or single-ended clock
input. The device initialization software must
configure this pin before the crystal oscillator is
enabled. To use this oscillator, a quartz crystal
circuit must be connected to X1 and X2. This
pin can also be used to feed a single-ended
3.3-V level clock. See the XTAL section for
usage details.
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SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
SIGNAL NAME
GPIO20 (See ANALOG
Section)
MUX
100 PZ 80 PN
POSITION
64 PM
64
PMQ
0, 4, 8, 12
48 PT
PIN
TYPE
DESCRIPTION
I/O
General-Purpose Input Output 20. This pin
also has analog functions which are described
in the ANALOG section of this table.
EQEP1_A
1
SPIB_SIMO
6
SD1_D3
7
I
SDFM-1 Channel 3 Data Input
MCAN_TX
9
O
CAN/CAN FD Transmit
0, 4, 8, 12
I/O
General-Purpose Input Output 21. This pin
also has analog functions which are described
in the ANALOG section of this table.
GPIO21 (See ANALOG
Section)
48
I
33
I/O
SPI-B Slave In, Master Out (SIMO)
ADVANCE INFORMATION
EQEP1_B
1
SPIB_SOMI
6
I/O
SD1_C3
7
I
SDFM-1 Channel 3 Clock Input
MCAN_RX
9
I
CAN/CAN FD Receive
GPIO22
49
I
eQEP-1 Input A
34
eQEP-1 Input B
SPI-B Slave Out, Master In (SOMI)
0, 4, 8, 12
I/O
General-Purpose Input Output 22
EQEP1_STROBE
1
I/O
eQEP-1 Strobe
SCIB_TX
3
O
SCI-B Transmit Data
SPIB_CLK
6
I/O
SPI-B Clock
SD1_D4
7
I
SDFM-1 Channel 4 Data Input
83
67
56
56
LINA_TX
9
O
LIN-A Transmit
CLB_OUTPUTXBAR1
10
O
CLB Output X-BAR Output 1
LINB_TX
11
O
LIN-B Transmit
HIC_A5
13
I
HIC Address 5
EPWM4_A
14
O
ePWM-4 Output A
HIC_D13
15
I/O
HIC Data 13
GPIO23
0, 4, 8, 12
I/O
General-Purpose Input Output 23
EQEP1_INDEX
1
I/O
eQEP-1 Index
SCIB_RX
3
I
SPIB_STE
6
I/O
SD1_C4
7
LINA_RX
9
CLB_OUTPUTXBAR3
SCI-B Receive Data
SPI-B Slave Transmit Enable (STE)
I
SDFM-1 Channel 4 Clock Input
I
LIN-A Receive
10
O
CLB Output X-BAR Output 3
LINB_RX
11
I
LIN-B Receive
HIC_A3
13
I
HIC Address 3
EPWM4_B
14
O
ePWM-4 Output B
HIC_D11
15
I/O
HIC Data 11
26
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81
65
54
54
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TMS320F280039C, TMS320F280037C
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SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
GPIO24
64 PM
64
PMQ
48 PT
PIN
TYPE
DESCRIPTION
0, 4, 8, 12
I/O
General-Purpose Input Output 24
OUTPUTXBAR1
1
O
Output X-BAR Output 1
EQEP2_A
2
I
eQEP-2 Input A
EPWM8_A
5
O
ePWM-8 Output A
SPIB_SIMO
6
I/O
SPI-B Slave In, Master Out (SIMO)
SD2_D1
7
LINB_TX
9
PMBUSA_SCL
10
I/OD
SCIA_TX
11
O
SCI-A Transmit Data
ERRORSTS
13
O
Error Status Output. This signal requires an
external pulldown.
HIC_D3
15
I/O
HIC Data 3
GPIO25
56
41
35
35
27
I
SDFM-2 Channel 1 Data Input
O
LIN-B Transmit
PMBus-A Open-Drain Bidirectional Clock
0, 4, 8, 12
I/O
General-Purpose Input Output 25
OUTPUTXBAR2
1
O
Output X-BAR Output 2
EQEP2_B
2
I
eQEP-2 Input B
EQEP1_A
5
I
eQEP-1 Input A
SPIB_SOMI
6
I/O
SD2_C1
7
I
SDFM-2 Channel 1 Clock Input
FSITXA_D1
9
O
FSITX-A Optional Additional Data Output
PMBUSA_SDA
10
I/OD
PMBus-A Open-Drain Bidirectional Data
SCIA_RX
11
I
SCI-A Receive Data
HIC_BASESEL0
14
I
HIC Base address range select 0
GPIO26
57
42
SPI-B Slave Out, Master In (SOMI)
0, 4, 8, 12
I/O
General-Purpose Input Output 26
OUTPUTXBAR3
1, 5
O
Output X-BAR Output 3
EQEP2_INDEX
2
I/O
eQEP-2 Index
SPIB_CLK
6
I/O
SPI-B Clock
SD2_D2
7
I
SDFM-2 Channel 2 Data Input
O
FSITX-A Primary Data Output
PMBus-A Control Signal - Slave Input/Master
Output
58
43
FSITXA_D0
9
PMBUSA_CTL
10
I/O
I2CA_SDA
11
I/OD
HIC_D0
14
I/O
I2C-A Open-Drain Bidirectional Data
HIC Data 0
HIC_A1
15
I
GPIO27
0, 4, 8, 12
I/O
General-Purpose Input Output 27
OUTPUTXBAR4
HIC Address 1
1, 5
O
Output X-BAR Output 4
EQEP2_STROBE
2
I/O
eQEP-2 Strobe
SPIB_STE
6
I/O
SPI-B Slave Transmit Enable (STE)
SD2_C2
7
FSITXA_CLK
9
PMBUSA_ALERT
10
I/OD
PMBus-A Open-Drain Bidirectional Alert Signal
I2CA_SCL
11
I/OD
I2C-A Open-Drain Bidirectional Clock
HIC_D1
14
I/O
HIC_A4
15
I
59
44
ADVANCE INFORMATION
SIGNAL NAME
MUX
100 PZ 80 PN
POSITION
I
SDFM-2 Channel 2 Clock Input
O
FSITX-A Output Clock
HIC Data 1
HIC Address 4
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SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
SIGNAL NAME
GPIO28
MUX
100 PZ 80 PN
POSITION
64 PM
64
PMQ
48 PT
PIN
TYPE
DESCRIPTION
0, 4, 8, 12
I/O
SCIA_RX
1
I
SCI-A Receive Data
EPWM7_A
3
O
ePWM-7 Output A
OUTPUTXBAR5
5
O
Output X-BAR Output 5
EQEP1_A
6
I
eQEP-1 Input A
SD2_D3
7
I
SDFM-2 Channel 3 Data Input
EQEP2_STROBE
9
LINA_TX
SPIB_CLK
1
4
2
2
2
General-Purpose Input Output 28
ADVANCE INFORMATION
I/O
eQEP-2 Strobe
10
O
LIN-A Transmit
11
I/O
SPI-B Clock
ERRORSTS
13
O
Error Status Output. This signal requires an
external pulldown.
I2CB_SDA
14
I/OD
HIC_NOE
I2C-B Open-Drain Bidirectional Data
15
O
HIC Output enable for data bus
GPIO29
0, 4, 8, 12
I/O
General-Purpose Input Output 29
SCIA_TX
1
O
SCI-A Transmit Data
EPWM7_B
3
O
ePWM-7 Output B
OUTPUTXBAR6
5
O
Output X-BAR Output 6
EQEP1_B
6
I
eQEP-1 Input B
SD2_C3
7
I
SDFM-2 Channel 3 Clock Input
EQEP2_INDEX
9
I/O
eQEP-2 Index
LINA_RX
10
I
LIN-A Receive
SPIB_STE
11
I/O
SPI-B Slave Transmit Enable (STE)
ERRORSTS
13
O
Error Status Output. This signal requires an
external pulldown.
I2CB_SCL
14
I/OD
15
I
HIC_NCS
AUXCLKIN
GPIO30
100
3
1
1
1
I2C-B Open-Drain Bidirectional Clock
HIC Chip select input
ALT
0, 4, 8, 12
I/O
CANA_RX
1
I
SPIB_SIMO
3
I/O
SPI-B Slave In, Master Out (SIMO)
OUTPUTXBAR7
5
O
Output X-BAR Output 7
EQEP1_STROBE
6
I/O
eQEP-1 Strobe
SD2_D4
7
FSIRXA_CLK
9
MCAN_RX
EPWM1_A
HIC_D8
28
98
1
General-Purpose Input Output 30
CAN-A Receive
I
SDFM-2 Channel 4 Data Input
I
FSIRX-A Input Clock
10
I
CAN/CAN FD Receive
11
O
ePWM-1 Output A
14
I/O
HIC Data 8
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SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
GPIO31
64 PM
64
PMQ
48 PT
PIN
TYPE
DESCRIPTION
0, 4, 8, 12
I/O
General-Purpose Input Output 31
CANA_TX
1
O
CAN-A Transmit
SPIB_SOMI
3
I/O
SPI-B Slave Out, Master In (SOMI)
OUTPUTXBAR8
5
O
Output X-BAR Output 8
EQEP1_INDEX
6
I/O
eQEP-1 Index
SD2_C4
7
I
SDFM-2 Channel 4 Clock Input
FSIRXA_D1
9
I
FSIRX-A Optional Additional Data Input
MCAN_TX
10
O
CAN/CAN FD Transmit
EPWM1_B
11
O
ePWM-1 Output B
HIC_D10
14
I/O
HIC Data 10
GPIO32
General-Purpose Input Output 32
99
2
0, 4, 8, 12
I/O
I2CA_SDA
1
I/OD
SPIB_CLK
3
I/O
SPI-B Clock
EPWM8_B
5
O
ePWM-8 Output B
LINA_TX
6
O
LIN-A Transmit
SD1_D2
7
I
SDFM-1 Channel 2 Data Input
FSIRXA_D0
9
I
FSIRX-A Primary Data Input
CANA_TX
10
O
CAN-A Transmit
PMBUSA_SDA
11
I/OD
ADCSOCBO
13
O
ADC Start of Conversion B for External ADC
64
49
40
40
32
I2C-A Open-Drain Bidirectional Data
PMBus-A Open-Drain Bidirectional Data
HIC_INT
15
O
HIC Device interrupt to host
GPIO33
0, 4, 8, 12
I/O
General-Purpose Input Output 33
I2CA_SCL
1
I/OD
SPIB_STE
3
I/O
SPI-B Slave Transmit Enable (STE)
OUTPUTXBAR4
5
O
Output X-BAR Output 4
LINA_RX
6
I
LIN-A Receive
SD1_C2
7
I
SDFM-1 Channel 2 Clock Input
I
FSIRX-A Input Clock
I
CAN-A Receive
FSIRXA_CLK
9
CANA_RX
10
53
38
32
32
25
I2C-A Open-Drain Bidirectional Clock
EQEP2_B
11
I
eQEP-2 Input B
ADCSOCAO
13
O
ADC Start of Conversion A for External ADC
SD1_C1
14
I
SDFM-1 Channel 1 Clock Input
HIC_D0
15
I/O
HIC Data 0
GPIO34
0, 4, 8, 12
I/O
General-Purpose Input Output 34
Output X-BAR Output 1
OUTPUTXBAR1
1
O
PMBUSA_SDA
6
I/OD
HIC_NBE1
13
I2CB_SDA
14
I/OD
HIC_D9
15
I/O
94
77
I
ADVANCE INFORMATION
SIGNAL NAME
MUX
100 PZ 80 PN
POSITION
PMBus-A Open-Drain Bidirectional Data
HIC Byte enable 1
I2C-B Open-Drain Bidirectional Data
HIC Data 9
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SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
SIGNAL NAME
GPIO35
MUX
100 PZ 80 PN
POSITION
64 PM
64
PMQ
48 PT
PIN
TYPE
DESCRIPTION
0, 4, 8, 12
I/O
SCIA_RX
1
I
General-Purpose Input Output 35
I2CA_SDA
3
I/OD
CANA_RX
5
I
PMBUSA_SCL
6
I/OD
LINA_RX
7
I
LIN-A Receive
EQEP1_A
9
I
eQEP-1 Input A
PMBUSA_CTL
10
EPWM5_B
SCI-A Receive Data
I2C-A Open-Drain Bidirectional Data
CAN-A Receive
PMBus-A Open-Drain Bidirectional Clock
ADVANCE INFORMATION
I/O
PMBus-A Control Signal - Slave Input/Master
Output
11
O
ePWM-5 Output B
SD2_C1
13
I
SDFM-2 Channel 1 Clock Input
HIC_NWE
14
I
HIC Data Write enable from host
15
I
JTAG Test Data Input (TDI) - TDI is the default
mux selection for the pin. The internal pullup is
disabled by default. The internal pullup should
be enabled or an external pullup added on the
board if this pin is used as JTAG TDI to avoid a
floating input.
TDI
GPIO37
63
48
39
39
31
0, 4, 8, 12
I/O
General-Purpose Input Output 37
OUTPUTXBAR2
1
O
Output X-BAR Output 2
I2CA_SCL
3
I/OD
SCIA_TX
5
O
SCI-A Transmit Data
CANA_TX
6
O
CAN-A Transmit
LINA_TX
7
O
LIN-A Transmit
EQEP1_B
9
I
eQEP-1 Input B
PMBUSA_ALERT
10
HIC_NRDY
14
TDO
GPIO39
61
46
37
37
29
I/OD
I2C-A Open-Drain Bidirectional Clock
PMBus-A Open-Drain Bidirectional Alert Signal
O
HIC Ready from device to host
15
O
JTAG Test Data Output (TDO) - TDO is the
default mux selection for the pin. The internal
pullup is disabled by default. The TDO function
will tristate when there is no JTAG activity,
leaving this pin floating; the internal pullup
should be enabled or an external pullup added
on the board to avoid a floating GPIO input.
General-Purpose Input Output 39
0, 4, 8, 12
I/O
MCAN_RX
6
I
CAN/CAN FD Receive
FSIRXA_CLK
7
I
FSIRX-A Input Clock
EQEP2_INDEX
9
CLB_OUTPUTXBAR2
11
SYNCOUT
EQEP1_INDEX
HIC_D7
30
I/O
eQEP-2 Index
O
CLB Output X-BAR Output 2
13
O
External ePWM Synchronization Pulse
14
I/O
eQEP-1 Index
15
I/O
HIC Data 7
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SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
GPIO40
64 PM
64
PMQ
48 PT
PIN
TYPE
DESCRIPTION
0, 4, 8, 12
I/O
General-Purpose Input Output 40
SPIB_SIMO
1
I/O
SPI-B Slave In, Master Out (SIMO)
EPWM2_B
5
O
ePWM-2 Output B
PMBUSA_SDA
6
I/OD
FSIRXA_D0
7
I
FSIRX-A Primary Data Input
80
64
53
53
PMBus-A Open-Drain Bidirectional Data
SCIB_TX
9
O
SCI-B Transmit Data
EQEP1_A
10
I
eQEP-1 Input A
LINB_TX
11
O
LIN-B Transmit
HIC_NBE1
14
I
HIC Byte enable 1
HIC_D5
15
I/O
HIC Data 5
GPIO41
0, 4, 8, 12
I/O
General-Purpose Input Output 41
EPWM2_A
5
O
ePWM-2 Output A
PMBUSA_SCL
6
I/OD
FSIRXA_D1
7
I
FSIRX-A Optional Additional Data Input
SCIB_RX
9
I
SCI-B Receive Data
EQEP1_B
10
I
eQEP-1 Input B
LINB_RX
11
I
LIN-B Receive
HIC_A4
13
I
HIC Address 4
SPIB_SOMI
14
I/O
SPI-B Slave Out, Master In (SOMI)
HIC_D12
15
I/O
HIC Data 12
GPIO42
0, 4, 8, 12
I/O
General-Purpose Input Output 42
LINA_RX
2
I
LIN-A Receive
OUTPUTXBAR5
3
O
Output X-BAR Output 5
PMBUSA_CTL
5
I/O
PMBus-A Control Signal - Slave Input/Master
Output
I2CA_SDA
6
EQEP1_STROBE
10
82
66
57
55
55
I/OD
PMBus-A Open-Drain Bidirectional Clock
I2C-A Open-Drain Bidirectional Data
I/O
eQEP-1 Strobe
CLB_OUTPUTXBAR3
11
O
CLB Output X-BAR Output 3
HIC_D2
14
I/O
HIC Data 2
HIC_A6
15
I
GPIO43
0, 4, 8, 12
I/O
General-Purpose Input Output 43
OUTPUTXBAR6
3
O
Output X-BAR Output 6
PMBUSA_ALERT
HIC Address 6
5, 9
I/OD
PMBus-A Open-Drain Bidirectional Alert Signal
I2CA_SCL
6
I/OD
I2C-A Open-Drain Bidirectional Clock
EQEP1_INDEX
10
I/O
eQEP-1 Index
CLB_OUTPUTXBAR4
11
O
CLB Output X-BAR Output 4
SD2_D3
13
I
SDFM-2 Channel 3 Data Input
HIC_D3
14
I/O
HIC_A7
15
I
54
ADVANCE INFORMATION
SIGNAL NAME
MUX
100 PZ 80 PN
POSITION
HIC Data 3
HIC Address 7
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SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
SIGNAL NAME
GPIO44
MUX
100 PZ 80 PN
POSITION
64 PM
64
PMQ
48 PT
PIN
TYPE
DESCRIPTION
ADVANCE INFORMATION
0, 4, 8, 12
I/O
General-Purpose Input Output 44
OUTPUTXBAR7
3
O
Output X-BAR Output 7
EQEP1_A
5
I
eQEP-1 Input A
PMBUSA_SDA
6
I/OD
FSITXA_CLK
7
O
FSITX-A Output Clock
PMBUSA_CTL
9
I/O
PMBus-A Control Signal - Slave Input/Master
Output
CLB_OUTPUTXBAR3
10
O
CLB Output X-BAR Output 3
FSIRXA_D0
11
I
FSIRX-A Primary Data Input
HIC_D7
13
I/O
HIC Data 7
LINB_TX
14
O
LIN-B Transmit
HIC_D5
15
I/O
HIC Data 5
GPIO45
85
69
PMBus-A Open-Drain Bidirectional Data
0, 4, 8, 12
I/O
General-Purpose Input Output 45
OUTPUTXBAR8
3
O
Output X-BAR Output 8
FSITXA_D0
7
O
FSITX-A Primary Data Output
PMBUSA_ALERT
9
CLB_OUTPUTXBAR4
10
SD2_C3
HIC_D6
73
I/OD
PMBus-A Open-Drain Bidirectional Alert Signal
O
CLB Output X-BAR Output 4
13
I
SDFM-2 Channel 3 Clock Input
15
I/O
HIC Data 6
GPIO46
0, 4, 8, 12
I/O
General-Purpose Input Output 46
LINA_TX
3
O
LIN-A Transmit
MCAN_TX
5
O
CAN/CAN FD Transmit
FSITXA_D1
7
O
FSITX-A Optional Additional Data Output
PMBUSA_SDA
9
I/OD
PMBus-A Open-Drain Bidirectional Data
SD2_C4
13
I
SDFM-2 Channel 4 Clock Input
HIC_NWE
15
I
HIC Data Write enable from host
GPIO47
0, 4, 8, 12
I/O
General-Purpose Input Output 47
LINA_RX
3
I
LIN-A Receive
MCAN_RX
5
I
CAN/CAN FD Receive
CLB_OUTPUTXBAR2
7
O
CLB Output X-BAR Output 2
PMBUSA_SCL
9
SD2_D4
13
I
SDFM-2 Channel 4 Data Input
FSITXA_TDM_CLK
14
I
FSITX-A Time Division Multiplexed Clock Input
HIC_A6
15
I
HIC Address 6
GPIO48
6
6
I/OD
PMBus-A Open-Drain Bidirectional Clock
0, 4, 8, 12
I/O
General-Purpose Input Output 48
OUTPUTXBAR3
1
O
Output X-BAR Output 3
CANA_TX
3
O
CAN-A Transmit
SCIA_TX
6
O
SCI-A Transmit Data
SD1_D1
7
I
SDFM-1 Channel 1 Data Input
PMBUSA_SDA
9
I/OD
HIC_A7
15
I
32
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PMBus-A Open-Drain Bidirectional Data
HIC Address 7
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SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
GPIO49
64 PM
64
PMQ
48 PT
PIN
TYPE
DESCRIPTION
0, 4, 8, 12
I/O
General-Purpose Input Output 49
OUTPUTXBAR4
1
O
Output X-BAR Output 4
CANA_RX
3
I
CAN-A Receive
SCIA_RX
6
I
SCI-A Receive Data
SD1_C1
7
I
SDFM-1 Channel 1 Clock Input
8
LINA_RX
9
I
LIN-A Receive
SD2_D1
13
I
SDFM-2 Channel 1 Data Input
FSITXA_D0
14
O
FSITX-A Primary Data Output
HIC_D2
15
I/O
HIC Data 2
GPIO50
0, 4, 8, 12
I/O
General-Purpose Input Output 50
EQEP1_A
1
I
eQEP-1 Input A
MCAN_TX
5
O
CAN/CAN FD Transmit
SPIB_SIMO
6
I/O
SPI-B Slave In, Master Out (SIMO)
SD1_D2
7
I2CB_SDA
9
SD2_D2
13
I
SDFM-2 Channel 2 Data Input
FSITXA_D1
14
O
FSITX-A Optional Additional Data Output
HIC_D3
15
I/O
HIC Data 3
GPIO51
0, 4, 8, 12
I/O
General-Purpose Input Output 51
EQEP1_B
1
I
eQEP-1 Input B
MCAN_RX
5
I
CAN/CAN FD Receive
SPIB_SOMI
6
I/O
SD1_C2
7
I2CB_SCL
9
SD2_D3
13
I
SDFM-2 Channel 3 Data Input
FSITXA_CLK
14
O
FSITX-A Output Clock
HIC_D6
15
I/O
HIC Data 6
GPIO52
9
I
I/OD
10
I
I/OD
SDFM-1 Channel 2 Data Input
I2C-B Open-Drain Bidirectional Data
SPI-B Slave Out, Master In (SOMI)
SDFM-1 Channel 2 Clock Input
I2C-B Open-Drain Bidirectional Clock
0, 4, 8, 12
I/O
General-Purpose Input Output 52
EQEP1_STROBE
1
I/O
eQEP-1 Strobe
CLB_OUTPUTXBAR5
5
O
CLB Output X-BAR Output 5
SPIB_CLK
6
I/O
SPI-B Clock
SD1_D3
7
11
I
SDFM-1 Channel 3 Data Input
SYNCOUT
9
O
External ePWM Synchronization Pulse
SD2_D4
13
I
SDFM-2 Channel 4 Data Input
FSIRXA_D0
14
I
FSIRX-A Primary Data Input
HIC_NWE
15
I
HIC Data Write enable from host
GPIO53
0, 4, 8, 12
I/O
General-Purpose Input Output 53
EQEP1_INDEX
1
I/O
eQEP-1 Index
CLB_OUTPUTXBAR6
5
O
CLB Output X-BAR Output 6
SPIB_STE
6
I/O
SPI-B Slave Transmit Enable (STE)
SD1_C3
7
12
ADVANCE INFORMATION
SIGNAL NAME
MUX
100 PZ 80 PN
POSITION
I
SDFM-1 Channel 3 Clock Input
ADCSOCAO
9
O
ADC Start of Conversion A for External ADC
CANA_RX
10
I
CAN-A Receive
SD1_C1
13
I
SDFM-1 Channel 1 Clock Input
FSIRXA_D1
14
I
FSIRX-A Optional Additional Data Input
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SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
SIGNAL NAME
GPIO54
MUX
100 PZ 80 PN
POSITION
64 PM
64
PMQ
48 PT
PIN
TYPE
DESCRIPTION
0, 4, 8, 12
I/O
General-Purpose Input Output 54
SPIA_SIMO
1
I/O
SPI-A Slave In, Master Out (SIMO)
EQEP2_A
5
I
eQEP-2 Input A
OUTPUTXBAR2
6
O
Output X-BAR Output 2
SD1_D4
7
I
SDFM-1 Channel 4 Data Input
13
ADVANCE INFORMATION
ADCSOCBO
9
O
ADC Start of Conversion B for External ADC
LINB_TX
10
O
LIN-B Transmit
SD1_C2
13
I
SDFM-1 Channel 2 Clock Input
FSIRXA_CLK
14
I
FSIRX-A Input Clock
FSITXA_TDM_D1
15
I
FSITX-A Time Division Multiplexed Additional
Data Input
0, 4, 8, 12
I/O
General-Purpose Input Output 55
SPIA_SOMI
1
I/O
SPI-A Slave Out, Master In (SOMI)
EQEP2_B
5
I
eQEP-2 Input B
OUTPUTXBAR3
6
O
Output X-BAR Output 3
SD1_C4
7
I
SDFM-1 Channel 4 Clock Input
ERRORSTS
9
O
Error Status Output. This signal requires an
external pulldown.
LINB_RX
10
I
LIN-B Receive
SD1_C3
13
I
SDFM-1 Channel 3 Clock Input
HIC Address 0
GPIO55
43
HIC_A0
15
I
GPIO56
0, 4, 8, 12
I/O
General-Purpose Input Output 56
SPIA_CLK
1
I/O
SPI-A Clock
CLB_OUTPUTXBAR7
2
O
CLB Output X-BAR Output 7
MCAN_TX
3
O
CAN/CAN FD Transmit
EQEP2_STROBE
5
I/O
eQEP-2 Strobe
SCIB_TX
6
O
SCI-B Transmit Data
SD2_D1
7
I
SDFM-2 Channel 1 Data Input
SPIB_SIMO
9
I/O
I2CA_SDA
10
I/OD
EQEP1_A
11
I
eQEP-1 Input A
SD1_C4
13
I
SDFM-1 Channel 4 Clock Input
FSIRXA_D1
14
I
FSIRX-A Optional Additional Data Input
HIC_D6
15
I/O
HIC Data 6
GPIO57
65
SPI-B Slave In, Master Out (SIMO)
I2C-A Open-Drain Bidirectional Data
0, 4, 8, 12
I/O
General-Purpose Input Output 57
SPIA_STE
1
I/O
SPI-A Slave Transmit Enable (STE)
CLB_OUTPUTXBAR8
2
O
CLB Output X-BAR Output 8
MCAN_RX
3
I
CAN/CAN FD Receive
EQEP2_INDEX
5
I/O
SCIB_RX
6
SD2_C1
7
SPIB_SOMI
9
I/O
I2CA_SCL
10
I/OD
EQEP1_B
11
I
eQEP-1 Input B
FSIRXA_CLK
14
I
FSIRX-A Input Clock
HIC_D4
15
I/O
34
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66
eQEP-2 Index
I
SCI-B Receive Data
I
SDFM-2 Channel 1 Clock Input
SPI-B Slave Out, Master In (SOMI)
I2C-A Open-Drain Bidirectional Clock
HIC Data 4
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F280039C TMS320F280037C
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SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
GPIO58
64 PM
64
PMQ
48 PT
PIN
TYPE
DESCRIPTION
0, 4, 8, 12
I/O
General-Purpose Input Output 58
OUTPUTXBAR1
5
O
Output X-BAR Output 1
SPIB_CLK
6
I/O
SPI-B Clock
SD2_D2
7
I
SDFM-2 Channel 2 Data Input
LINA_TX
9
O
LIN-A Transmit
CANA_TX
10
O
CAN-A Transmit
EQEP1_STROBE
11
I/O
eQEP-1 Strobe
SD2_C2
13
I
SDFM-2 Channel 2 Clock Input
FSIRXA_D0
14
I
FSIRX-A Primary Data Input
HIC_NRDY
15
O
HIC Ready from device to host
GPIO59
67
0, 4, 8, 12
I/O
General-Purpose Input Output 59
OUTPUTXBAR2
5
O
Output X-BAR Output 2
SPIB_STE
6
I/O
SPI-B Slave Transmit Enable (STE)
SD2_C2
7
I
SDFM-2 Channel 2 Clock Input
LINA_RX
9
I
LIN-A Receive
CANA_RX
10
I
CAN-A Receive
EQEP1_INDEX
11
I/O
SD2_C3
13
I
SDFM-2 Channel 3 Clock Input
FSITXA_TDM_D1
14
I
FSITX-A Time Division Multiplexed Additional
Data Input
GPIO60
92
eQEP-1 Index
0, 4, 8, 12
I/O
General-Purpose Input Output 60
MCAN_TX
3
O
CAN/CAN FD Transmit
OUTPUTXBAR3
5
O
Output X-BAR Output 3
SPIB_SIMO
6
I/O
SPI-B Slave In, Master Out (SIMO)
44
SD2_D3
7
I
SDFM-2 Channel 3 Data Input
SD2_C4
13
I
SDFM-2 Channel 4 Clock Input
HIC_A0
15
I
HIC Address 0
GPIO61
0, 4, 8, 12
I/O
MCAN_RX
3
I
CAN/CAN FD Receive
OUTPUTXBAR4
5
O
Output X-BAR Output 4
SPIB_SOMI
6
I/O
SPI-B Slave Out, Master In (SOMI)
SD2_C3
7
CANA_RX
14
91
ADVANCE INFORMATION
SIGNAL NAME
MUX
100 PZ 80 PN
POSITION
General-Purpose Input Output 61
I
SDFM-2 Channel 3 Clock Input
I
CAN-A Receive
I
JTAG test clock with internal pullup.
TEST, JTAG, AND RESET
TCK
TMS
60
62
45
47
36
38
36
38
28
30
I/O
JTAG test-mode select (TMS) with internal
pullup. This serial control input is clocked into
the TAP controller on the rising edge of TCK.
This device does not have a TRSTn pin. An
external pullup resistor (recommended 2.2 kΩ)
on the TMS pin to VDDIO should be placed on
the board to keep JTAG in reset during normal
operation.
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SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
SIGNAL NAME
MUX
100 PZ 80 PN
POSITION
XRSn
2
5
64 PM
3
64
PMQ
3
48 PT
3
ADVANCE INFORMATION
PIN
TYPE
DESCRIPTION
I/OD
Device Reset (in) and Watchdog Reset (out).
During a power-on condition, this pin is driven
low by the device. An external circuit may also
drive this pin to assert a device reset. This
pin is also driven low by the MCU when a
watchdog reset occurs. During watchdog reset,
the XRSn pin is driven low for the watchdog
reset duration of 512 OSCCLK cycles. A
resistor between 2.2 kΩ and 10 kΩ should
be placed between XRSn and VDDIO. If a
capacitor is placed between XRSn and VSS
for noise filtering, it should be 100 nF or
smaller. These values will allow the watchdog
to properly drive the XRSn pin to VOL within
512 OSCCLK cycles when the watchdog reset
is asserted. This pin is an open-drain output
with an internal pullup. If this pin is driven by
an external device, it should be done using an
open-drain device.
POWER AND GROUND
4, 46,
71, 87
8, 31,
53, 71
4, 27,
44, 59
VDDA
34
26
22
VDDIO
3, 47,
70, 88
VDD
VREGENZ
VSS
VSSA
36
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4, 27, 23, 36,
44, 59
45
22
1.2-V Digital Logic Power Pins. See the PMM
section for usage details.
3.3-V Analog Power Pins. Place a minimum
2.2-µF decoupling capacitor on each pin. See
the PMM section for usage details.
18
7, 32, 28, 43, 28, 43, 24, 35,
52, 72
60
60
46
73
46
5, 45,
72, 86
9, 30,
55, 70
5, 26,
45, 58
33
25
21
I
5, 26, 22, 37,
45, 58
44
21
3.3-V Digital I/O Power Pins. See the PMM
section for usage details.
17
Internal voltage regulator disable with internal
pulldown. Tie low to VSS to enable internal
VREG. Tie high to VDDIO to use an external
supply. See the PMM section for usage details.
Digital Ground
Analog Ground
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
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SPRSP61 – OCTOBER 2021
5.3 Signal Descriptions
5.3.1 Analog Signals
Table 5-2. Analog Signals
PIN TYPE
DESCRIPTION
100 PZ PIN
80 PN PIN
64 PM PIN
64 PMQ PIN
A0
I
ADC-A Input 0
GPIO PIN
23
19
15
15
11
A1
I
ADC-A Input 1
22
18
14
14
10
A2
I
ADC-A Input 2
17
13
9
9
6
A3
I
ADC-A Input 3
18
12
8
8
5
A4
I
ADC-A Input 4
36
27
23
23
19
A5
I
ADC-A Input 5
35
17
13
13
9
A6
I
ADC-A Input 6
14
10
6
6
4
A7
I
ADC-A Input 7
31
23
19
19
15
A8
I
ADC-A Input 8
37
24
20
20
16
A9
I
ADC-A Input 9
38
28
24
24
20
A10
I
ADC-A Input 10
40
29
25
25
21
A11
I
ADC-A Input 11
20
16
12
12
8
A12
I
ADC-A Input 12
28
22
18
18
14
A14
I
ADC-A Input 14
19
15
11
11
A15
I
ADC-A Input 15
14
10
10
7
AIO224
I
Analog Pin Used For Digital Input
224
17
13
9
9
6
AIO225
I
Analog Pin Used For Digital Input
225
36
27
23
23
19
AIO226
I
Analog Pin Used For Digital Input
226
15
11
7
7
4
AIO227
I
Analog Pin Used For Digital Input
227
38
28
24
24
20
AIO228
I
Analog Pin Used For Digital Input
228
14
10
6
6
4
AIO229
I
Analog Pin Used For Digital Input
229
18
AIO230
I
Analog Pin Used For Digital Input
230
40
29
25
25
21
AIO231
I
Analog Pin Used For Digital Input
231
23
19
15
15
11
AIO232
I
Analog Pin Used For Digital Input
232
22
18
14
14
10
AIO233
I
Analog Pin Used For Digital Input
233
14
10
10
7
AIO236
I
Analog Pin Used For Digital Input
236
39
28
24
24
20
AIO237
I
Analog Pin Used For Digital Input
237
20
16
12
12
8
AIO238
I
Analog Pin Used For Digital Input
238
28
22
18
18
14
AIO239
I
Analog Pin Used For Digital Input
239
19
15
11
11
AIO240
I
Analog Pin Used For Digital Input
240
37
AIO241
I
Analog Pin Used For Digital Input
241
24
20
20
16
AIO242
I
Analog Pin Used For Digital Input
242
16
12
8
8
5
AIO244
I
Analog Pin Used For Digital Input
244
21
17
13
13
9
AIO245
I
Analog Pin Used For Digital Input
245
31
23
19
19
15
AIO247
I
Analog Pin Used For Digital Input
247
42
AIO248
I
Analog Pin Used For Digital Input
248
29
22
18
18
14
AIO249
I
Analog Pin Used For Digital Input
249
35
AIO251
I
Analog Pin Used For Digital Input
251
30
Copyright © 2021 Texas Instruments Incorporated
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48 PT PIN
Submit Document Feedback
ADVANCE INFORMATION
SIGNAL NAME
37
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SPRSP61 – OCTOBER 2021
Table 5-2. Analog Signals (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
GPIO PIN
100 PZ PIN
ADVANCE INFORMATION
80 PN PIN
64 PM PIN
64 PMQ PIN
48 PT PIN
41
24
20
20
16
40
29
25
25
21
ADC-B Input 2
15
11
7
7
4
I
ADC-B Input 3
16
12
8
8
5
B4
I
ADC-B Input 4
39
28
24
24
20
B5
I
ADC-B Input 5
32, 48
33
B6
I
ADC-B Input 6
17
13
9
9
6
B7
I
ADC-B Input 7
22
18
14
14
10
B8
I
ADC-B Input 8
36
27
23
23
19
B9
I
ADC-B Input 9
18
14
10
10
7
B10
I
ADC-B Input 10
20
16
12
12
8
B11
I
ADC-B Input 11
30, 49
34
B12
I
ADC-B Input 12
21
17
13
13
9
B14
I
ADC-B Input 14
19
15
11
11
B15
I
ADC-B Input 15
23
19
15
15
C0
I
ADC-C Input 0
20
16
12
12
8
C1
I
ADC-C Input 1
29
22
18
18
14
C2
I
ADC-C Input 2
21
17
13
13
9
C3
I
ADC-C Input 3
31
23
19
19
15
C4
I
ADC-C Input 4
19
15
11
11
C5
I
ADC-C Input 5
28
12
8
8
5
C6
I
ADC-C Input 6
15
11
7
7
4
C7
I
ADC-C Input 7
18
14
10
10
7
C8
I
ADC-C Input 8
39
28
24
24
20
C9
I
ADC-C Input 9
17
13
9
9
6
C10
I
ADC-C Input 10
40
29
25
25
21
C11
I
ADC-C Input 11
41
24
20
20
16
C14
I
ADC-C Input 14
42
27
23
23
19
C15
I
ADC-C Input 15
23
19
15
15
11
CMP1_HN0
I
CMPSS-1 High Comparator Negative
Input 0
14
10
10
7
CMP1_HN1
I
CMPSS-1 High Comparator Negative
Input 1
20
16
12
12
8
CMP1_HP0
I
CMPSS-1 High Comparator Positive
Input 0
17
13
9
9
6
CMP1_HP1
I
CMPSS-1 High Comparator Positive
Input 1
20
16
12
12
8
CMP1_HP2
I
CMPSS-1 High Comparator Positive
Input 2
14
10
6
6
4
CMP1_HP3
I
CMPSS-1 High Comparator Positive
Input 3
14
10
10
7
CMP1_HP4
I
CMPSS-1 High Comparator Positive
Input 4
22
18
14
14
10
CMP1_HP5
I
CMPSS-1 High Comparator Positive
Input 5
32, 48
33
CMP1_LN0
I
CMPSS-1 Low Comparator Negative
Input 0
14
10
10
7
CMP1_LN1
I
CMPSS-1 Low Comparator Negative
Input 1
20
16
12
12
8
CMP1_LP0
I
CMPSS-1 Low Comparator Positive
Input 0
17
13
9
9
6
CMP1_LP1
I
CMPSS-1 Low Comparator Positive
Input 1
20
16
12
12
8
CMP1_LP2
I
CMPSS-1 Low Comparator Positive
Input 2
14
10
6
6
4
CMP1_LP3
I
CMPSS-1 Low Comparator Positive
Input 3
14
10
10
7
AIO252
I
Analog Pin Used For Digital Input
252
48
AIO253
I
Analog Pin Used For Digital Input
253
41
B0
I
ADC-B Input 0
B1
I
ADC-B Input 1
B2
I
B3
38
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11
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
PIN TYPE
100 PZ PIN
80 PN PIN
64 PM PIN
64 PMQ PIN
48 PT PIN
CMP1_LP4
I
CMPSS-1 Low Comparator Positive
Input 4
DESCRIPTION
GPIO PIN
22
18
14
14
10
CMP1_LP5
I
CMPSS-1 Low Comparator Positive
Input 5
32, 48
33
CMP2_HN0
I
CMPSS-2 High Comparator Negative
Input 0
40
29
25
25
21
CMP2_HN1
I
CMPSS-2 High Comparator Negative
Input 1
28
22
18
18
14
CMP2_HP0
I
CMPSS-2 High Comparator Positive
Input 0
36
27
23
23
19
CMP2_HP1
I
CMPSS-2 High Comparator Positive
Input 1
28
22
18
18
14
CMP2_HP2
I
CMPSS-2 High Comparator Positive
Input 2
38
28
24
24
20
CMP2_HP3
I
CMPSS-2 High Comparator Positive
Input 3
40
29
25
25
21
CMP2_HP4
I
CMPSS-2 High Comparator Positive
Input 4
41
24
20
20
16
CMP2_HP5
I
CMPSS-2 High Comparator Positive
Input 5
35
17
13
13
9
CMP2_LN0
I
CMPSS-2 Low Comparator Negative
Input 0
40
29
25
25
21
CMP2_LN1
I
CMPSS-2 Low Comparator Negative
Input 1
28
22
18
18
14
CMP2_LP0
I
CMPSS-2 Low Comparator Positive
Input 0
36
27
23
23
19
CMP2_LP1
I
CMPSS-2 Low Comparator Positive
Input 1
28
22
18
18
14
CMP2_LP2
I
CMPSS-2 Low Comparator Positive
Input 2
38
28
24
24
20
CMP2_LP3
I
CMPSS-2 Low Comparator Positive
Input 3
40
29
25
25
21
CMP2_LP4
I
CMPSS-2 Low Comparator Positive
Input 4
41
24
20
20
16
CMP2_LP5
I
CMPSS-2 Low Comparator Positive
Input 5
35
17
13
13
9
CMP3_HN0
I
CMPSS-3 High Comparator Negative
Input 0
16
12
8
8
5
CMP3_HN1
I
CMPSS-3 High Comparator Negative
Input 1
21
17
13
13
9
CMP3_HP0
I
CMPSS-3 High Comparator Positive
Input 0
15
11
7
7
4
CMP3_HP1
I
CMPSS-3 High Comparator Positive
Input 1
21
17
13
13
9
CMP3_HP2
I
CMPSS-3 High Comparator Positive
Input 2
23
19
15
15
11
CMP3_HP3
I
CMPSS-3 High Comparator Positive
Input 3
16
12
8
8
5
CMP3_HP4
I
CMPSS-3 High Comparator Positive
Input 4
19
15
11
11
CMP3_HP5
I
CMPSS-3 High Comparator Positive
Input 5
18
12
8
8
5
CMP3_LN0
I
CMPSS-3 Low Comparator Negative
Input 0
16
12
8
8
5
CMP3_LN1
I
CMPSS-3 Low Comparator Negative
Input 1
21
17
13
13
9
CMP3_LP0
I
CMPSS-3 Low Comparator Positive
Input 0
15
11
7
7
4
CMP3_LP1
I
CMPSS-3 Low Comparator Positive
Input 1
21
17
13
13
9
CMP3_LP2
I
CMPSS-3 Low Comparator Positive
Input 2
23
19
15
15
11
CMP3_LP3
I
CMPSS-3 Low Comparator Positive
Input 3
16
12
8
8
5
CMP3_LP4
I
CMPSS-3 Low Comparator Positive
Input 4
19
15
11
11
CMP3_LP5
I
CMPSS-3 Low Comparator Positive
Input 5
18
12
8
8
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F280039C TMS320F280037C
ADVANCE INFORMATION
Table 5-2. Analog Signals (continued)
SIGNAL NAME
5
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SPRSP61 – OCTOBER 2021
Table 5-2. Analog Signals (continued)
SIGNAL NAME
ADVANCE INFORMATION
PIN TYPE
DESCRIPTION
100 PZ PIN
80 PN PIN
64 PM PIN
64 PMQ PIN
48 PT PIN
CMP4_HN0
I
CMPSS-4 High Comparator Negative
Input 0
42
27
23
23
19
CMP4_HN1
I
CMPSS-4 High Comparator Negative
Input 1
31
23
19
19
15
CMP4_HP0
I
CMPSS-4 High Comparator Positive
Input 0
39
28
24
24
20
CMP4_HP1
I
CMPSS-4 High Comparator Positive
Input 1
31
23
19
19
15
CMP4_HP2
I
CMPSS-4 High Comparator Positive
Input 2
29
22
18
18
14
CMP4_HP3
I
CMPSS-4 High Comparator Positive
Input 3
42
27
23
23
19
CMP4_HP4
I
CMPSS-4 High Comparator Positive
Input 4
37
24
20
20
16
CMP4_HP5
I
CMPSS-4 High Comparator Positive
Input 5
30, 49
34
CMP4_LN0
I
CMPSS-4 Low Comparator Negative
Input 0
42
27
23
23
19
CMP4_LN1
I
CMPSS-4 Low Comparator Negative
Input 1
31
23
19
19
15
CMP4_LP0
I
CMPSS-4 Low Comparator Positive
Input 0
39
28
24
24
20
CMP4_LP1
I
CMPSS-4 Low Comparator Positive
Input 1
31
23
19
19
15
CMP4_LP2
I
CMPSS-4 Low Comparator Positive
Input 2
29
22
18
18
14
CMP4_LP3
I
CMPSS-4 Low Comparator Positive
Input 3
42
27
23
23
19
CMP4_LP4
I
CMPSS-4 Low Comparator Positive
Input 4
37
24
20
20
16
CMP4_LP5
I
CMPSS-4 Low Comparator Positive
Input 5
30, 49
34
DACA_OUT
O
Buffered DAC-A Output.
23
19
15
15
11
DACB_OUT
O
Buffered DAC-B Output.
22
18
14
14
10
GPIO20
I/O
General-Purpose Input Output 20
48
33
GPIO21
I/O
General-Purpose Input Output 21
30
34
HIC_A0
I
HIC Address 0
14
10
6
6
4
HIC_A1
I
HIC Address 1
15
11
7
7
4
HIC_A2
I
HIC Address 2
16
12
8
8
5
HIC_A3
I
HIC Address 3
17
13
9
9
6
HIC_A4
I
HIC Address 4
14
10
10
7
HIC_A5
I
HIC Address 5
19
15
11
11
HIC_A6
I
HIC Address 6
20
16
12
12
HIC_A7
I
HIC Address 7
21
17
13
13
9
HIC_BASESEL0
I
HIC Base address range select 0
22
18
14
14
10
HIC_BASESEL1
I
HIC Base address range select 1
23
19
15
15
11
HIC_BASESEL2
I
HIC Base address range select 2
40
29
25
25
21
HIC_NBE0
I
HIC Byte enable 0
38
28
24
24
20
HIC_NBE1
I
HIC Byte enable 1
37
24
20
20
16
HIC_NCS
I
HIC Chip select input
28
22
18
18
14
HIC_NOE
O
HIC Output enable for data bus
31
23
19
19
15
HIC_NWE
I
HIC Data Write enable from host
36
27
23
23
19
SD1_C1
I
SDFM-1 Channel 1 Clock Input
23
19
15
15
11
SD1_C2
I
SDFM-1 Channel 2 Clock Input
31
23
19
19
15
SD1_C3
I
SDFM-1 Channel 3 Clock Input
38
28
24
24
20
SD1_C4
I
SDFM-1 Channel 4 Clock Input
40
29
25
25
21
SD1_D1
I
SDFM-1 Channel 1 Data Input
19
15
11
11
SD1_D2
I
SDFM-1 Channel 2 Data Input
20
16
12
12
SD1_D3
I
SDFM-1 Channel 3 Data Input
21
17
13
13
9
SD1_D4
I
SDFM-1 Channel 4 Data Input
22
18
14
14
10
SD2_C1
I
SDFM-2 Channel 1 Clock Input
14, 37
10, 24
20, 6
20, 6
16, 4
40
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8
8
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Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
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SPRSP61 – OCTOBER 2021
PIN TYPE
100 PZ PIN
80 PN PIN
64 PM PIN
64 PMQ PIN
48 PT PIN
SD2_C2
I
SDFM-2 Channel 2 Clock Input
DESCRIPTION
GPIO PIN
36
27
23
23
19
SD2_C3
I
SDFM-2 Channel 3 Clock Input
28
22
18
18
14
SD2_C4
I
SDFM-2 Channel 4 Clock Input
48
SD2_D1
I
SDFM-2 Channel 1 Data Input
14
10
10
7
SD2_D2
I
SDFM-2 Channel 2 Data Input
16
12
8
8
5
SD2_D3
I
SDFM-2 Channel 3 Data Input
17
13
9
9
6
SD2_D4
I
SDFM-2 Channel 4 Data Input
15
11
7
7
4
VDAC
I
Optional external reference voltage
for on-chip DACs.
16
12
8
8
5
VREFHI
I
ADC High Reference. In external
reference mode, externally drive the
high reference voltage onto this pin.
In internal reference mode, a voltage
is driven onto this pin by the device.
In either mode, place at least a
2.2-µF capacitor on this pin. This
capacitor should be placed as close
to the device as possible between
the VREFHI and VREFLO pins.
24, 25
20
16
16
12
VREFLO
I
ADC Low Reference
26, 27
21
17
17
13
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Table 5-2. Analog Signals (continued)
SIGNAL NAME
41
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SPRSP61 – OCTOBER 2021
5.3.2 Digital Signals
Table 5-3. Digital Signals
SIGNAL NAME
PIN TYPE
DESCRIPTION
GPIO PIN
100 PZ PIN
80 PN PIN
64 PM PIN
64 PMQ PIN
48 PT PIN
ADCSOCAO
O
ADC Start of Conversion A for External ADC
33, 53, 8
12, 53, 74
38, 58
32, 47
32, 47
25
ADCSOCBO
O
ADC Start of Conversion B for External ADC
10, 32, 54
13, 64, 93
49, 76
40, 63
40, 63
32
29
100
3
1
1
1
AUXCLKIN
ADVANCE INFORMATION
CANA_RX
I
CAN-A Receive
12, 18, 3, 30, 33,
35, 49, 5, 53, 59,
61
12, 51, 53, 63, 68,
76, 8, 89, 91, 92,
98
1, 36, 38, 48, 50,
60, 74
30, 32, 39, 41, 49,
61
30, 32, 39, 41, 49,
61
25, 31, 33, 39, 47
CANA_TX
O
CAN-A Transmit
13, 17, 19, 2, 31,
32, 37, 4, 48, 58
50, 55, 61, 64, 67,
69, 7, 75, 77, 99
2, 35, 40, 46, 49,
51, 59, 61
29, 34, 37, 40, 42,
48, 50
29, 34, 37, 40, 42,
48, 50
29, 32, 34, 38, 40
CLB_OUTPUTXBAR1
O
CLB Output X-BAR Output 1
19, 22
69, 83
51, 67
42, 56
42, 56
34
CLB_OUTPUTXBAR2
O
CLB Output X-BAR Output 2
39, 47, 7
6, 84
56, 68
46, 57
57
43
CLB_OUTPUTXBAR3
O
CLB Output X-BAR Output 3
23, 42, 44
81, 85
57, 65, 69
54
54
CLB_OUTPUTXBAR4
O
CLB Output X-BAR Output 4
10, 43, 45
93
54, 73, 76
63
63
CLB_OUTPUTXBAR5
O
CLB Output X-BAR Output 5
5, 52, 8
11, 74, 89
58, 74
47, 61
47, 61
47
CLB_OUTPUTXBAR6
O
CLB Output X-BAR Output 6
15, 4, 53
12, 75, 95
59, 78
48
48
38
CLB_OUTPUTXBAR7
O
CLB Output X-BAR Output 7
1, 14, 56
65, 78, 96
62, 79
51
51
41
CLB_OUTPUTXBAR8
O
CLB Output X-BAR Output 8
57, 6
66, 79, 97
63, 80
52, 64
52, 64
42, 48
EPWM1_A
O
ePWM-1 Output A
30
79, 98
1, 63
52
52
42
EPWM1_B
O
ePWM-1 Output B
1, 31
78, 99
2, 62
51
51
41
EPWM2_A
O
ePWM-2 Output A
2, 41
77, 82
61, 66
50, 55
50, 55
40
EPWM2_B
O
ePWM-2 Output B
3, 40
76, 80
60, 64
49, 53
49, 53
39
EPWM3_A
O
ePWM-3 Output A
14, 4
75, 96
59, 79
48
48
38
EPWM3_B
O
ePWM-3 Output B
15, 5
89, 95
74, 78
61
61
47
EPWM4_A
O
ePWM-4 Output A
22, 6
83, 97
67, 80
56, 64
56, 64
48
EPWM4_B
O
ePWM-4 Output B
23, 7
81, 84
65, 68
54, 57
54, 57
43
EPWM5_A
O
ePWM-5 Output A
16, 8
54, 74
39, 58
33, 47
33, 47
26
EPWM5_B
O
ePWM-5 Output B
17, 35, 9
55, 63, 90
40, 48, 75
34, 39, 62
34, 39, 62
31
EPWM6_A
O
ePWM-6 Output A
10, 18
68, 93
50, 76
41, 63
41, 63
33
EPWM6_B
O
ePWM-6 Output B
11, 19
52, 69
37, 51
31, 42
31, 42
34
EPWM7_A
O
ePWM-7 Output A
12, 28
1, 51
36, 4
2, 30
2, 30
2
EPWM7_B
O
ePWM-7 Output B
13, 29
100, 50
3, 35
1, 29
1, 29
1
EPWM8_A
O
ePWM-8 Output A
14, 24
56, 96
41, 79
35
35
27
EPWM8_B
O
ePWM-8 Output B
15, 32
64, 95
49, 78
40
40
32
EQEP1_A
I
eQEP-1 Input A
10, 20, 25, 28, 35,
40, 44, 50, 56, 6
1, 48, 57, 63, 65,
80, 85, 9, 93, 97
33, 4, 42, 48, 64,
69, 76, 80
2, 39, 53, 63, 64
2, 39, 53, 63, 64
2, 31, 48
EQEP1_B
I
eQEP-1 Input B
11, 21, 29, 37, 41,
51, 57, 7
10, 100, 49, 52, 61,
66, 82, 84
3, 34, 37, 46, 66,
68
1, 31, 37, 55, 57
1, 31, 37, 55, 57
1, 29, 43
EQEP1_INDEX
I/O
eQEP-1 Index
13, 17, 23, 31, 39,
43, 53, 59, 9
12, 50, 55, 79, 81,
90, 92, 99
2, 35, 40, 54, 56,
63, 65, 75
29, 34, 46, 52, 54,
62
29, 34, 52, 54, 62
42
EQEP1_STROBE
I/O
eQEP-1 Strobe
12, 16, 22, 30, 42,
52, 58, 8
11, 51, 54, 67, 74,
83, 98
1, 36, 39, 57, 58,
67
30, 33, 47, 56
30, 33, 47, 56
26
42
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Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-3. Digital Signals (continued)
PIN TYPE
DESCRIPTION
GPIO PIN
100 PZ PIN
80 PN PIN
64 PM PIN
64 PMQ PIN
EQEP2_A
I
eQEP-2 Input A
11, 14, 18, 24, 54
13, 52, 56, 68, 96
37, 41, 50, 79
31, 35, 41
31, 35, 41
48 PT PIN
27, 33
EQEP2_B
I
eQEP-2 Input B
15, 16, 19, 25, 33,
55
43, 53, 54, 57, 69,
95
38, 39, 42, 51, 78
32, 33, 42
32, 33, 42
25, 26, 34
EQEP2_INDEX
I/O
eQEP-2 Index
26, 29, 39, 57
100, 58, 66
3, 43, 56
1, 46
1
1
EQEP2_STROBE
I/O
eQEP-2 Strobe
27, 28, 4, 56
1, 59, 65, 75
4, 44, 59
2, 48
2, 48
2, 38
ERRORSTS
O
Error Status Output. This signal requires an
external pulldown.
24, 28, 29, 55
1, 100, 43, 56
3, 4, 41
1, 2, 35
1, 2, 35
1, 2, 27
FSIRXA_CLK
I
FSIRX-A Input Clock
13, 30, 33, 39, 4,
54, 57
13, 50, 53, 66, 75,
79, 98
1, 35, 38, 56, 59,
63
29, 32, 46, 48, 52
29, 32, 48, 52
25, 38, 42
FSIRXA_D0
I
FSIRX-A Primary Data Input
12, 3, 32, 40, 44,
52, 58
11, 51, 64, 67, 76,
80, 85
36, 49, 60, 64, 69
30, 40, 49, 53
30, 40, 49, 53
32, 39
FSIRXA_D1
I
FSIRX-A Optional Additional Data Input
11, 2, 31, 41, 53,
56
12, 52, 65, 77, 82,
99
2, 37, 61, 66
31, 50, 55
31, 50, 55
40
FSITXA_CLK
O
FSITX-A Output Clock
10, 27, 44, 51, 7
10, 59, 84, 85, 93
44, 68, 69, 76
57, 63
57, 63
43
FSITXA_D0
O
FSITX-A Primary Data Output
26, 45, 49, 6, 9
58, 8, 90, 97
43, 73, 75, 80
62, 64
62, 64
48
FSITXA_D1
O
FSITX-A Optional Additional Data Output
25, 46, 5, 50, 6, 8
57, 74, 89, 9, 97
42, 58, 6, 74, 80
47, 61, 64
47, 61, 64
47, 48
FSITXA_TDM_CLK
I
FSITX-A Time Division Multiplexed Clock Input
18, 47, 8
6, 68, 74
50, 58
41, 47
41, 47
33
FSITXA_TDM_D0
I
FSITX-A Time Division Multiplexed Data Input
10, 19
69, 93
51, 76
42, 63
42, 63
34
FSITXA_TDM_D1
I
FSITX-A Time Division Multiplexed Additional Data
Input
1, 54, 59
13, 78, 92
62
51
51
41
GPIO0
I/O
General-Purpose Input Output 0
79
63
52
52
42
GPIO1
I/O
General-Purpose Input Output 1
1
78
62
51
51
41
GPIO2
I/O
General-Purpose Input Output 2
2
77
61
50
50
40
GPIO3
I/O
General-Purpose Input Output 3
3
76
60
49
49
39
GPIO4
I/O
General-Purpose Input Output 4
4
75
59
48
48
38
GPIO5
I/O
General-Purpose Input Output 5
5
89
74
61
61
47
GPIO6
I/O
General-Purpose Input Output 6
6
97
80
64
64
48
GPIO7
I/O
General-Purpose Input Output 7
7
84
68
57
57
43
GPIO8
I/O
General-Purpose Input Output 8
8
74
58
47
47
GPIO9
I/O
General-Purpose Input Output 9
9
90
75
62
62
GPIO10
I/O
General-Purpose Input Output 10
10
93
76
63
63
GPIO11
I/O
General-Purpose Input Output 11
11
52
37
31
31
GPIO12
I/O
General-Purpose Input Output 12
12
51
36
30
30
GPIO13
I/O
General-Purpose Input Output 13
13
50
35
29
29
GPIO14
I/O
General-Purpose Input Output 14
14
96
79
GPIO15
I/O
General-Purpose Input Output 15
15
95
78
GPIO16
I/O
General-Purpose Input Output 16
16
54
39
33
33
GPIO17
I/O
General-Purpose Input Output 17
17
55
40
34
34
GPIO18
I/O
General-Purpose Input Output 18
18
68
50
41
41
33
GPIO19
I/O
General-Purpose Input Output 19
19
69
51
42
42
34
GPIO20
I/O
General-Purpose Input Output 20
20
48
33
GPIO21
I/O
General-Purpose Input Output 21
21
49
34
26
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ADVANCE INFORMATION
SIGNAL NAME
43
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-3. Digital Signals (continued)
SIGNAL NAME
ADVANCE INFORMATION
GPIO PIN
100 PZ PIN
80 PN PIN
64 PM PIN
64 PMQ PIN
GPIO22
I/O
General-Purpose Input Output 22
22
83
67
56
56
GPIO23
I/O
General-Purpose Input Output 23
23
81
65
54
54
GPIO24
I/O
General-Purpose Input Output 24
24
56
41
35
35
27
GPIO25
I/O
General-Purpose Input Output 25
25
57
42
GPIO26
I/O
General-Purpose Input Output 26
26
58
43
GPIO27
I/O
General-Purpose Input Output 27
27
59
44
GPIO28
I/O
General-Purpose Input Output 28
28
1
4
2
2
2
GPIO29
I/O
General-Purpose Input Output 29
29
100
3
1
1
1
GPIO30
I/O
General-Purpose Input Output 30
30
98
1
GPIO31
I/O
General-Purpose Input Output 31
31
99
2
GPIO32
I/O
General-Purpose Input Output 32
32
64
49
40
40
32
GPIO33
I/O
General-Purpose Input Output 33
33
53
38
32
32
25
GPIO34
I/O
General-Purpose Input Output 34
34
94
77
GPIO35
I/O
General-Purpose Input Output 35
35
63
48
39
39
31
GPIO37
I/O
General-Purpose Input Output 37
37
61
46
37
37
29
GPIO39
I/O
General-Purpose Input Output 39
39
56
46
GPIO40
I/O
General-Purpose Input Output 40
40
80
64
53
53
GPIO41
I/O
General-Purpose Input Output 41
41
82
66
55
55
GPIO42
I/O
General-Purpose Input Output 42
42
GPIO43
I/O
General-Purpose Input Output 43
43
GPIO44
I/O
General-Purpose Input Output 44
44
GPIO45
I/O
General-Purpose Input Output 45
45
GPIO46
I/O
General-Purpose Input Output 46
46
GPIO47
I/O
General-Purpose Input Output 47
47
6
GPIO48
I/O
General-Purpose Input Output 48
48
7
GPIO49
I/O
General-Purpose Input Output 49
49
8
GPIO50
I/O
General-Purpose Input Output 50
50
9
GPIO51
I/O
General-Purpose Input Output 51
51
10
GPIO52
I/O
General-Purpose Input Output 52
52
11
GPIO53
I/O
General-Purpose Input Output 53
53
12
GPIO54
I/O
General-Purpose Input Output 54
54
13
GPIO55
I/O
General-Purpose Input Output 55
55
43
GPIO56
I/O
General-Purpose Input Output 56
56
65
GPIO57
I/O
General-Purpose Input Output 57
57
66
GPIO58
I/O
General-Purpose Input Output 58
58
67
GPIO59
I/O
General-Purpose Input Output 59
59
92
GPIO60
I/O
General-Purpose Input Output 60
60
44
GPIO61
I/O
General-Purpose Input Output 61
61
91
HIC_A0
I
HIC Address 0
55, 60, 8
43, 44, 74
58
47
47
HIC_A1
I
HIC Address 1
2, 26
58, 77
43, 61
50
50
44
PIN TYPE
DESCRIPTION
48 PT PIN
57
54
85
69
73
6
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40
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
PIN TYPE
DESCRIPTION
GPIO PIN
100 PZ PIN
80 PN PIN
64 PM PIN
64 PMQ PIN
48 PT PIN
HIC_A2
I
HIC Address 2
1
78
62
51
51
41
HIC_A3
I
HIC Address 3
23
81
65
54
54
HIC_A4
I
HIC Address 4
27, 41
59, 82
44, 66
55
55
HIC_A5
I
HIC Address 5
22
83
67
56
56
HIC_A6
I
HIC Address 6
42, 47, 7
6, 84
57, 68
57
57
43
HIC_A7
I
HIC Address 7
43, 48, 5
7, 89
54, 74
61
61
47
HIC_BASESEL0
I
HIC Base address range select 0
25, 9
57, 90
42, 75
62
62
HIC_BASESEL1
I
HIC Base address range select 1
HIC_BASESEL2
I
HIC Base address range select 2
79
63
52
52
42
4
75
59
48
48
38
HIC_D0
I/O
HIC Data 0
26, 33
53, 58
38, 43
32
32
25
HIC_D1
I/O
HIC Data 1
16, 27
54, 59
39, 44
33
33
26
HIC_D2
I/O
HIC Data 2
17, 42, 49
55, 8
40, 57
34
34
HIC_D3
I/O
HIC Data 3
24, 43, 50
56, 9
41, 54
35
35
27
HIC_D4
I/O
HIC Data 4
3, 5, 57
66, 76, 89
60, 74
49, 61
49, 61
39, 47
HIC_D5
I/O
HIC Data 5
13, 40, 44
50, 80, 85
35, 64, 69
29, 53
29, 53
HIC_D6
I/O
HIC Data 6
11, 45, 51, 56
10, 52, 65
37, 73
31
31
HIC_D7
I/O
HIC Data 7
39, 44
79, 85
56, 63, 69
46, 52
52
HIC_D8
I/O
HIC Data 8
30, 8
74, 98
1, 58
47
47
HIC_D9
I/O
HIC Data 9
2, 34
77, 94
61, 77
50
50
40
HIC_D10
I/O
HIC Data 10
1, 31
78, 99
2, 62
51
51
41
HIC_D11
I/O
HIC Data 11
13, 23
50, 81
35, 65
29, 54
29, 54
HIC_D12
I/O
HIC Data 12
15, 41
82, 95
66, 78
55
55
HIC_D13
I/O
HIC Data 13
12, 22
51, 83
36, 67
30, 56
30, 56
HIC_D14
I/O
HIC Data 14
6, 7
84, 97
68, 80
57, 64
57, 64
HIC_D15
I/O
HIC Data 15
14, 5
89, 96
74, 79
61
61
47
HIC_INT
O
HIC Device interrupt to host
12, 18, 32
51, 64, 68
36, 49, 50
30, 40, 41
30, 40, 41
32, 33
HIC_NBE0
I
HIC Byte enable 0
11, 19
52, 69
37, 51
31, 42
31, 42
34
HIC_NBE1
I
HIC Byte enable 1
34, 40, 6
80, 94, 97
64, 77, 80
53, 64
53, 64
48
HIC_NCS
I
HIC Chip select input
29
100
3
1
1
1
HIC_NOE
O
HIC Output enable for data bus
28, 3
1, 76
4, 60
2, 49
2, 49
2, 39
HIC_NRDY
O
HIC Ready from device to host
37, 58, 9
61, 67, 90
46, 75
37, 62
37, 62
29
HIC_NWE
I
HIC Data Write enable from host
10, 35, 4, 46, 52
11, 63, 75, 93
48, 59, 6, 76
39, 48, 63
39, 48, 63
31, 38
I2CA_SCL
I/OD
I2C-A Open-Drain Bidirectional Clock
1, 18, 27, 33, 37,
43, 57, 8
53, 59, 61, 66, 68,
74, 78
38, 44, 46, 50, 54,
58, 62
32, 37, 41, 47, 51
32, 37, 41, 47, 51
25, 29, 33, 41
I2CA_SDA
I/OD
I2C-A Open-Drain Bidirectional Data
10, 19, 26, 32, 35,
42, 56
58, 63, 64, 65, 69,
79, 93
43, 48, 49, 51, 57,
63, 76
39, 40, 42, 52, 63
39, 40, 42, 52, 63
31, 32, 34, 42
I2CB_SCL
I/OD
I2C-B Open-Drain Bidirectional Clock
15, 29, 3, 51, 9
10, 100, 76, 90, 95
3, 60, 75, 78
1, 49, 62
1, 49, 62
1, 39
I2CB_SDA
I/OD
I2C-B Open-Drain Bidirectional Data
14, 2, 28, 34, 50
1, 77, 9, 94, 96
4, 61, 77, 79
2, 50
2, 50
2, 40
23, 29, 33, 35, 42,
47, 49, 59
100, 53, 6, 63, 8,
81, 92
3, 38, 48, 57, 65
1, 32, 39, 54
1, 32, 39, 54
1, 25, 31
LINA_RX
I
LIN-A Receive
42
43, 48
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ADVANCE INFORMATION
Table 5-3. Digital Signals (continued)
SIGNAL NAME
45
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-3. Digital Signals (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
ADVANCE INFORMATION
GPIO PIN
100 PZ PIN
80 PN PIN
64 PM PIN
64 PMQ PIN
48 PT PIN
LINA_TX
O
LIN-A Transmit
22, 28, 32, 37, 46,
58
1, 61, 64, 67, 83
4, 46, 49, 6, 67
2, 37, 40, 56
2, 37, 40, 56
2, 29, 32
LINB_RX
I
LIN-B Receive
11, 13, 15, 19, 23,
41, 55, 9
43, 50, 52, 69, 81,
82, 90, 95
35, 37, 51, 65, 66,
75, 78
29, 31, 42, 54, 55,
62
29, 31, 42, 54, 55,
62
34
LINB_TX
O
LIN-B Transmit
10, 12, 14, 18, 22,
24, 40, 44, 54
13, 51, 56, 68, 80,
83, 85, 93, 96
36, 41, 50, 64, 67,
69, 76, 79
30, 35, 41, 53, 56,
63
30, 35, 41, 53, 56,
63
27, 33
MCAN_RX
I
CAN/CAN FD Receive
12, 21, 30, 39, 47,
5, 51, 57, 61
10, 49, 51, 6, 66,
79, 89, 91, 98
1, 34, 36, 56, 63,
74
30, 46, 52, 61
30, 52, 61
42, 47
MCAN_TX
O
CAN/CAN FD Transmit
1, 13, 20, 31, 4, 46,
50, 56, 60
44, 48, 50, 65, 75,
78, 9, 99
2, 33, 35, 59, 6, 62
29, 48, 51
29, 48, 51
38, 41
OUTPUTXBAR1
O
Output X-BAR Output 1
2, 24, 34, 58
56, 67, 77, 94
41, 61, 77
35, 50
35, 50
27, 40
OUTPUTXBAR2
O
Output X-BAR Output 2
25, 3, 37, 54, 59
13, 57, 61, 76, 92
42, 46, 60
37, 49
37, 49
29, 39
OUTPUTXBAR3
O
Output X-BAR Output 3
14, 26, 4, 48, 5, 55,
60
43, 44, 58, 7, 75,
89, 96
43, 59, 74, 79
48, 61
48, 61
38, 47
OUTPUTXBAR4
O
Output X-BAR Output 4
15, 27, 33, 49, 6,
61
53, 59, 8, 91, 95,
97
38, 44, 78, 80
32, 64
32, 64
25, 48
OUTPUTXBAR5
O
Output X-BAR Output 5
28, 42, 7
1, 84
4, 57, 68
2, 57
2, 57
2, 43
OUTPUTXBAR6
O
Output X-BAR Output 6
29, 43, 9
100, 90
3, 54, 75
1, 62
1, 62
1
OUTPUTXBAR7
O
Output X-BAR Output 7
11, 16, 30, 44
52, 54, 85, 98
1, 37, 39, 69
31, 33
31, 33
26
OUTPUTXBAR8
O
Output X-BAR Output 8
PMBUSA_ALERT
I/OD
17, 31, 45
55, 99
2, 40, 73
34
34
PMBus-A Open-Drain Bidirectional Alert Signal
13, 19, 27, 37, 43,
45
50, 59, 61, 69
35, 44, 46, 51, 54,
73
29, 37, 42
29, 37, 42
29, 34
PMBus-A Control Signal - Slave Input/Master
Output
12, 18, 26, 35, 42,
44
51, 58, 63, 68, 85
36, 43, 48, 50, 57,
69
30, 39, 41
30, 39, 41
31, 33
PMBUSA_CTL
I/O
PMBUSA_SCL
I/OD
PMBus-A Open-Drain Bidirectional Clock
15, 16, 24, 3, 35,
41, 47
54, 56, 6, 63, 76,
82, 95
39, 41, 48, 60, 66,
78
33, 35, 39, 49, 55
33, 35, 39, 49, 55
26, 27, 31, 39
PMBUSA_SDA
I/OD
PMBus-A Open-Drain Bidirectional Data
14, 17, 2, 25, 32,
34, 40, 44, 46, 48
55, 57, 64, 7, 77,
80, 85, 94, 96
40, 42, 49, 6, 61,
64, 69, 77, 79
34, 40, 50, 53
34, 40, 50, 53
32, 40
SCIA_RX
I
SCI-A Receive Data
17, 25, 28, 3, 35,
49, 9
1, 55, 57, 63, 76, 8,
90
4, 40, 42, 48, 60,
75
2, 34, 39, 49, 62
2, 34, 39, 49, 62
2, 31, 39
SCIA_TX
O
SCI-A Transmit Data
16, 2, 24, 29, 37,
48, 8
100, 54, 56, 61, 7,
74, 77
3, 39, 41, 46, 58,
61
1, 33, 35, 37, 47,
50
1, 33, 35, 37, 47,
50
1, 26, 27, 29, 40
SCIB_RX
I
SCI-B Receive Data
11, 13, 15, 19, 23,
41, 57
50, 52, 66, 69, 81,
82, 95
35, 37, 51, 65, 66,
78
29, 31, 42, 54, 55
29, 31, 42, 54, 55
34
SCIB_TX
O
SCI-B Transmit Data
10, 12, 14, 18, 22,
40, 56, 9
51, 65, 68, 80, 83,
90, 93, 96
36, 50, 64, 67, 75,
76, 79
30, 41, 53, 56, 62,
63
30, 41, 53, 56, 62,
63
33
SD1_C1
I
SDFM-1 Channel 1 Clock Input
17, 33, 49, 53
12, 53, 55, 8
38, 40
32, 34
32, 34
25
SD1_C2
I
SDFM-1 Channel 2 Clock Input
19, 33, 51, 54
10, 13, 53, 69
38, 51
32, 42
32, 42
25, 34
SD1_C3
I
SDFM-1 Channel 3 Clock Input
21, 53, 55
12, 43, 49
34
SD1_C4
I
SDFM-1 Channel 4 Clock Input
23, 55, 56
43, 65, 81
65
54
54
SD1_D1
I
SDFM-1 Channel 1 Data Input
16, 48
54, 7
39
33
33
26
SD1_D2
I
SDFM-1 Channel 2 Data Input
18, 32, 50
64, 68, 9
49, 50
40, 41
40, 41
32, 33
SD1_D3
I
SDFM-1 Channel 3 Data Input
20, 52
11, 48
33
SD1_D4
I
SDFM-1 Channel 4 Data Input
22, 54
13, 83
67
56
56
SD2_C1
I
SDFM-2 Channel 1 Clock Input
25, 35, 57
57, 63, 66
42, 48
39
39
46
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Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
PIN TYPE
DESCRIPTION
GPIO PIN
100 PZ PIN
80 PN PIN
SD2_C2
I
SDFM-2 Channel 2 Clock Input
27, 58, 59
59, 67, 92
44
SD2_C3
I
SDFM-2 Channel 3 Clock Input
29, 45, 59, 61
100, 91, 92
3, 73
SD2_C4
I
SDFM-2 Channel 4 Clock Input
31, 46, 60
44, 99
2, 6
SD2_D1
I
SDFM-2 Channel 1 Data Input
24, 49, 56
56, 65, 8
41
SD2_D2
I
SDFM-2 Channel 2 Data Input
26, 50, 58
58, 67, 9
43
SD2_D3
I
SDFM-2 Channel 3 Data Input
28, 43, 51, 60
1, 10, 44
4, 54
SD2_D4
I
SDFM-2 Channel 4 Data Input
30, 47, 52
11, 6, 98
1
64 PM PIN
64 PMQ PIN
48 PT PIN
1
1
1
35
35
27
2
2
2
SPIA_CLK
I/O
SPI-A Clock
12, 18, 3, 56, 9
51, 65, 68, 76, 90
36, 50, 60, 75
30, 41, 49, 62
30, 41, 49, 62
33, 39
SPIA_SIMO
I/O
SPI-A Slave In, Master Out (SIMO)
11, 16, 2, 54, 8
13, 52, 54, 74, 77
37, 39, 58, 61
31, 33, 47, 50
31, 33, 47, 50
26, 40
SPIA_SOMI
I/O
SPI-A Slave Out, Master In (SOMI)
1, 10, 13, 17, 55
43, 50, 55, 78, 93
35, 40, 62, 76
29, 34, 51, 63
29, 34, 51, 63
41
SPIA_STE
I/O
SPI-A Slave Transmit Enable (STE)
11, 19, 5, 57
52, 66, 69, 79, 89
37, 51, 63, 74
31, 42, 52, 61
31, 42, 52, 61
34, 42, 47
SPIB_CLK
I/O
SPI-B Clock
14, 22, 26, 28, 32,
4, 52, 58
1, 11, 58, 64, 67,
75, 83, 96
4, 43, 49, 59, 67,
79
2, 40, 48, 56
2, 40, 48, 56
2, 32, 38
SPIB_SIMO
I/O
SPI-B Slave In, Master Out (SIMO)
20, 24, 30, 40, 50,
56, 60, 7
44, 48, 56, 65, 80,
84, 9, 98
1, 33, 41, 64, 68
35, 53, 57
35, 53, 57
27, 43
SPIB_SOMI
I/O
SPI-B Slave Out, Master In (SOMI)
16, 21, 25, 31, 41,
51, 57, 6, 61
10, 49, 54, 57, 66,
82, 91, 97, 99
2, 34, 39, 42, 66,
80
33, 55, 64
33, 55, 64
26, 48
SPIB_STE
I/O
SPI-B Slave Transmit Enable (STE)
15, 23, 27, 29, 33,
53, 59
100, 12, 53, 59, 81,
92, 95
3, 38, 44, 65, 78
1, 32, 54
1, 32, 54
1, 25
SYNCOUT
O
External ePWM Synchronization Pulse
39, 52, 6
11, 97
56, 80
46, 64
64
48
TDI
I
JTAG Test Data Input (TDI) - TDI is the default mux
selection for the pin. The internal pullup is disabled
by default. The internal pullup should be enabled or
an external pullup added on the board if this pin is
used as JTAG TDI to avoid a floating input.
35
63
48
39
39
31
TDO
O
JTAG Test Data Output (TDO) - TDO is the default
mux selection for the pin. The internal pullup is
disabled by default. The TDO function will tristate
when there is no JTAG activity, leaving this pin
floating; the internal pullup should be enabled or
an external pullup added on the board to avoid a
floating GPIO input.
37
61
46
37
37
29
X1
I/O
Crystal oscillator input or single-ended clock input.
The device initialization software must configure
this pin before the crystal oscillator is enabled. To
use this oscillator, a quartz crystal circuit must be
connected to X1 and X2. This pin can also be used
to feed a single-ended 3.3-V level clock. See the
XTAL section for usage details.
19
69
51
42
42
34
X2
I/O
Crystal oscillator output.
XCLKOUT
O
External Clock Output. This pin outputs a divideddown version of a chosen clock signal from within
the device.
18
68
50
41
41
33
16, 18
54, 68
39, 50
33, 41
33, 41
26, 33
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Product Folder Links: TMS320F280039C TMS320F280037C
ADVANCE INFORMATION
Table 5-3. Digital Signals (continued)
SIGNAL NAME
47
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
5.3.3 Digital Signals by GPIO
Table 5-4. Digital Signals by GPIO
SIGNAL NAME
PIN
TYPE
DESCRIPTION
100 PZ
80 PN
64 PM
64 PMQ
48 PT
ADVANCE INFORMATION
ADCSOCAO
O
ADC Start of Conversion A for External
ADC
GPIO8
GPIO33
GPIO53
GPIO8
GPIO33
GPIO8
GPIO33
GPIO8
GPIO33
GPIO33
ADCSOCBO
O
ADC Start of Conversion B for External
ADC
GPIO10
GPIO32
GPIO54
GPIO10
GPIO32
GPIO10
GPIO32
GPIO10
GPIO32
GPIO32
AUXCLKIN
GPIO29
GPIO29
GPIO29
GPIO29
GPIO29
CANA_RX
CAN-A Receive
GPIO3
GPIO5
GPIO12
GPIO18
GPIO30
GPIO33
GPIO35/
TDI
GPIO49
GPIO53
GPIO59
GPIO61
GPIO3
GPIO5
GPIO12
GPIO18
GPIO30
GPIO33
GPIO35/
TDI
GPIO3
GPIO5
GPIO12
GPIO18
GPIO33
GPIO35/
TDI
GPIO3
GPIO5
GPIO12
GPIO18
GPIO33
GPIO35/
TDI
GPIO3
GPIO5
GPIO18
GPIO33
GPIO35/
TDI
GPIO2
GPIO4
GPIO13
GPIO17
GPIO19
GPIO31
GPIO32
GPIO37/
TDO
GPIO2
GPIO4
GPIO13
GPIO17
GPIO19
GPIO32
GPIO37/
TDO
GPIO2
GPIO4
GPIO13
GPIO17
GPIO19
GPIO32
GPIO37/
TDO
GPIO2
GPIO4
GPIO19
GPIO32
GPIO37/
TDO
I
CANA_TX
O
CAN-A Transmit
GPIO2
GPIO4
GPIO13
GPIO17
GPIO19
GPIO31
GPIO32
GPIO37/
TDO
GPIO48
GPIO58
CLB_OUTPUTXBAR1
O
CLB Output X-BAR Output 1
GPIO19
GPIO22
GPIO19
GPIO22
GPIO19
GPIO22
GPIO19
GPIO22
GPIO19
CLB_OUTPUTXBAR2
O
CLB Output X-BAR Output 2
GPIO7
GPIO47
GPIO7
GPIO39
GPIO7
GPIO39
GPIO7
GPIO7
CLB_OUTPUTXBAR3
O
CLB Output X-BAR Output 3
GPIO23
GPIO44
GPIO23
GPIO42
GPIO44
GPIO23
GPIO23
CLB_OUTPUTXBAR4
O
CLB Output X-BAR Output 4
GPIO10
GPIO10
GPIO43
GPIO45
GPIO10
GPIO10
CLB_OUTPUTXBAR5
O
CLB Output X-BAR Output 5
GPIO5
GPIO8
GPIO52
GPIO5
GPIO8
GPIO5
GPIO8
GPIO5
GPIO8
GPIO5
CLB_OUTPUTXBAR6
O
CLB Output X-BAR Output 6
GPIO4
GPIO15
GPIO53
GPIO4
GPIO15
GPIO4
GPIO4
GPIO4
CLB_OUTPUTXBAR7
O
CLB Output X-BAR Output 7
GPIO1
GPIO14
GPIO56
GPIO1
GPIO14
GPIO1
GPIO1
GPIO1
CLB_OUTPUTXBAR8
O
CLB Output X-BAR Output 8
GPIO0
GPIO6
GPIO57
GPIO0
GPIO6
GPIO0
GPIO6
GPIO0
GPIO6
GPIO0
GPIO6
EPWM1_A
O
ePWM-1 Output A
GPIO0
GPIO30
GPIO0
GPIO30
GPIO0
GPIO0
GPIO0
EPWM1_B
O
ePWM-1 Output B
GPIO1
GPIO31
GPIO1
GPIO31
GPIO1
GPIO1
GPIO1
48
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www.ti.com
SPRSP61 – OCTOBER 2021
SIGNAL NAME
DESCRIPTION
100 PZ
80 PN
64 PM
64 PMQ
48 PT
EPWM2_A
O
ePWM-2 Output A
GPIO2
GPIO41
GPIO2
GPIO41
GPIO2
GPIO41
GPIO2
GPIO41
GPIO2
EPWM2_B
O
ePWM-2 Output B
GPIO3
GPIO40
GPIO3
GPIO40
GPIO3
GPIO40
GPIO3
GPIO40
GPIO3
EPWM3_A
O
ePWM-3 Output A
GPIO4
GPIO14
GPIO4
GPIO14
GPIO4
GPIO4
GPIO4
EPWM3_B
O
ePWM-3 Output B
GPIO5
GPIO15
GPIO5
GPIO15
GPIO5
GPIO5
GPIO5
EPWM4_A
O
ePWM-4 Output A
GPIO6
GPIO22
GPIO6
GPIO22
GPIO6
GPIO22
GPIO6
GPIO22
GPIO6
EPWM4_B
O
ePWM-4 Output B
GPIO7
GPIO23
GPIO7
GPIO23
GPIO7
GPIO23
GPIO7
GPIO23
GPIO7
EPWM5_A
O
ePWM-5 Output A
GPIO8
GPIO16
GPIO8
GPIO16
GPIO8
GPIO16
GPIO8
GPIO16
GPIO16
GPIO9
GPIO17
GPIO35/
TDI
GPIO9
GPIO17
GPIO35/
TDI
GPIO9
GPIO17
GPIO35/
TDI
GPIO35/
TDI
EPWM5_B
O
ePWM-5 Output B
GPIO9
GPIO17
GPIO35/
TDI
EPWM6_A
O
ePWM-6 Output A
GPIO10
GPIO18
GPIO10
GPIO18
GPIO10
GPIO18
GPIO10
GPIO18
GPIO18
EPWM6_B
O
ePWM-6 Output B
GPIO11
GPIO19
GPIO11
GPIO19
GPIO11
GPIO19
GPIO11
GPIO19
GPIO19
EPWM7_A
O
ePWM-7 Output A
GPIO12
GPIO28
GPIO12
GPIO28
GPIO12
GPIO28
GPIO12
GPIO28
GPIO28
EPWM7_B
O
ePWM-7 Output B
GPIO13
GPIO29
GPIO13
GPIO29
GPIO13
GPIO29
GPIO13
GPIO29
GPIO29
EPWM8_A
O
ePWM-8 Output A
GPIO14
GPIO24
GPIO14
GPIO24
GPIO24
GPIO24
GPIO24
EPWM8_B
O
ePWM-8 Output B
GPIO15
GPIO32
GPIO15
GPIO32
GPIO32
GPIO32
GPIO32
eQEP-1 Input A
GPIO6
GPIO10
GPIO20
GPIO25
GPIO28
GPIO35/
TDI
GPIO40
GPIO44
GPIO50
GPIO56
GPIO6
GPIO10
GPIO20
GPIO25
GPIO28
GPIO35/
TDI
GPIO40
GPIO44
GPIO6
GPIO10
GPIO28
GPIO35/
TDI
GPIO40
GPIO6
GPIO10
GPIO28
GPIO35/
TDI
GPIO40
GPIO6
GPIO28
GPIO35/
TDI
eQEP-1 Input B
GPIO7
GPIO11
GPIO21
GPIO29
GPIO37/
TDO
GPIO41
GPIO51
GPIO57
GPIO7
GPIO11
GPIO21
GPIO29
GPIO37/
TDO
GPIO41
GPIO7
GPIO11
GPIO29
GPIO37/
TDO
GPIO41
GPIO7
GPIO11
GPIO29
GPIO37/
TDO
GPIO41
GPIO7
GPIO29
GPIO37/
TDO
EQEP1_A
EQEP1_B
I
I
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Product Folder Links: TMS320F280039C TMS320F280037C
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ADVANCE INFORMATION
Table 5-4. Digital Signals by GPIO (continued)
PIN
TYPE
49
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-4. Digital Signals by GPIO (continued)
SIGNAL NAME
EQEP1_INDEX
EQEP1_STROBE
ADVANCE INFORMATION
EQEP2_A
EQEP2_B
PIN
TYPE
I/O
I/O
I
I
DESCRIPTION
100 PZ
80 PN
64 PM
64 PMQ
48 PT
eQEP-1 Index
GPIO0
GPIO9
GPIO13
GPIO17
GPIO23
GPIO31
GPIO53
GPIO59
GPIO0
GPIO9
GPIO13
GPIO17
GPIO23
GPIO31
GPIO39
GPIO43
GPIO0
GPIO9
GPIO13
GPIO17
GPIO23
GPIO39
GPIO0
GPIO9
GPIO13
GPIO17
GPIO23
GPIO0
eQEP-1 Strobe
GPIO8
GPIO12
GPIO16
GPIO22
GPIO30
GPIO52
GPIO58
GPIO8
GPIO12
GPIO16
GPIO22
GPIO30
GPIO42
GPIO8
GPIO12
GPIO16
GPIO22
GPIO8
GPIO12
GPIO16
GPIO22
GPIO16
eQEP-2 Input A
GPIO11
GPIO14
GPIO18
GPIO24
GPIO54
GPIO11
GPIO14
GPIO18
GPIO24
GPIO11
GPIO18
GPIO24
GPIO11
GPIO18
GPIO24
GPIO18
GPIO24
eQEP-2 Input B
GPIO15
GPIO16
GPIO19
GPIO25
GPIO33
GPIO55
GPIO15
GPIO16
GPIO19
GPIO25
GPIO33
GPIO16
GPIO19
GPIO33
GPIO16
GPIO19
GPIO33
GPIO16
GPIO19
GPIO33
EQEP2_INDEX
I/O
eQEP-2 Index
GPIO26
GPIO29
GPIO57
GPIO26
GPIO29
GPIO39
GPIO29
GPIO39
GPIO29
GPIO29
EQEP2_STROBE
I/O
eQEP-2 Strobe
GPIO4
GPIO27
GPIO28
GPIO56
GPIO4
GPIO27
GPIO28
GPIO4
GPIO28
GPIO4
GPIO28
GPIO4
GPIO28
O
Error Status Output. This signal requires an
external pulldown.
GPIO24
GPIO28
GPIO29
GPIO55
GPIO24
GPIO28
GPIO29
GPIO24
GPIO28
GPIO29
GPIO24
GPIO28
GPIO29
GPIO24
GPIO28
GPIO29
FSIRX-A Input Clock
GPIO0
GPIO4
GPIO13
GPIO30
GPIO33
GPIO54
GPIO57
GPIO0
GPIO4
GPIO13
GPIO30
GPIO33
GPIO39
GPIO0
GPIO4
GPIO13
GPIO33
GPIO39
GPIO0
GPIO4
GPIO13
GPIO33
GPIO0
GPIO4
GPIO33
FSIRX-A Primary Data Input
GPIO3
GPIO12
GPIO32
GPIO40
GPIO44
GPIO52
GPIO58
GPIO3
GPIO12
GPIO32
GPIO40
GPIO44
GPIO3
GPIO12
GPIO32
GPIO40
GPIO3
GPIO12
GPIO32
GPIO40
GPIO3
GPIO32
FSIRX-A Optional Additional Data Input
GPIO2
GPIO11
GPIO31
GPIO41
GPIO53
GPIO56
GPIO2
GPIO11
GPIO31
GPIO41
GPIO2
GPIO11
GPIO41
GPIO2
GPIO11
GPIO41
GPIO2
ERRORSTS
FSIRXA_CLK
FSIRXA_D0
FSIRXA_D1
50
I
I
I
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Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
SIGNAL NAME
DESCRIPTION
100 PZ
80 PN
64 PM
64 PMQ
48 PT
GPIO7
GPIO10
GPIO27
GPIO44
GPIO7
GPIO10
GPIO7
GPIO10
GPIO7
FSITXA_CLK
O
FSITX-A Output Clock
GPIO7
GPIO10
GPIO27
GPIO44
GPIO51
FSITXA_D0
O
FSITX-A Primary Data Output
GPIO6
GPIO9
GPIO26
GPIO49
GPIO6
GPIO9
GPIO26
GPIO45
GPIO6
GPIO9
GPIO6
GPIO9
GPIO6
GPIO5
GPIO6
GPIO8
GPIO25
GPIO46
GPIO5
GPIO6
GPIO8
GPIO5
GPIO6
GPIO8
GPIO5
GPIO6
FSITXA_D1
O
FSITX-A Optional Additional Data Output
GPIO5
GPIO6
GPIO8
GPIO25
GPIO50
FSITXA_TDM_CLK
I
FSITX-A Time Division Multiplexed Clock
Input
GPIO8
GPIO18
GPIO47
GPIO8
GPIO18
GPIO8
GPIO18
GPIO8
GPIO18
GPIO18
FSITXA_TDM_D0
I
FSITX-A Time Division Multiplexed Data
Input
GPIO10
GPIO19
GPIO10
GPIO19
GPIO10
GPIO19
GPIO10
GPIO19
GPIO19
FSITXA_TDM_D1
I
FSITX-A Time Division Multiplexed
Additional Data Input
GPIO1
GPIO54
GPIO59
GPIO1
GPIO1
GPIO1
GPIO1
GPIO8
A6
GPIO8
A6
GPIO8
A6
A6
GPIO2
GPIO26
B2/C6
GPIO2
B2/C6
GPIO2
B2/C6
GPIO2
B2/C6
HIC_A0
I
HIC Address 0
GPIO8
GPIO55
GPIO60
A6
HIC_A1
I
HIC Address 1
GPIO2
GPIO26
B2/C6
HIC_A2
I
HIC Address 2
GPIO1
GPIO1
GPIO1
GPIO1
GPIO1
B3/VDAC B3/VDAC B3/VDAC B3/VDAC B3/VDAC
HIC_A3
I
HIC Address 3
GPIO23 GPIO23 GPIO23 GPIO23
A2/B6/C9
A2/B6/C9 A2/B6/C9 A2/B6/C9 A2/B6/C9
HIC_A4
I
HIC Address 4
GPIO27
GPIO41
HIC_A5
I
HIC Address 5
GPIO22 GPIO22 GPIO22 GPIO22
A14/B14/ A14/B14/ A14/B14/ A14/B14/
C4
C4
C4
C4
GPIO27
GPIO41
A15
GPIO41
A15
GPIO41
A15
A15
HIC_A6
I
HIC Address 6
GPIO7
GPIO7
GPIO7
GPIO7
GPIO7
GPIO47 GPIO42
A11/B10/ A11/B10/ A11/B10/
A11/B10/ A11/B10/
C0
C0
C0
C0
C0
HIC_A7
I
HIC Address 7
GPIO5
GPIO48
C2/B12
HIC Base address range select 0
GPIO9
GPIO9
GPIO9
GPIO9
GPIO25 GPIO25
A1/B7/
A1/B7/
A1/B7/
A1/B7/
A1/B7/
DACB_O
DACB_O DACB_O
DACB_O DACB_O
UT
UT
UT
UT
UT
HIC Base address range select 1
GPIO0
GPIO0
GPIO0
GPIO0
GPIO0
A0/B15/C A0/B15/C A0/B15/C A0/B15/C A0/B15/C
15/
15/
15/
15/
15/
DACA_O DACA_O DACA_O DACA_O DACA_O
UT
UT
UT
UT
UT
HIC_BASESEL0
HIC_BASESEL1
I
I
GPIO5
GPIO43
C2/B12
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F280039C TMS320F280037C
GPIO5
C2/B12
GPIO5
C2/B12
ADVANCE INFORMATION
Table 5-4. Digital Signals by GPIO (continued)
PIN
TYPE
GPIO5
C2/B12
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SPRSP61 – OCTOBER 2021
Table 5-4. Digital Signals by GPIO (continued)
SIGNAL NAME
HIC_BASESEL2
PIN
TYPE
I
DESCRIPTION
HIC Base address range select 2
100 PZ
80 PN
64 PM
64 PMQ
48 PT
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
A10/B1/C A10/B1/C A10/B1/C A10/B1/C A10/B1/C
10
10
10
10
10
ADVANCE INFORMATION
HIC_D0
I/O
HIC Data 0
GPIO26
GPIO33
GPIO26
GPIO33
GPIO33
GPIO33
GPIO33
HIC_D1
I/O
HIC Data 1
GPIO16
GPIO27
GPIO16
GPIO27
GPIO16
GPIO16
GPIO16
HIC_D10
I/O
HIC Data 10
GPIO1
GPIO31
GPIO1
GPIO31
GPIO1
GPIO1
GPIO1
HIC_D11
I/O
HIC Data 11
GPIO13
GPIO23
GPIO13
GPIO23
GPIO13
GPIO23
GPIO13
GPIO23
HIC_D12
I/O
HIC Data 12
GPIO15
GPIO41
GPIO15
GPIO41
GPIO41
GPIO41
HIC_D13
I/O
HIC Data 13
GPIO12
GPIO22
GPIO12
GPIO22
GPIO12
GPIO22
GPIO12
GPIO22
HIC_D14
I/O
HIC Data 14
GPIO6
GPIO7
GPIO6
GPIO7
GPIO6
GPIO7
GPIO6
GPIO7
GPIO6
GPIO7
HIC_D15
I/O
HIC Data 15
GPIO5
GPIO14
GPIO5
GPIO14
GPIO5
GPIO5
GPIO5
HIC_D2
I/O
HIC Data 2
GPIO17
GPIO49
GPIO17
GPIO42
GPIO17
GPIO17
HIC_D3
I/O
HIC Data 3
GPIO24
GPIO50
GPIO24
GPIO43
GPIO24
GPIO24
GPIO24
HIC_D4
I/O
HIC Data 4
GPIO3
GPIO5
GPIO57
GPIO3
GPIO5
GPIO3
GPIO5
GPIO3
GPIO5
GPIO3
GPIO5
HIC_D5
I/O
HIC Data 5
GPIO13
GPIO40
GPIO44
GPIO13
GPIO40
GPIO44
GPIO13
GPIO40
GPIO13
GPIO40
HIC_D6
I/O
HIC Data 6
GPIO11
GPIO51
GPIO56
GPIO11
GPIO45
GPIO11
GPIO11
HIC_D7
I/O
HIC Data 7
GPIO0
GPIO44
GPIO0
GPIO39
GPIO44
GPIO0
GPIO39
GPIO0
HIC_D8
I/O
HIC Data 8
GPIO8
GPIO30
GPIO8
GPIO30
GPIO8
GPIO8
HIC_D9
I/O
HIC Data 9
GPIO2
GPIO34
GPIO2
GPIO34
GPIO2
GPIO2
GPIO2
HIC_INT
O
HIC Device interrupt to host
GPIO12
GPIO18
GPIO32
GPIO12
GPIO18
GPIO32
GPIO12
GPIO18
GPIO32
GPIO12
GPIO18
GPIO32
GPIO18
GPIO32
HIC_NBE0
I
HIC Byte enable 0
GPIO11
GPIO19
A9
GPIO11
GPIO19
A9
GPIO11
GPIO19
A9
GPIO11
GPIO19
A9
GPIO19
A9
GPIO6
GPIO34
GPIO40
A8
GPIO6
GPIO40
A8
GPIO6
GPIO40
A8
GPIO6
A8
GPIO0
HIC_NBE1
I
HIC Byte enable 1
GPIO6
GPIO34
GPIO40
A8
HIC_NCS
I
HIC Chip select input
GPIO29
A12
GPIO29
A12
GPIO29
A12
GPIO29
A12
GPIO29
A12
HIC_NOE
O
HIC Output enable for data bus
GPIO3
GPIO28
C3/A7
GPIO3
GPIO28
C3/A7
GPIO3
GPIO28
C3/A7
GPIO3
GPIO28
C3/A7
GPIO3
GPIO28
C3/A7
52
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Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
SIGNAL NAME
HIC_NRDY
HIC_NWE
I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
LINA_RX
LINA_TX
LINB_RX
O
I
I/OD
I/OD
I/OD
I/OD
I
O
I
DESCRIPTION
100 PZ
80 PN
64 PM
64 PMQ
48 PT
HIC Ready from device to host
GPIO9
GPIO37/
TDO
GPIO58
GPIO9
GPIO37/
TDO
GPIO9
GPIO37/
TDO
GPIO9
GPIO37/
TDO
GPIO37/
TDO
HIC Data Write enable from host
GPIO4
GPIO10
GPIO35/
TDI
GPIO52
A4/B8
GPIO4
GPIO10
GPIO35/
TDI
GPIO46
A4/B8
GPIO4
GPIO10
GPIO35/
TDI
A4/B8
GPIO4
GPIO10
GPIO35/
TDI
A4/B8
GPIO4
GPIO35/
TDI
A4/B8
I2C-A Open-Drain Bidirectional Clock
GPIO1
GPIO8
GPIO18
GPIO27
GPIO33
GPIO37/
TDO
GPIO57
GPIO1
GPIO8
GPIO18
GPIO27
GPIO33
GPIO37/
TDO
GPIO43
GPIO1
GPIO8
GPIO18
GPIO33
GPIO37/
TDO
GPIO1
GPIO8
GPIO18
GPIO33
GPIO37/
TDO
GPIO1
GPIO18
GPIO33
GPIO37/
TDO
I2C-A Open-Drain Bidirectional Data
GPIO0
GPIO10
GPIO19
GPIO26
GPIO32
GPIO35/
TDI
GPIO56
GPIO0
GPIO10
GPIO19
GPIO26
GPIO32
GPIO35/
TDI
GPIO42
GPIO0
GPIO10
GPIO19
GPIO32
GPIO35/
TDI
GPIO0
GPIO10
GPIO19
GPIO32
GPIO35/
TDI
GPIO0
GPIO19
GPIO32
GPIO35/
TDI
I2C-B Open-Drain Bidirectional Clock
GPIO3
GPIO9
GPIO15
GPIO29
GPIO51
GPIO3
GPIO9
GPIO15
GPIO29
GPIO3
GPIO9
GPIO29
GPIO3
GPIO9
GPIO29
GPIO3
GPIO29
I2C-B Open-Drain Bidirectional Data
GPIO2
GPIO14
GPIO28
GPIO34
GPIO50
GPIO2
GPIO14
GPIO28
GPIO34
GPIO2
GPIO28
GPIO2
GPIO28
GPIO2
GPIO28
LIN-A Receive
GPIO23
GPIO29
GPIO33
GPIO35/
TDI
GPIO47
GPIO49
GPIO59
GPIO23
GPIO29
GPIO33
GPIO35/
TDI
GPIO42
GPIO23
GPIO29
GPIO33
GPIO35/
TDI
GPIO23
GPIO29
GPIO33
GPIO35/
TDI
GPIO29
GPIO33
GPIO35/
TDI
LIN-A Transmit
GPIO22
GPIO28
GPIO32
GPIO37/
TDO
GPIO58
GPIO22
GPIO28
GPIO32
GPIO37/
TDO
GPIO46
GPIO22
GPIO28
GPIO32
GPIO37/
TDO
GPIO22
GPIO28
GPIO32
GPIO37/
TDO
GPIO28
GPIO32
GPIO37/
TDO
LIN-B Receive
GPIO9
GPIO11
GPIO13
GPIO15
GPIO19
GPIO23
GPIO41
GPIO55
GPIO9
GPIO11
GPIO13
GPIO15
GPIO19
GPIO23
GPIO41
GPIO9
GPIO11
GPIO13
GPIO19
GPIO23
GPIO41
GPIO9
GPIO11
GPIO13
GPIO19
GPIO23
GPIO41
GPIO19
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F280039C TMS320F280037C
Submit Document Feedback
ADVANCE INFORMATION
Table 5-4. Digital Signals by GPIO (continued)
PIN
TYPE
53
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SPRSP61 – OCTOBER 2021
Table 5-4. Digital Signals by GPIO (continued)
SIGNAL NAME
LINB_TX
ADVANCE INFORMATION
MCAN_RX
MCAN_TX
OUTPUTXBAR1
OUTPUTXBAR2
OUTPUTXBAR3
PIN
TYPE
O
I
O
O
O
O
DESCRIPTION
100 PZ
80 PN
64 PM
64 PMQ
48 PT
LIN-B Transmit
GPIO10
GPIO12
GPIO14
GPIO18
GPIO22
GPIO24
GPIO40
GPIO44
GPIO54
GPIO10
GPIO12
GPIO14
GPIO18
GPIO22
GPIO24
GPIO40
GPIO44
GPIO10
GPIO12
GPIO18
GPIO22
GPIO24
GPIO40
GPIO10
GPIO12
GPIO18
GPIO22
GPIO24
GPIO40
GPIO18
GPIO24
CAN/CAN FD Receive
GPIO0
GPIO5
GPIO12
GPIO21
GPIO30
GPIO47
GPIO51
GPIO57
GPIO61
GPIO0
GPIO5
GPIO12
GPIO21
GPIO30
GPIO39
GPIO0
GPIO5
GPIO12
GPIO39
GPIO0
GPIO5
GPIO12
GPIO0
GPIO5
CAN/CAN FD Transmit
GPIO1
GPIO4
GPIO13
GPIO20
GPIO31
GPIO50
GPIO56
GPIO60
GPIO1
GPIO4
GPIO13
GPIO20
GPIO31
GPIO46
GPIO1
GPIO4
GPIO13
GPIO1
GPIO4
GPIO13
GPIO1
GPIO4
Output X-BAR Output 1
GPIO2
GPIO24
GPIO34
GPIO58
GPIO2
GPIO24
GPIO34
GPIO2
GPIO24
GPIO2
GPIO24
GPIO2
GPIO24
Output X-BAR Output 2
GPIO3
GPIO25
GPIO37/
TDO
GPIO54
GPIO59
GPIO3
GPIO25
GPIO37/
TDO
GPIO3
GPIO37/
TDO
GPIO3
GPIO37/
TDO
GPIO3
GPIO37/
TDO
Output X-BAR Output 3
GPIO4
GPIO5
GPIO14
GPIO26
GPIO48
GPIO55
GPIO60
GPIO4
GPIO5
GPIO14
GPIO26
GPIO4
GPIO5
GPIO4
GPIO5
GPIO4
GPIO5
GPIO6
GPIO15
GPIO27
GPIO33
GPIO6
GPIO33
GPIO6
GPIO33
GPIO6
GPIO33
OUTPUTXBAR4
O
Output X-BAR Output 4
GPIO6
GPIO15
GPIO27
GPIO33
GPIO49
GPIO61
OUTPUTXBAR5
O
Output X-BAR Output 5
GPIO7
GPIO28
GPIO7
GPIO28
GPIO42
GPIO7
GPIO28
GPIO7
GPIO28
GPIO7
GPIO28
OUTPUTXBAR6
O
Output X-BAR Output 6
GPIO9
GPIO29
GPIO9
GPIO29
GPIO43
GPIO9
GPIO29
GPIO9
GPIO29
GPIO29
OUTPUTXBAR7
O
Output X-BAR Output 7
GPIO11
GPIO16
GPIO30
GPIO44
GPIO11
GPIO16
GPIO30
GPIO44
GPIO11
GPIO16
GPIO11
GPIO16
GPIO16
54
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Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-4. Digital Signals by GPIO (continued)
OUTPUTXBAR8
PMBUSA_ALERT
PMBUSA_CTL
PMBUSA_SCL
PMBUSA_SDA
SCIA_RX
SCIA_TX
SCIB_RX
O
I/OD
I/O
I/OD
I/OD
I
O
I
DESCRIPTION
100 PZ
80 PN
64 PM
64 PMQ
Output X-BAR Output 8
GPIO17
GPIO31
GPIO17
GPIO31
GPIO45
GPIO17
GPIO17
PMBus-A Open-Drain Bidirectional Alert
Signal
GPIO13
GPIO19
GPIO27
GPIO37/
TDO
GPIO13
GPIO19
GPIO27
GPIO37/
TDO
GPIO43
GPIO45
GPIO13
GPIO19
GPIO37/
TDO
GPIO13
GPIO19
GPIO37/
TDO
GPIO19
GPIO37/
TDO
PMBus-A Control Signal - Slave Input/
Master Output
GPIO12
GPIO18
GPIO26
GPIO35/
TDI
GPIO44
GPIO12
GPIO18
GPIO26
GPIO35/
TDI
GPIO42
GPIO44
GPIO12
GPIO18
GPIO35/
TDI
GPIO12
GPIO18
GPIO35/
TDI
GPIO18
GPIO35/
TDI
PMBus-A Open-Drain Bidirectional Clock
GPIO3
GPIO15
GPIO16
GPIO24
GPIO35/
TDI
GPIO41
GPIO47
GPIO3
GPIO15
GPIO16
GPIO24
GPIO35/
TDI
GPIO41
GPIO3
GPIO16
GPIO24
GPIO35/
TDI
GPIO41
GPIO3
GPIO16
GPIO24
GPIO35/
TDI
GPIO41
GPIO3
GPIO16
GPIO24
GPIO35/
TDI
PMBus-A Open-Drain Bidirectional Data
GPIO2
GPIO14
GPIO17
GPIO25
GPIO32
GPIO34
GPIO40
GPIO44
GPIO48
GPIO2
GPIO14
GPIO17
GPIO25
GPIO32
GPIO34
GPIO40
GPIO44
GPIO46
GPIO2
GPIO17
GPIO32
GPIO40
GPIO2
GPIO17
GPIO32
GPIO40
GPIO2
GPIO32
SCI-A Receive Data
GPIO3
GPIO9
GPIO17
GPIO25
GPIO28
GPIO35/
TDI
GPIO49
GPIO3
GPIO9
GPIO17
GPIO25
GPIO28
GPIO35/
TDI
GPIO3
GPIO9
GPIO17
GPIO28
GPIO35/
TDI
GPIO3
GPIO9
GPIO17
GPIO28
GPIO35/
TDI
GPIO3
GPIO28
GPIO35/
TDI
SCI-A Transmit Data
GPIO2
GPIO8
GPIO16
GPIO24
GPIO29
GPIO37/
TDO
GPIO48
GPIO2
GPIO8
GPIO16
GPIO24
GPIO29
GPIO37/
TDO
GPIO2
GPIO8
GPIO16
GPIO24
GPIO29
GPIO37/
TDO
GPIO2
GPIO8
GPIO16
GPIO24
GPIO29
GPIO37/
TDO
GPIO2
GPIO16
GPIO24
GPIO29
GPIO37/
TDO
SCI-B Receive Data
GPIO11
GPIO13
GPIO15
GPIO19
GPIO23
GPIO41
GPIO57
GPIO11
GPIO13
GPIO15
GPIO19
GPIO23
GPIO41
GPIO11
GPIO13
GPIO19
GPIO23
GPIO41
GPIO11
GPIO13
GPIO19
GPIO23
GPIO41
GPIO19
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F280039C TMS320F280037C
48 PT
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ADVANCE INFORMATION
SIGNAL NAME
PIN
TYPE
55
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-4. Digital Signals by GPIO (continued)
SIGNAL NAME
SCIB_TX
SD1_C1
ADVANCE INFORMATION
SD1_C2
SD1_C3
SD1_C4
SD1_D1
PIN
TYPE
O
I
I
I
I
I
DESCRIPTION
SCI-B Transmit Data
SDFM-1 Channel 1 Clock Input
100 PZ
80 PN
64 PM
64 PMQ
48 PT
GPIO9
GPIO10
GPIO12
GPIO14
GPIO18
GPIO22
GPIO40
GPIO56
GPIO9
GPIO10
GPIO12
GPIO14
GPIO18
GPIO22
GPIO40
GPIO9
GPIO10
GPIO12
GPIO18
GPIO22
GPIO40
GPIO9
GPIO10
GPIO12
GPIO18
GPIO22
GPIO40
GPIO18
GPIO17
GPIO33 GPIO17 GPIO17 GPIO17
GPIO33
GPIO49 GPIO33 GPIO33 GPIO33
A0/B15/C
GPIO53 A0/B15/C A0/B15/C A0/B15/C
15/
A0/B15/C
15/
15/
15/
DACA_O
15/
DACA_O DACA_O DACA_O
UT
DACA_O
UT
UT
UT
UT
SDFM-1 Channel 2 Clock Input
GPIO19
GPIO33
GPIO51
GPIO54
C3/A7
GPIO19
GPIO33
C3/A7
GPIO19
GPIO33
C3/A7
GPIO19
GPIO33
C3/A7
GPIO19
GPIO33
C3/A7
SDFM-1 Channel 3 Clock Input
GPIO21
GPIO53
GPIO55
A9
GPIO21
A9
A9
A9
A9
SDFM-1 Channel 4 Clock Input
GPIO23
GPIO55 GPIO23 GPIO23 GPIO23
A10/B1/C
GPIO56 A10/B1/C A10/B1/C A10/B1/C
10
A10/B1/C
10
10
10
10
SDFM-1 Channel 1 Data Input
GPIO16
GPIO16 GPIO16 GPIO16
GPIO48
A14/B14/ A14/B14/ A14/B14/
A14/B14/
C4
C4
C4
C4
GPIO16
SD1_D2
I
SDFM-1 Channel 2 Data Input
GPIO18
GPIO18 GPIO18 GPIO18 GPIO18
GPIO32
GPIO32 GPIO32 GPIO32 GPIO32
GPIO50
A11/B10/ A11/B10/ A11/B10/ A11/B10/
A11/B10/
C0
C0
C0
C0
C0
SD1_D3
I
SDFM-1 Channel 3 Data Input
GPIO20
GPIO52
C2/B12
SDFM-1 Channel 4 Data Input
GPIO22
GPIO22 GPIO22 GPIO22
GPIO54
A1/B7/
A1/B7/
A1/B7/
A1/B7/
A1/B7/
DACB_O
DACB_O DACB_O DACB_O
DACB_O
UT
UT
UT
UT
UT
GPIO25
GPIO35/
TDI
A6
A8
GPIO35/
TDI
A6
A8
GPIO35/
TDI
A6
A8
GPIO35/
TDI
A6
A8
GPIO27
A4/B8
A4/B8
A4/B8
A4/B8
SD1_D4
I
SD2_C1
I
SDFM-2 Channel 1 Clock Input
GPIO25
GPIO35/
TDI
GPIO57
A6
A8
SD2_C2
I
SDFM-2 Channel 2 Clock Input
GPIO27
GPIO58
GPIO59
A4/B8
56
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GPIO20
C2/B12
C2/B12
C2/B12
C2/B12
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
SIGNAL NAME
DESCRIPTION
100 PZ
80 PN
64 PM
64 PMQ
48 PT
GPIO29
A12
GPIO29
A12
GPIO29
A12
GPIO24
A15
GPIO24
A15
GPIO24
A15
SD2_C3
I
SDFM-2 Channel 3 Clock Input
GPIO29
GPIO59
GPIO61
A12
GPIO29
GPIO45
A12
SD2_C4
I
SDFM-2 Channel 4 Clock Input
GPIO31
GPIO60
B5
GPIO31
GPIO46
SD2_D1
I
SDFM-2 Channel 1 Data Input
GPIO24
GPIO49
GPIO56
GPIO24
A15
SD2_D2
I
SDFM-2 Channel 2 Data Input
GPIO26
GPIO50 GPIO26
B3/VDAC B3/VDAC B3/VDAC
GPIO58 B3/VDAC
B3/VDAC
SD2_D3
I
SDFM-2 Channel 3 Data Input
GPIO28
GPIO28
GPIO51
GPIO28 GPIO28 GPIO28
GPIO43
GPIO60
A2/B6/C9 A2/B6/C9 A2/B6/C9
A2/B6/C9
A2/B6/C9
SD2_D4
SPIA_CLK
SPIA_SIMO
SPIA_SOMI
SPIA_STE
SPIB_CLK
SPIB_SIMO
I
I/O
I/O
I/O
I/O
I/O
I/O
SDFM-2 Channel 4 Data Input
GPIO30
GPIO47
GPIO52
B2/C6
GPIO30
B2/C6
B2/C6
B2/C6
B2/C6
SPI-A Clock
GPIO3
GPIO9
GPIO12
GPIO18
GPIO56
GPIO3
GPIO9
GPIO12
GPIO18
GPIO3
GPIO9
GPIO12
GPIO18
GPIO3
GPIO9
GPIO12
GPIO18
GPIO3
GPIO18
SPI-A Slave In, Master Out (SIMO)
GPIO2
GPIO8
GPIO11
GPIO16
GPIO54
GPIO2
GPIO8
GPIO11
GPIO16
GPIO2
GPIO8
GPIO11
GPIO16
GPIO2
GPIO8
GPIO11
GPIO16
GPIO2
GPIO16
SPI-A Slave Out, Master In (SOMI)
GPIO1
GPIO10
GPIO13
GPIO17
GPIO55
GPIO1
GPIO10
GPIO13
GPIO17
GPIO1
GPIO10
GPIO13
GPIO17
GPIO1
GPIO10
GPIO13
GPIO17
GPIO1
SPI-A Slave Transmit Enable (STE)
GPIO0
GPIO5
GPIO11
GPIO19
GPIO57
GPIO0
GPIO5
GPIO11
GPIO19
GPIO0
GPIO5
GPIO11
GPIO19
GPIO0
GPIO5
GPIO11
GPIO19
GPIO0
GPIO5
GPIO19
SPI-B Clock
GPIO4
GPIO14
GPIO22
GPIO26
GPIO28
GPIO32
GPIO52
GPIO58
GPIO4
GPIO14
GPIO22
GPIO26
GPIO28
GPIO32
GPIO4
GPIO22
GPIO28
GPIO32
GPIO4
GPIO22
GPIO28
GPIO32
GPIO4
GPIO28
GPIO32
SPI-B Slave In, Master Out (SIMO)
GPIO7
GPIO20
GPIO24
GPIO30
GPIO40
GPIO50
GPIO56
GPIO60
GPIO7
GPIO20
GPIO24
GPIO30
GPIO40
GPIO7
GPIO24
GPIO40
GPIO7
GPIO24
GPIO40
GPIO7
GPIO24
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F280039C TMS320F280037C
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ADVANCE INFORMATION
Table 5-4. Digital Signals by GPIO (continued)
PIN
TYPE
57
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SPRSP61 – OCTOBER 2021
Table 5-4. Digital Signals by GPIO (continued)
SIGNAL NAME
SPIB_SOMI
PIN
TYPE
I/O
DESCRIPTION
ADVANCE INFORMATION
100 PZ
80 PN
64 PM
64 PMQ
48 PT
SPI-B Slave Out, Master In (SOMI)
GPIO6
GPIO16
GPIO21
GPIO25
GPIO31
GPIO41
GPIO51
GPIO57
GPIO61
GPIO6
GPIO16
GPIO21
GPIO25
GPIO31
GPIO41
GPIO6
GPIO16
GPIO41
GPIO6
GPIO16
GPIO41
GPIO6
GPIO16
GPIO15
GPIO23
GPIO27
GPIO29
GPIO33
GPIO23
GPIO29
GPIO33
GPIO23
GPIO29
GPIO33
GPIO29
GPIO33
SPIB_STE
I/O
SPI-B Slave Transmit Enable (STE)
GPIO15
GPIO23
GPIO27
GPIO29
GPIO33
GPIO53
GPIO59
SYNCOUT
O
External ePWM Synchronization Pulse
GPIO6
GPIO52
GPIO6
GPIO39
GPIO6
GPIO39
GPIO6
GPIO6
I
JTAG Test Data Input (TDI) - TDI is the
default mux selection for the pin. The
internal pullup is disabled by default. The
internal pullup should be enabled or an
external pullup added on the board if this
pin is used as JTAG TDI to avoid a floating
input.
GPIO35/
TDI
GPIO35/
TDI
GPIO35/
TDI
GPIO35/
TDI
GPIO35/
TDI
O
JTAG Test Data Output (TDO) - TDO is
the default mux selection for the pin. The
internal pullup is disabled by default. The
TDO function will tristate when there is no
GPIO37/
JTAG activity, leaving this pin floating; the
TDO
internal pullup should be enabled or an
external pullup added on the board to avoid
a floating GPIO input.
GPIO37/
TDO
GPIO37/
TDO
GPIO37/
TDO
GPIO37/
TDO
X1
I/O
Crystal oscillator input or single-ended
clock input. The device initialization
software must configure this pin before the
crystal oscillator is enabled. To use this
oscillator, a quartz crystal circuit must be
connected to X1 and X2. This pin can
also be used to feed a single-ended 3.3-V
level clock. See the XTAL section for usage
details.
GPIO19
GPIO19
GPIO19
GPIO19
GPIO19
X2
I/O
Crystal oscillator output.
GPIO18
GPIO18
GPIO18
GPIO18
GPIO18
XCLKOUT
O
External Clock Output. This pin outputs a
divided-down version of a chosen clock
signal from within the device.
GPIO16
GPIO18
GPIO16
GPIO18
GPIO16
GPIO18
GPIO16
GPIO18
GPIO16
GPIO18
TDI
TDO
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5.3.4 Power and Ground
Table 5-5. Power and Ground
PIN TYPE
100 PZ PIN
80 PN PIN
64 PM PIN
64 PMQ PIN
48 PT PIN
VDD
1.2-V Digital Logic Power Pins. See
the PMM section for usage details.
4, 46, 71, 87
31, 53, 71, 8
27, 4, 44, 59
27, 4, 44, 59
23, 36, 45
VDDA
3.3-V Analog Power Pins. Place
a minimum 2.2-µF decoupling
capacitor on each pin. See the PMM
section for usage details.
34
26
22
22
18
VDDIO
3.3-V Digital I/O Power Pins. See the
PMM section for usage details.
3, 47, 70, 88
32, 52, 7, 72
28, 43, 60
28, 43, 60
24, 35, 46
Internal voltage regulator disable with
internal pulldown. Tie low to VSS to
enable internal VREG. Tie high to
VDDIO to use an external supply.
See the PMM section for usage
details.
73
VREGENZ
I
DESCRIPTION
GPIO PIN
46
VSS
Digital Ground
45, 5, 72, 86
30, 55, 70, 9
26, 45, 5, 58
26, 45, 5, 58
22, 37, 44
VSSA
Analog Ground
33
25
21
21
17
ADVANCE INFORMATION
SIGNAL NAME
5.3.5 Test, JTAG, and Reset
Table 5-6. Test, JTAG, and Reset
SIGNAL NAME
100 PZ
80 PN
64 PM
64 PMQ
48 PT
JTAG test clock with internal
pullup.
60
45
36
36
28
I/O
JTAG test-mode select
(TMS) with internal pullup.
This serial control input
is clocked into the TAP
controller on the rising edge
of TCK. This device does
not have a TRSTn pin.
An external pullup resistor
(recommended 2.2 kΩ) on
the TMS pin to VDDIO
should be placed on the
board to keep JTAG in reset
during normal operation.
62
47
38
38
30
X1
I/O
Crystal oscillator input or
single-ended clock input.
The device initialization
software must configure
this pin before the crystal
oscillator is enabled. To
use this oscillator, a quartz
crystal circuit must be
connected to X1 and X2.
This pin can also be used
to feed a single-ended 3.3-V
level clock.
69
51
42
42
34
X2
I/O
Crystal oscillator output.
68
50
41
41
33
TCK
TMS
PIN TYPE
DESCRIPTION
I
GPIO
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Table 5-6. Test, JTAG, and Reset (continued)
SIGNAL NAME
ADVANCE INFORMATION
XRSn
60
PIN TYPE
DESCRIPTION
I/OD
Device Reset (in) and
Watchdog Reset (out).
During a power-on condition,
this pin is driven low by the
device. An external circuit
may also drive this pin to
assert a device reset. This
pin is also driven low by the
MCU when a watchdog reset
occurs. During watchdog
reset, the XRSn pin is driven
low for the watchdog reset
duration of 512 OSCCLK
cycles. A resistor between
2.2 kΩ and 10 kΩ should
be placed between XRSn
and VDDIO. If a capacitor is
placed between XRSn and
VSS for noise filtering, it
should be 100 nF or smaller.
These values will allow
the watchdog to properly
drive the XRSn pin to VOL
within 512 OSCCLK cycles
when the watchdog reset
is asserted. This pin is an
open-drain output with an
internal pullup.
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GPIO
100 PZ
80 PN
64 PM
64 PMQ
48 PT
2
5
3
3
3
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5.4 Pin Multiplexing
5.4.1 GPIO Muxed Pins
Section 5.4.1.1 lists the GPIO muxed pins. The default mode for each GPIO pin is the GPIO function, except
GPIO35 and GPIO37, which default to TDI and TDO, respectively. Secondary functions can be selected by
setting both the GPyGMUXn.GPIOz and GPyMUXn.GPIOz register bits. The GPyGMUXn register should be
configured before the GPyMUXn to avoid transient pulses on GPIOs from alternate mux selections. Columns
that are not shown and blank cells are reserved GPIO Mux settings. GPIO ALT functions cannot be configured
with the GPyMUXn and GPyGMUXn registers. These are special functions that need to be configured from the
module.
Note
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ADVANCE INFORMATION
GPIO36 and GPIO38 do not exist on this device. GPIO62 to GPIO63 exist but are not pinned out on
any packages. Boot ROM enables pullups on GPIO62 to GPIO63. For more details, see Section 5.5.
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5.4.1.1 GPIO Muxed Pins
Table 5-7. GPIO Muxed Pins
0, 4, 8, 12
7
9
10
11
13
14
15
GPIO0
EPWM1_A
I2CA_SDA
SPIA_STE
FSIRXA_CLK
MCAN_RX
CLB_OUTPUTX
BAR8
EQEP1_INDEX
HIC_D7
HIC_BASESEL1
GPIO1
EPWM1_B
I2CA_SCL
SPIA_SOMI
MCAN_TX
CLB_OUTPUTX
BAR7
HIC_A2
FSITXA_TDM_D
1
HIC_D10
GPIO2
EPWM2_A
OUTPUTXBAR1
PMBUSA_SDA
SPIA_SIMO
SCIA_TX
FSIRXA_D1
I2CB_SDA
HIC_A1
CANA_TX
HIC_D9
GPIO3
EPWM2_B
OUTPUTXBAR2
PMBUSA_SCL
SPIA_CLK
SCIA_RX
FSIRXA_D0
I2CB_SCL
HIC_NOE
CANA_RX
HIC_D4
SPIB_CLK
EQEP2_STROB
E
FSIRXA_CLK
CLB_OUTPUTX
BAR6
HIC_BASESEL2
SPIA_STE
FSITXA_D1
CLB_OUTPUTX
BAR5
GPIO4
1
2
OUTPUTXBAR2
EPWM3_A
ADVANCE INFORMATION
GPIO5
EPWM3_B
GPIO6
EPWM4_A
GPIO7
EPWM4_B
GPIO8
EPWM5_A
GPIO9
EPWM5_B
3
MCAN_TX
OUTPUTXBAR4
SCIB_TX
CANA_TX
MCAN_RX
SYNCOUT
EQEP1_A
SPIB_SOMI
FSITXA_D0
OUTPUTXBAR5
EQEP1_B
SPIB_SIMO
FSITXA_CLK
ADCSOCAO
EQEP1_STROB
E
SCIA_TX
SPIA_SIMO
OUTPUTXBAR6
EQEP1_INDEX
SCIA_RX
SPIA_CLK
CANA_RX
I2CA_SCL
FSITXA_D1
CLB_OUTPUTX
BAR2
HIC_A7
HIC_D4
HIC_D15
HIC_NBE1
CLB_OUTPUTX
BAR8
HIC_D14
HIC_A6
HIC_D14
FSITXA_D1
CLB_OUTPUTX
BAR5
FSITXA_TDM_C
LK
HIC_A0
FSITXA_D0
LINB_RX
HIC_BASESEL0
I2CB_SCL
HIC_NRDY
CLB_OUTPUTX
BAR4
HIC_D8
EQEP1_A
SCIB_TX
SPIA_SOMI
I2CA_SDA
FSITXA_CLK
LINB_TX
HIC_NWE
OUTPUTXBAR7
EQEP1_B
SCIB_RX
SPIA_STE
FSIRXA_D1
LINB_RX
EQEP2_A
SPIA_SIMO
HIC_D6
HIC_NBE0
MCAN_RX
EQEP1_STROB
E
SCIB_TX
PMBUSA_CTL
FSIRXA_D0
LINB_TX
SPIA_CLK
CANA_RX
HIC_D13
HIC_INT
EQEP1_INDEX
SCIB_RX
PMBUSA_ALER
T
FSIRXA_CLK
LINB_RX
SPIA_SOMI
CANA_TX
HIC_D11
HIC_D5
ADCSOCBO
GPIO11
EPWM6_B
MCAN_TX
ALT
HIC_NWE
FSITXA_TDM_D
0
EPWM6_A
EPWM7_A
OUTPUTXBAR3
6
OUTPUTXBAR3
GPIO10
GPIO12
5
GPIO13
EPWM7_B
GPIO14
EPWM8_A
SCIB_TX
I2CB_SDA
OUTPUTXBAR3
PMBUSA_SDA
SPIB_CLK
EQEP2_A
LINB_TX
EPWM3_A
CLB_OUTPUTX
BAR7
HIC_D15
GPIO15
EPWM8_B
SCIB_RX
I2CB_SCL
OUTPUTXBAR4
PMBUSA_SCL
SPIB_STE
EQEP2_B
LINB_RX
EPWM3_B
CLB_OUTPUTX
BAR6
HIC_D12
PMBUSA_SCL
XCLKOUT
EQEP2_B
SPIB_SOMI
HIC_D1
PMBUSA_SDA
CANA_TX
HIC_INT
X2
X1
GPIO16
SPIA_SIMO
OUTPUTXBAR7
EPWM5_A
SCIA_TX
SD1_D1
EQEP1_STROB
E
GPIO17
SPIA_SOMI
OUTPUTXBAR8
EPWM5_B
SCIA_RX
SD1_C1
EQEP1_INDEX
HIC_D2
GPIO18
SPIA_CLK
SCIB_TX
CANA_RX
EPWM6_A
I2CA_SCL
SD1_D2
EQEP2_A
PMBUSA_CTL
XCLKOUT
LINB_TX
FSITXA_TDM_C
LK
GPIO19
SPIA_STE
SCIB_RX
CANA_TX
EPWM6_B
I2CA_SDA
SD1_C2
EQEP2_B
PMBUSA_ALER
T
CLB_OUTPUTX
BAR1
LINB_RX
FSITXA_TDM_D
0
HIC_NBE0
GPIO20
EQEP1_A
SPIB_SIMO
SD1_D3
MCAN_TX
GPIO21
EQEP1_B
SPIB_SOMI
SD1_C3
MCAN_RX
GPIO22
EQEP1_STROB
E
SCIB_TX
SPIB_CLK
SD1_D4
LINA_TX
CLB_OUTPUTX
BAR1
LINB_TX
HIC_A5
EPWM4_A
HIC_D13
GPIO23
EQEP1_INDEX
SCIB_RX
SPIB_STE
SD1_C4
LINA_RX
CLB_OUTPUTX
BAR3
LINB_RX
HIC_A3
EPWM4_B
HIC_D11
GPIO24
OUTPUTXBAR1
EQEP2_A
EPWM8_A
SPIB_SIMO
SD2_D1
LINB_TX
PMBUSA_SCL
SCIA_TX
ERRORSTS
GPIO25
OUTPUTXBAR2
EQEP2_B
EQEP1_A
SPIB_SOMI
SD2_C1
FSITXA_D1
PMBUSA_SDA
SCIA_RX
HIC_BASESEL0
GPIO26
OUTPUTXBAR3
EQEP2_INDEX
OUTPUTXBAR3
SPIB_CLK
SD2_D2
FSITXA_D0
PMBUSA_CTL
I2CA_SDA
HIC_D0
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HIC_D3
HIC_A1
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SPRSP61 – OCTOBER 2021
Table 5-7. GPIO Muxed Pins (continued)
1
2
GPIO27
OUTPUTXBAR4
EQEP2_STROB
E
GPIO28
SCIA_RX
GPIO29
GPIO30
3
5
6
7
9
10
11
I2CA_SCL
13
14
15
HIC_D1
HIC_A4
OUTPUTXBAR4
SPIB_STE
SD2_C2
FSITXA_CLK
PMBUSA_ALER
T
EPWM7_A
OUTPUTXBAR5
EQEP1_A
SD2_D3
EQEP2_STROB
E
LINA_TX
SPIB_CLK
ERRORSTS
I2CB_SDA
HIC_NOE
SCIA_TX
EPWM7_B
OUTPUTXBAR6
EQEP1_B
SD2_C3
EQEP2_INDEX
LINA_RX
SPIB_STE
ERRORSTS
I2CB_SCL
HIC_NCS
CANA_RX
SPIB_SIMO
OUTPUTXBAR7
EQEP1_STROB
E
SD2_D4
FSIRXA_CLK
MCAN_RX
EPWM1_A
GPIO31
CANA_TX
SPIB_SOMI
OUTPUTXBAR8
EQEP1_INDEX
SD2_C4
FSIRXA_D1
MCAN_TX
EPWM1_B
GPIO32
I2CA_SDA
SPIB_CLK
EPWM8_B
LINA_TX
SD1_D2
FSIRXA_D0
CANA_TX
PMBUSA_SDA
ADCSOCBO
GPIO33
I2CA_SCL
SPIB_STE
OUTPUTXBAR4
LINA_RX
SD1_C2
FSIRXA_CLK
CANA_RX
EQEP2_B
ADCSOCAO
SD1_C1
HIC_D0
GPIO34
OUTPUTXBAR1
HIC_NBE1
I2CB_SDA
HIC_D9
GPIO35
SCIA_RX
SD2_C1
HIC_NWE
TDI
HIC_NRDY
TDO
SYNCOUT
EQEP1_INDEX
HIC_D7
HIC_NBE1
HIC_D5
HIC_A4
SPIB_SOMI
HIC_D12
HIC_D2
HIC_A6
GPIO37
PMBUSA_SDA
I2CA_SDA
OUTPUTXBAR2
I2CA_SCL
CANA_RX
SCIA_TX
PMBUSA_SCL
LINA_RX
EQEP1_A
PMBUSA_CTL
PMBUSA_ALER
T
EPWM5_B
HIC_D10
HIC_INT
LINA_TX
EQEP1_B
MCAN_RX
FSIRXA_CLK
EQEP2_INDEX
EPWM2_B
PMBUSA_SDA
FSIRXA_D0
SCIB_TX
EQEP1_A
LINB_TX
EPWM2_A
PMBUSA_SCL
FSIRXA_D1
SCIB_RX
EQEP1_B
LINB_RX
OUTPUTXBAR5
PMBUSA_CTL
I2CA_SDA
EQEP1_STROB
E
CLB_OUTPUTX
BAR3
GPIO43
OUTPUTXBAR6
PMBUSA_ALER
T
I2CA_SCL
PMBUSA_ALER
T
EQEP1_INDEX
CLB_OUTPUTX
BAR4
SD2_D3
HIC_D3
HIC_A7
GPIO44
OUTPUTXBAR7
EQEP1_A
PMBUSA_SDA
FSITXA_CLK
PMBUSA_CTL
CLB_OUTPUTX
BAR3
FSIRXA_D0
HIC_D7
LINB_TX
HIC_D5
GPIO45
OUTPUTXBAR8
FSITXA_D0
PMBUSA_ALER
T
CLB_OUTPUTX
BAR4
GPIO46
LINA_TX
MCAN_TX
FSITXA_D1
PMBUSA_SDA
MCAN_RX
CLB_OUTPUTX
BAR2
PMBUSA_SCL
GPIO40
SPIB_SIMO
GPIO41
GPIO42
LINA_RX
GPIO47
LINA_RX
CLB_OUTPUTX
BAR2
SD2_C3
HIC_D6
SD2_C4
HIC_NWE
SD2_D4
FSITXA_TDM_C
LK
HIC_A6
FSITXA_D0
HIC_D2
GPIO48
OUTPUTXBAR3
CANA_TX
SCIA_TX
SD1_D1
PMBUSA_SDA
GPIO49
OUTPUTXBAR4
CANA_RX
SCIA_RX
SD1_C1
LINA_RX
SD2_D1
GPIO50
EQEP1_A
MCAN_TX
SPIB_SIMO
SD1_D2
I2CB_SDA
SD2_D2
FSITXA_D1
HIC_D3
GPIO51
EQEP1_B
MCAN_RX
SPIB_SOMI
SD1_C2
I2CB_SCL
SD2_D3
FSITXA_CLK
HIC_D6
GPIO52
EQEP1_STROB
E
CLB_OUTPUTX
BAR5
SPIB_CLK
SD1_D3
SYNCOUT
SD2_D4
FSIRXA_D0
HIC_NWE
GPIO53
EQEP1_INDEX
CLB_OUTPUTX
BAR6
SPIB_STE
SD1_C3
ADCSOCAO
CANA_RX
SD1_C1
FSIRXA_D1
GPIO54
SPIA_SIMO
EQEP2_A
OUTPUTXBAR2
SD1_D4
ADCSOCBO
LINB_TX
SD1_C2
FSIRXA_CLK
GPIO55
SPIA_SOMI
SD1_C3
GPIO56
SPIA_CLK
CLB_OUTPUTX
BAR7
GPIO57
SPIA_STE
CLB_OUTPUTX
BAR8
AUX
CLKI
N
HIC_D8
CANA_TX
GPIO39
ALT
ADVANCE INFORMATION
0, 4, 8, 12
HIC_A7
EQEP2_B
OUTPUTXBAR3
SD1_C4
ERRORSTS
LINB_RX
MCAN_TX
EQEP2_STROB
E
SCIB_TX
SD2_D1
SPIB_SIMO
I2CA_SDA
EQEP1_A
MCAN_RX
EQEP2_INDEX
SCIB_RX
SD2_C1
SPIB_SOMI
I2CA_SCL
EQEP1_B
SD1_C4
FSITXA_TDM_D
1
HIC_A0
FSIRXA_D1
HIC_D6
FSIRXA_CLK
HIC_D4
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Table 5-7. GPIO Muxed Pins (continued)
0, 4, 8, 12
1
2
3
5
6
7
9
10
11
13
14
15
SD2_C2
FSIRXA_D0
HIC_NRDY
SD2_C3
FSITXA_TDM_D
1
GPIO58
OUTPUTXBAR1
SPIB_CLK
SD2_D2
LINA_TX
CANA_TX
EQEP1_STROB
E
GPIO59
OUTPUTXBAR2
SPIB_STE
SD2_C2
LINA_RX
CANA_RX
EQEP1_INDEX
GPIO60
MCAN_TX
OUTPUTXBAR3
SPIB_SIMO
SD2_D3
GPIO61
MCAN_RX
OUTPUTXBAR4
SPIB_SOMI
SD2_C3
SD2_C4
ALT
HIC_A0
CANA_RX
AIO224
SD2_D3
HIC_A3
AIO225
SD2_C2
HIC_NWE
AIO226
SD2_D4
HIC_A1
AIO227
SD1_C3
HIC_NBE0
AIO228
SD2_C1
HIC_A0
AIO230
SD1_C4
HIC_BASESEL2
AIO231
SD1_C1
HIC_BASESEL1
AIO232
SD1_D4
HIC_BASESEL0
AIO233
SD2_D1
HIC_A4
AIO229
ADVANCE INFORMATION
AIO236
AIO237
SD1_D2
HIC_A6
AIO238
SD2_C3
HIC_NCS
AIO239
SD1_D1
HIC_A5
AIO240
SD2_C1
HIC_NBE1
AIO241
SD2_C1
HIC_NBE1
AIO242
SD2_D2
HIC_A2
AIO244
SD1_D3
HIC_A7
AIO245
SD1_C2
HIC_NOE
AIO247
AIO248
AIO249
AIO251
AIO252
SD2_C4
AIO253
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5.4.2 Digital Inputs on ADC Pins (AIOs)
GPIOs on port H (GPIO224–GPIO253) are multiplexed with analog pins. These are also referred to as AIOs.
These pins can only function in input mode. By default, these pins will function as analog pins and the GPIOs are
in a high-Z state. The GPHAMSEL register is used to configure these pins for digital or analog operation.
Note
If digital signals with sharp edges (high dv/dt) are connected to the AIOs, cross-talk can occur with
adjacent analog signals. The user should therefore limit the edge rate of signals connected to AIOs if
adjacent channels are being used for analog functions.
5.4.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
ADVANCE INFORMATION
Some GPIOs on this device are multiplexed with analog pins. These are also referred to as AGPIOs. Unlike
AIOs, AGPIOs have full input and output capability. This device has two GPIOs (GPIO20, GPIO21) that offer this
feature on the 100-Pin PZ and 80-Pin PN packages.
100-Pin PZ: On this package, there are dedicated pins for B5 (pin 32) and B11 (pin 30) which respectively also
have AIO252 and AIO251 functionality. In addition, GPIO20 (pin 48) and GPIO21 (pin 49) are also available as
B5 and B11 respectively. Since B5 and B11 are dedicated pins on this package, it is recommended to use them
instead of the ones on GPIO20/21.
80-Pin PN: On this package, GPIO20 (pin 33) and GPIO21 (pin 34) are also available as B5 and B11
respectively. There are no dedicated pin for B5 and B11.
By default the AGPIOs are not connected and have to be configured. Table 5-8 truth table shows how to
configure the AGPIOs using B5 (pin 32) and GPIO20 (pin 48) on the 100-Pin PZ as an example.
Table 5-8. AGPIO Configuration
AGPIOCTRLA.bit.GPIO20
GPAAMSEL.bit.GPIO20
GPHAMSEL.bit.GPIO252
0
0
0
B5 CONNECTED TO
GPIO20 CONNECTED TO
ADC
GPIO20
AIO252
ADC
GPIO20
AIO252
1
Yes
-
-
-
Yes
-
1
1
Yes
-
-
-
-
-
1
0
1
Yes
-
-
-
Yes
-
1
1
1
-
-
-
Yes
-
-
0
0
0
Yes
-
Yes
-
Yes
-
0
1
0
Yes
-
Yes
-
-
-
1
0
0
Yes
-
Yes
-
Yes
-
1
1
0
-
-
Yes
Yes
-
-
Note
If digital signals with sharp edges (high dv/dt) are connected to the AGPIOs, cross-talk can occur with
adjacent analog signals. The user should therefore limit the edge rate of signals connected to AGPIOs
if adjacent channels are being used for analog functions.
5.4.4 GPIO Input X-BAR
The Input X-BAR is used to route signals from a GPIO to many different IP blocks such as the ADCs, eCAPs,
ePWMs, and external interrupts (see Figure 5-6). Table 5-9 lists the input X-BAR destinations.
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GPIO0
GPIOx
Asynchronous
Synchronous
Sync. + Qual.
Input X-BAR
Other Sources
127:16
INPUT[16:1]
eCAP
Modules
INPUT16
INPUT15
INPUT14
INPUT13
INPUT12
INPUT11
INPUT10
INPUT9
INPUT8
INPUT7
INPUT6
INPUT5
INPUT4
INPUT3
INPUT2
INPUT1
15:0
DCCx Clock Source-1
TZ1,TRIP1
TZ2,TRIP2
TZ3,TRIP3
TRIP6
DCCx Clock Source-0
ADVANCE INFORMATION
XINT1
XINT2
XINT3
XINT4
XINT5
CPU PIE
CLA
TRIP4
TRIP5
ePWM
Modules
TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12
ePWM
X-BAR
Other
Sources
ADCEXTSOC
ADC
EXTSYNCIN1
ePWM and eCAP
Sync Scheme
EXTSYNCIN2
Other Sources
INPUT[1:16]
ERAD
INPUT[13:16]
EPG
Output X-BAR
Figure 5-6. Input X-BAR
Table 5-9. Input X-BAR Destinations
INPUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ECAP / HRCAP
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
EPWM X-BAR
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
CLB X-BAR
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
OUTPUT X-BAR
Yes
Yes
Yes
Yes
Yes
Yes
XINT1
XINT2
XINT3
CPU XINT
EPWM TRIP
TZ1, TZ2, TZ3,
TRIP1 TRIP2 TRIP3
XINT4 XINT5
TRIP6
ADC START OF
CONVERSION
ADCEX
TSOC
EPWM / ECAP
SYNC
EXTSY
NCIN1
EXTSY
NCIN2
CLK CLK
0
0
DCCx
EPG1 EPG1 EPG1 EPG1
IN1
IN2
IN3
IN4
EPG
ERAD
66
CLK1 CLK0
Yes
Yes
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Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
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5.4.5 GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
ADVANCE INFORMATION
The Output X-BAR has eight outputs that can be selected on the GPIO mux as OUTPUTXBARx. The CLB
X-BAR has eight outputs that are connected to the CLB global mux as AUXSIGx. The CLB Output X-BAR has
eight outputs that can be selected on the GPIO mux as CLB_OUTPUTXBARx. The ePWM X-BAR has eight
outputs that are connected to the TRIPx inputs of the ePWM. The sources for the Output X-BAR, CLB X-BAR,
CLB Output X-BAR, and ePWM X-BAR are shown in Figure 5-7.
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CMPSSx
ePWM and eCAP
Sync Chain
CTRIPOUTH
CTRIPOUTL
(Output X-BAR only)
CTRIPH
CTRIPL
(ePWM X-BAR only)
EXTSYNCOUT
ADVANCE INFORMATION
ADCSOCA0
Select Circuit
ADCSOCA0
ADCSOCB0
Select Circuit
ADCSOCB0
eCAPx
ECAPxOUT
ADCx
EVT1
EVT2
EVT3
EVT4
Input X-BAR
CLAHALT
CLB
X-BAR
CLB
Global
Mux
TRIP4
TRIP5
TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12
EPWM
X-BAR
INPUT1-6
INPUT7-14
(ePWM X-BAR only)
All
ePWM
Modules
eQEPx
CLAHALT
FLT1.COMPH
FLT1.COMPL
SDFMx
AUXSIG1
AUXSIG2
AUXSIG3
AUXSIG4
AUXSIG5
AUXSIG6
AUXSIG7
AUXSIG8
OUTPUTXBAR1
OUTPUTXBAR2
OUTPUTXBAR3
OUTPUTXBAR4
OUTPUTXBAR5
OUTPUTXBAR6
OUTPUTXBAR7
OUTPUTXBAR8
Output
X-BAR
FLT4.COMPH
FLT4.COMPL
GPIO
Mux
X-BAR Flags
(shared)
CLB Input X-BAR
CLB TILEx
CLB_OUTPUTXBAR1
CLB_OUTPUTXBAR2
CLB_OUTPUTXBAR3
CLB_OUTPUTXBAR4
CLB_OUTPUTXBAR5
CLB_OUTPUTXBAR6
CLB_OUTPUTXBAR7
CLB_OUTPUTXBAR8
CLB
Output
X-BAR
Figure 5-7. Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR Sources
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5.5 Pins With Internal Pullup and Pulldown
Some pins on the device have internal pullups or pulldowns. Table 5-10 lists the pull direction and when it is
active. The pullups on GPIO pins are disabled by default and can be enabled through software. To avoid any
floating unbonded inputs, the Boot ROM will enable internal pullups on GPIO pins that are not bonded out in
a particular package. Other pins noted in Table 5-10 with pullups and pulldowns are always on and cannot be
disabled.
Table 5-10. Pins With Internal Pullup and Pulldown
GPIOx
RESET
(XRSn = 0)
DEVICE BOOT
APPLICATION
Pullup disabled
Pullup disabled(1)
Application defined
GPIO35/TDI
Pullup disabled
GPIO37/TDO
Application defined
Pullup disabled
AGPIOx
Pullup disabled
Application defined
Pullup disabled
TCK
Pullup active
TMS
Pullup active
XRSn
Application defined
Pullup active
Other pins (including AIOs)
(1)
ADVANCE INFORMATION
PIN
No pullup or pulldown present
Pins not bonded out in a given package will have the internal pullups enabled by the Boot ROM.
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5.6 Connections for Unused Pins
For applications that do not need to use all functions of the device, Table 5-11 lists acceptable conditioning for
any unused pins. When multiple options are listed in Table 5-11, any option is acceptable. Pins not listed in Table
5-11 must be connected according to Section 5.
Table 5-11. Connections for Unused Pins
SIGNAL NAME
ACCEPTABLE PRACTICE
ANALOG
ADVANCE INFORMATION
VREFHI
Tie to VDDA (applies only if ADC is not used in the application)
VREFLO
Tie to VSSA
Analog input pins with
DACx_OUT
•
•
No Connect
Tie to VSSA through 4.7-kΩ or larger resistor
Analog input pins (except
DACx_OUT)
•
•
•
No Connect
Tie to VSSA
Tie to VSSA through resistor
Analog input pins (shared with
GPIOs)(1)
•
•
•
No connection (digital input mode with internal pullup enabled)
No connection (digital output mode with internal pullup disabled)
Pullup or pulldown resistor (any value resistor, digital input mode, and with internal pullup disabled)
DIGITAL
GPIOx
•
•
•
No connection (input mode with internal pullup enabled)
No connection (output mode with internal pullup disabled)
Pullup or pulldown resistor (any value resistor, input mode, and with internal pullup disabled)
When TDI mux option is selected (default), the GPIO is in Input mode.
GPIO35/TDI
•
•
Internal pullup enabled
External pullup resistor
When TDO mux option is selected (default), the GPIO is in Output mode only during JTAG activity;
otherwise, it is in a tri-state condition. The pin must be biased to avoid extra current on the input buffer.
GPIO37/TDO
•
•
Internal pullup enabled
External pullup resistor
TCK
•
•
No Connect
Pullup resistor
TMS
Pullup resistor
Turn XTAL off and:
GPIO19/X1
•
•
•
Input mode with internal pullup enabled
Input mode with external pullup or pulldown resistor
Output mode with internal pullup disabled
Turn XTAL off and:
GPIO18/X2
•
•
•
Input mode with internal pullup enabled
Input mode with external pullup or pulldown resistor
Output mode with internal pullup disabled
POWER AND GROUND
VDD
All VDD pins must be connected per Section 5.3. Pins should not be used to bias any external circuits.
VDDA
If a dedicated analog supply is not used, tie to VDDIO.
VDDIO
All VDDIO pins must be connected per Section 5.3.
VSS
All VSS pins must be connected to board ground.
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Table 5-11. Connections for Unused Pins (continued)
SIGNAL NAME
VSSA
AGPIO pins share analog and digital functionality. The actions here only apply if these pins are also not being used for analog
functions.
ADVANCE INFORMATION
(1)
ACCEPTABLE PRACTICE
If an analog ground is not used, tie to VSS.
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6 Specifications
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only and functional operation of the device beyond the Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability. All voltage values are with respect to VSS, unless otherwise noted.
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VDDIO with respect to VSS
–0.3
4.6
VDDA with respect to VSSA
–0.3
4.6
VDD with respect to VSS
–0.3
1.5
Input voltage
VIN (3.3 V)
–0.3
4.6
V
Output voltage
VO
–0.3
4.6
V
Digital/analog input (per pin), IIK (VIN < VSS/VSSA or VIN > VDDIO/
VDDA)(2)
–20
20
Total for all inputs, IIKTOTAL
(VIN < VSS/VSSA or VIN > VDDIO/VDDA)
–20
20
Output current
Digital output (per pin), IOUT
–20
20
mA
Free-Air temperature
TA
–40
125
°C
Operating junction temperature
TJ
–40
150
°C
Tstg
–65
150
°C
Supply voltage
ADVANCE INFORMATION
Input clamp current
Storage
(1)
(2)
temperature(1)
UNIT
V
mA
Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device
life. For additional information, see the Semiconductor and IC Package Thermal Metrics Application Report.
Continuous clamp current per pin is ±2 mA. Do not operate in this condition continuously as VDDIO/VDDA voltage may internally rise and
impact other electrical specifications.
6.2 ESD Ratings – Commercial
VALUE
UNIT
F280039C, F280039, F280037C, F280037, F280034, F280033 in 100-pin PZ package
V(ESD)
Electrostatic discharge (ESD)
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±2000
Charged-device model (CDM), per ANSI/ESDA/JEDEC
JS-002(2)
±500
V
F280039C, F280039, F280037C, F280037, F280034, F280033 in 80-pin PN package
V(ESD)
Electrostatic discharge (ESD)
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±2000
Charged-device model (CDM), per ANSI/ESDA/JEDEC
JS-002(2)
±500
V
F280039C, F280039, F280037C, F280037, F280034, F280033 in 64-pin PM package
V(ESD)
Electrostatic discharge (ESD)
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±2000
Charged-device model (CDM), per ANSI/ESDA/JEDEC
JS-002(2)
±500
V
F280037C, F280037, F280034, F280033 in 48-pin PT package
V(ESD)
(1)
(2)
72
Electrostatic discharge (ESD)
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±2000
Charged-device model (CDM), per ANSI/ESDA/JEDEC
JS-002(2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 ESD Ratings – Automotive
VALUE
UNIT
F280039C-Q1, F280039-Q1, F280037C-Q1, F280037-Q1 in 100-pin PZ package
V(ESD)
Electrostatic discharge
Human body model (HBM), per
AEC Q100-002(1)
All pins
±2000
Charged device model (CDM),
per AEC Q100-011
All pins
±500
Corner pins on 100-pin PZ:
1, 25, 26, 50, 51, 75, 76, 100
±750
Human body model (HBM), per
AEC Q100-002(1)
All pins
±2000
Charged device model (CDM),
per AEC Q100-011
All pins
±500
Corner pins on 64-pin PM:
1, 16, 17, 32, 33, 48, 49, 64
±750
Human body model (HBM), per
AEC Q100-002(1)
All pins
±2000
Charged device model (CDM),
per AEC Q100-011
All pins
±500
Corner pins on 48-pin PT:
1, 12, 13, 24, 25, 36, 37, 48
±750
V
F280038C-Q1, F280038-Q1, F280036C-Q1, F280036-Q1 in 64-pin PM package
Electrostatic discharge
V
ADVANCE INFORMATION
V(ESD)
F280037C-Q1, F280037-Q1, F280034-Q1 in 48-pin PT package
V(ESD)
(1)
Electrostatic discharge
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.4 Recommended Operating Conditions
Internal BOR
Device supply voltage, VDDIO and VDDA
enabled(3)
Internal BOR disabled
MIN
NOM
MAX
VBOR-VDDIO(MAX) + VBOR-VDDIO-GB
(2)
3.3
3.63
2.8
3.3
3.63
Device ground, VSS
Analog ground, VSSA
UNIT
V
0
V
0
V
Supply ramp rate(4)
SRSUPPLY
Digital input voltage
VSS – 0.3
VDDIO + 0.3
VSSA – 0.3
VDDA + 0.3
V
Junction temperature, TJ (1)
–40
150
°C
Free-Air temperature, TA
–40
125
°C
VIN
(1)
(2)
(3)
(4)
Analog input voltage
V
Operation above TJ = 105°C for extended duration will reduce the lifetime of the device. See Calculating Useful Lifetimes of Embedded
Processors for more information.
See the Power Management Module (PMM) section.
Internal BOR is enabled by default.
See the Power Management Module Operating Conditions table.
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6.5 Power Consumption Summary
Current values listed in this section are representative for the test conditions given and not the absolute
maximum possible. The actual device currents in an application will vary with application code and pin
configurations. Section 6.5.1 lists the system current consumption values. Section 6.5.2 lists the system current
consumption with VREG disabled.
6.5.1 System Current Consumption
over operating free-air temperature range (unless otherwise noted).
TYP : Vnom, 30℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
78.5
106
mA
3
6.5
mA
28.2
47.4
mA
0.01
0.1
mA
13.9
31.3
mA
0.01
0.1
mA
OPERATING MODE
ADVANCE INFORMATION
IDDIO
VDDIO current consumption during
operational usage
IDDA
VDDA current consumption during
operational usage
This is an estimation of current
for a typical heavily loaded
application. Actual currents will
vary depending on system
activity, I/O electrical loading
and switching frequency. This
includes Core supply current with
Internal Vreg Enabled.
- CPU is running from RAM
- Flash is powered up
- X1/X2 crystal is powered up
- PLL is enabled, SYSCLK=Max
Device frequency
- Analog modules are powered up
- Outputs are static without DC
Load
- Inputs are static high or low
IDLE MODE
IDDIO
VDDIO current consumption while
device is in Idle mode
IDDA
VDDA current consumption while
device is in Idle mode
- CPU is in IDLE mode
- Flash is powered down
- PLL is Enabled, SYSCLK=Max
Device Frequency, CPUCLK is
gated
- X1/X2 crystal is powered up
- Analog Modules are powered
down
- Outputs are static without DC
Load
- Inputs are static high or low
STANDBY MODE
IDDIO
VDDIO current consumption while
device is in Standby mode
IDDA
VDDA current consumption while
device is in Standby mode
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- CPU is in STANDBY mode
- Flash is powered down
- PLL is Enabled, SYSCLK &
CPUCLK are gated
- X1/X2 crystal is powered down
- Analog Modules are powered
down
- Outputs are static without DC
Load
- Inputs are static high or low
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6.5.1 System Current Consumption (continued)
over operating free-air temperature range (unless otherwise noted).
TYP : Vnom, 30℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
9.8
27.5
mA
0.01
0.1
mA
72
106
mA
0.1
2.5
mA
IDDIO
VDDIO current consumption while
device is in Halt mode
IDDA
VDDA current consumption while
device is in Halt mode
- CPU is in HALT mode
- Flash is powered down
- PLL is Disabled, SYSCLK &
CPUCLK are gated
- X1/X2 crystal is powered down
- Analog Modules are powered
down
- Outputs are static without DC
Load
- Inputs are static high or low
ADVANCE INFORMATION
HALT MODE
FLASH ERASE/PROGRAM
IDDIO
VDDIO current consumption during
Erase/Program cycle(1)
IDDA
VDDA current consumption during
Erase/Program cycle
- CPU is running from RAM
- Flash going through continuous
Program/Erase operation
- PLL is enabled, SYSCLK at 120
MHz.
- Peripheral clocks are turned
OFF.
- X1/X2 crystal is powered up
- Analog is powered down
- Outputs are static without DC
Load
- Inputs are static high or low
RESET MODE
IDDIO
VDDIO current consumption while
reset is active(2)
5.8
mA
IDDA
VDDA current consumption while reset
is active(2)
0.1
mA
(1)
(2)
Brownout events during flash programming can corrupt flash data and permanently lock the device. Programming environments using
alternate power sources (such as a USB programmer) must be capable of supplying the rated current for the device and other system
components with sufficient margin to avoid supply brownout conditions.
This is the current consumption while reset is active, that is XRSn is low.
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6.5.2 System Current Consumption (VREG Disable - External Supply)
over operating free-air temperature range (unless otherwise noted).
TYP : Vnom, 30℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
68
90
mA
7
15
mA
3
6.5
mA
25
43
mA
1.7
2.2
mA
0.01
0.1
mA
11.6
27.6
mA
1.7
2.3
mA
0.01
0.1
mA
8.5
25
mA
0.8
1.2
mA
0.01
0.1
mA
OPERATING MODE
ADVANCE INFORMATION
IDD
VDD current consumption during
operational usage
IDDIO
VDDIO current consumption during
operational usage
IDDA
VDDA current consumption during
operational usage
This is an estimation of current
for a typical heavily loaded
application. Actual currents will
vary depending on system
activity, I/O electrical loading and
switching frequency.
- CPU is running from RAM
- Flash is powered up
- X1/X2 crystal is powered up
- PLL is enabled, SYSCLK=Max
Device frequency
- Analog modules are powered up
- Outputs are static without DC
Load
- Inputs are static high or low
IDLE MODE
VDD current consumption while device - CPU is in IDLE mode
is in Idle mode
- Flash is powered down
- PLL is Enabled, SYSCLK=Max
VDDIO current consumption while
Device Frequency, CPUCLK is
device is in Idle mode
gated
- X1/X2 crystal is powered up
- Analog Modules are powered
VDDA current consumption while
down
device is in Idle mode
- Outputs are static without DC
Load
- Inputs are static high or low
IDD
IDDIO
IDDA
STANDBY MODE
VDD current consumption while device - CPU is in STANDBY mode
is in Standby mode
- Flash is powered down
- PLL is Enabled, SYSCLK &
VDDIO current consumption while
CPUCLK are gated
device is in Standby mode
- X1/X2 crystal is powered down
- Analog Modules are powered
down
VDDA current consumption while
- Outputs are static without DC
device is in Standby mode
Load
- Inputs are static high or low
IDD
IDDIO
IDDA
HALT MODE
IDD
IDDIO
IDDA
76
VDD current consumption while device - CPU is in HALT mode
is in Halt mode
- Flash is powered down
- PLL is Disabled, SYSCLK &
VDDIO current consumption while
CPUCLK are gated
device is in Halt mode
- X1/X2 crystal is powered down
- Analog Modules are powered
down
VDDA current consumption while
- Outputs are static without DC
device is in Halt mode
Load
- Inputs are static high or low
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6.5.2 System Current Consumption (VREG Disable - External Supply) (continued)
over operating free-air temperature range (unless otherwise noted).
TYP : Vnom, 30℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
41
60.5
mA
31
45.5
mA
0.1
2.5
mA
IDD
VDD Current consumption during
Erase/Program cycle(1)
IDDIO
VDDIO Current consumption during
Erase/Program cycle(1)
IDDA
VDDA Current consumption during
Erase/Program cycle
- CPU is running from RAM
- Flash going through continuous
Program/Erase operation
- PLL is enabled, SYSCLK at 120
MHz.
- Peripheral clocks are turned
OFF.
- X1/X2 crystal is powered up
- Analog is powered down
- Outputs are static without DC
Load
- Inputs are static high or low
ADVANCE INFORMATION
FLASH ERASE/PROGRAM
RESET MODE
IDD
VDD current consumption while reset
is active(2)
3.3
mA
IDDIO
VDDIO current consumption while
reset is active(2)
2.2
mA
IDDA
VDDA current consumption while reset
is active(2)
0.1
mA
(1)
(2)
Brownout events during flash programming can corrupt flash data and permanently lock the device. Programming environments using
alternate power sources (such as a USB programmer) must be capable of supplying the rated current for the device and other system
components with sufficient margin to avoid supply brownout conditions.
This is the current consumption while reset is active, that is XRSn is low.
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6.5.3 Operating Mode Test Description
Section 6.5.1 and Section 6.5.4.1 list the current consumption values for the operational mode of the device. The
operational mode provides an estimation of what an application might encounter. The test condition for these
measurements has the following properties:
• Code is executing from RAM.
• FLASH is read and kept in active state.
• No external components are driven by I/O pins.
• All peripherals have clocks enabled.
• The CPU is actively executing code.
• All analog peripherals are powered up. ADCs and DACs are periodically converting.
ADVANCE INFORMATION
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6.5.4 Reducing Current Consumption
The F28003x devices provide some methods to reduce the device current consumption:
• One of the two low-power modes—IDLE or STANDBY—could be entered during idle periods in the
application.
• The flash module may be powered down if the code is run from RAM.
• Disable the pullups on pins that assume an output function.
• Each peripheral has an individual clock-enable bit (PCLKCRx). Reduced current consumption may be
achieved by turning off the clock to any peripheral that is not used in a given application. Section 6.5.4.1
lists the typical current reduction that may be achieved by disabling the clocks using the PCLKCRx register.
• To realize the lowest VDDA current consumption in an LPM, see the Analog-to-Digital Converter (ADC)
chapter of the TMS320F28003x Real-Time Microcontrollers Technical Reference Manual to ensure each
module is powered down as well.
PERIPHERAL
IDD CURRENT REDUCTION (mA)
ADC(1)
0.73
CLA
0.56
CLA BGCRC
0.42
CLB
1.41
CMPSS(1)
0.33
CPU BGCRC
0.25
CPU TIMER
0.04
GPDAC
0.12
DCAN
1.28
DCC
0.12
DMA
0.57
eCAP1 and eCAP2
0.08
eCAP3(2)
0.29
ePWM1 to
ePWM4(3)
0.95
ePWM5 to ePWM8
0.78
ERAD
1.56
eQEP
0.1
FSI RX
0.34
FSI TX
0.27
HIC
0.17
I2C
0.26
LIN
0.35
MCAN (CAN FD)
1.01
PMBUS
0.28
SCI
0.16
SDFM
1.83
SPI
0.08
(1)
(2)
(3)
ADVANCE INFORMATION
6.5.4.1 Typical Current Reduction per Disabled Peripheral
This current represents the current drawn by the digital portion of the each module.
eCAP3 can also be configured as HRCAP.
ePWM1 to ePWM4 can also be configured as HRPWM.
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6.6 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
Digital and Analog IO
IOH = IOH MIN
VDDIO * 0.8
IOH = –100 μA
VDDIO – 0.2
ADVANCE INFORMATION
VOH
High-level output voltage
VOL
Low-level output voltage
IOH
High-level output source current for all output pins
IOL
Low-level output sink current for all output pins
ROH
High-level output impedance for all output pins
ROL
Low-level output impedance for all output pins
VIH
High-level input voltage
VIL
Low-level input voltage
VHYSTERESIS
Input hysteresis
IPULLDOWN
Input current
Pins with pulldown
VDDIO = 3.3 V
VIN = VDDIO
120
µA
IPULLUP
Input current
Digital inputs with pullup VDDIO = 3.3 V
enabled(1)
VIN = 0 V
160
µA
Pin leakage
Input capacitance
0.4
IOL = 100 µA
0.2
–4
4
mA
70
Ω
70
Ω
V
0.8
Analog pins (except
ADCINB3/VDAC)
V
mA
125
ADCINB3/VDAC
CI
IOL = IOL MAX
2.0
Digital inputs
ILEAK
V
V
mV
Pullups and outputs
disabled
0 V ≤ VIN ≤ VDDIO
0.1
µA
Analog drivers
disabled
0 V ≤ VIN ≤ VDDA
0.1
2
Digital inputs
2
Analog pins(2)
11
pF
VREG, POR and BOR
VREG, POR,
BOR(3)
(1)
(2)
(3)
80
See Pins With Internal Pullup and Pulldown table for a list of pins with a pullup or pulldown.
The analog pins are specified separately; see the Per-Channel Parasitic Capacitance tables that are in the ADC Input Model section.
See the Power Management Module (PMM) section.
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°C/W(1)
AIR FLOW (lfm)(2)
RΘJC
Junction-to-case thermal resistance
7.6
N/A
RΘJB
Junction-to-board thermal resistance
24.2
N/A
RΘJA (High k PCB)
Junction-to-free air thermal resistance
46.1
0
37.3
150
34.8
250
32.6
500
RΘJMA
PsiJT
PsiJB
(1)
(2)
Junction-to-moving air thermal resistance
Junction-to-package top
Junction-to-board
0.2
0
0.4
150
0.4
250
0.6
500
23.8
0
22.8
150
22.4
250
21.9
500
ADVANCE INFORMATION
6.7 Thermal Resistance Characteristics for PZ Package
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
lfm = linear feet per minute
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6.8 Thermal Resistance Characteristics for PN Package
°C/W(1)
AIR FLOW (lfm)(2)
RΘJC
Junction-to-case thermal resistance
14.2
N/A
RΘJB
Junction-to-board thermal resistance
21.9
N/A
RΘJA (High k PCB)
PsiJT
ADVANCE INFORMATION
PsiJB
(1)
(2)
82
Junction-to-free air thermal resistance
Junction-to-package top
Junction-to-board
49.9
0
38.3
150
36.7
250
34.4
500
0.8
0
1.18
150
1.34
250
1.62
500
21.6
0
20.7
150
20.5
250
20.1
500
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
lfm = linear feet per minute
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°C/W(1)
AIR FLOW (lfm)(2)
RΘJC
Junction-to-case thermal resistance
12.4
N/A
RΘJB
Junction-to-board thermal resistance
25.6
N/A
RΘJA (High k PCB)
Junction-to-free air thermal resistance
51.8
0
42.2
150
39.4
250
36.5
500
RΘJMA
PsiJT
PsiJB
(1)
(2)
Junction-to-moving air thermal resistance
Junction-to-package top
Junction-to-board
0.5
0
0.9
150
1.1
250
1.4
500
25.1
0
23.8
150
23.4
250
22.7
500
ADVANCE INFORMATION
6.9 Thermal Resistance Characteristics for PM Package
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
lfm = linear feet per minute
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6.10 Thermal Resistance Characteristics for PT Package
°C/W(1)
AIR FLOW (lfm)(2)
RΘJC
Junction-to-case thermal resistance
13.6
N/A
RΘJB
Junction-to-board thermal resistance
30.6
N/A
RΘJA (High k PCB)
PsiJT
ADVANCE INFORMATION
PsiJB
(1)
(2)
Junction-to-free air thermal resistance
Junction-to-package top
Junction-to-board
64
0
50.4
150
48.2
250
45
500
0.56
0
0.94
150
1.1
250
1.38
500
30.1
0
28.7
150
28.4
250
28
500
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
lfm = linear feet per minute
6.11 Thermal Design Considerations
Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems
that exceed the recommended maximum power dissipation in the end product may require additional thermal
enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor
that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care
should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the operating
junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. The thermal
application report Semiconductor and IC Package Thermal Metrics helps to understand the thermal metrics and
definitions.
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6.12 System
6.12.1 Power Management Module (PMM)
6.12.1.1 Introduction
The Power Management Module (PMM) handles all the power management functions required for device
operation.
6.12.1.2 Overview
The block diagram of the PMM is shown in Figure 6-1. As can be seen, the PMM comprises of various
sub-components which will be described in the subsequent sections.
MCU
PMM
I/O
POR
ADVANCE INFORMATION
To Rest of Chip
CPU Reset
Release
RISE
DELAY
(45us)
RISE
DELAY
(80us)
I/O
BOR
Internal
Power
Good
Signal
RISE
DELAY
(40us)
EN
VMONCTL.bit.BORLVMONDIS
CVDDIO
XRSn
VREGENZ
VSS
Internal
VDD
1.2v LDO
VREG
VSS
External
VDDIO
Internal
VDD
POR
OUT
IN
EN
External
CVDD
Figure 6-1. PMM Block Diagram
6.12.1.2.1 Power Rail Monitors
The PMM has voltage monitors on the supply rails that release the XRSn signal high once the voltages cross the
set threshold during power up. They also function to trip the XRSn signal low if any of the voltages drop below
the programmed levels. The various voltage monitors are described in the subsequent sections.
Note
Not all the voltage monitors are supported for device operation in an application. In the case where a
voltage monitor is not supported, an external supervisor is recommended if the device needs supply
voltage monitoring.
The three voltage monitors (I/O POR, I/O BOR, VDD POR) all have to release their respective outputs before the
device begins operation (i.e XRSn goes high). However, if any of the voltage monitors trips, XRSn is driven low.
The I/Os are held in high impedance when any of the voltage monitors trip.
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6.12.1.2.1.1 I/O POR (Power-On Reset) Monitor
The I/O POR monitor supervises the VDDIO rail. During power-up, this is the first monitor to release (i.e first to
untrip) on VDDIO.
6.12.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
The I/O BOR monitor also supervises the VDDIO rail. During power-up, this is the second monitor to release (i.e
second to untrip) on VDDIO. This monitor has a tighter tolerance compared to the I/O POR.
Any drop in voltage below the recommended operating voltages will trip the I/O BOR and reset the device but
this can be disabled by setting VMONCTL.bit.BORLVMONDIS to 1. The I/O BOR can only be disabled after the
device has fully booted up. If the I/O BOR is disabled, the I/O POR will reset the device for voltage drops.
ADVANCE INFORMATION
Note
The level that the I/O POR trips at is well below the minimum recommended voltage for VDDIO and
hence should not be used for device supervision.
Figure 6-2 shows the operating region of the I/O BOR.
3.63 V
+10%
0%
3.3 V
Recommended
System Voltage
Regulator Range
VDDIO
Operating
Range
3.1 V
–6.1%
3.0 V
–9.1%
VBOR-GB
BOR Guard Band
VBOR-VDDIO
Internal BOR Threshold
2.81 V
2.80 V
–14.8%
–15.1%
Figure 6-2. I/O BOR Operating Region
6.12.1.2.1.3 VDD POR (Power-On Reset) Monitor
The VDD POR monitor supervises the VDD rail. During power-up, this monitor releases i.e untrips once the
voltage crosses the programmed trip level on VDD.
Note
VDD POR is programmed at a level below the minimum recommended voltage for VDD and hence it
should not be relied upon for VDD supervision if that is required in the application.
6.12.1.2.2 External Supervisor Usage
VDDIO Monitoring: The I/O BOR is supported for application use so an external supervisor is not required to
monitor the I/O rail.
VDD Monitoring: The VDD POR is not supported for application use. If VDD monitoring is required by the
application, an external supervisor should be used to monitor the VDD rail.
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Note
Using an external supervisor with the internal VREG is not supported. If VDD monitoring is required
by the application, it is a requirement to use a package with VREGENZ pin in order to power VDD
externally.
6.12.1.2.3 Delay Blocks
The delay blocks in the path of the voltage monitors work together to delay the release time between the voltage
monitors and XRSn. This is to ensure that the voltages are stable when XRSn releases in external VREG mode.
They are only active during power-up i.e when VDDIO and VDD are ramping up.
They contribute to the minimum slew rates specified in Power Management Module Electrical Data and Timing
for the power rails.
ADVANCE INFORMATION
Note
The delay numbers specified in the block diagram are typical numbers.
6.12.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
The internal VREG is supplied by the VDDIO rail and can generate the 1.2V required to power the VDD pins. It
is enabled by tying the VREGENZ pin low. Although it eliminates the need to use an external supply for VDD,
decoupling capacitors are still required on the VDD pins for VREG stability and transients. See VDD Decoupling
for details.
6.12.1.2.5 VREGENZ
The VREGENZ (VREG disable) pin controls the state of the internal VREG. To enable the internal VREG,
VREGENZ pin should be tied low. For applications supplying VDD externally (external VREG), the internal
VREG should be disabled by tying the VREGENZ pin high.
Note
Not all device packages have VREGENZ pinned out. For packages without VREGENZ, external
VREG mode is not supported.
6.12.1.3 External Components
6.12.1.3.1 Decoupling Capacitors
VDDIO and VDD require decoupling capacitors for correct operation. The requirements are outlined in the
subsequent sections.
6.12.1.3.1.1 VDDIO Decoupling
It is recommended to place a minimum amount of decoupling capacitance on VDDIO. See the CVDDIO parameter
in Power Management Module Electrical Data and Timing. The actual amount of decoupling capacitance to use
is a requirement of the power supply driving VDDIO. Either of the configurations outlined below is acceptable:
• Configuration 1: Place a decoupling capacitor on each VDDIO pin per the CVDDIO parameter.
• Configuration 2: Install a single decoupling capacitor which is the equivalent of CVDDIO * VDDIO pins.
Note
It is critical to have the decoupling capacitor/s close to the device pins.
6.12.1.3.1.2 VDD Decoupling
It is recommended to place a minimum amount of decoupling capacitance on VDD. See the CVDD TOTAL
parameter in Power Management Module Electrical Data and Timing.
In external VREG mode, the actual amount of decoupling capacitance to use is a requirement of the power
supply driving VDD.
Either of the configurations outlined below is acceptable:
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•
•
Configuration 1: Divide CVDD TOTAL across the VDD pins.
Configuration 2: Install a single decoupling capacitor with value of CVDD TOTAL.
Note
It is critical to have the decoupling capacitor/s close to the device pins.
6.12.1.4 Power Sequencing
6.12.1.4.1 Supply Pins Ganging
It is strongly recommended that all 3.3v rails be tied together and supplied from a single source. This list
includes:
• VDDIO
• VDDA
ADVANCE INFORMATION
In addition, no power pin should be left unconnected.
In external VREG mode, the VDD pins should be tied together and supplied from a single source.
In internal VREG mode, tying the VDD pins together is optional as long as each VDD pin has a capacitor on it.
See VDD Decoupling for VDD decoupling configurations.
The analog modules on the device have fairly high PSRR and hence in most cases, noise on VDDA will have to
exceed the recommended operating conditions of the supply rails before the analog modules see performance
degradation. Due to this, supplying VDDA separately typically offers minimal benefits. Nevertheless, for the
purposes of noise improvement, placing a pi filter between VDDIO and VDDA is acceptable.
Note
All the supply pins per rail are tied together internally. For instance, all VDDIO pins are tied together
internally, all VDD pins are tied together internally etc.
6.12.1.4.2 Signal Pins Power Sequence
Before powering the device, no voltage larger than 0.3 V above VDDIO or 0.3 V below VSS should be applied
to any digital pin and no voltage larger than 0.3 V above VDDA or 0.3 V below VSSA should be applied to any
analog pin (including VREFHI and VDAC). Simply, the signal pins should only be driven after XRSn goes high
provided all the 3.3v rails are tied together. This sequencing is still required even if VDDIO and VDDA are not
tied together.
If the above sequence is violated, device malfunction and possibly damage can occur as current will flow through
unintended parasitic paths in the device.
6.12.1.4.3 Supply Pins Power Sequence
6.12.1.4.3.1 External VREG/VDD Mode Sequence
Figure 6-3 depicts the power sequencing requirements for external VREG mode. The values for all the
parameters indicated can be found in Power Management Module Electrical Data and Timing.
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VDDIO
VBOR-VDDIO-UP
SRVDDIO
VPOR-VDDIO
VDDIO
(i)
SRVDD
VBOR-VDDIO-DOWN(ii)
VDD
VDD
Internal
Power Good
Signal(iii)
XRSn
Internal
Power Good
Signal(iv)
SRVDD
VPOR-VDD-DOWN(ii)
VPOR-VDD-UP(i)
XRSn
SRVDDIO
VPOR-VDDIO
VDDIO - VDD
Delay
VDDIO-MON-TOT-DELAY
VXRSn-PU-DELAY
VXRSn-PD-DELAY
ADVANCE INFORMATION
(i) This trip point is the trip point before XRSn releases. See the PMM Characteriscs table.
(ii) This trip point is the trip point aer XRSn releases. See the PMM Characteris cs table.
(iii) During power up, the Power Good Signal goes high aer all POR and BOR monitors are released. See the PMM Block Diagram.
(iv) During power down, the Power Good Signal goes low if any of the POR or BOR monitors are tripped. See the PMM Block Diagram.
Figure 6-3. External VREG Power Up Sequence
•
•
For Power Up:
1. VDDIO i.e the 3.3 V rail should come up first with the minimum slew rate specified.
2. VDD i.e the 1.2 V rail should come up next with the minimum slew rate specified.
3. The time delta between the VDDIO rail coming up and when the VDD rail can come up is also specified.
4. After the times specified by vddio-mon-tot-delay and vxrsn-pu-delay, XRSn will be released and the
device starts the boot-up sequence.
There is an additional delay between XRSn releasing (i.e going high) and the boot-up sequence starting.
See Figure 6-1.
5. The VDD POR and I/O BOR monitors have different release point during power up.
6. During power up, both VDDIO and VDD rails have to be up before XRSn releases.
For Power-Down:
1. There is no requirement between VDDIO and VDD on which should power down first, however, there is a
minimum slew rate spec.
2. The VDD POR and I/O BOR monitors have different trip points during power down.
3. Any of the POR or BOR monitors that trips during power down will cause XRSn to go low after
VXRSN-PD-DELAY.
Note
The Power Good Signal is an internal signal.
Note
If there is an external circuit driving XRSn e.g a supervisor, the boot-up sequence does not start until
the XRSn pin is released by all internal and external sources.
6.12.1.4.3.2 Internal VREG/VDD Mode Sequence
Figure 6-4 depicts the power sequencing requirements for internal VREG mode. The values for all the
parameters indicated can be found in Power Management Module Electrical Data and Timing.
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VDDIO
VBOR-VDDIO-UP
VDDIO
(i)
VBOR-VDDIO-DOWN(ii)
Internal
Power Good
Signal(iii)
XRSn
SRVDDIO
Internal
Power Good
Signal(iv)
XRSn
SRVDDIO
VPOR-VDDIO
VPOR-VDDIO
VDDIO-MON-TOT-DELAY
VXRSn-PU-DELAY
VXRSn-PD-DELAY
ADVANCE INFORMATION
(i) This trip point is the trip point before XRSn releases. See the PMM Characteriscs table.
(ii) This trip point is the trip point aer XRSn releases. See the PMM Characteris cs table.
(iii) During power up, the Power Good Signal goes high aer all POR and BOR monitors are released. See the PMM Block Diagram.
(iv) During power down, the Power Good Signal goes low if any of the POR or BOR monitors are tripped. See the PMM Block Diagram.
Figure 6-4. Internal VREG Power Up Sequence
•
•
For Power-Up:
1. VDDIO i.e the 3.3 V rail should come up with the minimum slew rate specified.
2. The Internal VREG powers up after the I/O monitors (I/O POR and I/O BOR) are released.
3. After the times specified by VDDIO-MON-TOT-DELAY and VXRSN-PU-DELAY, XRSn will be released and the
device starts the boot-up sequence.
There is an additional delay between XRSn releasing (i.e going high) and the boot-up sequence starting.
See Figure 6-1.
4. The I/O BOR monitor has a different release point during power up.
For Power-Down:
1. The only requirement on VDDIO during power down is the slew rate.
2. The I/O BOR monitor has a different release point during power down.
3. The I/O BOR tripping will cause XRSn to go low after VXRSN-PD-DELAY and also power down the Internal
VREG.
Note
The Power Good Signal is an internal signal.
Note
If there is an external circuit driving XRSn e.g a supervisor, the boot-up sequence does not start until
the XRSn pin is released by all internal and external sources.
6.12.1.4.3.3 Supply Sequencing Summary and Effects of Violations
The acceptable power up sequence for the rails is summarized below. Power-up here means the rail in question
has reached the minimum recommended operating voltage. Non-acceptable sequences will lead to reliability
concerns and possibly damage. For simplicity, it is recommended to tie all the 3.3-V rails together and follow the
descriptions in Supply Pins Power Sequence.
Table 6-1. External VREG Sequence Summary
CASE
90
RAILS POWER-UP ORDER
ACCEPTABLE
VDDIO
VDDA
VDD
A
1
2
3
Yes
B
1
3
2
Yes
C
2
1
3
-
D
2
3
1
-
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Table 6-1. External VREG Sequence Summary (continued)
CASE
RAILS POWER-UP ORDER
ACCEPTABLE
VDDIO
VDDA
VDD
E
3
2
1
-
F
3
1
2
-
G
1
1
2
Yes
H
2
2
1
-
Table 6-2. Internal VREG Sequence Summary
ACCEPTABLE
VDDIO
VDDA
A
1
2
Yes
B
2
1
-
C
1
1
Yes
ADVANCE INFORMATION
RAILS POWER-UP ORDER
CASE
Note
The analog modules on the device should only be powered after VDDA has reached the minimum
recommended operating voltage.
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6.12.1.5 Power Management Module Electrical Data and Timing
6.12.1.5.1 Power Management Module Operating Conditions
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
General
CVDDIO (1) (2)
VDDIO Capacitance Per
Pin(7)
0.1
uF
CVDDA (1) (2)
VDDA Capacitance Per
Pin(7)
2.2
uF
SRVDDIO (3)
Supply Ramp Rate of 3.3V
Rail (VDDIO)
20
100
VBOR-VDDIO-GB VDDIO Brown Out Reset
(5)
Voltage Guardband
0.1
mV/us
V
ADVANCE INFORMATION
External VREG
CVDD
TOTAL(1) (4)
Total VDD Capacitance(7)
10
SRVDD (3)
Supply Ramp Rate of 1.2V
Rail (VDD)
20
VDDIO - VDD
Delay(6)
Ramp Delay Between VDDIO
and VDD
uF
100
mV/us
0
us
10
uF
Internal VREG
CVDD
TOTAL(4)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Total VDD Capacitance(7)
The exact value of the decoupling capacitance depends on the system voltage regulation solution that is supplying these pins.
It is recommended to tie the 3.3V rails (VDDIO, VDDA) together and supply them from a single source.
Supply ramp rate faster than the max can trigger the on-chip ESD protection.
See the Power Management Module (PMM) section on possible configurations for the total decoupling capacitance.
TI recommends VBOR-VDDIO-GB to avoid BOR-VDDIO resets due to normal supply noise or load-transient events on the 3.3-V VDDIO
system regulator. Good system regulator design and decoupling capacitance (following the system regulator specifications) are
important to prevent activation of the BOR-VDDIO during normal device operation. The value of VBOR-VDDIO-GB is a system-level design
consideration; the voltage listed here is typical for many applications.
Delay between when the 3.3v rail ramps up and when the 1.2v rail ramps up. See the supply sequencing table for the allowable supply
ramp sequences.
Capacitor tolerance should be less than 10%.
6.12.1.5.2 Power Management Module Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VVREG
Internal Voltage Regulator
Output
VPOR-VDDIO
VDDIO Power on Reset
Voltage
VBOR-VDDIO-UP VDDIO Brown Out Reset
(1)
Voltage on Ramp Up
VBOR-VDDIODOWN
(1)
VDDIO Brown Out Reset
Voltage on Ramp Down
DELAY
(3)
VXRSn-PDDELAY
92
(4)
XRSn Release Delay after
Supplies are Ramped Up
During Power-Up
1.152
1.2
1.248
V
Before XRSn Release
2.7
V
After XRSn Release
VDD Power on Reset Voltage
After XRSn Release
on Ramp Down
VXRSn-PU-
UNIT
V
VPOR-VDD(2)
MAX
2.3
VDD Power on Reset Voltage
Before XRSn Release
on Ramp Up
DOWN
TYP
Before and After XRSn
Release
VPOR-VDD-UP
(2)
MIN
2.81
3.0
This is the final delay
XRSn Trip Delay after
Supplies are Ramped Down
During Power-Down
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V
0.9
V
1
V
40
us
50
ns
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6.12.1.5.2 Power Management Module Characteristics (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
VDDIO-MONTOT-DELAY
VXRSn-MONRELEASE-DELAY
(3)
(4)
MIN
Total Delays in Path of
VDDIO Monitors (POR, BOR)
XRSn Release Delay after a
VDDIO BOR/VDD POR Event Supplies Within Operating
XRSn Release Delay after a Range
VDDIO POR Event
TYP
MAX
UNIT
45
us
40
us
90
us
See the Supply Voltages figure.
VPOR-VDD is not supported and it is set to trip at a level below the recommended operating conditions. If monitoring of VDD is needed,
an external supervisor is required.
Supplies are considered fully ramped up after they cross the minimum recommended operating conditions for the respective rail. All
POR and BOR monitors need to be released before this delay takes effect. RC network delay will add to this.
On power down, any of the POR or BOR monitors that trips will immediately trip XRSn. This delay is the time between any of the POR,
BOR monitors tripping and XRSn going low. It is variable and depends on the ramp down rate of the supply. RC network delay will add
to this.
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(1)
(2)
TEST CONDITIONS
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6.12.2 Reset Timing
XRSn is the device reset pin. It functions as an input and open-drain output. The device has a built-in power-on
reset (POR) and brown-out reset (BOR) monitors. During power up, the monitor circuits keep the XRSn pin low.
For more details, see the Power Management Module (PMM) section. A watchdog or NMI watchdog reset will
also drive the pin low. An external open-drain circuit may drive the pin to assert a device reset.
A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRSn and VDDIO. A capacitor should
be placed between XRSn and VSS for noise filtering, it should be 100 nF or smaller. These values will allow
the watchdog to properly drive the XRSn pin to VOL within 512 OSCCLK cycles when the watchdog reset is
asserted. Figure 6-5 shows the recommended reset circuit.
VDDIO
2.2 kW to 10 kW
ADVANCE INFORMATION
Optional open-drain
Reset source
XRSn
£100 nF
Figure 6-5. Reset Circuit
6.12.2.1 Reset Sources
The Reset Signals table summarizes the various reset signals and their effect on the device.
Table 6-3. Reset Signals
Reset Source
CPU Core Reset
(C28x, FPU, TMU)
Peripherals
Reset
JTAG / Debug
Logic Reset
IOs
XRS Output
POR
Yes
Yes
Yes
Hi-Z
Yes
BOR
Yes
Yes
Yes
Hi-Z
Yes
XRS Pin
Yes
Yes
No
Hi-Z
-
WDRS
Yes
Yes
No
Hi-Z
Yes
NMIWDRS
Yes
Yes
No
Hi-Z
Yes
SYSRS (Debugger Reset)
Yes
Yes
No
Hi-Z
No
SCCRESET
Yes
Yes
No
Hi-Z
No
SIMRESET. XRS
Yes
Yes
No
Hi-Z
Yes
SIMRESET. CPU1RS
Yes
Yes
No
Hi-Z
No
HWBISTRS
Yes
No
No
No
No
The parameter th(boot-mode) must account for a reset initiated from any of these sources.
See the Resets section of the System Control chapter in the TMS320F28003x Real-Time Microcontrollers
Technical Reference Manual.
CAUTION
Some reset sources are internally driven by the device. Some of these sources will drive XRSn low,
use this to disable any other devices driving the boot pins. The SCCRESET and debugger reset
sources do not drive XRSn; therefore, the pins used for boot mode should not be actively driven by
other devices in the system. The boot configuration has a provision for changing the boot pins in
OTP.
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6.12.2.2 Reset Electrical Data and Timing
6.12.2.2.1 Reset (XRSn) Timing Requirements
MIN
MAX
UNIT
th(boot-mode)
Hold time for boot-mode pins
1.5
ms
tw(RSL2)
Pulse duration, XRSn low on warm reset
3.2
µs
6.12.2.2.2 Reset (XRSn) Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
tw(RSL1)
Pulse duration, XRSn driven low by device after supplies are stable
tw(WDRS)
Pulse duration, reset pulse generated by watchdog
tboot-flash
Boot-ROM execution time to first instruction fetch in flash
TYP
MAX
100
UNIT
µs
512tc(OSCCLK)
cycles
ms
ADVANCE INFORMATION
1.2
6.12.2.2.3 Reset Timing Diagrams
VDDIO VDDA
(3.3V)
VDD (1.2V)
tw(RSL1)
XRSn(A)
tboot-flash
Boot ROM
CPU
Execution
Phase
User code
th(boot-mode)(B)
Boot-Mode
Pins
User code dependent
GPIO pins as input
Peripheral/GPIO function
Based on boot code
Boot-ROM execution starts
GPIO pins as input (pullups are disabled)
I/O Pins
User code dependent
A.
B.
The XRSn pin can be driven externally by a supervisor or an external pullup resistor, see the Pin Attributes table. On-chip monitors will
hold this pin low until the supplies are in a valid range.
After reset from any source (see the Reset Sources section), the boot ROM code samples Boot Mode pins. Based on the status of
the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on
conditions (in debugger environment), the boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based
on user environment and could be with or without PLL enabled.
Figure 6-6. Power-on Reset
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tw(RSL2)
XRSn
User code
CPU
Execution
Phase
Boot ROM
User code
Boot ROM execution starts
(initiated by any reset source)
Boot-Mode
Pins
Peripheral/GPIO function
GPIO Pins as Input
th(boot-mode)(A)
Peripheral/GPIO function
User-Code Execution Starts
ADVANCE INFORMATION
I/O Pins
User-Code Dependent
GPIO Pins as Input (Pullups are Disabled)
User-Code Dependent
A.
After reset from any source (see the Reset Sources section), the Boot ROM code samples BOOT Mode pins. Based on the status of
the Boot Mode pin, the boot code branches to destination memory or boot code function. If Boot ROM code executes after power-on
conditions (in debugger environment), the Boot code execution time is based on the current SYSCLK speed. The SYSCLK will be
based on user environment and could be with or without PLL enabled.
Figure 6-7. Warm Reset
96
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6.12.3 Clock Specifications
6.12.3.1 Clock Sources
Table 6-4. Possible Reference Clock Sources
CLOCK SOURCE
DESCRIPTION
INTOSC1
Internal oscillator 1.
Zero-pin overhead 10-MHz internal oscillator.
INTOSC2(1)
Internal oscillator 2.
Zero-pin overhead 10-MHz internal oscillator.
X1 (XTAL)
External crystal or resonator connected between the X1 and X2 pins or single-ended clock connected to the X1
pin.
On reset, internal oscillator 2 (INTOSC2) is the default clock source for the PLL (OSCCLK).
ADVANCE INFORMATION
(1)
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SYSCLKDIVSEL
Watchdog
Timer
SYSPLL
INTOSC1
INTOSC2
OSCCLK
PLLSYSCLK
NMIWD
SYS
Divider
PLLRAWCLK
FPU
TMU
Flash
CPUCLK
SYSPLLCLKEN
X1 (XTAL)
OSCCLKSRCSEL
CPU
SYSCLK
SYSCLK
ADVANCE INFORMATION
One per SYSCLK peripheral
PCLKCRx
PERx.SYSCLK
ePIE
CLA
GPIO
Mx RAMs
LSx RAMs
GSx RAMs
Boot ROM
Message RAMs
DCSM
System Control
WD
XINT
CPUTIMERs
CLB
ECAP
EQEP
EPWM
HRCAL
PMBUS
LIN
FSI
SDFM
EPG
AES
I2C
ADC
CMPSS
GPDAC
DCAN
MCAN
HIC
DCC
HWBIST
BGCRC
ERAD
One per LSPCLK peripheral
LOSPCP
PCLKCRx
LSP
Divider
PERx.LSPCLK
LSPCLK
SCI
SPI
CLKSRCCTL2.CANxBCLKSEL
CAN Bit Clock
Figure 6-8. Clocking System
98
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SYSPLL
÷
(REFDIV+1)
INTCLK
VCOCLK
VCO
÷
(ODIV+1)
PLLRAWCLK
ADVANCE INFORMATION
OSCCLK
÷
IMULT
Figure 6-9. System PLL
In Figure 6-9,
f PLLRAWCLK
f OSCCLK
REFDIV 1
u
IMULT
ODIV 1
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6.12.3.2 Clock Frequencies, Requirements, and Characteristics
This section provides the frequencies and timing requirements of the input clocks, PLL lock times, frequencies of
the internal clocks, and the frequency and switching characteristics of the output clock.
6.12.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
6.12.3.2.1.1 Input Clock Frequency
MIN
MAX
UNIT
f(XTAL)
Frequency, X1/X2, from external crystal or resonator
10
20
MHz
f(X1)
Frequency, X1, from external oscillator
10
25
MHz
6.12.3.2.1.2 XTAL Oscillator Characteristics
over recommended operating conditions (unless otherwise noted)
ADVANCE INFORMATION
PARAMETER
MIN
X1 VIL
Valid low-level input voltage
X1 VIH
Valid high-level input voltage
TYP
MAX
UNIT
–0.3
0.3 * VDDIO
V
0.7 * VDDIO
VDDIO + 0.3
V
6.12.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal)
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
X1 VIL
Valid low-level input voltage
X1 VIH
Valid high-level input voltage
MAX
UNIT
–0.3
0.3 * VDDIO
V
0.7 * VDDIO
VDDIO + 0.3
V
6.12.3.2.1.4 X1 Timing Requirements
MIN
MAX
tf(X1)
Fall time, X1
tr(X1)
Rise time, X1
tw(X1L)
Pulse duration, X1 low as a percentage of tc(X1)
45%
55%
tw(X1H)
Pulse duration, X1 high as a percentage of tc(X1)
45%
55%
MIN
MAX
UNIT
6
ns
6
ns
6.12.3.2.1.5 AUXCLKIN Timing Requirements
UNIT
tf(AUXI)
Fall time, AUXCLKIN
6
ns
tr(AUXI)
Rise time, AUXCLKIN
6
ns
tw(AUXL)
Pulse duration, AUXCLKIN low as a percentage of tc(XCI)
45%
55%
tw(AUXH)
Pulse duration, AUXCLKIN high as a percentage of tc(XCI)
45%
55%
6.12.3.2.1.6 APLL Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
PLL Lock time
SYS PLL Lock Time(1)
(1)
100
5µs + (1024 * (REFDIV + 1) * tc(OSCCLK))
us
The PLL lock time here defines the typical time that takes for the PLL to lock once PLL is enabled (SYSPLLCTL1[PLLENA]=1).
Additional time to verify the PLL clock using Dual Clock Comparator (DCC) is not accounted here. TI recommends using the latest
example software from C2000Ware for initializing the PLLs. For the system PLL, see InitSysPll() or SysCtl_setClock().
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6.12.3.2.1.7 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
over recommended operating conditions (unless otherwise noted)
PARAMETER(1)
MIN
MAX
UNIT
tf(XCO)
Fall time, XCLKOUT
5
ns
tr(XCO)
Rise time, XCLKOUT
5
ns
tw(XCOL)
Pulse duration, XCLKOUT low
H – 2(2)
H + 2(2)
ns
2(2)
2(2)
ns
50
MHz
tw(XCOH)
Pulse duration, XCLKOUT high
f(XCO)
Frequency, XCLKOUT
(1)
(2)
H–
H+
A load of 40 pF is assumed for these parameters.
H = 0.5tc(XCO)
MIN
f(SYSCLK)
Frequency, device (system) clock
tc(SYSCLK)
Period, device (system) clock
f(INTCLK)
Frequency, system PLL going into VCO (after REFDIV)
f(VCOCLK)
Frequency, system PLL VCO (before ODIV)
f(PLLRAWCLK)
Frequency, system PLL output (before SYSCLK divider)
f(PLL)
Frequency, PLLSYSCLK
NOM
UNIT
120
MHz
8.33
500
ns
2
20
MHz
220
600
MHz
6
240
MHz
2
120
MHz
(1)
f(PLL_LIMP)
Frequency, PLL Limp Frequency
f(LSP)
Frequency, LSPCLK
tc(LSPCLK)
Period, LSPCLK
f(OSCCLK)
Frequency, OSCCLK (INTOSC1 or INTOSC2 or XTAL or
X1)
f(EPWM)
Frequency, EPWMCLK
f(HRPWM)
Frequency, HRPWMCLK
(1)
MAX
2
45/(ODIV+1)
MHz
2
120
MHz
8.33
500
ns
See respective clock
60
ADVANCE INFORMATION
6.12.3.2.1.8 Internal Clock Frequencies
MHz
120
MHz
120
MHz
PLL output frequency when OSCCLK is dead (Loss of OSCCLK causes PLL to Limp).
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6.12.3.3 Input Clocks and PLLs
In addition to the internal 0-pin oscillators, three types of external clock sources are supported:
• A single-ended 3.3-V external clock. The clock signal should be connected to X1, as shown in Figure 6-10,
with the XTALCR.SE bit set to 1.
• An external crystal. The crystal should be connected across X1 and X2 with its load capacitors connected to
VSS as shown in Figure 6-11.
• An external resonator. The resonator should be connected across X1 and X2 with its ground connected to
VSS as shown in Figure 6-12.
Microcontroller
Microcontroller
VSS
GPIO19
GPIO18*
X1
X2
GPIO18
X1
X2
ADVANCE INFORMATION
* Available as a
GPIO when X1 is
used as a clock
+3.3 V
VDD
GPIO19
VSS
Out
3.3-V Oscillator
Gnd
Figure 6-11. External Crystal
Figure 6-10. Single-ended 3.3-V External Clock
Microcontroller
VSS
GPIO19
GPIO18
X1
X2
Figure 6-12. External Resonator
6.12.3.4 XTAL Oscillator
6.12.3.4.1 Introduction
The XTAL oscillator in this device is an embedded electrical oscillator that when paired with a compatible crystal
can generate the system clock required by the device.
6.12.3.4.2 Overview
The sections below describe the components of the electrical oscillator and crystal.
6.12.3.4.2.1 Electrical Oscillator
The electrical oscillator in this device is a Pierce oscillator design. It is a positive feedback inverter circuit that
requires a tuning circuit in order to oscillate. When it is paired with a compatible crystal, a tank circuit is formed.
This tank circuit oscillates at the fundamental frequency of the crystal component. On this device, it is designed
to operate in parallel resonance mode due to the shunt capacitor (C0) and required load capacitors (CL). Figure
6-13 illustrates the components of the electrical oscillator and the tank circuit.
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MCU
To Rest of Chip
XTAL Oscillator
Buffer
0
Comp
1
XCLKOUT
Circuit
[XTAL On]
XCLKOUT
Pierce Inverter
GPIO
External
X2
X1
Internal
Internal
External
Rd
Crystal
CL1
ADVANCE INFORMATION
Rbias
CL2
GND
GND
Figure 6-13. Electrical Oscillator Block Diagram
6.12.3.4.2.1.1 Modes of Operation
The electrical oscillator in this device has two modes of operation: crystal mode and single-ended mode.
6.12.3.4.2.1.1.1 Crystal Mode of Operation
In crystal mode of operation, a quartz crystal with load capacitors has to be connected to X1 and X2.
This mode of operation is engaged when [XTAL On]=1 which is achieved by setting XTALCR.OSCOFF=0 and
XTALCR.SE=0. There is an internal bias resistor for the feedback loop so an external one should not be used.
Adding an external bias resistor will create a parallel resistance with the internal Rbias, moving the bias point
of operation and possibly leading to clipped waveforms, out of spec duty cycle and reduction in the effective
negative resistance.
In this mode of operation, the resultant clock on X1 is passed through a comparator (Comp) to the rest of the
chip. The clock on X1 needs to meet the VIH and VIL of the comparator. See XTAL Oscillator Characteristics
table for the VIH and VIL requirements of the comparator.
6.12.3.4.2.1.1.2 Single-Ended Mode of Operation
In the single-ended mode of operation, a clock signal is connected to X1 with X2 left unconnected. A quartz
crystal should not be used in this mode.
This mode is enabled when [XTAL On]=0 which can be achieved by setting XTALCR.OSCOFF=1 and
XTALCR.SE=1.
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In this mode of operation, the clock on X1 is passed through a buffer (Buffer) to the rest of the chip. See X1 Input
Level Characteristics When Using an External Clock Source (Not a Crystal) table for the input requirements of
the buffer.
6.12.3.4.2.1.2 XTAL Output on XCLKOUT
The output of the electrical oscillator that is fed to the rest of the chip can be brought out on XCLKOUT for
observation by configuring CLKSRCCTL3.XCLKOUTSEL and XCLKOUTDIVSEL.XCLKOUTDIV registers . See
the GPIO mux table for a list of GPIOs that XCLKOUT comes out on.
6.12.3.4.2.2 Quartz Crystal
Electrically, a quartz crystal can be represented by an LCR circuit (Inductor-Capacitor-Resistor). However, unlike
an LCR circuit, crystals have very high Q due to the low motional resistance and are also very underdamped.
Components of the crystal are shown in Figure 6-14 and explained below.
ADVANCE INFORMATION
Quartz Crystal
Internal
External
Cm
Rm
C0
CL
Lm
Figure 6-14. Crystal Electrical Representation
Cm (Motional capacitance): Denotes the elasticity of the crystal.
Rm (Motional resistance): Denotes the resistive losses within the crystal. This is not the ESR of the crystal but
can be approximated as such depending on the values of the other crystal components.
Lm (Motional inductance): Denotes the vibrating mass of the crystal.
C0 (Shunt capacitance): The capacitance formed from the two crystal electrodes and stray package
capacitance.
CL (Load capacitance): This is the effective capacitance seen by the crystal at its electrodes. It is external to
the crystal. The frequency ppm specified in the crystal datasheet is usually tied to the CL parameter.
Note that most crystal manufacturers specify CL as the effective capacitance seen at the crystal pins while some
crystal manufacturers specify the CL as the capacitance on just one of the crystal pins. Check with the crystal
manufacturer for how the CL is specified in order to use the correct values in calculations.
From Figure 6-13, CL1 and CL2 are in series so to find the equivalent total capacitance seen by the crystal, the
capacitance series formula has to be applied which simply evaluates to [CL1]/2 if CL1=CL2.
It is recommended to add stray PCB capacitance to this value. 3pF to 5pF are reasonable estimates but the
actual value will depend on the PCB in question.
Note that the load capacitance is a requirement of both the electrical oscillator and crystal. The value chosen has
to satisfy both the electrical oscillator and the crystal.
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The effect of CL on the crystal is frequency pulling. If the effective load capacitance is lower than the target, the
crystal frequency will increase and vice-versa. However, the effect of frequency pulling is usually very minimal
and typically results in less than 10ppm variation from the nominal frequency.
6.12.3.4.2.3 GPIO Modes of Operation
On this device, X1 and X2 can be used as GPIO19 and GPIO18 respectively depending on the operating mode
of the XTAL. Refer to the External Oscillator (XTAL) TRM section.
6.12.3.4.3 Functional Operation
6.12.3.4.3.1 ESR - Effective Series Resistance
ESR = Rm * 1 + C0
CL
2
(1)
Note that the ESR is not the same as motional resistance of the crystal but can be approximated as such if the
effective load capacitance is much greater than the shunt capacitance.
6.12.3.4.3.2 Rneg - Negative Resistance
Negative resistance is the impedance presented by the electrical oscillator to the crystal. It is the amount of
energy the electrical oscillator must supply to the crystal to overcome the losses incurred during oscillation. It
depicts a circuit that provides rather than consume energy and can also be viewed as the overall gain of the
circuit.
The generally accepted practice is to have Rneg > 3x-5x ESR to ensure the crystal starts up under all
conditions. Note that it takes slightly more energy to start-up the crystal than it does to sustain oscillation and
hence if it can be ensured that the negative resistance requirement is met at start-up, then oscillation sustenance
will not be an issue.
Figure 6-15 and Figure 6-16 show the variation between negative resistance and the crystal components for this
device. As can be seen from the chart, the crystal shunt capacitance (C0) and effective load capacitance (CL)
greatly influence the negative resistance of the electrical oscillator. Note that these are typical graphs so refer to
Table 6-5 for min/max values for design considerations.
6.12.3.4.3.3 Start-up Time
Start-up time is an important consideration when selecting the components of the crystal circuit. As mentioned
in the negative resistance section, for reliable start-up across all conditions, it is recommended that the Rneg >
3x-5x the ESR of the crystal.
Crystal ESR and dampening resistor (Rd) greatly affect the start-up time. The higher the two, the longer the
crystal takes to start-up. Longer start-up times are usually a sign the crystal and components are not a correct
match.
Refer to Crystal Oscillator Specifications for the typical start-up times. Note that the numbers specified here are
typical numbers provided for guidance only. Actual start-up time depends heavily on the crystal in question and
the external components.
6.12.3.4.3.3.1 X1/X2 Precondition
On this device, the GPIO19/18 alternate functionality on X1/X2 can be used to speed up the start-up time of the
crystal if needed. This functionality is achieved by preconditioning the load capacitors CL1 and CL2 to a known
state before the XTAL is turned on. See the TRM for details.
6.12.3.4.3.4 DL - Drive Level
Drive level refers to how much power is provided by the electrical oscillator and dissipated by the crystal. The
maximum drive level specified in the crystal manufacturer’s datasheet is usually the maximum the crystal can
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ADVANCE INFORMATION
This is the resistive load the crystal presents to the electrical oscillator at resonance. The higher the ESR, the
lower the Q and less likelihood the crystal will start-up or maintain oscillation. The relationship between ESR and
the crystal components is indicated below.
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dissipate without damage or significant reduction in operating life. On the other hand, the drive level specified
by the electrical oscillator is the maximum power it can provide. The actual power provided by the electrical
oscillator is not necessarily the max power and depends on the crystal and board components.
For cases where the actual drive level from the electrical oscillator exceeds the maximum drive level
specification of the crystal, a dampening resistor (Rd) should be installed to limit the current and reduce the
power dissipated by the crystal. Note that Rd reduces the circuit gain and hence the actual value to use should
be evaluated to make sure all other conditions for start-up and sustained oscillation are met.
6.12.3.4.4 How to Choose a Crystal
Using Crystal Oscillator Specifications as a reference:
ADVANCE INFORMATION
1. Pick a crystal frequency e.g: 20MHz
2. Check that the ESR of the crystal = 1mW. If this requirement is not met, a dampening
resistor Rd can be used. Refer to DL - Drive Level on other points to consider when using Rd.
6.12.3.4.5 Testing
It is recommended that the user have the crystal manufacturer completely characterize the crystal with their
board to ensure the crystal always starts up and maintains oscillation.
Below is a brief overview of some measurements that can be performed:
Due to how sensitive the crystal circuit is to capacitance, it is recommended not to connect scope probes to X1
and X2. If scope probes must be used to monitor X1/X2, an active probe with
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