Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
18-Bit Registered Transceivers
SCCS056A - August 1994 - Revised October 2001
Features
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CY74FCT16500T
CY74FCT162500T
Functional Description
FCT-C speed at 4.6 ns
Ioff supports partial-power- mode operation
Edge-rate control circuitry for significantly improved
noise characteristics
Typical output skew < 250 ps
ESD > 2000V
TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages
Industrial temperature range of −40˚C to +85˚C
VCC = 5V ± 10%
These 18-bit universal bus transceivers can be operated in
transparent, latched, or clock modes by combining D-type
latches and D-type flip-flops. Data flow in each direction is
controlled by output-enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock inputs (CLKAB and CLKBA)
inputs. For A-to-B data flow, the device operates in transparent
mode when LEAB is HIGH. When LEAB is LOW, the A data is
latched if CLKAB is held at a HIGH or LOW logic level. If LEAB
is LOW, the A bus data is stored in the latch/flip-flop on the
HIGH-to-LOW transition of CLKAB. OEAB performs the output
enable function on the B port. Data flow from B-to-A is similar
to that of A-to-B and is controlled by OEBA, LEBA, and
CLKBA.
CY74FCT16500T Features:
• 64 mA sink current, 32 mA source current
• Typical VOLP (ground bounce)
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