GC4016-PBZ

SLWS133A GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 August 27, 2001 Graychip reserves the right to make changes in circuit design and/or specifications at any time without notice. The user is cautioned to verify that datasheets are current before placing orders. Information provided by Graychip is believed to be accurate and reliable. No responsibility is assumed by Graychip for its use, nor for any infringement of patents or other rights of third parties which may arise from its use. No license is granted by implication or otherwise under any patent rights of Graychip. Ó GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 REVISION HISTORY Revision Date Description 0.1 February 24, 2000 Original 0.2 April 10, 2000 Rewritten to reflect 2.5volt core, 3.3volt I/O power requirements, Removed all references to TQ100 thin quad flat package, All references to GC4017 are changed to GC4016, Added Vcore and Vpin descriptions throughout, Updated power consumption equations, Simplified AC timing specifications, Corrected Resampler Filter Specs, Corrected typos, and miscellaneous errors. 0.3 April 20, 2000 Corrected Table 10: GC4016 Pin Out Locations, B14 and C14 VCORE and VPAD swapped, other VPAD and GND pins added. 0.4 August 8, 2000 Minor Editing throughout Page 12, Table 2, corrected +90 and -90 values Added TAG_22 descriptions throughout Added four separate frame strobe mode descriptions Added resampler and ratio sync descriptions Added one shot mode descriptions Added parallel output timing diagram Revised initialization procedures 1.0 August 27, 2001 Minor editing throughout Electrical and Timing Specifications in Section 6 updated to match production test References to LVDS levels changed to differential inputs. Diagnostics, GC4016 Configuration Generator, IS95 and UMTS examples added  GRAYCHIP,INC. -i- August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 CONTACTING GRAYCHIP CORPORATE OFFICES: GRAYCHIP, Inc. 2185 Park Blvd. Palo Alto, CA 94306 PHONE: (650) 323-2955 FAX: (650) 323-0206 WEB PAGE: www.graychip.com E-MAIL: sales@graychip.com tech-support@graychip.com  GRAYCHIP,INC. - ii - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 Table of Contents 1.0 KEY FEATURES ......................................................................................................................... 1 2.0 BLOCK DIAGRAM ...................................................................................................................... 1 3.0 FUNCTIONAL DESCRIPTION .................................................................................................... 2 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 4.0 CONTROL INTERFACE ............................................................................................................................................ 2 INPUT FORMAT ........................................................................................................................................................ 4 THE DOWN CONVERTERS ..................................................................................................................................... 4 MULTICHANNEL MODES....................................................................................................................................... 10 RESAMPLER........................................................................................................................................................... 12 OVERALL GAIN ...................................................................................................................................................... 15 PEAK COUNTER .................................................................................................................................................... 15 OUTPUT MODES .................................................................................................................................................... 16 CLOCKING .............................................................................................................................................................. 22 POWER DOWN MODES......................................................................................................................................... 23 SYNCHRONIZATION .............................................................................................................................................. 24 INITIALIZATION ...................................................................................................................................................... 25 DATA LATENCY...................................................................................................................................................... 25 DIAGNOSTICS ........................................................................................................................................................ 25 JTAG........................................................................................................................................................................ 25 MASK REVISION REGISTER ................................................................................................................................. 26 PACKAGING ............................................................................................................................. 27 4.1 5.0 GC4016-PB 160 Ball Plastic Ball Grid Array (PBGA) .............................................................................................. 27 CONTROL REGISTERS ........................................................................................................... 31 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 6.0 GLOBAL CONTROLS ............................................................................................................................................. 31 PAGED REGISTERS .............................................................................................................................................. 34 CFIR COEFFICIENT PAGES .................................................................................................................................. 35 PFIR COEFFICIENT PAGES .................................................................................................................................. 35 CHANNEL FREQUENCY PAGES........................................................................................................................... 36 CHANNEL CONTROL PAGES................................................................................................................................ 37 RESAMPLER COEFFICIENT PAGES .................................................................................................................... 42 RESAMPLER CONTROL PAGE ............................................................................................................................. 43 RESAMPLER RATIO PAGE) .................................................................................................................................. 45 CHANNEL OUTPUT PAGES .................................................................................................................................. 45 OUTPUT CONTROL PAGE .................................................................................................................................... 46 SPECIFICATIONS..................................................................................................................... 53 6.1 6.2 6.3 6.4 6.5 6.6 7.0 ABSOLUTE MAXIMUM RATINGS .......................................................................................................................... 53 RECOMMENDED OPERATING CONDITIONS ...................................................................................................... 53 THERMAL CHARACTERISTICS............................................................................................................................. 53 POWER CONSUMPTION ....................................................................................................................................... 54 DC CHARACTERISTICS......................................................................................................................................... 54 AC CHARACTERISTICS ......................................................................................................................................... 55 APPLICATION NOTES ............................................................................................................. 56 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 POWER AND GROUND CONNECTIONS .............................................................................................................. 56 STATIC SENSITIVE DEVICE .................................................................................................................................. 56 MOISTURE SENSITIVE PACKAGE........................................................................................................................ 56 THERMAL MANAGEMENT ..................................................................................................................................... 56 EXAMPLE CFIR FILTER SETS............................................................................................................................... 57 EXAMPLE PFIR FILTER SETS ............................................................................................................................... 58 EXAMPLE RESAMPLER CONFIGURATIONS ....................................................................................................... 60 GC4016 CONFIGURATION GENERATOR............................................................................................................. 61 EXAMPLE GSM APPLICATION .............................................................................................................................. 62 EXAMPLE IS-136 DAMPS APPLICATION.............................................................................................................. 64 IS-95 NB-CDMA APPLICATION.............................................................................................................................. 66 UMTS WB-CDMA APPLICATION ........................................................................................................................... 68 DIAGNOSTICS ........................................................................................................................................................ 71 OUTPUT TEST CONFIGURATION......................................................................................................................... 73  GRAYCHIP,INC. - iii - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 LIST OF FIGURES Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: GC4016 Block Diagram ......................................................................................................................................................... 1 Normal Control I/O Timing ..................................................................................................................................................... 3 Edge Write Control Timing..................................................................................................................................................... 3 The Down Converter Channel ............................................................................................................................................... 5 Zero Pad Synchronization...................................................................................................................................................... 6 NCO Circuit............................................................................................................................................................................ 6 Example NCO Spurs.............................................................................................................................................................. 7 NCO Peak Spur Plot .............................................................................................................................................................. 7 Five Stage CIC Decimate by N Filter .....................................................................................................................................8 Typical CFIR Specifications ................................................................................................................................................... 9 Typical PFIR Specifications ................................................................................................................................................... 9 Resampler Channel Block Diagram..................................................................................................................................... 12 The Resampler’s Spectral Response .................................................................................................................................. 13 Wide Word Microprocessor Port .......................................................................................................................................... 19 Serial Output Formats.......................................................................................................................................................... 21 Parallel Mode Timing ........................................................................................................................................................... 23 GC4016 160 Pin Plastic Ball Grid Array .............................................................................................................................. 27 GC4016 Pin Assignments.................................................................................................................................................... 28 Overall Spectral Responses of Example Filters................................................................................................................... 59 Frequency Response for the Example GSM Application ..................................................................................................... 62 Frequency Response for the Example DAMPS Application ................................................................................................ 64 Frequency Response for the Example IS95 Application...................................................................................................... 66 Frequency Response for the Example UMTS Application................................................................................................... 69 Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Table 26: Table 27: Table 28: Table 29: Table 30: Table 31: Table 32: Table 33: Table 34: Table 35: Table 36: Table 37: Table 38: Table 39: Table 40: Input Mode Controls...............................................................................................................................................................4 Multichannel mode settings ................................................................................................................................................. 12 Output Mode Controls.......................................................................................................................................................... 17 Channel Output Map, Synchronous Four Channel Mode .................................................................................................... 18 Channel Output Map, Synchronous Two Channel Mode..................................................................................................... 18 Channel Output Map, Single Channel Mode ....................................................................................................................... 18 Sync Modes ......................................................................................................................................................................... 24 Recommended Sync Settings.............................................................................................................................................. 24 Mask Revisions.................................................................................................................................................................... 26 GC4016 Pin Out Locations Top View .................................................................................................................................. 29 Global Control Registers...................................................................................................................................................... 31 Page Assignments ............................................................................................................................................................... 34 CFIR Coefficient Pages ....................................................................................................................................................... 35 PFIR Coefficient Pages........................................................................................................................................................ 35 Channel Control Registers................................................................................................................................................... 37 Resampler Coefficient Pages (Single filter mode) ............................................................................................................... 42 Resampler Control Registers............................................................................................................................................... 43 Resampler Ratio Page......................................................................................................................................................... 45 Output Control Registers ..................................................................................................................................................... 46 Absolute Maximum Ratings ................................................................................................................................................. 53 Recommended Operating Conditions.................................................................................................................................. 53 Thermal Data ....................................................................................................................................................................... 53 DC Operating Conditions ..................................................................................................................................................... 54 AC Characteristics ............................................................................................................................................................... 55 Example CFIR Filters........................................................................................................................................................... 57 Default PFIR Filters.............................................................................................................................................................. 58 Resampler Bypass Mode..................................................................................................................................................... 60 Resampler Modes................................................................................................................................................................ 60 Desired GSM Specifications ................................................................................................................................................ 62 Example GSM Configuration ............................................................................................................................................... 63 Desired DAMPS Specifications............................................................................................................................................ 64 Example DAMPS Configuration........................................................................................................................................... 65 Desired IS95 NB-CDMA Specifications ............................................................................................................................... 66 Example IS95 NB-CDMA Configuration .............................................................................................................................. 68 Desired UMTS Specifications .............................................................................................................................................. 68 Example UMTS Configuration ............................................................................................................................................. 70 Diagnostic Test 1 ................................................................................................................................................................. 71 Diagnostic Test 2 ................................................................................................................................................................. 71 Diagnostic Test 3 ................................................................................................................................................................. 72 Diagnostic Test 4 ................................................................................................................................................................. 73 LIST OF TABLES  GRAYCHIP,INC. - iv - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP KEY FEATURES BLOCK DIAGRAM B IN (14 BITS) A IN (14 BITS) CROSSBAR SWITCH DIAGNOSTICS CONTROL INTERFACE 21 TAP PROGRAMMABLE DECIMATE BY 2 FILTER (CFIR) A[0:4] FILTER 21 TAP PROGRAMMABLE DECIMATE BY 2 FILTER (CFIR) FILTER 21 TAP PROGRAMMABLE DECIMATE BY 2 FILTER (CFIR) GENERATOR NCO SINE/COSINE NCO GENERATOR DECIMATE BY 4 TO 4K DECIMATE BY 4 TO 4K FILTER 21 TAP PROGRAMMABLE DECIMATE BY 2 FILTER (CFIR) PHASE OFFSET WR DECIMATE BY 4 TO 4K TUNING FREQUENCY FILTER TUNING FREQUENCY DECIMATE BY 4 TO 4K CE RD GENERATOR NCO (16 bit input and 12 bit floating point modes use the DIN pins for the LSB’s of inputs AIN, BIN, and CIN) SINE/COSINE CLOCK DOUBLING AND DISTRIBUTION CIRCUIT PHASE OFFSET CK DIN (14 BITS) CIN (14 BITS) SINE/COSINE 2.0 PHASE OFFSET • • • • • • TUNING FREQUENCY • • • • • NCO • • • • GENERATOR • • • • • SINE/COSINE • Input rates up to 100 MSPS Four independent digital down convert (DDC) channels Single channel GC4011 and Dual channel GC4012 derivatives are available Independent decimation and resampling Independent tuning, phase and gain controls Input Crossbar Switch for: Four 14 bit Inputs, or Three 16 bit Inputs, or Three 12 bit + 3 bit exponent inputs, or Two 14 bit differential inputs. Decimation factors of 32 to 16,384 in each channel 16 to 32 by combining two channels 8 to 16 by combining four channels Zero padding for lower decimation factors Resampler for arbitrary decimation factors Peak detection counters for AGC loop controls Outputs can be either: Bit serial, or Nibble serial (link port), or Parallel port, or Memory mapped registers 12, 16, 20, or 24 bit output samples 0.02 Hz tuning resolution >100 dB far band rejection >115 dB spur free dynamic range User programmable 21 tap and 63 tap decimate by two filters, independent per channel. Nyquist filtering for QPSK or QAM symbol data Resampler provides additional filtering and allows arbitrary input/output rate selections Microprocessor interface for control Built in diagnostics Application examples: Four 4X oversampled GSM, DAMPS, or IS95 CDMA carriers, Two 8X oversampled IS95 CDMA carriers, or Two 2X oversampled 3.84MB UMTS carriers, or One 4X oversampled 3.84MB UMTS carrier Core power consumption at 80 MHz, 2.5 volts: 100 mW per DAMPS channel 115 mW per GSM channel 115 mW per IS95 channel 620 mW per 3.84MB UMTS channel Industrial temperature range (-40C to +85C) GC4016-PB 160 ball PBGA (15mm by 15mm) package 3.3volt I/O voltage, 2.5volt core voltage JTAG Boundary Scan PHASE OFFSET • • • • • • TUNING FREQUENCY 1.0 DATA SHEET REV 1.0 C[0:7] TCK TMS TDI TDO 63 TAP PROGRAMMABLE DECIMATE BY 2 FILTER (PFIR) 63 TAP PROGRAMMABLE DECIMATE BY 2 FILTER (PFIR) 63 TAP PROGRAMMABLE DECIMATE BY 2 FILTER (PFIR) 63 TAP PROGRAMMABLE DECIMATE BY 2 FILTER (PFIR) JTAG BOUNDARY SCAN TEST LOGIC RESAMPLER AND GAIN BLOCK COMBINES CHANNELS, FILTERS, RESAMPLES AND ADJUSTS GAIN ACKNOWLEDGE (LINK MODE) (FILTERING, RESAMPLING AND GAIN ADJUSTMENTS ARE PERFORMED INDEPENDENTLY ON EACH CHANNEL) 24 BIT PARALLEL OUTPUT A B C D (BIT SERIAL OUTPUTS) Figure 1. GC4016 Block Diagram  GRAYCHIP,INC. -1- READY SO OUTPUT FORMAT FRAME SYNCS SIB SYNC COUNTER AND DIAGNOSTIC TEST GENERATOR BIT-CLOCK SIA August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP 3.0 DATA SHEET REV 1.0 FUNCTIONAL DESCRIPTION 3.1 The GC4016 quad receiver chip contain four identical down-conversion circuits. Each downconvert circuit accepts a real sample rate up to 100 MHz, down converts a selected carrier frequency to zero, decimates the signal rate by a programmable factor ranging from 32 to 16,384 and then resamples the channel to adjust the sample rate up or down by an arbitrary factor. In the real output mode the output sample rate is doubled and the signal is output as a real signal centered at Fout/4. The channels may be combined to The chip is configured by writing control information into control registers within the chip. The control registers are grouped into 8 global registers and 128 pages of registers, each page containing up to 16 registers. The global registers are accessed as addresses 0 through 7. Address 2 is the page register which selects which page is accessed by addresses 16 through 31. The contents of these control registers and how to use them are described in Section 5. The registers are written to or read from using the C[0:7], A[0:4], CE, RD and WR pins. Each control register has been assigned a unique address within the chip. This interface is designed to allow the GC4016 chip to appear to an external processor as a memory mapped peripheral (the pin RD is equivalent to a memory chip’s OE pin). produce wider band and/or oversampled outputs or to process complex input data. The chip outputs the down-converted signals in any one of several formats (microprocessor, four serial lines, one TDM serial line, nibble, LINK, or 24 bit parallel port. The chip contains two user programmable output filters per path which can be used to arbitrarily shape the received data’s spectrum. These filters can be used as Nyquist receive filters for digital data transmission. The chip also contains a resampling filter to provide additional filtering and to allow the user complete flexibility in the selection of input and output sample rates. An external processor (a microprocessor, computer, or DSP chip) can write into a register by setting A[0:4] to the desired register address, selecting the chip using the CE pin, setting C[0:7] to the desired value and then pulsing WR low. The data will be written into the selected register when both WR and CE are low and will be held when either signal goes high. An alternate “edge write” mode can be used to strobe the data into the selected register when either WR or CE goes high. This is useful for processors that do not guarantee valid data when the write strobe goes low, but guarantee that the data will be stable before the write strobe goes high. The edge write mode is necessary for these processors, as some control registers (such as most sync or reset registers) are sensitive to transient values on the C[0:7] data bus. Two downconverter paths can be merged to be used as a single complex input down-conversion circuit. Two paths may also be combined to support wider band output rates or oversampled outputs. Four paths may be combined to support both wider band output and oversampling. The downconverters are designed to maintain over 115 dB of spur free dynamic range and over 100 dB of out of band rejection. A five stage CIC and 20 bit internal datapaths support this high dynamic range signal processing requirement. Each downconvert circuit accepts 16 bit inputs and produces 24 bit outputs (can be rounded back to 12, 16, or 20 bits). The frequencies and phase offsets of the four sine/cosine sequence generators can be independently specified, as can the decimation and filter parameters of each circuit. To read from a control register the processor must set A[0:4] to the desired address, select the chip with the CE pin, and then set RD low. The chip will then drive C[0:7] with the contents of the selected register. After the processor has read the value from C[0:7] it should set RD and CE high. The C[0:7] pins are turned off (high impedance) whenever CE or RD are high or when WR is low. The chip will only drive these pins when both CE and RD are low and WR is high. On chip diagnostic circuits are provided to simplify system debug and maintenance. One can also ground the RD pin and use the WR pin as a read/write direction control and use the CE pin as a control I/O strobe. Figure 2 shows timing diagrams illustrating both I/O modes. The chip receives configuration and control information over a microprocessor compatible bus consisting of an 8 bit data I/O port, a 5 bit address port, a chip enable strobe, a read strobe and a write strobe. The chip’s control registers (8 bits each) are memory mapped into the 5 bit address space of the control port. The edge write mode, enabled by the EDGE_WRITE control bit in register 0, allows for rising edge write cycles. In this mode the C[0:7] data only needs to be stable for a setup time before the rising edge of the write strobe, and held for a small hold time afterwards. This mode is appropriate for Sections 7.9 through 7.12 describe how to use the chip for GSM, D-AMPS, CDMA and UMTS applications, including control register values and filter coefficients.  GRAYCHIP,INC. CONTROL INTERFACE -2- August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP CE WR DATA SHEET REV 1.0 tREC tCSU RD tREC tCSU A[0-4] tCDLY C[0-7] tCZ READ CYCLE- NORMAL MODE CE WR tREC tCSPW tCSU RD tREC tCSU A[0-4] tCHD C[0-7] WRITE CYCLE- NORMAL MODE CE tREC WR tREC tCSU A[0-4] tCDLY C[0-7] tCZ READ CYCLE- RD HELD LOW CE WR tCSPW tREC tCSU A[0-4] tREC tCHD C[0-7] WRITE CYCLE- RD HELD LOW Figure 2. Normal Control I/O Timing chip’s expansion bus. Address pin A3 is grounded in this mode and the LSB of the page register (address 2) is used in its place. The four bit mode is turned on using the 4_BIT_ADDRESS control bit in address 4. processors that do not provide stable data before the start of the write pulse. Figure 3 shows the timing for this mode. The setup, hold and pulse width requirements for control read or write operations are given in Section 6.0. The chip also operates in a four bit address mode which is intended to be used with the 4 address bit TI320C6X DSP CE WR RD tREC tCSPW tCSU tREC tCSU A[0-4] tCHD C[0-7] EDGE WRITE MODE tEWCSU Figure 3. Edge Write Control Timing  GRAYCHIP,INC. -3- August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP 3.2 DATA SHEET REV 1.0 3.3 INPUT FORMAT THE DOWN CONVERTERS Each down converter contains an NCO and a mixer to quadrature down convert the signal to baseband, followed by The chip accept five input formats: (1) Four input ports of 14 bit data, a 5 stage Cascade Integrate Comb (CIC)1 filter and two stages of decimate by two filtering to isolate the desired signal. The signal is then sent to a resampler which can increase or decrease the final output sample rate to match the post-processing requirements for baud rate sampling or oversampling. (2) Three input ports of 16 bit data, (3) Two input ports of 14 bit low voltage differential data, (Contact Graychip for more information) (4) Three ports of 12 bit with 3 bit exponent floating point data, and (5) Three ports of multiplexed, dual channel, 12 bit with 3 bit exponent floating point data A block diagram of the channel is shown in Figure 4. The INPUT FORMAT circuit converts the selected input data into the 19 bit format described in Section 3.2. The ZERO PAD function allows the user to clock the chip at a higher rate than the input sample rate. The 12, 14 and 16 bit input words are in a two’s complement format. The MSB_POL control bit in address 27 of the channel control pages can be used to convert offset binary data to the desired two’s complement format. The 3 bit exponent in the floating point format is an unsigned integer ranging from 0 to 7. All inputs are converted to the internal 19 bit format at the input to each channel. The 14 and 16 bit input words are put into the upper 14 and 16 bits respectfully of the 19 bit word. The unused LSBs are cleared. The NCO/Mixer circuit tunes the desired center frequency down to DC where it is low pass filtered by the CIC, CFIR, PFIR and Resampler filters. The CIC filter reduces the sample rate by a programmable factor ranging from 8 to 4,096. The CIC outputs are followed by a coarse gain stage and then followed by two stages of decimate by 2 filtering. The coarse gain circuit allows the user to boost the gain of weak signals up to 42 dB in 6 dB steps. The first stage of the two stage filter is a 21 tap decimate by 2 filter (CFIR) with user programmable tap weights. The 21 tap symmetrical lowpass filter is downloaded into the chip as 12 words, 16 bits each. This filter is typically programmed to decimate by two, while The 12 bit floating point word is shifted down and sign extended by the amount specified by the 3 bit exponent and then put into the MSBs of 19 bit word. A crossbar switch allows the user to route any input source to any downconverter channel. Table 1 shows the suggested control register settings required for each input mode. See Section 5.6 for detailed descriptions of each control setting 1. Hogenhauer, An Economical Class of Digital Filters for Decimation and Interpolation, IEEE transactions on ASSP, April 1981. Table 1: Input Mode Controls 16 bit mode 14 bit differential mode 12 + 3 bit exponent mode Multiplexed 12 + 3 bit exponent mode 4 to 7 4 to 7 4 to 7 unused unused 16 1 1 1 0 0 23 1 1 1 0 0 Control Address in Channel Control Pages 7, 15, 23 and 31 14 bit mode SHIFT1 16 USE_SHIFT MIX20B1 INPUT_SEL 3 SEL_AB 27 0,1,2,3 0,1,2 4,5 0,1,2 0,1,2 27 0 0 0 0 0 or 1 INPUT_MODE 27 0 1 0 2 2 DIFF_IN 4 (Global Page) 0 0 1 0 0 NOTES: 1. SHIFT is normally left at 4, see Section 3.3.3 for details. 2. For decimations over 3104, MIX20B should be 0 to allow SHIFT to be less than 4, see Section 3.3.3. 3. INPUT_SEL is used to select the input port used by each channel, 0=port A, 1=portB, 2=port C, 3=portD.  GRAYCHIP,INC. -4- August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 compensating for the droop in the CIC filter’s passband. The second stage is a 63 tap decimate by 2 filter (PFIR) with user programmable tap weights. The user can customize the channel’s spectral response using the PFIR filter. A typical use of the PFIR is to perform matched (root-raised cosine) filtering. The 63 tap symmetrical filter is downloaded into the chip as 32 words, 16 bits each. Both filters must be programmed as there are no default filter coefficient sets. bit word (6 integer bits and 26 fractional bits). The time resolution of the new sampling points is user programmable down to 1/64th of the PFIR output’s sample period. If R is a multiple of the selected time resolution, then the resampling process will have no resampling time jitter. If R is not a multiple of the time resolution, then the output will be generated at the time instant closest to the desired output time. The CIC, CFIR, and PFIR filters can all be configured in a SPLITIQ mode where the channel only processes the real portion of the mixer output. In this case the minimum CIC decimation is 4. By using two channels in parallel one can process twice the output bandwidth by processing the real portion of the mixer output in one channel and the imaginary portion in a second channel (hence the name “split I/Q”). One can also offset the decimation timing between channels so that two or even four channels can be used to generate oversampled data. Using this capability each GC4016 chip can downconvert wideband signals such as 4X oversampled 5.12 Msymbol/sec MCNS data, or 4X oversampled 5 MHz WB-CDMA (UMTS) data, or two 8X oversampled NB-CDMA IS95 signals. The resampler is typically used to either generate oversampled output data (for instance 4x oversampled QPSK or GMSK data), or to alter the sampler rate to match a multiple of the baud rate of a QPSK or GMSK signal. The resampling operation allows the user to design a system where the ADC sample rate does not need to be equal to an integer multiple of the baud rate of the desired output signal. The resampler can also be used as a final filtering stage. A final shift circuit allows the user to shift the data by up to 15 bits to properly place it in the output word. The output word may be rounded to 12,16, 20, or 24 bits. The data may be output from the chip via a microprocessor interface, serial pins, or using a parallel port. The parallel port is particularly valuable for wideband output data. The PFIR will also, if desired, convert the complex output data to real. The complex to real conversion also doubles the output sample rate so that the PFIR does not decimate in this mode. This mode is useful when one wants to output real data. 3.3.1 Zero Padding 20 20 FINAL SHIFT CHANNELS) RESAMPLER RES TAPS RATIO FINE GAIN PFIR TAPS PFIR FILTER DECIMATE BY 2 CFIR FILTER DECIMATE BY 2 COARSE GAIN 24 (SHARED BETWEEN 20 CIC FILTER DECIMATE BY 8 TO 4K 19 INPUT FORMAT AND ZERO PAD IN 12-16 bits N COARSE The PFIR filter is followed by a resampler. The resampler filters the PFIR output to generate new sample points in between the PFIR output samples. The resampler is programmed to generate new output samples spaced in time by “R” times the PFIR output’s sample period. The value R is called the resampling ratio. If R is less than one, the resampler will interpolate. If R is greater than one, the resampler will decimate. The value of R is specified as a 32 CFIR TAPS The input samples are normally clocked into the chip at the clock rate, i.e., the input sample rate is equal to the clock rate. Input rates lower than the clock rate can be accepted by using the zero pad mode. When enabled by setting the ZPAD_EN bit in address 19 of the channel control pages, the zero pad mode will insert “NZERO” zeroes between each input sample, where NZERO ranges from 0 to 15, allowing input data rates down to 1/16th the clock rate. NZERO is set in address 19 24 I TO OUTPUT CIRCUIT Q 12,16, 20 or 24 bits 20 TUNING FREQUENCY PHASE OFFSET NCO Figure 4. The Down Converter Channel  GRAYCHIP,INC. -5- August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 CK Sample taken SIB Input Data is sampled every (NZERO+1) clocks thereafter 3+NZERO CLOCKS Figure 5. Zero Pad Synchronization The tuning frequency is set to FREQ according to the Zero padding lowers the effective decimation ratio. For example, the minimum complex output decimation using a single channel is normally 32. If the input data rate is 5 MSPS and the system can clock the chip at 40 MHz, then the zero pad function can be used to insert seven zeros between each sample, padding the 5 MSPS input data rate up by a factor of eight to 40 MSPS. The minimum decimation of 32 from the 40MHz rate results in an output rate of 1.25 MSPS, which is an effective decimation of 4 relative to the original 5 MSPS data. formula FREQ = 232F/FCK, where F is the desired tuning frequency and FCK is the chip’s clock rate. The 16 bit phase offset setting is PHASE = 216P/2π, where P is the desired phase in radians ranging between 0 and 2π. Note that a positive tuning frequency should be used to downconvert the signal. A negative tuning frequency can be used to upconvert the negative (spectrally flipped) image of the desired signal. FREQ and PHASE are set in addresses 16 through 21 of each channel frequency pages. A sync signal is used to synchronize the zero padding. The ZPAD_SYNC control in address 19 selects the source of the sync signal. The sync signal can be used to identify when the chip will sample the input data. Figure 5 shows the timing when SIB (ZPAD_SYNC=3) is selected as the sync source. The NCO’s frequency, phase and accumulator can be initialized and synchronized with other channels using the FREQ_SYNC, PHASE_SYNC, and NCO_SYNC controls in addresses 17 and 18 of the channel control pages. The FREQ_SYNC and PHASE_SYNC controls determine when new frequency and phase settings become active. Normally these are set to “always” so that they take effect immediately, but can be used to synchronize frequency hopping or beam forming systems. The NCO_SYNC control is usually set to never, but can be used to synchronize the LOs of multiple channels. Zero padding can be used to synchronize extracting data from a TDM bus. By adjusting the timing of SIB as shown in Figure 5, the user can choose which sample to take from the TDM bus. The zero pad function has a gain equal to: ZPAD_GAIN =1/(1+NZERO). The NCO’s spur level is reduced to below -113 dB through the use of phase dithering. The spectrums in Figure 7 show the NCO spurs for a worst case tuning frequency before and after dithering has been turned on. Notice that the spur level decreases from -105 dB to -116 dB. Dithering is turned on or off using the DITHER_SYNC control in address 18. 3.3.2 The Numerically Controlled Oscillator (NCO) The tuning frequency of each down converter is specified as a 32 bit word and the phase offset is specified as a 16 bit word. The NCOs can be synchronized with NCOs on other chips. This allows multiple down converter outputs to be coherently combined, each with a unique phase and amplitude. A block diagram of the NCO circuit is shown in Figure 6. The worst case NCO spurs at -113 to -116dB, such as the one shown in Figure 7(b), are due to a few frequencies that are related to the sampling frequency by multiples of FCK/96 and FCK/124. In these cases the rounding errors in DITHER PHASE GENERATOR 32 BITS 32 BITS 16 BITS 23 MSBs 5 BITS 18 MSBs FREQ SINE/COSINE LOOKUP TABLE 20 BITS SINE/COSINE OUT Figure 6. NCO Circuit  GRAYCHIP,INC. -6- August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 FREQ=5/24 F S FREQ=5/24 F S -105 dB -116 dB a) Worst case spectrum without dither b) Spectrum with dither (tuned to same frequency) Figure 7. Example NCO Spurs -107 dB -121 dB a) Plot without dither or phase initialization b) Plot with dither and phase initialization Figure 8. NCO Peak Spur Plot achieve a CIC gain of less than or equal to unity when the CIC decimation is greater than 3104. See Table 1. the sine/cosine lookup table repeat in a regular fashion, thereby concentrating the error power into a single frequency, rather than spreading it across the spectrum. These worst case spurs can be eliminated by selecting an initial phase that minimizes the errors or by changing the tuning frequency by a small amount (50 Hz). Setting the initial phase to 4 for multiples of FCK/96 or FCK/124 (and to 0 3.3.3 Five Stage CIC Filter The mixer outputs are decimated by a factor of N in a five stage CIC filter, where N is any integer between 8 and 4096 (between 4 and 2048 for SPLITIQ mode). The value of N is programmed independently for each channel in addresses 21 and 22 of each channel control page. The programmable decimation allows the chip’s usable output bandwidth to range from less than 4 kHz to over 3 MHz when the input rate is 100 MHz. Wider output bandwidths are obtainable by using multiple channels (see Section 3.4). A block diagram of the CIC filter is shown in Figure 9. for other frequencies) will result in spurs below -115 for all frequencies. Figure 8 shows the maximum spur levels as the tuning frequency is scanned over a portion of the frequency range with the peak hold function of the spectrum analyzer turned on. Notice that the peak spur level is -107 dB before dithering and is -121 dB after dithering has been turned on and the phase initialization described above has been used. The output of the mixer may be rounded to 16 or 20 bits. Twenty bit rounding (MIX20B is set in address 23) is normally used with the 14 or 16 bit input modes. Sixteen bit rounding (MIX20B disabled) is normally used with the floating point, 12 bit input modes. Sixteen bit rounding is also required to  GRAYCHIP,INC. -7- August 27, 2001 This document contains information which may be changed at any time without notice CIC_SCALE DATA 20 BITS IN DATA SHEET REV 1.0 DECIMATE BY FACTOR OF N GC4016 MULTI-STANDARD QUAD DDC CHIP CLOCKED AT FULL RATE UPPER 24 BITS 24 BITS DATA OUT CLOCKED AT 1/N RATE Figure 9. Five Stage CIC Decimate by N Filter 3.3.5 The First Decimate By Two Filter (CFIR) The CIC filter has a gain equal to N5 which must be compensated for in the “CIC_SCALE” circuit shown in Figure 9. The CIC_SCALE circuit has a gain equal to The CIC/Coarse gain outputs are filtered by two stages of filtering. The first stage is a 21 tap decimate by 2 filter with programmable 16 bit coefficients. Since this filter decimates by two, a stopband must be created in that portion of the spectrum that would alias into the signal of interest. This filter has very lax transition band specifications so 21 taps is sufficient to both provide the required anti-aliasing stopband, and to provide compensation for the droop in the CIC filter’s passband. The CFIR is also used, in some cases, to provide additional stopband rejection for the second stage PFIR filter. Figure 10 illustrates the passband and stopband requirements of the filter. FCFIR is the input sample rate to the 2(SHIFT+SCALE+6*BIG_SCALE-62), where SCALE ranges from 0 to 5 and BIG_SCALE ranges from 0 to 7. The range of SHIFT is 4-7 if MIX20B is enabled and is 0-7 if MIX20B is disabled. The overall gain of the CIC circuit is equal to: 5 CIC_GAIN = N 2 ( SHIFT +SCALE + 6 × BIG_SCALE – 62 ) The user must select values for SHIFT, SCALE and BIG_SCALE (addresses 16 and 23 of each channel control page) such that CIC_GAIN (including ZPAD_GAIN if blanking is used) is less than one, i.e., SHIFT, SCALE and BIG_SCALE must be selected such that: CFIR filter. FCFIR/4 is the output sample rate of the channel ( SHIFT + SCALE + 6 × BIG_SCALE ) ≤ before resampling. ( 62 – 5log2 N + log2 (NZERO+1) ) The user downloaded filter coefficients are 16 bit 2’s complement numbers. Unity gain will be achieved through the filter if the sum of the 21 coefficients is equal to 65536. If the sum is not 65536, then CFIR will introduce a gain equal Overflows due to improper gain settings will go undetected if this relationship is violated. For example, if N is equal to 8 and SHIFT=4, then this restriction means that BIG_SCALE and SCALE should be less than or equal to 7 and 1 respectively. The SHIFT, BIG_SCALE and SCALE settings are independent for each channel. See Section 3.7 for a description of the channel’s overall gain. to: The gain of each channel can be boosted up to 42 dB by shifting the output of the CIC filter up by 0 to 7 bits prior to rounding it to 20 bits. The coarse gain is: COARSE The 21 coefficients are identified as coefficients h0 through h20, where h10 is the center tap. The coefficients are , where COARSE ranges from assumed to be symmetric, so only the first 11 coefficients (h0 0 to 7. COARSE is set in address 25 of each channel control page. Overflows in the coarse gain circuit are saturated to plus or minus full scale. The coarse gain is used to increase the gain of an individual signal after the input bandwidth of the downconverter has been reduced by a factor of N in the CIC filter. If the signal power across the input bandwidth is relatively flat, as is the case in most frequency division multiplexed (FDM) systems, then one would want to boost the signal power out of the CIC filter by a factor of COARSE_GAIN = , where CFIR_SUM is the sum of the 21 coefficients. Coefficient sets for a variety of standards in cellular and cable modem applications are given in Section 7. The output of CFIR is rounded to 20 bits (using the round-to-even algorithm). Overflows are detected and hard limited. Overflows can be directed to the channel overflow detection block. 3.3.4 Coarse Channel Gain COARSE_GAIN = 2 CFIR_SUM CFIR_GAIN = ----------------------------65536 through h10) are loaded into the chip. A non-symmetric mode (NO_SYM_CFIR in address 25) allows the user to download an 11 tap non-symmetric filter as taps h0 through h10. The newest sample is multiplied by h0 and the oldest is multiplied by h10. NOTE: Filters normally multiply h0 by the oldest data, hence one may wish to reverse the tap order in the non-symmetric mode. CFIR has a programmable delay of one CFIR input sample. This delay is used in a multichannel mode to alter N . Each channel can be given its own coarse gain setting. See Section 3.7 for a description of the channel’s overall gain.  GRAYCHIP,INC. -8- August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 Signal of Interest Passband (Typically 0.05 to 0.125 FCFIR) 0 dB Very wide transition band Power Stopband (Typically starts at 0.375 F CFIR) -100 dB 0 FCFIR/8 FCFIR/4 FCFIR/2 Frequency Figure 10. Typical CFIR Specifications the filter if the sum of the 63 coefficients is equal to 65536. If the sum is not 65536, then PFIR will introduce a gain equal the decimate by two phasing in order to generate oversampled or wider bandwidth output data. This delay is independently programmable for each channel and is also independent for I and Q (QDLY_CFIR and IDLY_CFIR in address 25). A special mode (SPLITIQ in address 24) is also available where CFIR generates two I outputs rather than one I and one Q. See Section 3.4 for details. to: PFIR_GAIN = PFIR_SUM ---------------------------65536 , where PFIR_SUM is the sum of the 63 coefficients. The 63 coefficients are identified as coefficients h0 through h62, where h31 is the center tap. The coefficients are assumed to be symmetric, so only the first 32 coefficients (h0 3.3.6 The Second Decimate By 2 Filter through h31) are loaded into the chip. A non-symmetric mode (PFIR) (NO_SYM_PFIR in address 26) allows the user to download a 32 tap non-symmetric filter as taps h0 through h31. The The second stage decimate by two filter is a 63 tap decimate by 2 filter with programmable 16 bit coefficients. Fine gain is applied at the output of the PFIR and rounded to 24 bits. Overflows are detected and hard limited. Overflows can be directed to the channel overflow detection block. newest sample is multiplied by h0 and the oldest is multiplied by h31. NOTE: Filters normally multiply h0 by the oldest data, hence one may wish to reverse the tap order in the non-symmetric mode. PFIR coefficient sets for a variety of standards in cellular and cable modem applications are given in Section 7. The PFIR filter passband must be flat in the region of the signal of interest, and have the desired out of band rejection in the region that will alias into the signal’s bandwidth after decimation. Figure 11 below illustrates the passband and stopband requirements of the filter. FPFIR is the input sample The output samples can be multiplied by +/- 1 using a 4 bit control (NEG_CTL in register 24). If the LSB of NEG_CTL is a 1 the even time real words are multiplied by -1. The second LSB controls the even time imaginary words. The third controls the odd time real and the fourth the odd time imaginary. These can be used to invert the signal (NEG_CTL=0xF), frequency shift by Fs/2 (NEG_CTL=0x3), or flip the spectrum (NEG_CTL=0xA). It is also used in complex to real conversion (see the following section). rate to the PFIR filter. FPFIR/2 is the output sample rate of the channel before resampling. The externally downloaded coefficients can be used to tailor the spectral response to the user’s needs. For example, it can be programmed as a Nyquist (typically a root-raised-cosine) filter for matched filtering of digital data. The user downloaded filter coefficients are 16 bit 2’s complement numbers. Unity gain will be achieved through A fine gain is applied to the data after filtering and negation. The fine gain is a positive 14 bit integer (FINE) ranging from 0 to 16383. Fine gain is equal to: FINE . Setting FINE to zero will clear the FINE_GAIN = --------------- 1024 channel. The GAIN_SYNC control in address 22 can be used Signal of Interest Passband (Typically 0.125 to 0.2 of FPFIR) 0 dB Narrow transition band Power Stopband (Typically starts between 0.3 and 0.375 FPFIR) -100 dB 0 FPFIR/4 FPFIR/2 Frequency Figure 11. Typical PFIR Specifications  GRAYCHIP,INC. -9- August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 to determine when a new fine gain setting takes effect. It is normally set to take effect immediately, but can be used to synchronize the gain changes between multiple channels in a beam forming system. PFIR also contains a one PFIR sample input delay that is independently programmable for the I and Q paths and for the four channels (QDLY_PFIR and IDLY_PFIR in address 26). The delay is used when combining channels to allow wider output bandwidth and/or more oversampling. It is also used for complex to real conversion in PFIR. 3.3.7 Complex to Real Mode PFIR can be used to convert from the complex format to a real format for users desiring real output. This mode uses PFIR to low pass filter the signal so it resides from -FPFIR/4 to FPFIR /4, where FPFIR is the sample rate into the PFIR (in this mode PFIR does not decimate by two so it is also the output sample rate). The signal is then mixed up by FPFIR/4 (so it now resides from 0 to FPFIR/2) and the imaginary portion is discarded. In implementation, the samples to be discarded are never generated. This is implemented by delaying the I data by 1 input sample (set IDLY_PFIR in address 26 of the channel’s control page) and mixing the PFIR output with FPFIR /4 (set NEG_CTL=6 in address 24 of the channel’s control page). The QONLY flag in address 24 of the channel’s control page also needs set (The Q-half, rather than the I-half is used due to hardware details). When outputting real data the sample rate out of the PFIR filter is FCK/(2N). The REAL_ONLY bit in address 18 of the output control page can be set to tell the output section to output real samples. If this bit is not set, then the output will be in a complex format with the real samples in the Q-part of the complex word. The REAL_ONLY mode reduces the data rate out of the chip. Note that the REAL_ONLY bit effects all channels, so the chip does not support some channels outputting complex data while other channels output real data. 3.4 MULTICHANNEL MODES The GC4016 chip contains four independent channels and each channel can output complex sample rates up to Fck/321. Depending on the filter coefficients and the clock rate, the maximum single channel output bandwidth is just under 2MHz. This output bandwidth can be doubled by 1. The Resampler (Section 3.5) can be used to increase this rate for oversampling.  GRAYCHIP,INC. combining two channels using the SPLITIQ mode. Four channels may be combined to provide 3 to 4 times the single channel output bandwidth (with reduced out of band rejection). The two or four multichannel modes may also be used in the complex to real mode described in Section 3.4.6. Two channels can also be combined to process complex input data, thereby doubling the input bandwidth going into the chip. 2 Four channels can be combined to both process complex input data and to double the output bandwidth of the chip. Combined channels are assigned to a single resampler or output channel using the channel map controls (CHAN_MAP_A, B, C and D) in the resampler’s control page. Finally, for digital modulation formats, the resampler allows the downconverter’s output sample rate to be between 1.5 and 2 samples per baud (symbol). The resampler will then up-sample this to exactly 2 or 4 samples per baud. This allows the GC4016 chip to downconvert one 4X oversampled signal at symbol rates up to 8 MBaud, or two 4X oversampled signals at 3MBaud, or four 4X oversampled signals at 1.5MBaud (assuming a 100MHz clock rate). 3.4.1 Double Bandwidth Downconverter Mode (SplitI/Q Mode) Two channels work together in the SplitI/Q mode to double the output bandwidth of the downconverter. In the splitI/Q mode the real half of the complex output data is processed in one channel and the imaginary half in the other. In the splitIQ mode the CIC has a minimum decimation of 4 instead of 8, which allows channel output sample rates up to FCK/16. The two channels being combined in the splitI/Q mode should be programmed identically, including the tuning frequency, except that the imaginary channel should have a +90 degree phase shift (PHASE=0x4000). The IONLY bit in the real channel should be set and the QONLY bit in the imaginary channel should be set. This mode is used in the example UMTS configuration described in Section 7.12. Typically the chip is configured in the SPLITIQ mode so that channels A and B are combined as one downconverter and C and D are combined as the other. Mixed modes may be used, such as having A and B used as narrowband downconverters while C and D are combined into a double bandwidth downconverter. The resampler’s CHAN_MAP_A,B,C and D controls must be set so that the combined channels point to the same resampler channel. 2. The GC2011A digital filter chip can be used to convert sample rates up to 200MSPS into complex sample rates up to 100 MSPS. One GC2011A chip will convert 12 bit data, two chips will convert 24 bit data. - 10 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 Double rate real output can be generated by combining SPLITIQ and complex to real conversion. The complex to real signal processing is the same as described in Section 3.3.7. Here however, one channel contains the real portion of the signal and another contains the complex portion. To convert this complex data to real, the real channel must be delayed (set QDLY_PFIR=1), multiplied by a pattern 1,-1, 1, -1 (set NEG_CTL=5), and QONLY should be set. The imaginary channel should be multiplied by the sequence -1,1,-1,1 (set NEG_CTL=10) and QONLY should be set. The output is then available as the Q data in the selected resampler and output channel (see CHAN_MAP_A,B,C and D in the resampler’s control page, also see REAL_ONLY). 3.4.2 Wideband Downconvert Mode Even wider output bandwidth is possible by combining all four channels. This is done by noticing that PFIR decimates the signal by two. If one pair of channels in the SPLITIQ mode are used to generate even time sample outputs and the other pair are used to generate odd time sample outputs, then the PFIR filter effectively does not decimate the signal. This allows a wider bandwidth filter to be used in the CFIR and PFIR. Adjacent channel rejection, however, will be reduced due to the increase in the output bandwidth relative to the CIC’s stopbands. Also the increase in output bandwidth makes it harder for the CFIR and PFIR to achieve deep stop bands. Fortunately, signals that require wideband processing are also typically signals that do not require as much stop band rejection as narrowband signals such as GSM. The wide output mode uses the chip in the SPLITIQ mode described in Section 3.5.1. In addition the QDLY_PFIR bits are set in channels A and B. The delay of one input sample into the PFIR will offset the decimate by two operation so that the channel A and B outputs are the real and imaginary parts of the even time samples and the C and D outputs are the real and imaginary parts of the odd time samples. This mode is used in the example UMTS configuration described in Section 7.12. Performing real to complex conversion in this mode involves setting the controls as above, but also setting QDLY_CFIR on channels A and C; setting NEG_CTL to 15 for channels B and C; setting QONLY=1 (and IONLY=0) for all channels. one channel while the imaginary portion (QIN) is processed in the next channel. Channels A and B are described here, channels C and D can be combined as well. The desired and mixer output is IOUT=(IIN*cos-QIN*sin) QOUT=(IIN*sin+QIN*cos). Channel A is used in the normal mode and will output (IIN*cos) and (IIN*sin). A 90 degree offset (PHASE=0x4000) in channel B will cause channel B to output (-QIN*sin) and (QIN*cos). The desired result is achieved by adding the channel A outputs to the channel B outputs in the resampler. The resampler is told to add the channels together by setting the ADD_A_TO_B bit for channel A in the resampler’s control page. The complex to real mode described in Section 3.3.7 can be used in conjunction with the complex input mode. If both channels are configured as described in Section 3.3.7, then the combined complex input downconverter will be in the complex to real mode. 3.4.4 Complex Input, Double Bandwidth (SplitI/Q) Mode The complex input and SPLITIQ modes can be combined. Channels A and D will process the IIN inputs. Channels B and C will process the QIN input data. Channel A will output (IIN*cos). Channel B will output (-QIN*sin) if its phase is set to 90 degrees (PHASE=0x4000). Channel C will output (QIN*cos). Channel D will output (IIN*sin) if its phase is set to -90 degrees (PHASE=0xC000). The I OUT output is formed by adding channel A to channel B, and the QOUT output is formed by adding channel C to channel D. The IONLY bits must be set for channels A and B, and the QONLY bits must be set for channels C and D. The complex to real mode can be added to this mode by delaying the I word by half (set QDLY_PFIR in channels A and B) and mixing by Fs/4 (set NEG_CTL to 5 in channels A & B and set NEG_CTL to 10 in channels C & D). QONLY instead of IONLY needs to be set in channels A and B. 3.4.5 Multichannel Summary Table 2 summarizes the settings for the eight multichannel modes. A phase setting of 90 indicates a +90 degree phase offset, or a value of 0x4000. A phase setting of -90 indicates a -90 degree phase offset, or a value of 0xC000. 3.4.3 Complex Input, Narrowband output Complex input data can be processed using two channels. The real portion of the input (IIN) is processed in  GRAYCHIP,INC. - 11 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 Table 2: Multichannel mode settings Input Real Output Rate Two 2X output channels Single 4x output channel 1x Output Format Complex Complex Complex Channel A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D SPLITIQ PHASE QDLY_CFIR IDLY_PFIR QDLY_PFIR NEG_CTL IONLY QONLY ADD_TO CHAN_MAP 1 0 0 0 0 0 1 0 0 0 1 90 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 1 1 90 0 0 0 0 0 1 0 1 1 0 0 0 1 5 0 1 0 0 1 90 0 0 0 10 0 1 0 0 1 0 0 0 1 5 0 1 0 1 1 90 0 0 0 10 0 1 0 1 1 0 0 0 1 0 1 0 0 0 1 90 0 0 1 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 1 90 0 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 0 1 90 0 0 1 15 0 1 0 0 1 0 1 0 0 15 0 1 0 0 1 90 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 90 0 0 0 0 0 0 0 1 0 0 0 1 0 6 0 1 1 0 0 90 0 1 0 6 0 1 0 0 0 0 0 1 0 6 0 1 1 1 0 90 0 1 0 6 0 1 0 1 1 0 0 0 0 0 1 0 1 0 1 90 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 1 -90 0 0 0 0 0 1 0 0 1 0 0 0 1 5 0 1 1 0 1 90 0 0 1 5 0 1 0 0 1 0 0 0 0 10 0 1 1 0 1 -90 0 0 0 10 0 1 0 0 3.5 Complex Real Real RESAMPLER around 1.5 to 2 times the signal’s bandwidth1. The resampler is then used to increase the sample rate up to the required 2X, 4X or 8X rate. Section 7.7 shows example resampler configurations and their performance. The resampler can also be used as an additional filter to optimize the passband or stopband response of the channel. 1. The PFIR’s 63 tap filter’s stopband, transition band and passband ripple performance improves as its output rate decreases relative to the signal’s bandwidth. The resampler’s performance, however, begins to decrease when the PFIR output rate is below 1.5 times the signal’s bandwidth. Complex Real The resampler consists of an input buffer, an interpolation filter, and a final shift block. A functional block diagram of the resampler is shown in Figure 12. The resampler’s sampling rate change is the ratio NDELAY/NDEC where NDELAY and NDEC are the interpolation and decimation factors shown in Figure 12. The decimation amount NDEC is a mixed integer/fractional number. When NDEC is an integer, then the exact sampling instance is computed and there is no phase jitter. If NDEC is fractional, then the desired sampling instance will not be one of the possible NDELAY interpolated values. Instead the nearest interpolated sample is used. This introduces a timing error (jitter) of no more than 1/(2*NDELAY) times the input sample period. The input buffer accepts 24 bit data from the four input channels, and adds them as necessary to form 1,2, or 4 resampler channels (see the ADD_TO control bits in address 21 of the resampler control page). The input buffer serves both as a FIFO between the channels and the resampler, and as a data delay line for the interpolation filter. The 64 complex word input buffer can be configured as four segments of 16 complex words each to support 4 resampler Interpolation Filter INPUT BUFFER Real 3.5.1 Functional Description The resampler will independently filter and change the data rate of each channel. The most common application of the resampler is to increase the sample rate of the data so that it will match a desired symbol or bit rate. Demodulators for digital modulation schemes, such as GMSK, QPSK, QAM or CDMA, for example, require sample rates which are 1X, 2X, 4X or 8X times the bit or symbol rate of the modulation. In these cases, the maximum down converter filter performance is achieved when the PFIR output rate is IN 2x Fractional Decimation NDEC NDELAY QTAP Filter Coefs FINAL SHIFT AND ROUND OUT Resampling Filter Figure 12. Resampler Channel Block Diagram  GRAYCHIP,INC. - 12 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 the zero padded data in order to suppress the interpolation images. The last spectrum shows the final result after channels, or as two segments of 32 complex words each to support 2 resampler channels, or as a single segment of 64 complex words to support a single resampler channel. The number of segments is set by NCHAN in address 16 of the resampler control page. decimating by NDEC. 3.5.2 The Resampler Filter The interpolation filter zero pads the input data by a factor of NDELAY and then filters the zero padded data using a QTAP length filter. The output of the QTAP filter is then decimated by a factor of NDEC. Figure 13(b) illustrates the spectral shape requirements of the QTAP filter. If the desired signal bandwidth is B, then the filter’s passband must be flat out to B/2 and the filter’s stop band must start before FS-B/2. The user designs this The resampling ratio for each channel is determined by setting the 32 bit RATIO controls in addresses 16 through 31 of the resampler ratio page. The value of RATIO is defined as: RATIO = 2 filter assuming a sample rate equal to NDELAY*FS. Section 7.7 contains example resampler filters coefficient sets. Other passband and stopband responses can be used, such as root raised cosine receive filters, as desired. The resampler filter can also be used to augment the CIC, CFIR and PFIR filters’ spectral response. 26  NDEC  26 INPUT SAMPLE RATE ------------------------ = 2  --------------------------------------------------------------------  NDELAY  OUTPUT SAMPLE RATE The number of filter coefficients, QTAP, is equal to NMULT*NDELAY, where NMULT is the number of multiplies available to compute each resampler output, and NDELAY is either 4, 8, 16, 32 or 64 as will be described later. The maximum filter length is 512. The user specifies NMULT in address 17 of the resampler control page. Up to four ratios can be stored within the chip. A ratio map register (address 23) selects which ratio is used by each channel. The three spectral plots shown in Figure 13 illustrate the steps required to resample the channel data. The first spectral plot shows the data just after zero padding. The sample rate after zero padding is NDELAY*FS, where FS is The filter can be symmetric, or non-symmetric, as selected by the NO_SYM_RES control in address 17 of the resampler control page. The symmetric filter is of even length which means the center tap repeats. the sample rate into the resampler. The second spectrum shows the shape of the QTAP filter which must be applied to NDELAY Images added by zero padding Power ... ... Freq -3FS -2FS -FS -FS/2 FS/2 FS 2FS 3FS a) Spectrum after zero padding QTAP Filter Frequency Response Power Images reduced by Filtering ... ... -3FS -2FS -FS -FS/2 FS/2 FS 2FS Freq 3FS b) Spectrum after filtering In-band aliasing caused by decimation by NDEC Power -FO -FO /2 FO/2 Freq FO =(NDELAY/NDEC)FS c) Final Spectrum after decimating by NDEC Figure 13. The Resampler’s Spectral Response  GRAYCHIP,INC. - 13 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 The 12 bit filter coefficients are stored in a 256 word memory which can be divided into one, two, or four equal blocks. This allows the user to store one symmetric filter of up to 512 taps, two symmetric filters of up to 256 taps each, or four symmetric filters of up to 128 taps each. The number of filters is set by NFILTER in address 16 of the resampler control page. The filter used by each channel is selected using the FILTER_SEL controls in address 18 of the resampler control page. The filter lengths are cut in half if the filters are not symmetric. The coefficients are stored in memory with h0 stored in the lowest address, where h0 is the coefficient multiplied by the newest piece of data. The center tap of a symmetric filter is h (QTAP/2)-1. The coefficients for multiple filters (NFILTER>1), are interleaved in the 256 word memory. 3.5.3 Restrictions on NMULT The user does not directly set the value of NDELAY. The chip sets the value of NDELAY using NO_SYM_RES, NMULT and NFILTER according to: NDELAY ( 2 – NO_SYM_RES ) = Floor_2 [ 256 ---------------------------------------------] ( NMULT ) ( NFILTER ) where the function FLOOR_2[X] means the power of two value that is equal to or less than “X”. Since NMULT is restricted to be greater than or equal to 6 and less than or equal to 64, then NDELAY is either 4, 8, 16, 32 or 64. The length of the filter is then: The value of NMULT determines both the length of the filter and the number of delays in the resampling operation. In general one would choose the largest value of NMULT which gives an adequately large value of NDELAY. The choice of NMULT, however, must meet several restrictions. NMULT must be greater than a minimum, it cannot exceed the available number of multiplier cycles, and it must be less than the input delay line segment size. These restrictions are described below. The minimum value of NMULT is determined by the minimum number of clock cycles required to update the resampler’s state. This is a hardware restriction imposed by the chip’s architecture. This limitation is: if there are two or more outputs NMULT ≥ 7 if there is only one output NMULT is the number of complex multiplier operations required to compute an output sample. Since the resampler can perform two multiplies every clock cycle, the value of NMULT cannot exceed two times the number of clock cycles  GRAYCHIP,INC. ∑ Note that the resampler’s output sample rate is usually much less than the clock rate, so that NMULT is rarely limited by this restriction. NOTE: THE NUMBER OF CLOCK CYCLES AVAILABLE TO THE RESAMPLER IS REDUCED BY THE CLOCK DIVIDER DISCUSSED IN THE NEXT SECTION. The value of NMULT must also be less than the size of the delay line formed by the input buffer. The size of the delay line is either 16 for four resampler channels, 32 for two channels or 64 for a single channel as set by the NCHAN control in address 16 of the resampler control page. This limits NMULT to be less than or equal to 15, 31 or 63 dependent upon the number of resampler channels1. The typical resampler configuration will have four active channels, all using the same filter and the same resampling ratios. The typical configuration has NCHAN set to 4, NFILTER set to 1, NMULT set to 15 and NO_SYM_RES set to 0. This sets NDELAY to 32 and QTAPS to 480. See Section 7.7. 3.5.4 The Resampler Clock Divider QTAP = ( NDELAY ) ( NMULT ) NMULT ≥ 6 available to the resampler for each channel. The number of clock cycles available to the resampler is equal to the clock rate to the chip divided by the sum of the output sample rates for each resampler channel. Hence, NMULT must satisfy: F CK NMULT ≤ 2 × -----------------------------------------------------------( OUTPUT RATES ) The resampler has a clock divider that can be used to reduce power consumption and to slow the calculation rate of the resampler. The clock divider divides the internal clock by factors of one to 256 using the RES_CLK_DIV control in address 22 of the resampler control page. The clock divider reduces the resampler’s computational throughput, so care must be taken not to reduce the clock rate to the point that the computations can not be completed on time. 3.5.5 Final Shift and Round The gain of each resampler output is adjusted by an up-shift by 0-15 bits (FINAL_SHIFT). This up-shift is applied just before rounding to the 12, 16, 20 or 24 MSBs (ROUND). The values of FINAL_SHIFT and ROUND are set in control register 19 of the resampler control page. The resampler 1. NOTE: If the resampler is being used at much less than its maximum capacity, i.e., NMULT is much less than twice the number of clock cycles available (See also RES_CLK_DIV), AND the channels are synchronous, then NMULT may equal the size of the delay line. - 14 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 3.7 gain is: RES_SUM RES_GAIN = ( ----------------------------------------------)(2 32768 × NDELAY FINAL_SHIFT ) where RES_SUM is the sum of the QTAP coefficients. 3.5.6 By-Passing the Resampler The resampler is bypassed by using a configuration which has h0 set to 1024, all other taps set to zero, NMULT set to 7, NO_SYM_RES set to 1, FINAL_SHIFT set to 5, and RATIO set to 226 (0x04000000). Note that the NDELAY term in the RES_GAIN equation shown above does not apply in this case and should be set to unity in the gain equation. 3.5.7 Adaptive Ratio Change The ratio maps (address 23) can be used to dynamically adjust each channel’s resampling ratio. Four different ratios can be loaded into the chip. The ratio map indicates which ratio is to be used by which channel. This feature can be used to lock the resampling to a desired output timing by adaptively selecting ratios which are slightly larger or smaller or equal to the desired ratio. If the timing needs to be accelerated, then the larger ratio is selected, if the timing is correct, then the exact ratio is used and if the timing needs to be retarded, then a smaller ratio is used. The ratio change can be synchronized using the RATIO_SYNC control in address 21. 3.6 OVERALL GAIN The overall gain of the chip is a function of the amount of blanking (NZEROS), the decimation programmed into the chip (N), the scale circuit setting in the CIC filter (SHIFT, SCALE and BIG_SCALE), the coarse gain setting (COARSE), the sum of the CFIR coefficients (CFIR_SUM), the sum of the PFIR coefficients (PFIR_SUM), the fine gain (FINE_GAIN), the sum of the resampler coefficients (RES_SUM), the number of delays in the resampler filter (NDELAY) and the final shift (FINAL_SHIFT). The overall gain is shown below. The term in braces should be less than or equal to unity. Note that the NDELAY term is unity if the resampler is bypassed (see Section 3.5.6). Unity gain is defined relative to the MSB of the I/O data. Unity gain means that a maximum DC input with a tuning frequency of zero, will produce a maximum DC output, independent of the I/O words sizes. PEAK COUNTER Each channel has a peak counter which can monitor the input signal’s strength, or can count the number of overflows detected at three points within the channel. The peak counter can count overflows due to the COARSE_GAIN circuit, it can count overflows at the output from the CFIR, and it can count overflows at the output of the PFIR. If PEAK_MODE is set to 0 in address 28 of the channel control page, then the peak counter will monitor the signal strength at the input to the channel. The magnitude of each input sample is compared against a threshold selected by the PEAK_THRESH control in the same address. The threshold can be 1/4, 1/2 3/4 or full scale. The peak counter increments each time the magnitude equals or exceeds the threshold. The input threshold crossings can be used in an AGC loop to optimize the input signal level to the ADC. If PEAK_MODE is 1, then the peak counter monitors overflows at points selected by the PEAK_SELECT control in address 26 of the channel control page. The peak counter increments each time an overflow is detected. Note that the data value is saturated to plus or minus full scale, as appropriate, when the overflow occurs. The overflow count can be used to check if the signal gain is set too high anywhere along the processing chain. The counter counts up to 255 and stops. The counter value is saved in a holding register and the counter is cleared by the sync selected by the PEAK_SYNC signal (see register 28). The sync can either be one of the chip’s input syncs, a one-shot pulse, or the terminal count of the chip’s sync counter. A periodic sync allows the user to count threshold crossings or overflows during fixed time periods. The user reads the count through the PEAK_COUNT control register at address 29 of the channel control page. The holding register contents are transferred to the PEAK_COUNT register a clock cycle after the user reads the PEAK_COUNT register. This transfer is delayed to prevent the user from reading a peak count value at the same time the circuit is updating the register. Note that there are two other points in the chip where overflows can occur. The first is at the input to the resampler where samples from two channels can be added together as when processing complex input data. This may cause an overflow even though the samples feeding the resampler did not overflow. If an overflow occurs here, the sample is saturated and a control bit in the status register (address 1)  5 ( SHIFT + SCALE + 6 × BIG_SCALE – 62 )  COARSE CFIR_SUM PFIR_SUM FINE_GAIN FINAL_SHIFT 1 RES_SUM )N 2 ) ( ------------------) ( ------------------ ) ( -------------------) ( --------------------------------------------)(2 ) GAIN =  ( --------------------( 2 32768 × NDELAY NZEROS + 1 65536 65536 1024    GRAYCHIP,INC. - 15 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 is set. The user can clear this bit by writing a 0 to the register. The control bit indicates that at least one sample overflowed since the last time the bit was cleared. Since the datapath going into the resampler is 24 bits, it is recommended that the gain be set such that this overflow never occurs. The second overflow point is at the resampler output. The user can check for these overflows by examining the chip’s output data for maximum (saturated) values. 3.8 OUTPUT MODES Data from the resampler can be output in one of several modes: (1) The microprocessor mode where the outputs are read from the 8 bit control port, The chip supports different decimation ratios and/or different resampling ratios for each channel. If different ratios are used, or if the channels have not been synchronized using the DEC_SYNC controls (See Section 3.11), then the channels are asynchronous and tag bits are required in order to sort out the channel data. If the same ratios are used, and the channels have been synchronized, then the output is synchronous and the tag bits are not required. If the complex to real conversion modes of the PFIR described in Section 3.3.7 are used, then the REAL_ONLY control bit in address 18 can be used to output real rather than complex data. The REAL_ONLY control can only be used if all of the channels are in the complex to real mode, a mix of complex and real data is not allowed. If the complex output format is used to output real data (REAL_ONLY=0), then the real outputs are output as the Q-half of the complex output words. The I-half should be ignored. (2) The wide word microprocessor mode where the outputs are read as 32 bit integers from a wide word control port, (3) The synchronous serial mode where the outputs are output through one or more of the four serial ports, (4) The asynchronous serial mode where the channels are output on the same serial stream, but have their own serial frame sync, The suggested control register settings for each of the output modes are shown in Table 3. These settings assume all four channels are active and the outputs are synchronous. (5) The nibble mode where the outputs are output in a 4-bit at a time nibble serial format, (6) The link mode which is compatible with the four bit SHARC link port, or (7) The parallel mode which outputs the data as 24 bit words. Only one mode is supported at a time. The output modes are controlled by writing to addresses 16 through 26 within page 98 (the output control page). A FIFO memory holds blocks of resampler output data, where each block contains one, two or four complex samples as specified by the BLOCK_SIZE control in address 20. The FIFO is used to buffer the data rate between the resampler and the output. The number of blocks held in the FIFO depends upon the output mode being used. The data from the resampler can be rounded to 12,16, 20 or 24 bits. The BITS_PER_WORD control in address 20 will set the serial mode word size to be between 12 and 32 bits, or to set nibble and link mode words to be either 16 or 32 bits. If the output word size is larger than the resampler’s output size, then the unused LSBs are cleared. Tag bits (four bits per tag) may be programmed to replace the four LSBs of the specified output word size. The tags are used to identify the source of the data. The user can program eight different tag values in addresses 23, 24, 25  GRAYCHIP,INC. and 26, two for each of the four complex output words. Tags are enabled using the TAG_EN control bit in address 17. A special 2 bit tag mode control (TAG_22 in address 19 of the resampler control page) can be used to output 24 bit words containing 22 bits of data and 2 bits of tag. The output circuitry is reset upon power up. It is enabled by clearing the OUT_BLK_RESET and PAD_RESET bits in address 0. See Section 3.12 for the proper initialization procedures. An output block sync is provided (OUT_BLK_SYNC in address 17) which can be used to synchronize the serial clocks of multiple chips. See Section 3.12 for the proper synchronization sequences. 3.8.1 Microprocessor Mode In the microprocessor mode (OUTPUT_MODE=0 in address 18) the outputs are read in bytes from the control port. The outputs are accessed by reading addresses 16 through 31 in pages 96 and 97. The output FIFO buffers two blocks of complex samples in this mode. One block is accessed through the microprocessor port as another block is being filled with new data. When the new block is filled, the FIFO swaps the blocks so that the user can access the new data. The block size is usually set to buffer four complex samples per block (BLOCK_SIZE=3). If only one or two channels are being output, then the block size may be reduced, but it is suggested to keep it at four samples per block in order to - 16 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 Table 3: Output Mode Controls Suggested Default for Each Mode (hex values) Control Register Address (Page 98) Microprocessor mode Wide Word microprocessor mode Serial modes Four serial outputs Nibble mode Link mode Parallel mode FF (synchronous) Asynchronous Mode Tristate Controls 16 02 FA 7F 7F1 7F1 7F1 7D Output Formats 17 40 40 40 40 40 40 48 40 Output Modes 18 08 08 28 282 282 4A CB 6C TDM output Output Frame Controls 19 00 00 01 073 01 07 00 00 Output Word Sizes 20 E8 E8 E9 EF 29 C8 08 E85 Output Clocks 21 00 00 B1 01 01 01 01 01 Serial Mux Controls 22 00 00 E4 E4 E4 00 00 00 Output Tag A 23 10 00 10 Output Tag B 24 32 11 32 Output Tag C 25 45 22 45 Output Tag D 26 67 33 67 Miscellaneous 28 02 034 02 NOTES: 1. For TDM serial or nibble modes the master chip’s value should be 7F, the slaves’ 7D. 2. For TDM serial or nibble modes the master chip’s value should be 28, the slaves’ 20. 3. For multi-chip modes the frame length is set as described in Section 3.8.3. 4. Also set the RND22control bit in address 19 (bit 6) of the resampler control page (page 64). 5. For Asynchronous parallel modes set address 20 to 28. reduce the interrupt rate and to let the user read more samples after each interrupt. When the user has finished reading the block of data he sets the READY control bit in the Status Register (address1). When the output FIFO has a new block of data ready, it will clear the READY bit. If a block of data completes and the READY bit is not set, then the chip sets the MISSED control bit. The MISSED bit serves as a diagnostic indicating that the processor was too slow and missed a block of data. Note that the rate at which the blocks are filled, and therefore the rate at which the data needs to be read from the microprocessor port, is dependent upon how fast the resampler can generate new output samples. When the resampler is interpolating, which is the resampler’s most commonly used mode, it will generate multiple output samples each time it receives a sample from a downconverter channel. The user should use the resampler’s clock divider to slow its computation rate if the resampler is generating outputs too fast (See Section 3.5.4). The RDY pin can serve as an interrupt to inform the processor that a new block of samples is ready. The width and polarity of the RDY pulse is programmable (See EN_RDY in address16 and INV_RDY and RDY_WIDTH in address 17). The mapping of the output data into registers 16 through 31 is dependent upon the OUTPUT_ORDER control mode in address 21, the number of active channels, and whether the channels are synchronous or asynchronous. If OUTPUT_ORDER=0 and BLOCK_SIZE=3, then each block will contain the next four samples output from the  GRAYCHIP,INC. resampler. If the channels are synchronous, then the block will contain one sample from each channel. If there are only two active channels, then the block will contain two samples from each channel. If there is only one active output channel, then the block will contain four consecutive samples from the active channel. If the channels are asynchronous, or if there are three active channels, then the output block will contain the next four samples computed by the resampler. In this case tags are required to separate the channels. OUTPUT_ORDER=0 must be used for asynchronous data. If OUTPUT_ORDER=1 or 2, then the channels are written into the FIFO using the channel number as part of the address. In this mode the previous block is complete when the Q-half of the output from channel A arrives. If the resampler ratio is the same integral value for all channels, then channels B, C and D can be powered down and back up again while maintaining proper channel ordering. Channel A may not be powered down because it provides the “Block Complete” timing signal. OUTPUT_ORDER settings of 1 and 2 are valid for synchronous channels, but NOT for asynchronous channels. The following tables illustrate how the 24 bit channel outputs are mapped into addresses 16 through 31 of pages 96 and 97. Note that addresses 16, 20, 24 and 28 are the unused LSBs of the 32 bit words and always read back zero. Addresses 19, 23, 27 and 31 contain the MSBs of the output. In the 12,16, or 20 bit output mode, all values are rounded into the MSBs and the unused LSBs are cleared. These tables assume that BLOCK_SIZE = 3 which sets the block size to four complex words. - 17 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 Table 4: Channel Output Map, Synchronous Four Channel Mode CHANNEL OUTPUT PAGE 96 ADDRESSES OUTPUT_ORDER=0 OUTPUT_ORDER=1 OUTPUT_ORDER=2 16,17,18,19 AOUT, I-half AOUT, I-half AOUT, I-half 20,21,22,23 AOUT, Q-half BOUT, I-half BOUT, I-half 24,25,26,27 BOUT, I-half AOUT, Q-half COUT, I-half 28,29,30,31 BOUT, Q-half BOUT, Q-half DOUT, I-half CHANNEL OUTPUT PAGE 97 ADDRESSES OUTPUT_ORDER=0 OUTPUT_ORDER=1 OUTPUT_ORDER=2 16,17,18,19 COUT, I-half COUT, I-half AOUT, Q-half 20,21,22,23 COUT, Q-half DOUT, I-half BOUT, Q-half 24,25,26,27 DOUT, I-half COUT, Q-half COUT, Q-half 28,29,30,31 DOUT, Q-half DOUT, Q-half DOUT, Q-half Table 5: Channel Output Map, Synchronous Two Channel Mode CHANNEL OUTPUT PAGE 96 ADDRESSES OUTPUT_ORDER=0 OUTPUT_ORDER=1 OUTPUT_ORDER=2 16,17,18,19 A(i)OUT, I-half AOUT, I-half AOUT, I-half 20,21,22,23 A(i)OUT, Q-half BOUT, I-half BOUT, I-half 24,25,26,27 B(i)OUT, I-half AOUT, Q-half unused 28,29,30,31 B(i)OUT, Q-half BOUT, Q-half CHANNEL OUTPUT PAGE 97 ADDRESSES OUTPUT_ORDER=0 OUTPUT_ORDER=1 OUTPUT_ORDER=2 16,17,18,19 A(i+1)OUT, I-half unused AOUT, Q-half 20,21,22,23 A(i+1)OUT, Q-half BOUT, Q-half 24,25,26,27 B(i+1)OUT, I-half unused 28,29,30,31 B(i+1)OUT, Q-half Table 6: Channel Output Map, Single Channel Mode CHANNEL OUTPUT PAGE 96 ADDRESSES OUTPUT_ORDER=0 OUTPUT_ORDER=1 OUTPUT_ORDER=2 16,17,18,19 A(i)OUT, I-half AOUT, I-half AOUT, I-half 20,21,22,23 A(i)OUT, Q-half unused unused 24,25,26,27 A(i+1)OUT, I-half AOUT, Q-half 28,29,30,31 A(i+1)OUT, Q-half unused CHANNEL OUTPUT PAGE 97 ADDRESSES OUTPUT_ORDER=0 OUTPUT_ORDER=1 OUTPUT_ORDER=2 16,17,18,19 A(i+2)OUT, I-half unused AOUT, Q-half 20,21,22,23 A(i+2)OUT, Q-half 24,25,26,27 A(i+3)OUT, I-half 28,29,30,31 A(i+3)OUT, Q-half  GRAYCHIP,INC. unused - 18 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 In the complex to real conversion modes (see Section 3.3.7), the real output is available in the Q portion of the registers and the I portion is invalid. The REAL_ONLY control has no effect upon the microprocessor mode. Tables 4, 5 and 6 assume the block size control (BLOCK_SIZE in address 20) is set to four samples. If the block size is two and OUTPUT_ORDER is 0, then page 97 is unused. If the block size is one and OUTPUT_ORDER is 0, then only addresses 16 through 23 of page 96 are used. 3.8.2 Wide Word Microprocessor Mode The wide word microprocessor mode is selected by setting OUTPUT_MODE=0 and by enabling the parallel output port (EN_P0=EN_P1=EN_P2=EN_P3=EN_PAR=1 in address 16). The wide word microprocessor mode allows the user to read 32 bit words, rather than bytes. The 8 bit microprocessor port is augmented with the 24 bit parallel port to provide the 32 bit interface. The bit mapping into the 32 bit port is shown below. 32 BIT Wide Word PORT MSB LSB P23 P0 C7 PARALLEL PORT (contains the 24 bit output data) C0 CONTROL PORT (reads back zero) Figure 14. Wide Word Microprocessor Port The channel outputs are read using addresses 16, 20, 24, and 28 of pages 96 and 97. The channel ordering is the same as described in Section 3.8.1 above and shown in Tables 4, 5 and 6. The upper 24 bits of the wide word microprocessor port are read only bits. The port and has the same control and timing characteristics as shown in Figures 2 and 3 for the normal microprocessor port. 3.8.3 Synchronous Serial Outputs The serial mode is selected by setting OUTPUT_MODE=1, MASTER=1 and enabling the serial output pins (EN_SCK=EN_SFS=EN_P0,1,2,3=1 in address 16). The chip provides a bit serial clock (SCK), a frame strobe (SFS) and four data bit lines (SOUT A,B,C and D) to output the data in a serial format. The I and Q parts of complex outputs are always multiplexed onto the same bit-serial pin. The I-part is output first, MSB to LSB, followed by the Q-part. In the real mode (REAL_ONLY=1), only the Q word per channel is output. The REAL_ONLY mode is used with the complex to real conversion mode of the PFIR. The serial clock is the input clock (CK) divided by 1-16 (SCK_RATE control in address 21). For even divisions, the serial clock changes on the rising edge of CK. The serial clock has a 50% duty cycle for all divisions. The polarity of the serial clock is programmable (which allows output data to be sampled on the rising or falling edge of SCK). The serial output word size is programmable to be 12,16,20,24,28, or 32 bits per word (BITS_PER_WORD control in address 20). Note that the maximum word size out of the resampler is 24 bits so for output word sizes of 28 or 32 bits the lower bits are always zero. For complex data outputs, pairs of words, each being 12 to 32 bits, are output. Synchronous channel outputs can be transmitted as one channel per serial output on four separate bit-serial output pins (SOUTA, SOUTB, SOUTC, and SOUTD), or multiplexed as two channels per pin onto two output pins (SOUTA and SOUTB), or multiplexed as all four channels on the same pin (SOUTA) as specified by the OUTPUT_ORDER and NSERIAL control bits in address 21. The four channel, each on their own serial pin, mode uses NSERIAL=3 and OUTPUT_ORDER=2. The two channels per pin mode uses NSERIAL=1 and OUTPUT_ORDER=1. The four channels on a single pin mode uses NSERIAL=0 and OUTPUT_ORDER=0. The serial streams SOUTA, SOUTB, SOUTC and SOUTD are normally output on pins P0, P1, P2 and P3, respectfully. If required, the SMUX_0, SMUX_1, SMUX_2 and SMUX_3 controls in address 22 can be used to select which stream is output on which of these pins. For synchronous channels the FIFO block size (BLOCK_SIZE) should be set to match the number of active channels. If four channels are active, then BLOCK_SIZE should be set to 3. If two channels are active, then BLOCK_SIZE should be set to 1. If only one channel is active, then BLOCK_SIZE should be set to 0. The outputs are output in frames. Output frames start when the previous frame has completed AND a new data block is ready in the FIFO (See BLOCK_SIZE above). The minimum output frame length can be programmed to be 1 to 64 words (up to 32 complex samples) using the FRAME_LENGTH control in address 19. Longer frame sizes can be used to time division multiplex (TDM) channels from multiple chips onto a signal serial bus or to smooth data flow when resampling. The number of words output on each serial pin during a frame can be programmed to be 1 to 8 words (1 to 4 complex  GRAYCHIP,INC. - 19 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 samples) using the WORDS_PER_FRAME control in address 20. The WORDS_PER_FRAME control is usually set to match the number of active output channels multiplexed onto each serial pin using the NSERIAL control. In real output modes each sample is one word. In complex output modes each sample is two words. NOTE: FRAME_LENGTH must be greater than or equal to WORDS_PER_FRAME. If the selected number of words have been output, and the frame is not complete, or a new FIFO block is not ready, then the frame strobe (SFS) will remain inactive, the data bits will go tristate, and the serial clock (SCK) will continue. In this case a new frame will start on the next SCK pulse after the frame completes and a new FIFO block is ready. If new outputs are ready before the previous frame is finished, then the FIFO will buffer the new data until the previous frame is complete. THE FRAME LENGTH AND SERIAL CLOCK RATES MUST BE SET SO THAT THE FRAME RATE IS GREATER THAN OR EQUAL TO THE AVERAGE RESAMPLER OUTPUT RATE. This means that: (Average # of clocks per resampler output) ≥ (Frame length)(bits per word)(clocks per bit) where the average # of clocks per resampler output is equal to: (Average # of clocks per resampler output) = (Channel deciation)(NDEC/NDELAY) and NDEC/NDELAY is the resampling ratio (see Section 3.5.1). The frame strobe signal (SFS) is programmable to come once per frame, once per complex word, or once per word using the SFS_MODE control in address 19. SFS is one SCK clock cycle wide and always comes one SCK ahead of the first output bit in the transfer. Its polarity is programmable (INV_SFS in address 17). If the outputs are synchronous and the frame strobe signal is once per frame, then a word’s position in the frame relative to the SFS strobe can be used to identify which channel each sample belongs to. If not, tags may be used to identify channels. Some processors require an SFS strobe with each word so the position within a frame relative to the SFS strobe cannot be used to identify channels. Tag bits must be used for these processors, but may be turned off once synchronization has been achieved. Note that frames can be generated back to back, specifically, the frame strobe can occur at the same time as the last bit in the previous frame. The serial frame timing is illustrated below in Figure 15. Synchronous data from multiple chips may be time division multiplexed (TDM) onto the same serial bus. A master GC4016 chip (MASTER=1 in address 18 and  GRAYCHIP,INC. EN_RDY=1 in address 16) provides the frame strobe signal and serial clock and a RDY start of frame pulse. The bidirectional RDY pin is an output pin from the master chip and is an input pin for the slave chips (MASTER=0, EN_RDY=0). The slave chips use the RDY input frame strobe to identify the start of frame. The master will drive the serial outputs for the first 1-8 words (WORDS_PER_FRAME) of the frame, and then will tristate its serial data out. The slave chips are programmed using the FRAME_LENGTH control to delay the start of their outputs by 1-63 words from the beginning of frame. Note that the delay is programmed in words, NOT complex samples. The delay can be programmed independently for each slave chip so that each chip can have its own block of time in which to output data. For example, a four chip TDM stream can be generated, where each chip is outputting eight words (four complex outputs), by setting WORDS_PER_FRAME=7 (8 words per chip) in all four chips, FRAME_LENGTH=31 in the master chip (32 words per frame), FRAME_LENGTH=7 in the second chip (start at word 8), FRAME_LENGTH=15 in the third chip (start at word 16) and FRAME_LENGTH=23 in the fourth chip (start at word 24). The TDM mode requires that the serial clocks in the master and slave chips have been synchronized using the OUT_BLK_SYNC control. See Section 3.12 for details. The TDM mode is intended for use with a single serial output stream (NSERIAL=0), but will also work with one, two or four streams. The TDM outputs are then identified within each stream according to the NSERIAL and OUTPUT_ORDER controls as shown in Figure 15(c). 3.8.4 Asynchronous Serial Outputs Asynchronous channels must be output on a single serial stream. Tag bits or separate frame strobes must be used to identify the channels. In the asynchronous mode each channel sample is output as a serial word (or complex pair) as soon as the resampler has finished generating it. Tag bits or separate frame strobes are used to match the serial output word with the channel it came from. Asynchronous channels must use NSERIAL=0, OUTPUT_ORDER=0, and BLOCK_SIZE=0. WORDS_PER_FRAME and FRAME_LENGTH must be set to 0 for real data and 1 for complex data. Four bit tags are enabled by setting TAG_EN=1 and TAG_22=0. The two bit tag mode (TAGEN=0, TAG22=1) can be used to output 24 bit words that are 22 bits of data plus 2 bits of tag. Separate frame strobes are enabled by using the two bit tag mode and setting the EN_4_FS control bit (address 28 of - 20 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 clock is continuous SCK The data pins go tristate after the last bit SFS SOUT I15 I14 I1 I0 Q15 Q14 Q1 Q0 (a) SFS_MODE=3: FRAME SYNC AT THE START OF EACH WORD (16 bit words shown) SCK SFS I15 SOUT I14 I1 I0 Q15 Q1 Q14 Q0 (b) SFS_MODE=2: ONE FRAME SYNC AT THE START OF EACH COMPLEX WORD The minimum output frame length is set by FRAME_LENGTH SFS SOUTA SOUTB SOUTC SOUTD IA QA IA IB QB IB QA QB IC QC IC QC ID QD ID QD Four Output streams: NSERIAL=3, WORDS_PER_FRAME=1, OUTPUT_ORDER=2 SFS SOUTA SOUTB SFS SOUTA IA QA QA IB QB IC QC ID QD IC QC Two Output Streams: NSERIAL=1, WORDS_PER_FRAME=3, OUTPUT_ORDER=1 IB QB IA ID QD IA QA IB QB IC QC ID QD QA IA Single Output Stream: NSERIAL=0, WORDS_PER_FRAME=7, OUTPUT_ORDER=0 IB QB IC QC (c) ONE, TWO OR FOUR CHANNEL MUX MODES (the timing shown is for SFS_MODE=2,and BLOCK_SIZE=3) Figure 15. Serial Output Formats the output page). When the EN_4_FS bit is set, the two bit tag is used to generate the four frame strobes FSA (tag=0), FSB (tag=1), FSC (tag=2) and FSD (tag=3). The timing for these frame strobes are the same as shown for SFS in Figure 15. The separate frame strobe mode (TAG_22=1 and EN_4_FS=1) is valid for all serial word sizes, but the 2 bit tag will only be output for 24, 28 or 32 bit serial word sizes. The four frame strobes share output pins P4, P5, P6 and P7. 3.8.5 Nibble Mode Output The four serial output pins (P0, P1, P2 and P3), the serial clock pin (SCK) and the frame sync pin (SFS) can be configured as a nibble wide output by setting OUTPUT_MODE=2, MASTER=1 and NIBBLE=1 in address 18. These pins are in a tristate condition when the chip powers up and need to be enabled by setting EN_SCK, EN_SFS, EN_P0, EN_P1, EN_P2 and EN_P3 in address 16. The nibble mode functions the same as the serial mode except 4 bits are output at a time, the word size is restricted  GRAYCHIP,INC. to being 16 or 32 bits, all channels are output on the same nibble port, and the SFS signal is coincident with the first nibble of a transfer, rather than being one SCK clock early. The nibble mode requires that OUTPUT_ORDER=0 and NSERIAL=0. For synchronous channels, BLOCK_SIZE should be set to the number of active channels, WORDS_PER_FRAME should be set to match the number of active words (two per active channel for complex data) and FRAME_LENGTH should be set to define the minimum number of words per frame. Asynchronous channels must use BLOCK_SIZE=0 and TAG_EN=1. WORDS_PER_FRAME must be set to 0 for real data and 1 for complex data. The nibble mode can support TDM of multiple chips, in which case the RDY pin is used to synchronize master and slave chips in the same way it was used in the serial TDM mode. To use the TDM mode set MASTER=1 and - 21 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 EN_RDY=1 in the master chip, and set MASTER=0 and EN_RDY=0 in the slave chips. The SFS strobe behaves the same in the nibble mode as in the serial mode except that the SFS strobe is coincident with the first nibble in the word and that the SFS strobe can not come every word in the real 16 bits per word mode (REAL_ONLY=1, BITS_PER_WORD=0). The latter exception means that for 16 bit real data, SFS_MODE must be equal to 0 (one SFS strobe at the beginning of the frame) AND the frame length cannot be one word (FRAME_LENGTH can not equal 0). This restriction does not apply to complex outputs or to 32 bit nibble output modes The separate frame strobe mode described for asynchronous serial data can also be used in the nibble mode. 3.8.6 LINK Mode Output The four serial output pins (P0, P1, P2 and P3) and the serial clock (SCK) and RDY pins can be configured as a nibble wide link port by setting OUTPUT_MODE=2, NIBBLE=1 and LINK=1 in address 18. The link port can feed an ADSP-2106x SHARC DSP chip’s link port. The P0, P1, P2, P3 and SCK pins are in a tristate condition when the chip powers up and need to be enabled by setting EN_SCK, EN_P0, EN_P1, EN_P2 and EN_P3 in address 16. EN_RDY must be low. In the LINK mode the RDY output pin becomes the ACK (acknowledge) input pin which is tied to the link port “LACK” signal. LACK is used to stall the output until the processor is ready for it. The outputs are transmitted in four bit nibbles on the rising edge of SCK (INV_SCK in address 17 must be low). If the ACK signal is low at the end of a 32 bit transfer, then the clock will remain high and the transmission of the next word will be delayed until ACK goes high again. The link port transfers data as 32 bit packets. The user can choose to transmit two 16 bit words per packet, or a single 32 bit word. To transmit two 16 bit words per packet the user must set BITS_PER_WORD to 0 and WORDS_PER_FRAME to 1. To transmit a single 32 bit word per packet the user must set BITS_PER_WORD to 1 and WORDS_PER_FRAME to 0. The link mode requires OUTPUT_ORDER, NSERIAL and BLOCK_SIZE to be set to 0. FRAME_LENGTH and SFS_MODE are unused and should also be set to 0. The link mode clock rate is set by SCK_RATE. If the outputs are synchronous, and the chip has been initialized properly (see Section 3.12), then the first transfer will be the I part of channel A followed by the Q part, followed  GRAYCHIP,INC. by the I/Q pairs from channels B, C and D. If the channels are asynchronous, or initialization is not possible, then tag bits must be used to identify the channel data. The tag bits for synchronous data may be disabled once synchronization is achieved. The link mode normally puts the least significant bit in P0. Note that this is opposite of the GC4014. For pin compatibility with the GC4014 the control SMUX_0 in address 22 should be set to 1. This will put the least significant bit in P3. When transferring two 16 bit words in a 32 bit link packet the first word will end up in the upper 16 bits of the packet and the second word in the lower 16 bits. This means that the memory order in the DSP chip may end up being (QA, IA, QB, IB, ...) for complex data and (I1, I0, I3, I2, ...) for single channel real data. The REVERSE_IQ control bit in address 18 will eliminate this problem by swapping the I/Q pair (or the I0/I1 pair) in the 32 bit packet. 3.8.7 Parallel Mode Output The SCK, SFS, RDY and P0 through P23 pins are used in the parallel mode to output 24 bit wide data samples. The mode is enabled by setting the EN_SCK, EN_SFS, EN_RDY, EN_P0, EN_P1, EN_P2, EN_P3 and EN_PAR bits in address 16, and by setting OUTPUT_MODE=3, MASTER=1, and PARALLEL=1 in address 18. The parallel mode also requires NSERIAL=0 and OUTPUT_ORDER=0 in address 21. FRAME_LENGTH is unused and should be set to 0 in address 20. The 24 bit samples are clocked out on the rising edge of SCK (or the falling edge if INV_SCK is set). The SCK clock is continuous and the SFS and RDY outputs are used to identify when a valid sample has been clocked out. The data valid flags will go high during the SCK clock period when the 24 bit sample is valid. The SFS and RDY flags behave in two modes as controlled by the SFS_MODE control bits in address 19. If SFS_MODE is 0 or 1, then the SFS is IVALID and RDY is QVALID. If the outputs are synchronous, and the chip has been initialized properly (see Section 3.12), then the first valid sample after initialization will be the I part of channel A. The next valid sample will be the Q part, followed by the I/Q pairs from channels B, C and D. If the channels are asynchronous, or initialization is not possible, then tag bits must be used to identify the channel data. The tag bits for synchronous data may be disabled once synchronization is achieved. - 22 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 SCK SFS (I Valid) RDY (Q Valid) P[0:23] AI0 AQ0 BI0 BQ0 CI0 CQ0 DI0 DQ0 AI1 AQ1 BI1 AI1 AQ1 BI1 (a) Synchronous Channels, SFS_MODE=0, BLOCK_SIZE=3 SCK SFS (I or Q Valid) RDY (Frame Start) P[0:23] AI0 AQ0 BI0 BQ0 CI0 CQ0 DI0 DQ0 (b) Synchronous Channels, SFS_MODE=2, BLOCK_SIZE=3 SCK SFS (I Valid) RDY (Q Valid) P[0:23] AI0 AQ0 BI0 BQ0 CI0 CQ0 (c) Asynchronous Channels, SFS_MODE=0, BLOCK_SIZE=0 SCK SFS (I or Q Valid) RDY (Frame Start) P[0:23] AI0 AQ0 BI0 BQ0 CI0 CQ0 (d) Asynchronous Channels, SFS_MODE=2, BLOCK_SIZE=0 Figure 16. Parallel Mode Timing If SFS_MODE is 2 or 3, then SFS is a data valid flag (I or Q) and the RDY output is a start of frame flag which identifies the I part of channel A. If the outputs are synchronous, then the channel data can be identified by its position in the frame relative to the RDY flag. If the outputs are asynchronous, then tags must be used to identify the channel data. The parallel output timing is illustrated in Figure 16. Note that when SFS_MODE is 2 or 3, then the RDY flag goes high at the end of the frame and goes low after the first word of the next frame. This is illustrated in Figures 16 b and d. The polarities of the SFS and RDY flags are controlled by the INV_SFS and INV_RDY bits in address 17. 3.9 CLOCKING The clock rate is equal to the input data rate which can be up to 80 MHz. An internal clock doubler doubles the clock rate so that the internal circuitry is clocked at twice the data rate. The clock doubler requires a  GRAYCHIP,INC. continuous clock (no deleted clock pulses) for proper operation. The DVAL input is used as an active low data valid signal which is clocked into the chip on the rising edge of CK. The data in the next CK cycle is ignored when DVAL is high. The DVAL signal operates by gating the output of the clock doubler. It does not affect the clock to the output circuitry, so the output will continue while DVAL is high. The DVAL signal allows users to input data in bursts, such as data which is being read from a memory or FIFO. The DVAL signal should never be high for more than a 1msec. Normally DVAL will be grounded. The clock doubler can be bypassed and an externally generated 2X clock can be used in its place by setting the CK_2X_EN control bit in address 0. In this mode the DVAL pin becomes the external CK_2X input. This mode is intended for test purposes only. The CK_2X_TEST control bit in address 0 enables the clock test mode where the internal doubled clock is output on the SO pin. The DVAL pin must be low in this test mode. - 23 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP 3.10 DATA SHEET REV 1.0 POWER DOWN MODES The 3 bit sync mode control for each sync circuit is defined in Table 7: The chip has a power down and clock loss detect circuit. This circuit detects if the clock is absent long enough to cause dynamic storage nodes to lose state. If clock loss is detected, an internal reset state is entered to force the dynamic nodes to become static. The control registers are not reset and will retain their values, but any data values within the chip will be lost. When the clock returns to normal the chip will automatically return to normal. In the reset state the chip consumes only a small amount of standby power. The user can select whether this circuit is in the automatic clock-loss detect mode, is always on (power down mode), or is disabled (the clock reset never kicks in) using the CK_LOSS_DETECT and GLOBAL_RESET control bits in address 0. The whole chip, or individual down converter channels can be powered down. NOTE: Resampler channel 0 provides the “block complete” signal to the output FIFO when OUTPUT_ORDER=1 or 2. This means that the channel feeding resampler channel 0, typically channel A (see CHAN_MAP in the resampler control page), can not be powered down when OUTPUT_ORDER=1 or 2. 3.11 SYNCHRONIZATION Each GC4016 chip can be synchronized through the use of one of two sync input signals, an internal one shot sync generator, or a sync counter. The sync to each circuit can also be set to be always on or always off. Each circuit within the chip, such as the sine/cosine generators or the decimation control counter can be synchronized to one of these sources. These syncs can also be output from the chip so that multiple chips can be synchronized to the syncs coming from a designated “master” GC4016 chip. Table 7: Sync Modes MODE SYNC SOURCE 0,1 off (never asserted) 2 SIA 3 SIB 4 ONE_SHOT 5 TC (terminal count of internal counter) 6,7 on (always active) NOTE: the internal syncs are active high. The SIA and SIB inputs have been inverted to be the active high syncs SIA and SIB in Table 7. The ONE_SHOT can either be a level or a pulse as selected by the OS_MODE control bit. The level mode is used to initialize the chip, the pulse mode is used to synchronously switch frequency, phase or gain values. Typically the decimation counters (DEC_SYNC), the flush circuits (FLUSH_SYNC) and the output block sync (OUT_BLK_SYNC) will be set to SIA, while the NCO phase accumulator syncs (NCO_SYNC) will be set to SIB. The SIA input can then be used to initialize and flush the channels and the SIB sync input can be used, if desired, to synchronize the phases of the NCOs. The recommended sync mode settings are summarized in Table 8. The SIA and SIB sync inputs are either connected to a user defined sync generator, for example, an FPGA, or are tied to a GC4016 chip’s sync output pin (SO). If there are multiple GC4016 chips in the system, then the SO pin of one chip can be used to drive the SIA input of all chips, and the SO pin of another chip can drive the SIB inputs of all chips. Table 8: Recommended Sync Settings Global Syncs (Addresses 4 and 5) Channel Syncs (Pages 7, 15, 23 and 31) Sync Value Description Sync Value Description DIAG_SYNC 7 (always) Only used during diagnostics PHASE_SYNC 7 (always) Use phase settings as they are loaded OUTPUT_SYNC 4 (OS) The SO output is used during initialization FREQ_SYNC 7 (always) Use frequency settings as they are loaded COUNTER_SYNC 4 (OS) Sync counter with one shot pulse NCO_SYNC 2 (SIA) Sync the phase accumulator during initialization. Set to SIB for frequency hopping. DITHER_SYNC 0 (never) or 2 (SIA) Can free run except during diagnostics, or reset during initialization ZPAD_SYNC 2 (SIA) Sync the zero pad circuit during initialization DEC_SYNC 2 (SIA) Sync the channel decimation during initialization Output Circuit Sync (Page 98) OUT_BLK_SYNC 2 (SIA) Sync the output block during initialization Resampler syncs (Page 64) RES_SYNC 2 (SIA) Sync the Resampler during initialization FLUSH_SYNC 2 (SIA) Flush the channels during initialization RATIO_SYNC 7(always) Set to always except when synchronously changing ratios GAIN_SYNC 7 (always) Use fine gain settings as they are loaded PEAK_SYNC 5 (TC) Periodically capture peak count data  GRAYCHIP,INC. - 24 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 This arrangement allows the user to use the SO sync output to synchronously drive the SIA or SIB sync inputs of all chips. The sync source for SO is selected using the OUTPUT_SYNC control bits in address 4. (1) Reset the chip by setting address 0, the global reset register, to 0xF8; (2) Configure the rest of the chip including setting the DEC_SYNC, RES_SYNC and OUT_BLK_SYNC to be ONE_SHOT (mode 4) and the OS_MODE to be 1; The resampler time delay accumulator is synchronized by the RES_SYNC control. Typically the resampler is only synchronized during initialization. (3) Assert the syncs by setting ONE_SHOT high; (4) Release the global resets by setting address 0 to 0x08; and (5) Release the syncs by setting ONE_SHOT to 0. 3.12 INITIALIZATION 3.13 Two initialization procedures are recommended. The first is recommended for multi-GC4016 chip configuration. The second can be used for stand alone GC4016 chips. 3.12.1 Initializing Multiple GC4016 Chips The multi-GC4016 initialization procedure assumes that the SIA sync input pins of all GC4016 chips are tied together and are connected to the SO output of the “master” chip, or to a common sync source. The procedure is to: (1) Reset the chip by setting address 0, the global reset register, to 0xF8; (2) Configure the rest of the chip including setting the DEC_SYNC, RES_SYNC and OUT_BLK_SYNC to be SIA, the OS_MODE to be 1, and the OUTPUT_SYNC to be OS (see Table 7); (3) Assert the SIA sync input by setting ONE_SHOT high (or by setting the external SIA source low); (4) Release the global resets by setting address 0 to 0x08; and (5) Release the SIA sync by setting ONE_SHOT to 0 (or the external SIA source high). The global resets are asserted before configuring the chip so that the operation of all of the pins, including the directions of the bidirectional and tristate pins, will be established before the global resets release them. The SIA sync is asserted before releasing the global resets so that the channels will remain in a reset state after the global resets are released. All channels, the resampler and the output block will then start synchronously by releasing the SIA sync. If there are multiple chips which need synchronized, then synchronously releasing the SIA sync to them all will force them all to be synchronized. 3.12.2 Initializing Stand Alone GC4016 chips The initialization sequence for a stand alone GC4016 chip is similar to the one for the multi-GC4016 procedure, except that the ONE_SHOT is used to synchronize the chip, not the SIA input sync. The procedure is to:  GRAYCHIP,INC. DATA LATENCY The data latency through the chip is defined as the delay from the rising edge of a step function input to the chip to the rising edge of the step function as it leaves the chip. This delay is dominated by the number of taps in each of the filters. An estimate of the overall latency through the chip, expressed as the number of input clock cycles is: (CIC latency = 2.5N) + (CFIR latency = 0.5N*CTAP) + (PFIR latency = N*PTAP) + (Resampler latency = 2N*NMULT) + (Output delay) + (Pipeline delay) where N is the CIC decimation ratio, CTAP is the number of CFIR taps, and PTAP is the number of PFIR taps. CTAP and PTAP are normally 21 and 63. Latency can be reduced by using the NO_SYM_CFIR and NO_SYM_PFIR modes to shorten these filters. The latency in the resampler can be minimized by using the bypass configuration (See Section 3.5.6). The Output delay depends upon the output mode, but is approximately equal to the fifo block size (BLOCK_SIZE+1) times the output’s sample period. The Pipeline delay is approximately 40 clock cycles. 3.14 DIAGNOSTICS The chip has an internal ramp generator which can be used in place of the data inputs for diagnostics. An internal checksum circuit generates a checksum of the output data to verify the chip’s operation. Section 7.13 gives suggested checksum configurations and their expected checksums. Besides the internal diagnostics, the chip can support board level testing. An output test configuration which can help initial debug as well as production test is described in Section 7.14. 3.15 JTAG The GC4016 supports a four pin (TDI, TDO, TCK and TMS) boundary scan interface. Contact GRAYCHIP to receive the GC4016’s BSDL file. - 25 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP 3.16 DATA SHEET REV 1.0 MASK REVISION REGISTER An 8 bit mask revision code (REVISION) can be read from address 27 of the output control page (page 98). The revision code allows users to determine, through software, what version of the GC4016 chips are being used. The current mask revision codes are: Table 9: Mask Revisions GC4016 Revision Code (REVISION) Release Date Mask Code on Package Description 0 April 2000 SAMPLE Early samples 1 Sept. 2000 1001ACBA First Release, Has 40 ohm Vcore to Vpad short, no JTAG 2 March 2001 1001ACBB Production Release, JTAG added, short removed.  GRAYCHIP,INC. - 26 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 4.0 PACKAGING 4.1 GC4016-PB 160 Ball Plastic Ball Grid Array (PBGA) The GC4016 chip is packaged in a 160 lead plastic ball grid array package. 0.36 mm A2 1.56 mm D1 13 mm A1 A DIMENSION D (width body) D1 (width cover) P (ball pitch) B (ball width) L (overhang) A (overall height) A1 (ball height) A2 (substrate thickness) 0.4 mm GRAYCHIP GC4016-PB QUAD DDC MMMMMM LLL YYWW D 15 mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B C D E F G H J K L M N P 160 BALL PLASTIC BALL GRID ARRAY TYP 15 mm 13 mm 1.0 mm 0.5 mm 1.0 mm 1.56 mm 0.4 mm 0.36 mm TOLERANCE +-0,05 mm +0.7 -0.05 mm +-0.05 mm +-0.1 mm +-0.05 mm +0.19 -0.21 mm +-0.1 mm +-0.05 mm MARKING: MMMMMM = Mask Code LLL = Lot Code YYWW = Date Code TOP VIEW L 1.0 mm P N M L K J H G F E D C B A P VCORE: C14, D2, L5, L13, M8, P3, P10 VPAD: B14, C3, D6, D8, D10, G12, M3, P5, P12 GND: A3, A12, L7, L9, M1, M5, N11 A8, A13, C1, D11, E4, G11, M14, N3, P4 GND (THERMAL): G7, G8, H7, H8 UNUSED: A2, B1, B2, B3, B13, C2, M2, M12, M13, N1, N2, N12, N13, N14, P2, P13 JTAG: B12 (TCK), C10 (TMS), C12 (TDO), C13 (TDI) 1.0 mm B 0.5 mm NOTE: 0.01 to 0.1 µf DECOUPLING CAPACITORS SHOULD BE PLACED AS CLOSE AS POSSIBLE TO THE MIDDLE OF EACH SIDE OF THE CHIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 BOTTOM VIEW Figure 17. GC4016 160 Pin Plastic Ball Grid Array  GRAYCHIP,INC. - 27 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 Schematic symbols and pin assignments for the GC4016 in each of its input configurations are shown below. N5 N6 P6 L6 N7 L8 P9 M9 M10 PORT B L10 (MSB) P23 CIN13 (MSB) P22 CIN12 CIN11 P21 P20 CIN10 P19 CIN9 P18 H4 P11 P10 CIN1 CIN0 P9 BIN13 (MSB) BIN12 P8 (FSD) P7 (FSC) P6 BIN11 BIN10 (FSB) P5 (FSA) P4 (SOUTD) P3 (SOUTC) P2 (SOUTB) P1 (SOUTA) P0 (MSB) C7 C6 C5 C4 C3 C2 PORT A J12 AIN13 (MSB) H13 AIN12 H14 AIN11 H11 AIN10 H12 AIN9 G14 AIN8 G13 AIN7 F14 AIN6 F12 AIN5 F13 C1 C0 (MSB) A4 A3 AIN4 AIN3 A2 A1 A0 M6 K4 J4 H3 F4 D4 D5 D7 C7 J12 H14 B11 H12 WR H13 H11 G14 B7 A7 C8 G13 F14 F12 F13 B8 E14 C9 E12 A9 B9 E13 D14 J3 B5 C5 J2 A5 E1 B6 E3 C6 F2 F1 C4 B4 CE F3 G2 G1 G4 D3 SIA SO D1 E2 P8 (MSB) P23 DIN4 P22 BIN13 (MSB) BIN12 P21 P20 P19 P18 P12 P11 P10 P9 P8 (FSD) P7 (FSC) P6 (FSB) P5 AIN13 (MSB) AIN12 (FSA) P4 (SOUTD) P3 AIN11 (SOUTC) P2 AIN10 (SOUTB) P1 AIN9 (SOUTA) P0 E11 F11 K11 L11 N10 K2 F3 N9 N8 M7 L3 G1 M6 AIN5 (MSB) C7 C6 C5 AIN4 C4 AIN3 AIN2 C3 C2 AIN1 C1 AIN0 C0 AIN6 DIN1 (MSB) A4 A3 DIN0 A2 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 A1 A0 L4 H2 H4 N6 J3 H3 F4 L6 D4 D5 D7 C7 D9 B10 A11 C11 B11 SIA A6 B7 A7 C8 B8 C9 A9 B9 RD L8 J12 H14 L10 B5 C5 H12 A5 B6 C6 M11 G13 L14 F12 K14 C4 E14 B4 CE J13 E13 SO P8 DVAL 14 Bit Input Configuration A10 DIN2 DIN0 CIN0 (MSB) P23 DIN13 (MSB) P22 CIN13 DIN11 P21 P20 CIN11 P19 DIN9 CIN9 P18 L11 N10 H4 P11 P10 P9 BIN11 C3 C2 C1 C0 AIN11 AIN9 (MSB) A4 A3 BIN7 A2 AIN7 A1 BIN5 A0 BIN9 AIN5 BIN3 AIN3 BIN1 M6 K4 J4 H3 F4 D4 D5 D7 C7 A11 C11 H14 B11 H12 RD H11 G13 F14 F12 F13 E14 B8 C9 E12 A9 B9 E13 D14 J3 B5 C5 J2 A5 B6 E1 E3 C6 F2 A4 WR H13 G14 A7 C8 C4 B4 CE F1 F3 G2 G1 G4 AIN1 SO E2 D1 P7 P8 DVAL 16 Bit Input Configuration RDY D12 D13 A10 CIN5 CIN4 CIN3 CIN2 CIN1 (EXP2) CIN0 (EXP1) (MSB) P23 DIN5 (EXP0) DIN4 (A/B) P22 P21 P20 P19 P18 P12 P11 P10 P9 P8 (FSD) P7 (FSC) P6 (FSB) P5 AIN13 (MSB) AIN12 (FSA) P4 (SOUTD) P3 AIN11 (SOUTC) P2 AIN10 (SOUTB) P1 AIN9 (SOUTA) P0 E11 F11 J11 K11 L11 N10 N9 N8 M7 M6 K4 J4 H4 H3 F4 D4 D5 D7 C7 D9 B10 A11 C11 B11 AIN8 AIN7 AIN5 (MSB) C7 C6 C5 AIN4 C4 AIN3 AIN2 C3 C2 AIN1 (EXP2) C1 AIN0 (EXP1) C0 AIN6 DIN1 (EXP0) DIN0 (A/B) DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 (MSB) A4 A3 A2 A1 A0 SIA A6 B7 A7 C8 B8 C9 A9 B9 B5 C5 A5 B6 C6 A4 RD WR C4 B4 CE D3 SO E2 D1 SIB CK SCK SFS CIN7 CIN6 GC4016 P17 QUAD P16 P15 RECEIVER P14 CHIP P13 D9 B10 B7 CIN9 CIN8 BIN13 (MSB) P9 BIN12 M9 BIN11 M10 BIN10 L10 BIN9 P11 BIN8 M11 BIN7 L12 BIN6 L14 BIN5 K13 BIN4 K14 BIN3 K12 BIN2 J13 BIN1 (EXP2) J14 BIN0 (EXP1) H2 DIN3 (EXP0) J1 DIN2 (A/B) J12 A6 CIN11 CIN10 L8 K11 CIN3 P12 AIN13 L4 N5 N6 H1 J11 N9 N8 M7 BIN13 (MSB) N4 M4 N7 G3 E11 F11 GC4016 P17 QUAD P16 P15 DIN5 RECEIVER P14 CIN5 CHIP P13 DIN3 DIN7 CIN7 DIN1 CIN1 L3 L2 P6 L6 CIN2 SIA SIB P7 RDY D12 D13 DIN4 CIN4 D3 E2 D1 CK CIN6 P9 P8 BIN12 (MSB) H13 (FSD) P7 AIN12 M10 (FSC) P6 BIN10 H11 (FSB) P5 AIN10 P11 (FSA) P4 BIN8 G14 (SOUTD) P3 AIN8 (SOUTC) P2 L12 BIN6 F14 (SOUTB) P1 AIN6 K13 (SOUTA) P0 BIN4 F13 AIN4 K12 BIN2 (MSB) C7 E12 AIN2 C6 J14 C5 BIN0 D14 C4 AIN0 M9 A4 WR N4 G3 K4 J4 AIN8 AIN7 E1 K1 F2 J11 DIN6 SCK SFS PORT C PLUS N7 CIN0 DIN5 D3 SIB P7 P6 J2 GC4016 P17 QUAD P16 P15 RECEIVER P14 CHIP P13 A11 C11 A6 J1 CIN2 CIN1 BIN11 M10 BIN10 L10 BIN9 P11 BIN8 M11 BIN7 L12 BIN6 L14 BIN5 K13 BIN4 K14 BIN3 K12 BIN2 J13 BIN1 J14 BIN0 H2 DIN3 J1 DIN2 D9 B10 A4 RD E12 AIN2 E13 AIN1 D14 AIN0 P9 M9 L11 N10 CIN2 P12 L8 K11 N9 N8 M7 BIN9 P11 BIN8 M11 BIN7 L12 BIN6 L14 BIN5 K13 BIN4 K14 BIN3 K12 BIN2 J13 BIN1 J14 BIN0 E14 J11 GC4016 P17 QUAD P16 CIN6 P15 CIN5 RECEIVER P14 CIN4 CHIP P13 CIN3 CIN8 CIN7 G3 H1 E11 F11 N5 CIN4 CIN3 DIN8 CIN8 Pins shared with serial outputs M4 L4 DIN0 M4 H1 CIN10 CIN13 (MSB) CIN12 (Must be Grounded) N4 DIN2 DIN1 A10 K2 L1 PORT B PORT C L3 L2 P6 L6 N7 RDY G4 CIN12 DIN10 PORT A L1 N5 N6 DIN4 DIN3 CIN6 CIN5 D13 G2 L2 K1 K3 DIN12 (MSB) UNUSED K3 K2 M4 L4 D12 PORT B K1 A10 SCK SFS MINUS J2 RDY L1 CIN9 CIN8 CIN7 PLUS J3 DIN6 DIN5 L2 N4 CIN11 CIN10 PORT A H1 H2 J1 DIN7 D12 D13 F1 MINUS G4 G3 SCK SFS E3 K3 CIN13 (MSB) CIN12 (Must be Grounded) G1 DIN9 DIN8 PORT C G2 L1 L3 DIN10 PORT B PORT D F1 F3 K3 K2 DIN12 DIN11 PORT A F2 K1 DIN13 (MSB) UNUSED E1 E3 CK DVAL 14 Bit Differential Input Configuration SIB P7 P8 CK DVAL 12 Bit Plus Exponent Configuration NOTE: All unused inputs must be grounded JTAG Pins are: B12 (TCK), C10 (TMS), C12 (TDO), C13 (TDI) Figure 18. GC4016 Pin Assignments  GRAYCHIP,INC. - 28 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 Table 10: GC4016 Pin Out Locations Top View 1: 2: A: 3: 4: 5: 6: 7: 8: 9: 10: 11: 12: 13: 14: * GND RD A2 C7 C5 GND C1 RDY P2 GND GND B: * * * CE A4 A1 C6 C3 C0 P3 P0 TCK * VPAD C: GND * VPAD WR A3 A0 P5 C4 C2 TMS P1 TDO TDI VCORE D: SIB VCORE SIA P8 P7 VPAD P6 VPAD P4 VPAD GND SCK SFS AIN0 E: DIN13 SO DIN12 GND P23 AIN2 AIN1 AIN3 F: DIN10 DIN11 DIN9 P9 P22 AIN5 AIN4 AIN6 G: DIN7 DIN8 DIN5 DIN6 TGND TGND GND VPAD AIN7 AIN8 H: DIN4 DIN3 P10 P11 TGND TGND AIN10 AIN9 AIN12 AIN11 J: DIN2 DIN0 DIN1 P12 P21 AIN13 BIN1 BIN0 K: CIN13 CIN11 CIN12 P13 P20 BIN2 BIN4 BIN3 L: CIN10 CIN8 CIN9 CIN5 VCORE CIN1 GND BIN13 GND BIN9 P19 BIN6 VCORE BIN5 M: GND * VPAD CIN6 GND P14 P15 VCORE BIN11 BIN10 BIN7 * * GND N: * * GND CIN7 CIN4 CIN3 CIN0 P16 P17 P18 GND * * * * VCORE GND VPAD CIN2 CK DVAL BIN12 VCORE BIN8 VPAD * P: VPAD =Pad Ring Power (3.3v) VCORE = Core Power (2.5v) TGND = Thermal Ground * = unused ball  GRAYCHIP,INC. - 29 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 SIGNAL DESCRIPTION A,B,C, DIN INPUT DATA, Active high input pins The 14 bit 2’s complement input data for the four channels. The inputs are clocked into the chip on the rising edge of the clock (CK). These pins can be configured to support three 16 bit ports, two 14 bit differential ports, three 12 bit + 3 bit exponent ports, or three 12 bit + 3 bit exponent + A/B selection ports. See Section 3.2 and Figure 18. P[0:3] BIT SERIAL AND NIBBLE OUTPUT DATA, Active high tristate output pins The nibble and bit serial output pins. In the serial mode these are individual outputs, in the nibble mode these form a four bit nibble (P0 is normally the LSB of the Nibble, P3 is the MSB). The output bits are clocked out coincident with the rising edge of SCK (falling edge if INV_SCK=1). These pins are tristated at power up and are enabled by EN_P0, EN_P1, EN_P2 and EN_P3. P[0:23] PARALLEL OUTPUT DATA, Active high tri state output pins The 24 bit parallel output port. These output bits are clocked out by CK coincident with the rising edge of SCK (falling edge if INV_SCK=1) with the SFS and RDY pins used to identify valid data (Section 3.8.6). These pins are tristated at power up and are enabled by the EN_PAR control register bit. These pins can are used in the wide word microprocessor mode. In this mode the pins are used as part of the control bus when read from the data output page (See Section 3.8). SCK SERIAL DATA CLOCK, Active high or low tristate output pin The serial, nibble, link and parallel data output clock. The SCK signal is clocked out on the rising edge of CK. The SFS, RDY and P output signals are clocked out of the chip coincident with the active edge of this clock. The active edge of the clock is user programmable. This pin is tristated at power up and is enabled by the EN_SCK control register bit. SFS SERIAL FRAME STROBE, Active high or low tristate output pin The bit serial word strobe. This strobe identifies the beginning of a frame, a complex pair, or a word within bit serial output streams as controlled by the SFS_MODE control register bits. The polarity of this signal is user programmable. This pin is tristated at power up and is enabled by the EN_SFS control register bit. This pin is also used as a data valid signal for parallel outputs. RDY READY FLAG, programmable active high or low bidirectional I/O pin Used to identify when new outputs are available in the serial, nibble and microprocessor output modes. In the link mode RDY is an input signal tied to the LACK output signal from SHARC DSP chips. In the parallel mode it is a data valid flag. The RDY signal is clocked out on the rising edge of CK. This pin is tristated at power up and is enabled by the EN_RDY control register bit. CK INPUT CLOCK. Active high input pin The clock input to the chip. The AIN, BIN, CIN, DIN, DVAL, SIA and SIB input signals are clocked into the chip on the rising edge of this clock. The SO, P, SFS, SCK and RDY outputs are clocked out on the rising edge of this clock. DVAL DATA VALID. Active low input pin This pin is normally grounded. This pin must be low to enable the internal clock. DVAL is clocked into the chip on the rising edge of CK, and, if high, disables the following CK edge to the channels and resampler. It does not effect the clock to the output circuitry. Since DVAL enables or disables the internal clock, it can be used as a data enable for non-continuous input data. This pin should never be held high for more than 1ms. DVAL is used as a 2X clock input when the CK_2X_EN control bit is high (see Section 3.9). SIA, SIB SYNC IN A and B. Active low input pins The sync inputs to the chip. All timers, accumulators, and control counters (except the resampler time delay accumulator) are, or can be, synchronized to SIA or SIB. These syncs are clocked into the chip on the rising edge of the input clock (CK). SO SYNC OUT. Active low output pin This signal is either a delayed version of one of the input syncs SIA or SIB, the sync counter’s terminal count (TC), or a one-shot strobe. The SO signal is clocked out of the chip on the rising edge of the input clock (CK). C[0:7] CONTROL DATA I/O BUS. Active high bidirectional I/O pins This is the 8 bit control data I/O bus. Control registers are written to or read from through these pins. The chip drives these pins when CE is low, RD is low and WR is high. Note that when the output is in the wide word microprocessor mode, the P[0:23] pins are used when reading and will behave the same as the C[0:7] pins. When reading from the output page the P[0:23] pins will output data, when reading from all other pages the P[0:23] pins will read back high. A[0:4] CONTROL ADDRESS BUS. Active high input pins These pins are used to address the control registers within the chip. Each of the control registers within the chip are assigned a unique address. A control register can be written to or read from by setting A[0:4] to the register’s address and setting the page register appropriately. An alternate method using a 4 bit addressing scheme is available to support using buses with limited addressing (for example the TI320C6X family peripheral host interface bus). See Section 3.1. RD READ ENABLE. Active low input pin The register selected by A[0:4] and the page register is output on the C[0:7] pins when RD and CE are low. WR WRITE ENABLE. Active low input pin The value on the C[0:7] pins is written into the register selected by the A[0:4] and page register when WR and CE are low. CE CHIP ENABLE. Active low input pin This control strobe enables the read or write operations. TCK,TDI,TMS,TDO JTAG INTERFACE. Active high input (TCK, TMS, TDI) and tristate output (TDO) pins The JTAG interface (See Section 3.15)  GRAYCHIP,INC. - 30 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP 5.0 DATA SHEET REV 1.0 CONTROL REGISTERS The chip is configured by writing to eight bit control registers. These registers are accessed for reading or writing using the control bus pins (CE, RD, WR, A[0:4], and C[0:7]) described in Section 3.1. The 32 word address space is split into eight global registers (addresses 0-7), eight unused registers (addresses 8-15) and 16 paged registers (addresses 16-31). The global registers are available from each page. Address 2 is the page register which selects which control registers are accessed by addresses 16 through 31. 5.1 GLOBAL CONTROLS The eight global control registers are: Table 11: Global Control Registers ADDRESS NAME DESCRIPTION 0 Global Reset Miscellaneous general controls. 1 Status uP ready/missed, resampler overflows, checksum ready, 2 Page Page register for both 4 and 5 bit addressing modes 3 Checksum Checksum results register 4 General Syncs Syncs for output, checksum. One shot. 5 Count Sync Sync for counter, ramp selection 6 Counter Byte 0 Ramp counter least significant byte. 7 Counter Byte 1 Ramp counter most significant byte. ADDRESS 0: Global Reset, Powers up as 0xF0. Suggested Default is 0xF8 during configuration, 0x08 afterwards. BIT TYPE NAME DESCRIPTION 0 LSB R/W CK_LOSS_DETECT Disable the clock loss detection circuitry. This circuitry protects the chip against a current surge that may result if the clock is inactive for more than 100mS. Setting this bit turns off the clock loss detection circuitry. Used for test, not recommended for general use. 1 R/W CK_2X_TEST Test mode to output the doubled clock on SO. DVAL must be low. Normally set to zero. 2 R/W CK_2X_EN Changes the DVAL pin to become a CK_2X input pin. The chip normally uses an internally generated doubled clock (twice the CK clock). Setting this bit allows an externally generated doubled clock to be used. Used in test, not recommended for general use. 3 R/W EDGE_WRITE Sets the edge write mode for the control interface. When low the data must be stable while the write strobe is low. When high the outputs are latched on the rising edge of the write strobe (WR | CE). A short (approximately 15 nS) write recovery time is required during which time the chip should not be read from or written to. Recommended to be set high. 4 R/W RESAMPLER_RESET 5 R/W PAD_RESET Forces SFS and RDY pads to tristate during power up. The user needs to clear this bit for proper operation of SFS and RDY. 6 R/W OUT_BLK_RESET This bit resets the output formatter block. This bit is set during power up and is cleared after configuration. 7 R/W GLOBAL_RESET This bit powers down the chip and tristates the output pins. This bit is set during power up and is cleared after configuration.  GRAYCHIP,INC. This bit resets the resampler. This bit is set during power up and is cleared after configuration. - 31 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP ADDRESS 1: DATA SHEET REV 1.0 Status Register, Suggested default = 0x00 BIT TYPE NAME DESCRIPTION 0 LSB R/W READY The user sets this bit after reading the output registers. The chip clears this bit when new values have been loaded and it is time to read them. 1 R/W MISSED The chip sets this bit If the user has not set the READY bit before the chip loads the output registers. This bit high indicates that an error has occurred. 2 R/W RES_IOV This control bit is set by the chip whenever the resampler I channel overflows. The user can monitor this bit to see if the gain is too high. The user clears the bit by writing a zero to it. 3 R/W RES_QOV This control bit is set by the chip whenever the resampler Q channel overflows. The user can monitor this bit to see if the gain is too high. The user clears the bit by writing a zero to it. 4 R/W CHECK_DONE This bit is set when the checksum sync is active (see DIAG_SYNC in address 4). The user can count sync cycles by clearing this bit and then waiting for it to be set. The checksum will be complete after it this bit has been cleared and set four times. 5-7 MSB R ZERO Reads back as zero. The READY bit is used to tell an external processor when new output samples are ready to be read. If desired, the RDY pin can be used as an interrupt to the external processor (See Section 3.8.1) to tell the processor when to read new samples. The user does not need to set the READY bit if RDY is used. If READY is not set, however, the MISSED flag will not be valid. ADDRESS 2: Page Register BIT TYPE NAME DESCRIPTION 0 LSB R/W A3 Used in the 4_BIT_ADDRESS mode (see global register 4) as address bit A3. This bit is unused if 4_BIT_ADDRESS=0. 1-7 MSB R/W PAGE[0:6] Page number for addressing different portions of the chip. In normal mode, the LSB is unused. PAGE is decoded to select the different control pages (see Table 12). Note that addresses 0-7 are globally visible regardless of the PAGE value. Addresses 8-15 are unused. Addresses 16-31 are paged. In the four bit address mode, the LSB provides address bit A3, effectively reducing each page to 8 words and doubling the number of pages. ADDRESS 3: Checksum Register BIT TYPE NAME DESCRIPTION 0-7 R CHECKSUM[0:7] The checksum. The checksum register is a read only register which contains the checksum of the output data. The checksum is stored in the checksum register and then starts over again each time the DIAG_SYNC (See address 4) occurs.  GRAYCHIP,INC. - 32 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP ADDRESS 4: DATA SHEET REV 1.0 General Sync Register, Suggested default = 0x27, Cleared by power up BIT TYPE NAME DESCRIPTION 0-2 (LSB) R/W DIAG_SYNC The Checksum generator is strobed by this sync. See Table 7 for the possible sync selections. 3-5 R/W OUTPUT_SYNC The selected sync is inverted and output on the SO pin. See Table 7. 6 R/W 4_BIT_ADDRESS This mode allows four address bits (such as the expansion bus of the TI320C6202) instead of 5 to be used. In this mode each page contains 8 words (rather than 16). The LSB of the page register is used as address bit A3. Pin A3 should be grounded in this mode. 7 (MSB) R/W DIFF_IN Enables differential receivers. Both this bit and the corresponding bits in each channel must be set to properly receive differential signals. This bit should be cleared for other inputs and for minimum power consumption. Contact Graychip for the use of the differential input mode. ADDRESS 5: Count Sync Register, Suggested default = 0x50 BIT TYPE NAME DESCRIPTION 0-1 LSB R/W DIAG_SOURCE This two bit field selects the diagnostic input source used when the INPUT_SEL field in each channel’s control register is set to 6 or 7 (See channel control address 27). DIAG_SOURCE = 0 selects the 16 LSB’s of the counter (see addresses 6&7) as a diagnostic ramp. DIAG_SOURCE=1 is a zero input, DIAG_SOURCE=2 is unused, DIAG_SOURCE= 3 gives a 0x4000 constant input. 2-4 R/W COUNTER_SYNC Synchronizes the sync counter. This counter is used to generate the periodic TC sync. See Table 7. 5 R/W COUNT_TEST Used during factory tests. Should be set to 0 for normal operation. 6 R/W OS_MODE The ONE_SHOT signal is a level, not a pulse when this bit is set. 7 (MSB) R/W ONE_SHOT The one shot sync signal (OS) is generated when this bit is set. If OS_MODE is low, then a one shot pulse (one clock cycle wide) is generated. If OS_MODE is high, then the ONE_SHOT sync is active while this bit is high. This bit must be cleared before another one shot pulse can be generated. ADDRESS 6: Counter Byte 0, Suggested default = DEC (CIC decimation value) BIT TYPE NAME DESCRIPTION 0-7 R/W CNT[0:7] The LSBs of the counter cycle period ADDRESS 7: Counter Byte 1, Suggested default = DEC BIT TYPE NAME DESCRIPTION 0-7 R/W CNT[8:15] The 8 MSBs of the counter cycle period The chip’s internal sync counter counts in cycles of 256(CNT+1) clocks. A terminal count signal (TC) is output at the end of each cycle. The counter can be synchronized to an external sync as specified in the Count Sync Register (address 5). If CNT is set so that 256(CNT+1) is a multiple of sixteen times the CIC decimation ratio (i.e., a multiple of 16N), then the terminal count of this counter can be output on the SO pin and used to periodically synchronize multiple GC4016 chips.  GRAYCHIP,INC. - 33 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP 5.2 DATA SHEET REV 1.0 PAGED REGISTERS Addresses 16 to 31 are used in pages as determined by the page map register (address 2). Table 12: Page Assignments Page Description 0,1 Channel A CFIR Coefficients 2-5 Channel A PFIR Coefficients 6 Channel A Frequency 7 Channel A Control 8,9 Channel B CFIR Coefficients 10-13 Channel B PFIR Coefficients 14 Channel B Frequency 15 Channel B Control 16,17 Channel C CFIR Coefficients 18-21 Channel C PFIR Coefficients 22 Channel C Frequency 23 Channel C Control 24,25 Channel D CFIR Coefficients 26-29 Channel D PFIR Coefficients 30 Channel D Frequency 31 Channel D Control 32-63 Resampler Coefficients 64 Resampler Control 65 Resampler Ratios 66-95 unused 96,97 Output Data 98 Output Control 99-127 unused The following sections describe each of these pages.  GRAYCHIP,INC. - 34 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP 5.3 DATA SHEET REV 1.0 CFIR COEFFICIENT PAGES The user programmable filter CFIR coefficients are stored using pages 0 and 1 for channel A, pages 8 and 9 for channel B, pages 16 and 17 for channel C, and pages 24 and 25 for channel D. Table 13: CFIR Coefficient Pages Pages 0, 8, 16, or 24 Pages 1, 9, 17, or 25 Address Description Description 16 h0 LSBs (end or first tap) h8 LSBs 17 h0 MSBs (end or first tap) h8 MSBs 18 h1 LSBs h9 LSBs 19 h1 MSBs h9 MSBs 20 h2 LSBs h10 LSBs (center tap) 21 h2 MSBs h10 MSBs (center tap) 22 h3 LSBs unused 23 h3 MSBs 24 h4 LSBs 25 h4 MSBs 26 h5 LSBs 27 h5 MSBs 28 h6 LSBs 29 h6 MSBs 30 h7 LSBs 31 h7 MSBs Coefficient h0 is the first coefficient and coefficient h10 is the center coefficient of the filter’s impulse response. The 16 bit 2’s complement coefficients are stored in two bytes, least significant byte first, for example, the LSBs of coefficient 0 are stored in address 16 and the MSBs in address 17. TO LOAD A COEFFICIENT THE USER MUST WRITE THE LSBYTE FIRST FOLLOWED BY THE MSBYTE. Unknown values will be written into the LSBs if the MSB is written first. The coefficient registers are read/write. 5.4 PFIR COEFFICIENT PAGES The user programmable filter PFIR coefficients are stored using pages 2, 3, 4 and 5 for channel A, pages 10, 11, 12 and 13 for channel B, pages 18, 19, 20 and 21 for channel C, and pages 26, 27, 28 and 29 for channel D. Table 14: PFIR Coefficient Pages Pages 2, 10, 18, or 26 Pages 3, 11, 19, or 27 Pages 4, 12, 20, or 28 Pages 5, 13, 21, or 29 Address Description Description Description Description 16 h0 LSBs (end tap) h8 LSBs h16 LSBs h24 LSBs 17 h0 MSBs (end tap) h8 MSBs h16 MSBs h24 MSBs 18 h1 LSBs h9 LSBs h17 LSBs h25 LSBs 19 h1 MSBs h9 MSBs h17 MSBs h25 MSBs 20 h2 LSBs h10 LSBs h18 LSBs h26 LSBs 21 h2 MSBs h10 MSBs h18 MSBs h26 MSBs 22 h3 LSBs h11 LSBs h19 LSBs h27 LSBs 23 h3 MSBs h11 MSBs h19 MSBs h27 MSBs 24 h4 LSBs h12 LSBs h20 LSBs h28 LSBs 25 h4 MSBs h12 MSBs h20 MSBs h28 MSBs 26 h5 LSBs h13 LSBs h21 LSBs h29 LSBs 27 h5 MSBs h13 MSBs h21 MSBs h29 MSBs 28 h6 LSBs h14 LSBs h22 LSBs h30 LSBs 29 h6 MSBs h14 MSBs h22 MSBs h30 MSBs 30 h7 LSBs h15 LSBs h23 LSBs h31 LSBs (center tap) 31 h7 MSBs h15 MSBs h23 MSBs h31 MSBs (center tap)  GRAYCHIP,INC. - 35 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 Coefficient h0 is the first coefficient and coefficient h31 is the center coefficient of the filter’s impulse response. The 16 bit 2’s complement coefficients are stored in two bytes, least significant byte first, for example, the LSBs of coefficient 0 are stored in address 16 and the MSBs in address 17. TO LOAD A COEFFICIENT THE USER MUST WRITE THE LSBYTE FIRST FOLLOWED BY THE MSBYTE. Unknown values will be written into the LSBs if the MSB is written first. The coefficient registers are read/write. 5.5 CHANNEL FREQUENCY PAGES Pages 6, 14, 22, and 30 contain the phase and frequency control settings for the four channels. The frequency and phase for channel A are set in page 6. The frequency and phase for channel B are set in page 146. The frequency and phase for channel C are set in page 22. The frequency and phase for channel D are set in page 30. All registers are read/write. ADDRESSES 16, 17: Phase ADDRESS TYPE NAME DESCRIPTION 16 R/W PHASE[0:7] Byte 0 (LSBs) of PHASE 17 R/W PHASE[8:15] Byte 1 (MSBs) of PHASE The 16 bit phase offset is defined as: PHASE = 216P/2π where P is the desired phase in radian from 0 to 2π. ADDRESSES 18, 19, 20, and 21: Frequency ADDRESS TYPE NAME DESCRIPTION 18 R/W FREQ[0:7] Byte 0 (LSBs) of FREQ 19 R/W FREQ[8:15] Byte 1 of FREQ 20 R/W FREQ[16:23] Byte 2 of FREQ 21 R/W FREQ[24:31] Byte 3 (MSBs) of FREQ The 32 bit frequency control word is defined as: FREQ = 2 32F/FCK where F is the desired tuning frequency and FCK is the chip’s clock rate (CK). Use positive frequency values to downconvert signals. Use negative frequency values to invert the signal’s spectrum. The 32 bit 2’s complement frequency words are entered as four bytes, the least significant byte in the lowest address, the most significant in the highest address.  GRAYCHIP,INC. - 36 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP 5.6 DATA SHEET REV 1.0 CHANNEL CONTROL PAGES These pages contain the various control settings for the four channels. To configure channels A, B, C and D use pages 7, 15, 23, and 31 respectfully. All registers are read/write. The following table summarizes the registers: Table 15: Channel Control Registers ADDRESS NAME DESCRIPTION 16 Channel Reset Resets the channel and sets SHIFT 17 Frequency Sync Phase and Frequency syncs 18 NCO sync NCO and dither syncs 19 Blank Blank controls 20 Dec Sync Synchronizes CIC decimation and flush 21,22 Decimation Ratio Sets CIC decimation and sync for fine gain 23 CIC Scale Sets CIC gain and MIX20B 24 SplitIQ SplitIQ and negate control 25 CFIR Quarter delays, Coarse, Nosym1 26 PFIR Half delays, Nosym2 27 Input Selects input format and port. 28 Peak Control Controls peak and overflow detection counter 29 Peak Read Number of peaks (overflows) during last sync period. 30,31 Fine Gain Fine gain control ADDRESS 16: Channel Reset Set to 0x80 on power up, Suggested default = 0x0C BIT TYPE NAME DESCRIPTION 0-2 (LSBs) R/W SHIFT Value used to shift up the mixer output if USE_SHIFT is high. Note that if USE_SHIFT is high and MIX20B is set, then SHIFT is restricted to the range of 4-7. 3 R/W USE_SHIFT Selects SHIFT if high. If low the mixer output shift value is provided by the exponent bits of the floating point input format (see Section 3.2). 4-6 R/W Unused 7 R/W CH_RESET ADDRESS 17: This bit resets the channel. If high, the channel is in a reset state with the clock disabled. Frequency Sync, Suggested default = 0x77 BIT TYPE NAME DESCRIPTION 0-2 LSB R/W PHASE_SYNC The new phase offset takes effect on this sync 3 R/W Unused 4-6 R/W FREQ_SYNC 7 MSB R/W Unused The new frequency setting takes effect on this sync. These syncs use the selections shown in Table 7. The FREQ_SYNC and PHASE_SYNC are typically set to be “always” so that frequency and phase settings will take effect immediately as they are written into their control registers. Due to the asynchronous nature of the interface in this mode a few samples will be mixed with transient frequencies until the new frequency and phase values are established. If these transients are undesirable OR if the accumulated phase must be controlled, then another sync source should be used.  GRAYCHIP,INC. - 37 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP ADDRESS 18: DATA SHEET REV 1.0 NCO Sync, Suggested default = 0x22 BIT TYPE NAME DESCRIPTION 0-2 LSB R/W NCO_SYNC The NCO is initialized to the phase setting by this sync 3 R/W Unused 4-6 R/W DITHER_SYNC 7 MSB R/W Unused The dither circuit is reset by this sync to zero. These syncs use the selections shown in Table 7. The NCO_SYNC can be changed to “SIB” so that the SIB sync can be used to synchronize the NCO phases of multiple channels or chips. The DITHER_SYNC is used to turn on or off the dithering of the NCO phase. Dithering is turned on by setting DITHER_SYNC to “never”. Dithering is turned off by setting DITHER_SYNC to “always” which causes it to remain reset to zero. During diagnostics the NCO_SYNC and DITHER_SYNC should be set to “TC” (5). If the user wishes to allow the chip to free run, asynchronous to other chips, then these sync settings can be set to “never”. ADDRESS 19: Zero Pad Mode Control Register, Suggested default = 0x20 BIT TYPE NAME DESCRIPTION 0-3 LSB R/W NZEROS The number of zeroes to insert between each sample in the blank mode. Ranges from 0 to 15. Note that this introduces a gain of 1/(NZEROS+1). 4-6 R/W ZPAD_SYNC The sync selection from Table 7 for the zero pad function (See Figure 5). 7 MSB R/W ZPAD_EN Turn on zero padding for this channel. ADDRESS 20: Dec and Flush Sync Register, Suggested default = 0x22 BIT TYPE NAME DESCRIPTION 0-2 LSB R/W DEC_SYNC Synchronizes the decimation control counter. The decimation counter controls the filtering of each channel. 3 R/W Unused 4-6 R/W FLUSH_SYNC 7 MSB R/W Unused Synchronizes the flush sync for this channel. The decimation counter sync (DEC_SYNC) may be periodic without interrupting processing so long a the sync period is a multiple of 8N. A decimation sync should be issued if the decimation control is changed. Each channel should be flushed (FLUSH_SYNC) when the chip is being initialized or when the decimation control is changed. The flush lasts for 24N clocks after the sync occurs. The channel flush syncs will normally be left in a “never” mode. During diagnostics the channels will need to be flushed at the beginning of each sync cycle. The user may wish to flush a channel when a new frequency is selected in order to purge the datapath of the last signal.  GRAYCHIP,INC. - 38 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP ADDRESS 21: DATA SHEET REV 1.0 Decimation Ratio Byte 0, Suggested default = 0x07 BIT TYPE NAME DESCRIPTION 0-7 R/W DEC[0:7] The LSBs of the decimation control ADDRESS 22: Decimation Ratio Byte 1, Suggested default = 0x70 BIT TYPE NAME DESCRIPTION 0-3 R/W DEC[8:11] The 4 MSBs of the decimation control 4-6 R/W GAIN_SYNC The new fine gain takes effect on this sync. 7 MSB R/W Unused The CIC decimation is N. When processing in normal mode (not SPLITIQ) DEC should be set to N-1 where N ranges from 8 to 4096. When processing in SPLITIQ mode DEC should be set to 2N-1 where N ranges from 4 to 2048. ADDRESS 23: CIC Scale, Suggested default = 0x79 BIT TYPE NAME DESCRIPTION 0-2 R/W SCALE SCALE ranges from 0 to 5. 3-5 R/W BIG_SCALE BIG_SCALE ranges from 0 to 7. 6 R/W MIX20B Round mixer output to 20 bits if MIX20B=1 or to 16 bits if MIX20B=0. If MIX20B=1 then SHIFT (see address 16) must be at least 4 to shift the extra 4 bottom bits into the datapath. For very large decimations (>3104) unity gain through the CIC can only be accomplished by using a smaller SHIFT and hence MIX20B must be zero. The default is MIX20B=1. 7 R/W unused The CIC filter has a gain which is equal to N5. To remove this gain the CIC inputs are pre-scaled down by (62-SHIFT-SCALE-6*BIG_SCALE) bits before filtering. The values of SHIFT, SCALE and BIG_SCALE must be such that: ( SHIFT + SCALE + 6 × BIG_SCALE ) ≤ ( 62 – 5log2 N + log2 (NZERO+1) ) Overflows due to improper gain settings will go undetected if this relationship is violated. For example, this restriction means that for N equal to 8, and SHIFT equal to 4, BIG_SCALE and SCALE should be less than or equal to 7 and 1 respectively. ADDRESS 24: SplitIQ, Suggested default = 0x00 BIT TYPE NAME DESCRIPTION 0-3 R/W NEG_CTL A four bit pattern that multiplies the output of PFIR by +/- 1. This is used to perform complex to real conversion (Fs/4 upconvert), flip the spectrum, or perform an Fs/2 frequency shift. 4 R/W SPLITIQ Process only the real data (at twice the throughput). Used to allow two channels to be ganged together for wider output bandwidth. 5 R/W IONLY All samples output by this channel are real. Used in the SPLITIQ mode to identify the channel generating the I-half of the complex output. 6 R/W QONLY All samples output by this channel are imaginary. Used in the SPLITIQ mode to identify the channel generating the I-half of the complex output. When performing complex to real conversion this bit must be set (amongst others). 7 R/W Unused Sections 3.3 and 3.4 describe how to use these controls.  GRAYCHIP,INC. - 39 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP ADDRESS 25: DATA SHEET REV 1.0 CFIR, Suggested default = 0x00 BIT TYPE NAME DESCRIPTION 0 LSB R/W NO_SYM_CFIR When this bit is high, CFIR is an 11 tap asymmetric filter. Coefficient h0 is multiplied by the newest data. 1 R/W QDLY_CFIR Delay the Q sample stream by one CFIR input sample. Effectively, this is a 1/4 sample delay of the output PFIR. Used in the multi-channel modes (see Section 3.4). 2 R/W IDLY_CFIR Delay the I-sample stream by one CFIR input sample. Effectively, this is a 1/4 sample delay of the output PFIR.Used in the multi-channel modes (see Section 3.4). 3 R/W Unused 4-6 R/W COARSE This introduces a gain of 2COARSE after the CIC but before rounding to 20 bits to feed CFIR. This allows optimization of gain in applications where it is known that most of the signal energy presented to the A/D has been filtered out by the CIC. An example of such an application is an FDM stack. 7 R/W TEST Test mode. Should be set to 0. ADDRESS 26: PFIR, Suggested default = 0x00 BIT TYPE NAME DESCRIPTION 0 LSB R/W NO_SYM_PFIR When this bit is high PFIR is an 32 tap asymmetric filter. Coefficient h0 is multiplied by the newest data. 1 R/W QDLY_PFIR Delay the Q sample stream by one PFIR input sample. Effectively, this is a 1/2 sample delay of the output PFIR. Used in the real or multi-channel modes (see Sections 3.3 and 3.4). 2 R/W IDLY_PFIR Delay the I-sample stream by one PFIR input sample. Effectively, this is a 1/2 sample delay of the output PFIR.Used in the real or multi-channel modes (see Sections 3.3 and 3.4). 3-4 R/W PEAK_SELECT Select the overflow detection source for the peak counter. Only used if PEAK_MODE=1. Selects CFIR, COARSE_GAIN, or PFIR for values 0,1, or 2 respectively (the values 2 and 3 are the same). See address 28 below. 5-7 R/W Unused ADDRESS 27: Input, Suggested default = 0x00 BIT TYPE NAME DESCRIPTION 0-2 (LSBs) R/W INPUT_SEL Selects which input port to use for this channel. Values 0-3 select inputs A-D respectively. Values 4 and 5 select differential inputs A and B. Values 6 and 7 select the internal diagnostic source (see general address 5). Note that for differential inputs one must also enable the differential receivers by setting the DIFF_IN bit in register 4. 3 R/W SEL_AB Selects the A/B channel in the dual 12 bit plus exponent mode (INPUT_MODE=3). If SEL_AB is 0, then the samples with their A/B flag low are used. If SEL_AB is high, then the samples with their A/B flag high are used. 4-5 R/W INPUT_MODE Selects the input format: 0 is the 14 bit input mode, 1 is the 16 bit input mode, 2 is the 12 bit plus exponent mode, and 3 is the dual 12 bit plus exponent mode. 6 R/W Unused 7 MSB R/W MSB_POL  GRAYCHIP,INC. Invert the MSB polarity. This will convert an offset binary formatted input to 2’s complement format. - 40 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP ADDRESS 28: DATA SHEET REV 1.0 Peak Control, Suggested default = 0x1D BIT TYPE NAME DESCRIPTION 0-2 LSB R/W PEAK_SYNC Synchronizes the peak counter circuitry using the mode selected in Table 7. When the selected sync occurs, the counter transfers its contains to a read only control register and clears the counter. 3-4 R/W PEAK_THRESHOLD When the input peak detect mode is selected (PEAK_MODE=0), the input word is checked against a threshold. The threshold values are 1/4, 1/2, 3/4, or 4/4 (full scale) for PEAK_THRESH= 0,1,2, or 3 respectively. The absolute value of the top 11 bits is compared to the selected threshold. This is only used when the PEAK_MODE is zero. 5 R/W PEAK_MODE If PEAK_MODE is zero, the input word is selected as the source to the peak counter, otherwise one of three overflow bits (see PEAK_SELECT at address 26) is monitored by the peak counter. 6-7 R/W Unused ADDRESS 29: Peak Count, Read only BIT TYPE NAME DESCRIPTION 0-7 R PEAK_COUNT Count of number of overflows or samples above threshold during last sync period. The counter hard-limits at 255. ADDRESS 30: Fine Gain Byte 0, Suggested default = 0x00 BIT TYPE NAME DESCRIPTION 0-7 R/W FINE_GAIN[0:7] The LSBs of the fine gain control ADDRESS 31: Fine Gain Byte 1, Suggested default = 0x00 BIT TYPE NAME DESCRIPTION 0-5 R/W FINE_GAIN[8:13] The MSBs of the fine gain control 6-7 MSB R/W Unused The fine gain control can apply a gain of FINE_GAIN/1024 providing a range of 0 to almost 16. Double buffering and synchronization for data transfer is provided to allow the user to change the gain dynamically without causing glitches in the signal (See GAIN_SYNC in address 22). This also allows the user to synchronously change gain in multiple channels even across different chips.  GRAYCHIP,INC. - 41 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP 5.7 DATA SHEET REV 1.0 RESAMPLER COEFFICIENT PAGES (PAGES 32-63) These pages store the 256 resampler coefficients. Storing resampler coefficient values is similar to storing the coefficients for the CFIR and PFIR filters. The resampler coefficients are 12 bits with the 8 LSBs written in one address, and the upper 4 bits written as the 4 LSBs of the next address. When reading back resampler coefficients the top four bits of the second address always read back zero. The resampler coefficient RAM must be written in blocks of eight addresses (four coefficients). Writes to the RAM occur when a write is done to addresses 23 or 31. Supplying coefficients in sequential order will write correctly to the RAM. If just a portion of the resampler coefficient RAM is to be updated, then one must write in blocks of the eight addresses 16 to 23, or 24 to 31. Writing to less than eight addresses will either result in no change to the RAM or unknown changes to some coefficients. TO LOAD A COEFFICIENT THE USER MUST WRITE IN BLOCKS OF FOUR COEFFICIENTS. ONE MUST WRITE TO ADDRESSES 16-22 THEN ADDRESS 23 OR TO ADDRESSES 24-30 THEN ADDRESS 31. Table 16: Resampler Coefficient Pages (Single filter mode) Page Address 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 16 h0 h8 h 16 h24 h32 h40 h48 h 56 h64 h72 h80 h88 h96 h 104 h112 h120 17 h0 h8 h 16 h24 h32 h40 h48 h 56 h64 h72 h80 h88 h96 h 104 h112 h120 18 h1 h9 h 17 h25 h33 h41 h49 h 57 h65 h73 h81 h89 h97 h 105 h113 h121 19 h1 h9 h 17 h25 h33 h41 h49 h 57 h65 h73 h81 h89 h97 h 105 h113 h121 20 h2 h10 h 18 h26 h34 h42 h50 h 58 h66 h74 h82 h90 h98 h 106 h114 h122 21 h2 h10 h 18 h26 h34 h42 h50 h 58 h66 h74 h82 h90 h98 h 106 h114 h122 22 h3 h11 h 19 h27 h35 h43 h51 h 59 h67 h75 h83 h91 h99 h 107 h115 h123 23 h3 h11 h 19 h27 h35 h43 h51 h 59 h67 h75 h83 h91 h99 h 107 h115 h123 24 h4 h12 h 20 h28 h36 h44 h52 h 60 h68 h76 h84 h92 h100 h 108 h116 h124 25 h4 h12 h 20 h28 h36 h44 h52 h 60 h68 h76 h84 h92 h100 h 108 h116 h124 26 h5 h13 h 21 h29 h37 h45 h53 h 61 h69 h77 h85 h93 h101 h 109 h117 h125 27 h5 h13 h 21 h29 h37 h45 h53 h 61 h69 h77 h85 h93 h101 h 109 h117 h125 28 h6 h14 h 22 h30 h38 h46 h54 h 62 h70 h78 h86 h94 h102 h 110 h118 h126 29 h6 h14 h 22 h30 h38 h46 h54 h 62 h70 h78 h86 h94 h102 h 110 h118 h126 30 h7 h15 h 23 h31 h39 h47 h55 h 63 h71 h79 h87 h95 h103 h 111 h119 h127 31 h7 h15 h 23 h31 h39 h47 h55 h 63 h71 h79 h87 h95 h103 h 111 h119 h127 Page Address 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 16 h128 h136 h 144 h152 h160 h168 h176 h 184 h192 h200 h208 h216 h224 h 232 h240 h248 17 h128 h136 h 144 h152 h160 h168 h176 h 184 h192 h200 h208 h216 h224 h 232 h240 h248 18 h129 h137 h 145 h153 h161 h169 h177 h 185 h193 h201 h209 h217 h225 h 233 h241 h249 19 h129 h137 h 145 h153 h161 h169 h177 h 185 h193 h201 h209 h217 h225 h 233 h241 h249 20 h130 h138 h 146 h154 h162 h170 h178 h 186 h194 h202 h210 h218 h226 h 234 h242 h250 21 h130 h138 h 146 h154 h162 h170 h178 h 186 h194 h202 h210 h218 h226 h 234 h242 h250 22 h131 h139 h 147 h155 h163 h171 h179 h 187 h195 h203 h211 h219 h227 h 235 h243 h251 23 h131 h139 h 147 h155 h163 h171 h179 h 187 h195 h203 h211 h219 h227 h 235 h243 h251 24 h132 h140 h 148 h156 h164 h172 h180 h 188 h196 h204 h212 h220 h228 h 236 h244 h252 25 h132 h140 h 148 h156 h164 h172 h180 h 188 h196 h204 h212 h220 h228 h 236 h244 h252 26 h133 h141 h 149 h157 h165 h173 h181 h 189 h197 h205 h213 h221 h229 h 237 h245 h253 27 h133 h141 h 149 h157 h165 h173 h181 h 189 h197 h205 h213 h221 h229 h 237 h245 h253 28 h134 h142 h 150 h158 h166 h174 h182 h 190 h198 h206 h214 h222 h230 h 238 h246 h254 29 h134 h142 h 150 h158 h166 h174 h182 h 190 h198 h206 h214 h222 h230 h 238 h246 h254 30 h135 h143 h 151 h159 h167 h175 h183 h 191 h199 h207 h215 h223 h231 h 239 h247 h255 31 h135 h143 h 151 h159 h167 h175 h183 h 191 h199 h207 h215 h223 h231 h 239 h247 h255 Table 16 shows the coefficient register assignments when there is a single filter (NF=0). For two filters (NF=1), the two filters are interleaved, i.e., the heven in Table 16 will contain one filter and hodd will contain the other. Four four filters (NF=3), the four filters are interleaved, i.e., h0, h4, h8, ... is the first filter, h1, h5, ... is the second, etc.  GRAYCHIP,INC. - 42 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP 5.8 DATA SHEET REV 1.0 RESAMPLER CONTROL PAGE (PAGE 64) This page controls the resampler. The address assignments are: Table 17: Resampler Control Registers ADDRESS NAME DESCRIPTION 16 N-channels Sets the number of channels and filters 17 N-Multiplies Sets the number of multiplies per output 18 Filter Select Maps channels to filter sets 19 Final Shift Sets the final gain shift 20 Channel Map Maps channels to outputs 21 Add To Adds channel outputs together 22 Clock Divide Divides the clock to the resampler 23 Ratio Map Maps ratios to output channels 24-31 Unused ADDRESS 16: N-Channels Out Register, Suggested default = 0x23 BIT TYPE NAME DESCRIPTION 0-1 LSB R/W NC Must be set to NC=NCHAN-1, where NCHAN is the number of output channels to be generated. A value of NC=0 means one output channel. A value of NC=1 means two output channels. Use a value of NC=3 for either three or four output channels. A value of 2 is illegal and will produce erroneous results. 2-3 R/W NF Must be set to NF=NFILTER-1, where NFILTER is the number of resampler filters. Used to partition the resampler coefficient RAM. A value of NF=0 means one filter (normal case). A value of NF=1 means two filters. A value of NF=3 means four filters. A value of 2 is illegal. 4-6 R/W RES_SYNC The resampler is synchronized to this sync source (See Table 7). Resets the delay accumulators in all channels at the same time. 7 MSB R/W Unused ADDRESS 17: N-Multiplies Register, Suggested default = 0x0E BIT TYPE NAME DESCRIPTION 0-5 LSB R/W NM Must be set to NM=NMULT-1, where NMULT is the number of resampler multiplies. The minimum legal value is NM=5, the maximum is NM=63 but typically the maximum will be set by other constraints (see Section 3.5). In the case of a single channel output the minimum value is NM=6. 6 R/W NO_SYM_RES The resampler filter is presumed to be symmetric unless this bit is set. 7 MSB R/W Unused ADDRESS 18: Filter Select Register, Suggested default = 0x00 BIT TYPE NAME DESCRIPTION 0-1 LSB R/W FILTER_SEL_0 The filter map for output channel 0. This select which of the NFILTER filters to use for this channel. Must be less than or equal to NFILTER 2-3 R/W FILTER_SEL_1 The filter map for output channel 1. 4-5 R/W FILTER_SEL_2 The filter map for output channel 2. 6-7 MSB R/W FILTER_SEL_3 The filter map for output channel 3.  GRAYCHIP,INC. - 43 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP ADDRESS 19: DATA SHEET REV 1.0 Final Shift Register, Suggested default = 0x34 BIT TYPE NAME DESCRIPTION 0-3 LSB R/W FINAL_SHIFT The final shift up applied to all output channels before rounding and outputting. Legal values are 0-15. 4-5 R/W ROUND Round the output to 12 (ROUND=0), 16 (ROUND=1), 20 bits (ROUND=2) or 24 bits (ROUND=3). Note, the data is output from the resampler in all cases as 24 bit words. Rounding is into the MSBs, unused LSBs of the 24 bit output words are not cleared. The chip’s output word size is set by BITS_PER_WORD in the output page, not by ROUND. 6 R/W TAG_22 Two bit tag mode. Replaces the 2 LSBs of the 24 bit resampler output word with the 2 LSBs of the tag words. Changes the 24 bit round mode (ROUND=3), if it is used, to be a 22 bit round mode. 7 (MSB R/W Unused ADDRESS 20: Channel Map Register, Suggested default = 0xE4 BIT TYPE NAME DESCRIPTION 0-1 LSB R/W CHAN_MAP_A The channel map for channel A. This tells the hardware which output channel the results of down converter channel A should be directed to. 2-3 R/W CHAN_MAP_B The channel map for down converter channel B. 4-5 R/W CHAN_MAP_C The channel map for down converter channel C. 6-7 MSB R/W CHAN_MAP_D The channel map for down converter channel D. This register maps down converter channels to output (resampler) channels. For most applications this will be a simple map of channel A to output channel 0, channel B to output channel 1, etc. However, for multichannel modes (see Section 3.4) such as SPLITIQ two or even four channels may be directed to the same output channel. ADDRESS 21: Add-To Register, Suggested default = 0x70 BIT TYPE NAME DESCRIPTION 0 LSB R/W ADD_A_TO_B Add down converter channel A to down converter channel B. 1 R/W ADD_B_TO_C Add down converter channel B to down converter channel C. 2 R/W ADD_C_TO_D Add down converter channel C to down converter channel D. 3 R/W ADD_D_TO_NEXT_A Not useful. Must be set to zero. 4-6 R/W RATIO_SYNC Changes to the ratio map (address 23) are synchronized to this sync source. 7 MSB R/W Unused When processing complex input signals partial results are computed in adjacent channels that must be summed together to produce a meaningful result. This control bit informs the resampler to save the data presented to it’s input and add it to the next sample presented (if the chip is properly set up this will be from the next channel). In this manner the real and imaginary portions of the input are rejoined prior to resampling. ADDRESS 22: Resampler Clock Divide Register, Suggested default = 0x00 BIT TYPE NAME DESCRIPTION 0-7 R/W RES_CLK_DIV Resampler clock division. In many applications only a small portion of the resampler computational throughput is required. Power can be reduced by dividing the clock driving the resampler. The resampler clock rate is 2*FCK/(1+RES_CLK_DIV). Caution must be used to avoid  GRAYCHIP,INC. - 44 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 dividing the clock so far that there is not enough clock cycles to complete the computations (see Section 3.5). It is recommended that an application first be brought up without resampler clock division. ADDRESS 23: Ratio Map Register Suggested default = 0x00 BIT TYPE NAME DESCRIPTION 0-1 LSB R/W RATIO_MAP_0 The ratio map for channel 0. This tells the hardware which resampler ratio should be use for output channel 0. 2-3 R/W RATIO_MAP_1 The ratio map for output channel 1. 4-5 R/W RATIO_MAP_2 The ratio map for output channel 2. 6-7 MSB R/W RATIO_MAP_3 The ratio map for output channel 3. The default ratio maps select ratio 0 for output 0, ratio 1 for output 1, ratio 2 for output 2, and ratio 3 for output 3. The ratio maps can also be used to synchronously switch between resampling ratios. This allows the chip’s resampler to be used in timing loops where the ratio must toggle between several values which have been programmed into the chip. 5.9 RESAMPLER RATIO PAGE (PAGE 65) This page stores four resampler ratios to be used by the resampler channels. Each ratio is a 32 bit ratio of the input sample rate to the output sample rate with an implicit decimal point six bits down from the top. The total range for the ratio is then 0 to 63. The hardware limits the decimation to be less than 32 (hence the MSB of the 32 bit word should always be zero). Table 18: Resampler Ratio Page 5.10 ADDRESS NAME ADDRESS NAME 16 RATIO_0 (LSBs) 24 RATIO_2 (LSBs) 17 RATIO_0 25 RATIO_2 18 RATIO_0 26 RATIO_2 19 RATIO_0 (MSBs) 27 RATIO_2 (MSBs) 20 RATIO_1 (LSBs) 28 RATIO_3 (LSBs) 21 RATIO_1 29 RATIO_3 22 RATIO_1 30 RATIO_3 23 RATIO_1 (MSBs) 31 RATIO_3 (MSBs) CHANNEL OUTPUT PAGES (PAGE 96 & 97) Addresses 16 through 31 on these pages are used to read output values. The outputs are 24 bit two’s complement numbers which are read as three 8 bit bytes. Reading address 16 will output 0 on C[0:7]. Reading address 17 will output the least significant byte. Address 18 provides the middle byte. Address 19 provides the most significant byte. If microprocessor mode is enabled, and pin P0-23 are enabled (by setting EN_P0-3, EN_PAR) the full 24 bit word is simultaneously output P[0:23].These are all read only registers. See Tables 4, 5 and 6 for the data order in these pages.  GRAYCHIP,INC. - 45 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP 5.11 DATA SHEET REV 1.0 OUTPUT CONTROL PAGE (PAGE 98) This page controls the output. The following table summarizes the registers: Table 19: Output Control Registers ADDRESS NAME DESCRIPTION 16 Tristate Controls Enables serial and parallel ports and controls. 17 Output Format Sync output. Invert SCK, SFS, and RDY. Set RDY width. Enable tags. 18 Output Mode Select serial, nibble, parallel, or uP output. Select real or complex output. Enable nibble reverse. 19 Output Frame Control Select output frame length. Control SFS behavior. 20 Output Word Sizes Select output word size, output block size, and word per frame. 21 Output Clock Control Set clock divider for serial clock. Set number of active serial outputs. 22 Serial Mux Control Route serial streams to serial ports. 23 Output Tag A Tags for outputs AI and AQ 24 Output Tag B Tags for outputs BI and BQ 25 Output Tag C Tags for outputs CI and CQ 26 Output Tag D Tags for outputs DI and DQ 27 Mask Revision Reads back the chip’s mask revision number 28 Miscellaneous Output enable for SO, four frame strobe mode control ADDRESS 16: Tristate Controls, Cleared on power up, Suggested default = (see Table 3) BIT TYPE NAME DESCRIPTION 0 (LSB) R/W EN_SCK Enable SCK output. Used in serial, nibble, LINK, and parallel modes. 1 R/W EN_RDY Enable RDY output. Used for parallel and uP modes. RDY should be enabled for the master chip in serial or nibble TDM modes. RDY should not be enabled for slave chips, or for the LINK mode. 2 R/W EN_SFS Enable SFS output. Used in serial, nibble, and parallel modes. Can be used as an interrupt in LINK mode. 3 R/W EN_P0 Enable P0. Required for serial mode when outputting on P0, LINK or Nibble modes, wide word uP, and parallel modes. 4 R/W EN_P1 Enable P1. Required for serial mode when outputting on P1, LINK or Nibble modes, wide word uP, and parallel modes. 5 R/W EN_P2 Enable P2. Required for serial mode when outputting on P2, LINK or Nibble modes, wide word uP, and parallel modes. 6 R/W EN_P3 Enable P3. Required for serial mode when outputting on P3, LINK or Nibble modes, wide word uP, and parallel modes. 7 (MSB) R/W EN_PAR Enable P4-P23. Used for parallel output and wideword uP modes. All outputs except SO and the control port (C0-7) power up into a high impedance, tristate, mode until they are enabled. The control port (C0-7) is tristate until both CE and RD are low and WR is high.  GRAYCHIP,INC. - 46 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP ADDRESS 17: DATA SHEET REV 1.0 Output Format, Suggested default = 0x40 BIT TYPE NAME DESCRIPTION 0 (LSB) R/W INV_SCK Invert SCK output. The serial, nibble, link and parallel outputs normally change on the rising edge of SCK. If INV_SCK is set high the clock is inverted so data changes on the falling edge. 1 R/W INV_RDY Invert RDY output. RDY is normally active high. This control bit is used for uP and parallel modes. It has no effect in serial, LINK, or nibble modes. 2 R/W INV_SFS Invert SFS output. SFS is normally active high. 3 R/W TAG_EN Enable tags. The four bit tags replace the four LSBs of the data when TAG_EN is set. The BITS_PER_WORD (address 20) control determines the tag location. 4 R/W RDY_WIDTH The RDY pulse is 4 (RDY_WIDTH=0) or 16 (RDY_WIDTH=1) CK cycles. Valid for the uP mode only, must be set to 0 for all other modes. 5-7 (MSB) R/W OUT_BLK_SYNC Output circuit sync source. See table 7 for the sync modes. The OUT_BLK_SYNC is used to synchronize the output timing among multiple GC4016 chips. The OUT_BLK_SYNC should only be made active during initialization. Use during operation may cause unknown output transients. ADDRESS 18: Output Mode Cleared on powerup., Suggested default = (see Table 3) BIT TYPE NAME DESCRIPTION 0 (LSB) R/W LINK Enable LINK protocol. This mode supports Analog Devices LINK protocol. In this mode the RDY pin serves as LINK Acknowledge and is an input to the GC4016 (EN_RDY must be low). NIBBLE must also be set high (eight bit LINK mode is not supported) and OUTPUT_MODE must be set to 2. The PARALLEL control bit must be low. 1 R/W NIBBLE Enable nibble mode. This mode is similar to serial except the four pins P0-3 output one nibble at a time. TDM of several chips is supported with one acting as the master (EN_RDY=MASTER=1) and the others as the slave (EN_RDY=MASTER=0). 2 R/W PARALLEL Enable parallel mode. 3 R/W MASTER Normally set high. Is set low by slave chips in TDM serial or nibble modes. The RDY pin is an output when MASTER=1, and is an input when MASTER=0. 4 R/W REAL_ONLY Normally set low. Is set high when outputting real, instead of complex, data. Normally used with the complex to real modes of the PFIR (see Section 3.3.7). 5-6 R/W OUTPUT_MODE The output mode selection is: 0 for microprocessor mode, 1 for serial mode, 2 for nibble or LINK modes, or 3 for parallel mode. Note that only one mode is supported at a time. 7 (MSB) R/W REVERSE_IQ Used when OUTPUT_ORDER=0 to swap I and Q. This is useful for link or nibble mode outputs when packing two 16 bit words into a 32 bit transfer. See Section 3.8.5.  GRAYCHIP,INC. - 47 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP ADDRESS 19: DATA SHEET REV 1.0 Output Frame Control, Suggested default = (see Table 3) BIT TYPE NAME DESCRIPTION 0-5 (LSB) R/W FRAME_LENGTH Used in the serial and nibble modes to set the frame length, and is not used in the microprocessor, link or parallel modes. Serial, nibble modes: The output frame length is (FRAME_LENGTH+1) in words (not complex pairs). The frame length must be equal or greater than the number of output words on the serial port. Values larger than the number of output words can be useful to smooth the data output rate by slowing down the output frame rate. The output frame rate must be at least as fast as the average output data rate. In the 16 bit nibble mode (BITS_PER_WORD=0), FRAME_LENGTH must be greater than or equal to one (a frame length of at least two words). If this is the master chip in a multi-chip TDM mode (FRAME_LENGTH+1) sets the TDM frame length. The master chip will occupy the first (WORDS_PER_FRAME+1) time slots of the frame. If this is a slave chip, then (FRAME_LENGTH+1) is the delay, in number of words, from the start of frame before outputting its data. Microprocessor, link or parallel modes: Unused, set to 0 6-7 (MSB) R/W SFS_MODE Used in the serial, nibble and parallel modes to set the frame strobe modes. Not used in the microprocessor or link modes. Serial mode: (See Figure 15) In the serial mode SFS is active for one SCK cycle ahead of the first bit. If SFS_MODE=0 (or = 2), then SFS is active for one SCK cycle at the start of the frame. If SFS_MODE=1, then SFS is active once for each I word. If SFC=3 then SFS is active for each word (I or Q). Link mode: The SFS behavior in the nibble mode is similar except the frame strobe occurs concurrent with the first nibble rather than 1 SCK cycle early. Parallel mode: (See Figure 16) In the parallel mode, SFS and RDY are used as flags to indicate valid output data. If SFS_MODE=0 or 1, then SFS is active for one SCK cycle when the I sample is valid and RDY is active for one SCK cycle when Q is valid. If SFS_MODE=2 or 3, then SFS is active for one SCK cycle when either I or Q are valid and RDY is a start of frame signal which is active for when the first I sample of an output block is valid (see BLOCK_SIZE address 20 and Figure 16). Note that when SFS_MODE=2 or 3 the RDY flag goes high after the last word in a frame and goes low after the first word in the next frame. Microprocessor or link modes: Unused, set to 0  GRAYCHIP,INC. - 48 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP ADDRESS 20: DATA SHEET REV 1.0 Output Word Sizes, Suggested default = (see Table 3) BIT TYPE NAME DESCRIPTION 0-2 (LSB) R/W WORDS_PER_FRAME Serial, nibble and parallel modes: The number of output words (not complex pairs) in a frame is (WORDS_PER_FRAME+1). This value should be less than or equal to the frame length. It should also be less than or equal to the number of output channels. Serial or nibble TDM modes: (WORDS_PER_FRAME+1) is the number of words THIS chip inserts into the TDM stream. Link mode: In the link mode only 32 bit transfers are understood. A single 32 bit word is transferred by setting WORDS_PER_FRAME to 0 and BITS_PER_WORD to 1. Two 16 bit words packed together in a single 32 bit transfer is done by setting WORDS_PER_FRAME to 1 and BITS_PER_WORD to 0. Microprocessor mode: Unused, set to 0. 3-5 R/W BITS_PER_WORD Sets the number of bits per word in the serial, nibble and link modes and determines the location of tag bits in all modes. Serial mode: For serial outputs the number of bits per serial word is set as 4*(BITS_PER_WORD+1), where BITS_PER_WORD ranges from 2 to 7. Values 2-5 create 12-24 bit serial outputs with tags (if enabled) in the least significant nibble. Values 6 and 7 create 28 and 32 bit outputs respectively with the last one or two nibbles zeros and tags in the sixth nibble. Nibble and link modes: For nibble and link modes the number of bits per word are 16 for BITS_PER_WORD=0 and 32 for BITS_PER_WORD=1. Tag bits replace the least significant nibble when BITS_PER_WORD=0, and replace the sixth nibble when BITS_PER_WORD=1. The least significant two nibbles are always zero when BITS_PER_WORD=1. Parallel or microprocessor modes: For parallel or uP outputs BITS_PER_WORD only affects the placement of the tag bits. The least significant four bits of the 4*(BITS_PER_WORD+1) bits are replaced. BITS_PER_WORD ranges from 2 to 5 in these modes. Note that rounding is independent and is controlled by the ROUND control in address 19 of the resampler control page. 6-7 (MSB) R/W BLOCK_SIZE Outputs are transferred from the resampler to the output in blocks of size (BLOCK_SIZE+1) complex samples (two words per sample). Values 0,1, and 3 are valid. Value 2 is mapped to be the same as 3. Synchronous serial, nibble and parallel modes: For synchronous serial, nibble and parallel outputs the block size will typically match the number of output channels. Link mode and asynchronous serial, nibble and parallel modes: For link and asynchronous outputs the block size should be minimum (BLOCK_SIZE=0). Microprocessor mode: For the microprocessor modes the BLOCK_SIZE should be 3 which will minimize the interrupt rate to one interrupt per 4 samples (real or complex).  GRAYCHIP,INC. - 49 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP ADDRESS 21: DATA SHEET REV 1.0 Output Clock Control, Suggested default = (see Table 3) BIT TYPE NAME DESCRIPTION 0-3 (LSB) R/W SCK_RATE Serial clock rate is SCK = CK/(1+SCK_RATE). SCK_RATE can be 0 to 15. If SCK_RATE=0, then the serial clock rate will be equal to CK. SCK is also the output clock for nibble and parallel modes. 4-5 R/W NSERIAL The number of serial pins used to output the data is NSERIAL+1. Values 0,1, and 3 are valid (value 2 is mapped to be the same as value 3). A value of 0 means that all outputs will be multiplexed onto one serial stream. See Figure 15(c). Must be 0 for nibble, and link modes. Unused for uP, and parallel modes. 6-7 (MSB) R/W OUTPUT_ORDER OUTPUT_ORDER is normally set to 0 which will cause the data to be output in the same order as it is computed by the resampler. If the channels are synchronous, then the order will be IA,QA,IB,QB,IC,QC,ID,QD. OUTPUT_ORDER must be set to 0 for asynchronous data. OUTPUT_ORDER equal to 1 or 2 is only valid for synchronous channel data. These modes allow channels B, C and D to be powered up and down without disturbing the channel order. Channel A can not be powered down. OUTPUT_ORDER=1 will cause the output order to be IA,IB,QA,QB,IC,ID,QC,QD. This is appropriate for complex synchronous serial data output on two streams. OUTPUT_ORDER=2 (or 3) will cause the output order to be IA,IB,IC,ID,QA,QB,QC,QD. This is appropriate for synchronous serial data output on four 4 serial streams. See Figure 15(c). ADDRESS 22: Serial Mux Control, Suggested default = 0xE4 BIT TYPE NAME DESCRIPTION 0-1 (LSB) R/W SMUX_0 Serial stream selection for serial pin P0. A four to one multiplexer allows serial streams SOUTA (SMUX_0=0), SOUTB (SMUX_0=1), SOUTC (SMUX_0=2) and SOUTD (SMUX_0=3) to be routed to serial pin P0. See Figure 15 for the definition of serial streams SOUTA, SOUTB, SOUTC and SOUTD. If SMUX_0 is set to 1 in the LINK or NIBBLE output modes then the bit order within the nibble is reversed (nibble LSB will be on P3 rather than P0). This allows backwards compatibility with the GC4014 in LINK mode. 2-3 R/W SMUX_1 Serial stream selection for serial pin P1 as above. Note that the same serial stream may be routed to more than one serial pin if desired. 4-5 R/W SMUX_2 Serial stream selection for serial pin P2. 6-7 (MSB) R/W SMUX_3 Serial stream selection for serial pin P3.  GRAYCHIP,INC. - 50 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP ADDRESS 23: DATA SHEET REV 1.0 Output Tag A, Suggested default = 0x10 BIT TYPE NAME DESCRIPTION 0-3 (LSB) R/W TAG_AI Four bit tag for serial stream A, I word. 4-7 (MSB) R/W TAG_AQ Four bit tag for serial stream A, Q word. ADDRESS 24: Output Tag B, Suggested default = 0x32 BIT TYPE NAME DESCRIPTION 0-3 (LSB) R/W TAG_BI Four bit tag for serial stream B, I word. 4-7 (MSB) R/W TAG_BQ Four bit tag for serial stream B, Q word. ADDRESS 25: BIT Output Tag C, Suggested default = 0x54 TYPE NAME DESCRIPTION 0-3 (LSB) R/W TAG_CI Four bit tag for serial stream C, I word. 4-7 (MSB) R/W TAG_CQ Four bit tag for serial stream C, Q word. ADDRESS 26 BIT Output Tag D, Suggested default = 0x76 TYPE NAME DESCRIPTION 0-3 (LSB) R/W TAG_DI Four bit tag for serial stream D, I word. 4-7 (MSB) R/W TAG_DQ Four bit tag for serial stream D, Q word. Note: in the real output mode (REAL_ONLY=1), only the Q tags will be used. ADDRESS 27: Mask Revision, Read Only BIT TYPE NAME DESCRIPTION 0-7 R REVISION Mask revision number. This address allows the user to read the current mask revision code from software. See Section 3.16 for details. ADDRESS 28 Miscellaneous Controls, Suggested default = 0x02, Cleared by power up. BIT TYPE NAME DESCRIPTION 0 (LSB) R/W EN_4_FS Enables the four frame strobe mode. The four frame strobe mode is used with asynchronous serial or nibble data to identify words from each channel. TAG_22 in address 19 of the resampler control page must also be set. The two LSBs of the tag words are used to generate the frame strobes. The output timing of the frame strobes are the same as for SFS. If the Tag is 0, then a copy of SFS is output as FSA, if the tag is 1, then a copy of SFS is output on FSB, if the tag is 2 then a copy of SFS is output on FSC, and if the tag is 3, then a copy of SFS is output on FSD. 1 R/W EN_SO The output enable control for SO 3-7 (MSB) R/W unused  GRAYCHIP,INC. - 51 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 THIS PAGE IS INTENTIONALLY BLANK  GRAYCHIP,INC. - 52 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP 6.0 SPECIFICATIONS 6.1 ABSOLUTE MAXIMUM RATINGS DATA SHEET REV 1.0 Table 20: Absolute Maximum Ratings CAUTION: Exceeding the absolute maximum ratings (min or max) may cause permanent damage to the part. These are stress only ratings and are not intended for operation. PARAMETER SYMBOL MIN MAX UNITS Pad Ring Supply Voltage VPAD -0.3 4.1 V Core Supply Voltage V CORE -0.3 3.0 V Input voltage (undershoot and overshoot) V IN -0.5 VPAD+0.5 V Storage Temperature TSTG -65 150 Junction Temperature under operation TJ °C °C °C 125 Lead Soldering Temperature (10 seconds) NOTES 300 1 ESD Classification Class 3A Human Body Model (4 kV) (JESD22-A114-B) Class 4 Charged Device Model (1 kV) (JESD22-C101-A) Moisture Sensitivity Class 2 1. The circuit is designed for junction temperatures up to 125C. Sustained operation above 125C junction temperature will reduce long term reliability. 6.2 RECOMMENDED OPERATING CONDITIONS Table 21: Recommended Operating Conditions PARAMETER SYMBOL MIN MAX UNITS NOTES Pad Ring Supply Voltage VPAD 3.0 3.6 V 1 Core Supply Voltage V CORE 2.3 2.7 V 1 Temperature Ambient, no air flow TA -40 +85 Junction Temperature TJ °C °C 100 1 2 1. DC and AC specifications in Tables 23 and 24 are production tested over these ranges. 2. Thermal management may be required for full rate operation, See Table 22 below and Section 7.4. 6.3 THERMAL CHARACTERISTICS Table 22: Thermal Data 160 PBGA THERMAL CONDUCTIVITY SYMBOL UNITS 0.5 Watt Theta Junction to Ambient Theta Junction to Case θJA θJC 1 Watt TBD: Estimated at 32 TBD TBD °C/W °C/W Note: Air flow will reduce θja and is highly recommended.  GRAYCHIP,INC. - 53 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP 6.4 DATA SHEET REV 1.0 POWER CONSUMPTION The maximum power consumption is a function of the operating mode of the chip. The following equation estimates the typical power supply current for the chip. Chip to chip variation is typically +/- 5%. Table 24 provides maximum current in a maximum configuration used in production test. o u t I PAD (TYP) = ( V PAD )  F ------- ( N o u t ) ( C o u t + 2pF )  4  V CORE FCK  225 23  I CORE (TYP) =  -------------  ---------- + ------ mA  2.5   80M 10 + A  31 + -------N R Where A is the number of active channels (0 to 4), N is the CIC decimation ratio, R is the resampler clock division, Fout is the output SCK rate, Nout is the number of active output data pins , and Cout is the average capacitive load on each data pin. The equation assumes random data transition density of 1 rising edge per four SCK cycles. 6.5 DC CHARACTERISTICS Table 23: DC Operating Conditions (-40 to 85 °C case unless noted) VPAD = 3.0 to 3.6V PARAMETER MIN Voltage input low VIL Voltage input high VIH Voltage output low (IOL = 2mA) VOL Voltage output high (IOH = -2mA) VOH Leakage current (V IN = 0V or VPAD) Inputs or Outputs in tristate condition UNITS TEST LEVEL V IV V IV V IV V IV 1 uA IV 35 uA IV 2 mA IV SYMBOL MAX 0.8 2.0 0.5 2.4 IIN Pullup current (VIN = 0V) (TDI, TMS, TCK) | I PU | 5 Quiescent supply current, I CORE or IPAD (V IN=0 or V IN=VPAD, Address 0 = F0, DIFF_IN=0) ICCQ Data input capacitance (All inputs except CK) CIN 4 (typical) pF I Clock input capacitance (CK input) CCK 13 (typical) pF I Notes: Currents are measured at nominal voltages, high temperature (85C). Voltages are measured at low speed. Output voltages are measured with the indicated current load Test Levels: I. Controlled by design and process and not directly tested or recommended practice. II. Verified on initial part evaluation. III. 100% tested at room temperature, sample tested at hot and cold. IV. 100% tested at hot, sample tested cold. V. 100% tested at hot and cold.  GRAYCHIP,INC. - 54 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP 6.6 DATA SHEET REV 1.0 AC CHARACTERISTICS Table 24: AC Characteristics (-40 TO +85oC Case, across recommended voltage range, unless noted) PARAMETER Clock Frequency Clock low or high period SYMBOL MIN MAX UNITS TEST LEVEL FCK Note 1 100 MHz IV tCKL/H 3 ns IV 70 % II 2 ns I Clock Duty Cycle (t CKH as a percentage of the clock period) Clock rise and fall times (VIL to VIH ) tRF Input setup before CK goes high (AIN, BIN, CIN, DIN, or SI) Single ended tSU 2 ns IV Input hold time after CK goes high tHD 0.8 ns IV Data output delay from rising edge of CK. (P[0:23], SFS, SCK, RDY, or SO) tDLY 1 5 ns IV Data output skew from rising edge of SCK. (P[0:23], SFS, or RDY) tSKEW -2.5 2.5 ns IV JTAG Clock Frequency FJCK 40 MHz IV JTAG Clock low period (Below VIL) tJCKL 10 ns IV JTAG Clock high period (Above V IH) tJCKH 10 ns IV JTAG Input (TDI or TMS) setup before TCK goes high tJSU 1 ns IV JTAG Input (TDI or TMS) hold time after TCK goes high tHD 10 ns IV JTAG output (TDO) delay from rising edge of TCK. tDLY ns IV Control setup during reads or writes.See Figures 2 and 3. tCSU 2 ns IV tEWCSU 4 ns IV tCHD 1 ns IV Control strobe (CS and WR low) pulse width (Write operation). See Figures 2 and 3. tCSPW 20 ns IV Control output delay CS and RD low and A stable to C (Read Operation). See Figures 2 and 3. tCDLY 12 ns IV Control recovery time between reads or writes. See Figures 2 and 3. tREC 20 ns I Core dynamic supply current nominal voltages, 100 MHz, 4 channels active, resampler at full speed, high temperature. ICDYN 390 mA IV Control data setup during writes (edge mode). See Figure 3. Control hold during writes. See Figures 2 and 3. 10 100 Notes: 1. The minimum clock rate must satisfy FCK/(4N) > 10KHz, where N is the CIC decimation ratio. 2. Timing between signals is measured from mid-voltage (VPAD/2) to mid-voltage. Output loading is a 50 Ohm transmission line. Test Levels: I. Controlled by design and process and not directly tested or recommended practice. II. Verified on initial part evaluation. III. 100% tested at room temperature, sample tested at hot and cold. IV. 100% tested at hot, sample tested cold. V. 100% tested at hot and cold.  GRAYCHIP,INC. - 55 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 7.0 APPLICATION NOTES 7.1 POWER AND GROUND CONNECTIONS The GC4016 chips are very high performance chips which require solid power and ground connections to avoid noise on the VCORE, V PAD and GND pins. If possible the GC4016 chip should be mounted on a circuit board with dedicated power and ground planes and with at least two decoupling capacitors (0.01µf) adjacent to each side of the chip, one for VCORE and one for VPAD. IMPORTANT THE GC4016 CHIP MAY NOT OPERATE PROPERLY IF THESE POWER AND GROUND GUIDELINES ARE VIOLATED. 7.2 STATIC SENSITIVE DEVICE The GC4016 chips are fabricated in a high performance CMOS process which is sensitive to the high voltage transients caused by static electricity. These parts can be permanently damaged by static electricity and should only be handled in static free environments. See Table 20. 7.3 MOISTURE SENSITIVE PACKAGE The GC4016 come in level 2 moisture sensitive packages. Dry pack storage is required prior to assembly. If parts are stored out of dry pack for more than 72 hours, then parts must be baked for 24 hours at 100°C prior to assembly. 7.4 THERMAL MANAGEMENT The parameters in Section 6.0 are tested at a case temperature of 100°C. In any case, the junction temperature must be kept below 125 °C for reliable operation. To determine the junction temperature, the user should calculate the chip’s power dissipation using the equation for supply current in Section 6.4 and then use the package’s thermal conductivity shown in Section 6.3. The junction temperature is calculated by adding the operating ambient temperature (or case temperature) to the product of the power consumption times the thermal conductivity. For example, the GC4016 chip operating in the GSM mode described in Section 7.9, consumes 0.3 Watts of power. The junction to ambient rise of the PBGA160 package is 32 degrees (TBD) per Watt. This represents a rise of 10 degrees over ambient. This means that under these conditions the ambient temperature has to be less than 90°C to keep the junction temperature below 100°C. Air flow will decrease the thermal resistance by 10% to 40%, allowing ambient temperatures up to 96°C. Increasing the decimation ratio (N) or decreasing the number of active channels (A) will also allow a higher ambient temperature.  GRAYCHIP,INC. - 56 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP 7.5 DATA SHEET REV 1.0 EXAMPLE CFIR FILTER SETS The CFIR filter must be flat over the output passband of interest, and have a stopband which rejects out of band signals which will fall into the passband of interest. The spectral requirements of this filter are shown in Figure 10 in Section 3.3.5. The CFIR filter must also compensate for the passband roll off of the CIC filter. The following filters compensate for the CIC roll off and provide passband bandwidths which are between 17% and 150% of the down converter’s output sample rate (the PFIR output rate before resampling). The filter taps can be copied from this table, or requested by e-mail from tech-support@graychip.com, or downloaded from the web at www.graychip.com. The filter taps are available in two file formats. The first, .taps, is an ascii listing of the taps. The second, .cmd, is a command file which could be used to write the filter taps into a GC4016 chip. The commands are formatted as “write ,” where and are unsigned hex integers. The recommended default filter is cfir_80 which is flat out to 80% of the channel output’s usable bandwidth. The narrower filters have less ripple and better out of band rejection. The wider filters (100% and 150%) are designed for the single wideband output per chip mode where all four channels are used as one wideband channel. These modes have more ripple and less out of band rejection than the narrowband filters. Table 25: Example CFIR Filters Name Usable Output Bandwidth Passband Passband Stopband Stopband CFIR Gain Ripple Cutoff Start Rejection (CFIR_SUM) (pk to pk) Applications Taps (first 11) cfir_17 17% 0.085 0.01dB 1.5 110dB 2.0413 (133781) 8x oversampled outputs. 5 39 -166 -1301 -3009 -2848 1280 9009 18952 28546 32767 cfir_34 34% 0.17 0.01dB 1.5 110dB 1.5429 (101113) 4x oversampled outputs, -24 74 494 548 -977 -3416 2X GSM or EDGE outputs -3672 1525 13074 26547 32767 cfir_68 68% 0.34 0.02dB 1.55 100dB 1.2665 (83001) 2x oversampled outputs, 12 -93 -62 804 1283 -1273 1X GSM or EDGE outputs -5197 -3512 8332 24823 32767 cfir_80 (default) 80% 0.4 0.025dB 1.5 100dB 0.9899 (64877) 1.5x oversampled outputs, Default filter for most applications cfir_100 100% 0.5 0.08dB 1.5 100dB 0.9109 (59695) Single wideband DDC -3 40 -75 -437 291 1951 -489 mode (See Section 3.4.2) -6365 -1185 19736 32767 cfir_150 150% 0.75 0.6dB 1.25 60dB 0.9154 (59993) Single wideband DDC 47 -102 -1184 -1274 1487 3243 mode (See Section 3.4.2) -1798 -7760 15 20939 32767 5 -8 -172 -192 806 1493 -1889 -6182 1085 21109 32767 Key: The Usable Output Bandwidth is the passband bandwidth expressed as a percentage of the DDC channel output sample rate. The Passband Cutoff frequency is relative to the DDC channel output sample rate. The Stopband Start frequency is relative to the DDC channel output sample rate. The Taps are the first 11 taps of the 21 tap filter. The final 10 taps are a mirror image of the first 10 taps. The center taps are scaled to the full scale positive value of 32767. The Gain is CFIR_SUM/65536, the value in parenthesis is the CFIR_SUM  GRAYCHIP,INC. - 57 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP 7.6 DATA SHEET REV 1.0 EXAMPLE PFIR FILTER SETS The spectral requirements of the PFIR filter are shown in Figure 11 in Section 3.3.6. The filters in Table 26 provide passband bandwidths which are between 17% and 150% of the down converter channel output sample rate (before resampling). The filter taps can be copied from this table, or requested by e-mail from tech-support@graychip.com, or downloaded from the web at www.graychip.com. The filter taps are available in two file formats. The first, .taps, is an ascii listing of the taps. The second, .cmd, is a command file which could be used to write the filter taps into a GC4016 chip. The commands are formatted as “write ”, where and are unsigned hex integers. Table 26: Default PFIR Filters Name Usable Output Bandwidth Passband Stopband Passband Stopband Ripple Rejection PFIR Gain Applications Cutoff Start (pk to pk) near/far pfir_17 17% 0.085 0.01dB 0.125 97dB/ 120dB 3.1262 (204881) 8x oversampled outputs. 6 17 33 49 54 33 -28 -132 -263 -380 -424 -329 -49 408 964 1461 1690 1445 597 -826 -2589 -4252 -5228 -4908 -2819 1222 7006 13910 20982 27118 31289 32767 pfir_34 34% 0.17 0.02dB 0.3 83dB/ 108dB 2.2370 (146605) 4x oversampled outputs, 2X GSM or EDGE outputs 14 30 41 27 -29 -118 -200 -212 -95 150 435 598 475 5 -680 -1256 -1330 -653 669 2112 2880 2269 101 -2996 -5632 -6103 -3091 3666 13042 22747 30053 32767 pfir_68 68% 0.34 0.015dB 0.5 90dB/ 98dB 1.2140 (79563) 2x oversampled outputs, 1X GSM or EDGE outputs 2 1 -11 -23 -2 45 43 -48 -117 -8 191 155 -189 -375 26 579 358 -601 -918 248 1469 618 -1680 -1995 1104 3690 845 -5354 -5506 6574 24277 32767 pfir_80 80% 0.4 0.15dB 0.5 78dB/ 93dB 1.1494 (75329) 1.5x oversampled outputs, Default filter for most applications 31 136 208 107 -123 -181 69 277 46 -353 -235 358 483 -246 -750 -24 967 470 -1046 -1081 884 1817 -360 -2608 -689 3365 2594 -3992 -6527 4407 23277 32767 pfir_100 100% 0.5 0.2dB 0.6 75dB/ 84dB 0.9189 (60221) Single wideband DDC mode (See Section 3.4.2) -30 -141 -180 2 151 -34 -186 87 232 -171 -273 293 292 -458 -270 668 181 -916 4 1192 -325 -1479 837 1758 -1647 -2005 3015 2201 -5914 -2326 19169 32767 pfir_150 150% 0.75 0.75dB 0.82 50dB/ 65dB 0.6320 (41417) Single wideband DDC mode (See Section 3.4.2) -32 -234 98 -24 -74 165 -199 138 13 -198 329 -323 149 145 -437 577 -456 73 445 -867 955 -576 -213 1138 -1778 1706 -659 -1331 3909 -6474 8360 32767 Taps (first 32) Key: The Usable Output Bandwidth is the passband bandwidth expressed as a percentage of the DDC channel output sample rate. The Passband Cutoff frequency is relative to the DDC channel output sample rate. The Stopband Start frequency is relative to the DDC channel output sample rate. The Taps are the first 32 taps of the 63 tap filter. The final 31 taps are a mirror image of the first 31 taps. The center taps are scaled to the full scale positive value of 32767. The Gain is PFIR_SUM/65536, the value in parenthesis is the PFIR_SUM The recommended default filter is PFIR_80 which is flat out to 80% of the channel output’s usable bandwidth. The narrower filters have less ripple and better out of band rejection. The wider filters (100% and 150%) are designed for the single wideband output per chip mode where all four channels are used as one wideband channel. These modes have more ripple and less out of band rejection than the narrowband filters. The PFIR can also be used to apply receive filters for digital modulation formats such as QPSK, OQPSK or QAM. The most common receive filter is the root-raised cosine (RRC) filter. A program (written in C) designed to generate RRC pfir filters is available from graychip by e-mail or from the web. This program asks for the input sample rate, the baud rate and the desired roll off (alpha) factor. The output is a 63 tap PFIR filter tap file and a GC4016 command file.  GRAYCHIP,INC. - 58 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 cfir_17 with pfir_17 cfir_34 with pfir_34 cfir_68 with pfir_68 cfir_80 with pfir_80 cfir_100 with pfir_100 cfir_150 with pfir_150 Figure 19. Overall Spectral Responses of Example Filters  GRAYCHIP,INC. - 59 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP 7.7 DATA SHEET REV 1.0 EXAMPLE RESAMPLER CONFIGURATIONS This Section describes some commonly used resampler configurations and the filter coefficient sets used for them. 7.7.1 Bypass Mode The resampler is bypassed by using a configuration which has h0 set to 1024, all other taps set to zero, NMULT set to 7, NO_SYM_RES set to 1, FINAL_SHIFT set to 5, and RATIO set to 226 (0x04000000). Note that the NDELAY term in the RES_GAIN equation does not apply in this case and should be set to unity in the gain equation. The resampler control register setting for this mode are shown in Table 27. Table 27: Resampler Bypass Mode Address 16 17 18 Page 32 00 04 00 Pages 33-63 00 19 20 21 22 23 24 25 Page 64 23 46 00 35 E4 70 00 00 unused Page 65 00 00 00 04 00 00 00 04 00 00 26 27 28 29 30 31 00 04 00 00 00 04 7.7.2 Resampling Modes Several resampler configurations are summarized in Table 28. These configurations use the default values for the resampler controls except for NMULT in address 17, which must be set to the value in Table 28. The defaults (hex) are 23, NM, 00, 34, E4, 00, 00 and 00, respectfully for addresses 16 through 23 of page 64. NM is NMULT-1. Table 28: Resampler Modes Configuration Name NMULT %BW PB Ripple (dB) Image Rejection (dB) RES_SUM Application Configurations with NDELAY = 64, These offer the best resampling phase jitter performance (-48dB inband noise), but the % input bandwidth must be 60% or less res_6x64_60 6 res_7x64_60 7 res_8x64_60 8 res_8x64_80 60 0.18 52 134786 Use if NMULT must be 6 0.16 55 138292 Use if NMULT must be less than 8 60 0.03 62 134782 SUGGESTED DEFAULTBest 60% bandwidth mode, Adequate for most applications 80 0.7 43 139894 An 80% mode with NMULT=8 Configurations with NDELAY = 32, These offer higher % bandwidth, but fewer resampling delays (-42dB inband jitter noise) res_9x32_60 9 60 0.01 63 64700 Best 60% mode for interpolating by integer amounts res_12x32_80 12 80 0.11 48 65610 Alternate if NMULT must be less than 15 res_15x32_80 15 0.05 58 66482 Best 80% mode, Very good for interpolating by integer amounts Configurations with NDELAY = 16, These are restricted to single or dual channel modes, very good for interpolating by integer amounts. res_19x16_80 19 80 0.02 65 32988 Good filter, but only for single or dual channel modes The %BW column reflects the percentage passband of the signal relative to the sample rate going into the resampler. The resampler’s response is flat over this bandwidth to within the passband ripple indicated above. The image rejection is the amount that the resampling images are rejected relative to the signal. The filter taps for these configurations can be requested by e-mail from tech-support@graychip.com, or downloaded from the web at www.graychip.com. The filter taps are available in two file formats. The first, .taps, is an ascii listing of the taps. The second, .cmd, is a command file which could be used to write the filter taps into a GC4016 chip. The commands are formatted as “write ”, where and are unsigned hex integers.  GRAYCHIP,INC. - 60 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP 7.8 DATA SHEET REV 1.0 GC4016 CONFIGURATION GENERATOR A GC4016 configuration generator is available from Graychip in the form of a “C” program which can be obtained via email or the web. The program is described below. Usage: cmd4016 [-gc100 | -TI | -sim] where is a file containing a list of control register settings of the form: print [gc100 | TI | sim ] channel [0-3] copy_channel [0-3] cfir_coef pfir_coef res_coef where is one of the gc4016 control register fields identified in the datasheet or quick reference guide. Cmd4016 reads the file of control register settings and creates output files which summarize the control register values needed to program the chip. The program creates config_file.tbl, which contains a summary of all of the control register settings in a table format. A second file is created which is in a format suitable for programming the chip. Three formats are supported: gc100, TI, and sim. The format is either chosen on the command line, or is chosen using the “print [gc100 | TI | sim]” command. These options create config_file.gc100, config_file.ti or config_file.sim output files. The gc100 format is used by the gc100 test card interface. This format contains commands of the form: write or write_block ... The TI format is for use with the 4 bit addressing mode and contains commands of the form: The sim format is used by the “ifan” simulator and contains commands of the form: writec The “4_bit_address” mode is required in the TI mode, it is illegal in the gc100 or sim modes. A warning will be printed and the appropriate 4_bit_address mode will be forced if this is violated. cmd4016 then checks the configuration for sanity and calculates the gains throughout the chip. Example configuration files can also be provided by email, or downloaded from the web.  GRAYCHIP,INC. - 61 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP 7.9 DATA SHEET REV 1.0 EXAMPLE GSM APPLICATION This section describes how to configure the chip to downconvert GSM (or EDGE) signals and meet the stringent GSM processing specifications. The desired GSM Specifications are: Table 29: Desired GSM Specifications Specification Value Comment Clock (CK) 69.333MHz =256*270.833KHz Can be any value equal to 4NB, where N is the CIC decimation ratio and B is the GSM bit rate of 270.833KHz Input Sample Rate Same as clock rate Can be 1/2, 1/3, 1/4, ..., 1/N times the clock rate using the zero pad feature. Input Format A port, 14 Bit, 2’s Complement Can be modified as desired Spur free dynamic range > -110dB The GC4016 NCO provides more than 115 dB of spur free dynamic range Output Sample Rate 270.833KHz, complex data Can be 2X, 4X, 8X or any multiple of this rate by changing the resampler ratios Passband Width 160KHz The filter response must be flat over this bandwidth to within the passband ripple Passband Ripple < 0.1dB peak to peak To meet the GSM BER specification Stopband Rejection Set by GSM Specification See the GSM adjacent channel and blocker mask in Figure 20 Output Format Four serial streams, 24 bit I and Q data Can be modified as desired 7.9.1 GSM Filter Response Figure 20 shows the overall response using CFIR filter, cfir_68, and a set of PFIR coefficients tuned for GSM. The GSM out of band rejection mask is also shown. The passband ripple is less than 0.1 dB (peak to peak). The passband ripple specification for GSM is not directly specified. Instead it is specified in terms of bit error rate (BER). Trade offs between transition bandwidth and passband ripple in order to optimize the BER can easily be made by reprogramming the PFIR filter. Adjacent Band Rejection Blocker Requirements Figure 20. Frequency Response for the Example GSM Application The PFIR coefficients are: 132 182 1 -309 -330 119 560 343 -424 -834 -278 696 960 149 -916 -1132 -212 1075 1514 421 -1518 -2374 -673 2529 3817 726 -4796 -6888 -650 12967 26898 32767 These coefficients are available by e-mail or over the web as pfir_gsm.taps. The PFIR_SUM for this set of coefficients is 96277.  GRAYCHIP,INC. - 62 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 7.9.2 Oversampling Using the Resampler This example assumes the input sample rate is equal to 4*N*B, where N is the decimation in the CIC filter (See Section 5.6) and B is the GSM bit rate (270.833 KHz). The outputs are one complex sample per bit (270.833 KHz) with the resampler set to interpolate by unity (no interpolation). The output rate can be doubled or quadrupled as desired by changing the resampler ratio. The resampler uses the configuration res_8x64_60. (See Section 7.7). This configuration introduces 0.03dB of passband ripple and -62dB inband noise, neither being large enough to effect the BER. The resampler ratio for one sample per bit (270.833KHz) is 0x04000000. It is 0x02000000 for two samples per bit (541.666KHz) and it is 0x010000000 for four samples per bit (1.08333MHz). 7.9.3 Gain The example configuration assumes a CIC decimation of N=64, which corresponds to an ADC clock rate (CK) of 69.333248 MHz. The values of SCALE and BIG_SCALE must be chosen to satisfy: ( SHIFT + SCALE + 6 × BIG_SCALE ) ≤ ( 62 – 5log2 N ) . N is 64 and SHIFT is 4, so ( SCALE + 6 × BIG_SCALE ) ≤ 28 , which is satisfied by setting SCALE=4 and BIG_SCALE=4. If other values of N are chosen, then SCALE and BIG_SCALE need to be modified as necessary. The overall gain is adjusted using FINE_GAIN and FINAL_SHIFT. The overall gain is:  5 ( SHIFT + SCALE + 6 × BIG_SCALE – 62 )  COARSE CFIR_SUM PFIR_SUM FINE_GAIN FINAL_SHIFT 1 RES_SUM -)(2 - ) ( -------------------GAIN =  ( --------------------) ( ------------------) )N 2 ) ( -----------------) ( --------------------------------------------( 2 32768 × NDELAY NZEROS + 1 65536 65536 1024   where NZEROS=0, N=64, SHIFT=4, SCALE=4, BIG_SCALE=4, COARSE=0, CFIR_SUM=83001, PFIR_SUM=96277, RES_SUM=134782 and NDELAY=64. Because of the loss of 1/2 when converting real data to complex, the desired gain is 2.0. This can be achieved by setting FINE_GAIN to 1070 and FINAL_SHIFT equal to 4. 7.9.4 GSM Configuration The control register settings for this example are shown in table 30. It is assumed that output pin SO is tied to input pin SIA. Table 30: Example GSM Configuration Global Registers Address 0 1 2 3 4 5 6 7 F8 00 00 - 27 DC 00 00 After configuration set address 0 to 08, then set address 5 to 5C Paged Registers Address CH A CH B CH C CH D RES OUT 16 17 18 19 20 Pages 0,1 Load CFIR coefficients: cfir_68.taps Pages 2-5 Load PFIR coefficients: pfir_gsm.taps Page 6 00 00 FREQ Page 7 0C 77 00 Pages 8.9 Load CFIR coefficients: cfir_68.taps Pages 10-13 Load PFIR coefficients pfir_gsm.taps 21 22 3F 70 3F 70 3F 70 3F 70 23 24 25 26 27 28 29 30 31 64 00 00 00 00 1D - 2E 04 64 00 00 00 00 1D - 2E 04 64 00 00 00 00 1D - 2E 04 64 00 00 00 00 1D - 2E 04 00 00 04 unused 20 22 Page 14 00 00 FREQ Page 15 0C 77 00 unused Pages 16,17 Load CFIR coefficients: cfir_68.taps Pages 18-21 Load PFIR coefficients: pfir_gsm.taps 20 22 Page 22 00 00 FREQ Page 23 0C 77 00 unused Pages 24,25 Load CFIR coefficients: cfir_68.taps Pages26-29 Load PFIR coefficients: pfir_gsm.taps 20 22 Page 30 00 00 FREQ Page 31 0C 77 00 unused Page 32-63 Load resampler coefficients: res_8x64_60.taps 20 22 Page 64 23 07 00 34 E4 00 00 00 unused Page 65 00 00 00 04 00 00 00 04 00 00 00 04 00 Page 98 7F 40 28 01 E9 B0 E4 10 32 54 76 02 unused  GRAYCHIP,INC. - 63 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP 7.10 DATA SHEET REV 1.0 EXAMPLE IS-136 DAMPS APPLICATION This section describes how to configure the chip to downconvert DAMPS signals, apply the root-raised-cosine receive filter, and output samples at two times, four times or eight times the DAMPS symbol rate. The desired DAMPS Specifications are: Table 31: Desired DAMPS Specifications Specification Value Comment Clock (CK) 62.208MHz =8*320*24.3KHz Can be any value equal to 8NB, where N is the CIC decimation ratio and B is the DAMPS symbol rate of 24.3KHz Input Sample Rate Same as clock rate Can be 1/2, 1/3, 1/4, ... 1/N of the clock rate by using the zero pad feature. Input Format A port, 14 Bit, 2’s Complement Can be modified as desired Spur free dynamic range > -110dB The GC4016 NCO provides more than 115 dB of spur free dynamic range Output Sample Rate 48.6KHz, complex data (2X) Can be 4X, 8X or any multiple of the symbol rate by changing the resampler ratios Passband Response RRC with alpha=0.35 Matches the required receive filter Stopband Rejection Set by DAMPS Specification See the DAMPS rejection mask in Figure 21 Output Format Four serial streams, 24 bit I and Q data Can be modified as desired 7.10.1 DAMPS Filter Response Figure 21 shows the overall response using CFIR filter, cfir_68, and a set of RRC PFIR coefficients tuned for 2X oversampled output data. The DAMPS out of band rejection mask is also shown. Rejection Mask Figure 21. Frequency Response for the Example DAMPS Application The RRC PFIR coefficients are: -12 -117 -113 8 127 112 -38 -175 -134 82 275 224 -71 -348 -307 61 398 286 -286 -761 -442 766 1954 1708 -660 -4042 -5641 -2533 6187 18177 28625 32767 These coefficients are available by e-mail or over the web as pfir_damps_2x.taps. The PFIR_SUM for this set of coefficients is 119387. 7.10.2 Oversampling Using the Resampler This example assumes the input sample rate is equal to 8*N*B, where N is the decimation in the CIC filter (See Section 5.6) and B is the DAMPS symbol rate (24.3 KHz). The outputs are two complex samples per symbol (48.6 KHz) with the resampler set to interpolate by unity (no interpolation). The output rate can be doubled or quadrupled as desired by changing the resampler  GRAYCHIP,INC. - 64 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 ratio. The resampler uses the configuration res_15x32_80. (See Section 7.7). This configuration introduces 0.05dB of passband ripple and -58dB inband noise, neither being large enough to effect the BER. The resampler ratio for two samples per symbol (48.6KHz) is 0x04000000, for four samples per symbol (97.2KHz) is 0x02000000, and for eight samples per symbol (194.4KHz) is 0x01000000. 7.10.3 Gain The example configuration assumes a CIC decimation of N=320, which corresponds to an ADC clock rate (CK) of 62.208 MHz. The values of SCALE and BIG_SCALE must be chosen to satisfy: ( SHIFT + SCALE + 6 × BIG_SCALE ) ≤ ( 62 – 5log2 N ) . N is 320 and SHIFT=4, so ( SCALE + 6 × BIG_SCALE ) ≤ 16.4 , which is satisfied by setting SCALE=4 and BIG_SCALE=2. If other values of N are chosen, then SCALE and BIG_SCALE need to be modified as necessary. The overall gain is adjusted using FINE_GAIN and FINAL_SHIFT. The overall gain is:  5 ( SHIFT + SCALE + 6 × BIG_SCALE – 62 )  COARSE CFIR_SUM PFIR_SUM FINE_GAIN FINAL_SHIFT 1 RES_SUM GAIN =  ( --------------------)N 2 ) ( ------------------) ( ------------------ ) ( -------------------) ( --------------------------------------------)(2 ) ( 2 32768 × NDELAY NZEROS + 1 65536 65536 1024   where NZEROS=0, N=320, SHIFT=4, SCALE=4, BIG_SCALE=2, COARSE=0, CFIR_SUM=83001, PFIR_SUM=119387, RES_SUM=66554 and NDELAY=32. Because of the loss of 1/2 when converting real data to complex, the desired gain is 2.0. This can be achieved by setting FINE_GAIN to 1147 and FINAL_SHIFT equal to 4. 7.10.4 DAMPS Configuration The control register settings for this example are shown in table 32. It is assumed that output pin SO is tied to input pin SIA. Table 32: Example DAMPS Configuration Global Registers Address 0 1 2 3 4 5 6 7 F8 00 00 - 27 DC 00 00 After configuration set address 0 to 08, then set address 5 to 5C Paged Registers Address CH A CH B CH C CH D RES OUT 16 17 18 19 20 21 Pages 0,1 Load CFIR coefficients: cfir_68.taps Pages 2-5 Load PFIR coefficients: pfir_damps_2x.taps Page 6 00 00 FREQ Page 7 0C 77 00 Pages 8.9 Load CFIR coefficients: cfir_68.taps Pages 10-13 Load PFIR coefficients pfir_damps_2x.taps 22 23 24 25 26 27 28 29 30 31 54 00 00 00 00 1D - 7B 04 54 00 00 00 00 1D - 7B 04 54 00 00 00 00 1D - 7B 04 54 00 00 00 00 1D - 7B 04 00 00 04 unused 20 22 3F Page 14 00 00 FREQ Page 15 0C 77 00 Pages 16,17 Load CFIR coefficients: cfir_68.taps Pages 18-21 Load PFIR coefficients: pfir_damps_2x.taps 71 unused 20 22 3F Page 22 00 00 FREQ Page 23 0C 77 00 Pages 24,25 Load CFIR coefficients: cfir_68.taps Pages26-29 Load PFIR coefficients: pfir_damps_2x.taps 71 unused 20 22 3F Page 30 00 00 FREQ Page 31 0C 77 00 Page 32-63 Load resampler coefficients: res_15_32_80.taps 71 unused 20 22 3F 71 Page 64 23 0E 00 34 E4 00 00 00 unused Page 65 00 00 00 04 00 00 00 04 00 00 00 04 00 Page 98 7F 40 28 01 D9 B1 E4 10 32 54 76 02 unused  GRAYCHIP,INC. - 65 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP 7.11 DATA SHEET REV 1.0 EXAMPLE IS-95 NB-CDMA APPLICATION This section describes how to configure the chip to downconvert IS-95 NB-CDMA signals and output samples at two times (2X), four times (4X) or eight times (8X) the IS-95 symbol rate of 1.2288MHz. The desired IS-95 Specifications are: Table 33: Desired IS-95 NB-CDMA Specifications Specification Value Comment Clock (CK) 58.9824MHz =48*1.2288MHz Can be any value greater than this, does not need to be a multiple of 1.2288MHz. Input Sample Rate Same as clock rate Can be 1/2, 1/3, 1/4, ... 1/N times the clock rate using the zero pad feature Input Format A port, 14 Bit, 2’s Complement Can be modified as desired Spur free dynamic range > -110dB The GC4016 NCO provides more than 115 dB of spur free dynamic range Output Sample Rate 4.9152MHz, complex data (4X) Can be 2X or 4X multiple of the symbol rate by changing the resampler ratio. Can be 8X by using the dual channel mode. Passband Width 615kHz 1.25MHz signal spacing Passband Ripple 0.4 dB Stopband Rejection 50 dB at 750kHz, 87dB at 900kHz offset Far band rejection > 120dB Output Format Parallel output, 24 bit I and Q data Can be modified as desired, allows simple AGC in an FPGA or ASIC to 4 or 6 bits. 7.11.1 IS-95 Filter Response Figure 22 shows the overall response when the channel decimates to 1.5 times the baud rate. This uses the CFIR filter, cfir_68, and the PFIR filter pfir_is95_1.5x. The passband ripple is less than 0.4 dB (peak to peak). 750 kHZ 900 kHz 615 kHz -87 dB Figure 22. Frequency Response for the Example IS95 Application The PFIR coefficients are: -4 -45 -166 -349 -452 -299 96 420 302 -225 -612 -321 471 881 267 -866 -1191-64 1461 1516 -388 -2351 -1826 1303 3804 2088 -3358 -6915 -2266 11185 26207 32767 These coefficients are available by e-mail or over the web as pfir_is95_1.5x.taps. The PFIR_SUM for this set of coefficients is 89373.  GRAYCHIP,INC. - 66 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 7.11.2 Oversampling Using the Resampler This example assumes the input sample rate is equal to 6*N*B, where N is the decimation in the CIC filter (See Section 5.6) and B is the IS95 symbol rate (1.2288 MHz). The PFIR filter output rate is 1.5 samples per symbol (1.5X). The outputs are two complex samples per symbol (2.4576 MHz) if the resampler is set to interpolate by 4/3. The output rate can be 4X or 8X as desired by changing the resampler ratio. The resampler uses the configuration res_6x64_60. (See Section 7.7). This configuration introduces -58dB inband noise, not enough to effect the BER. The spectral effect of the resampler is included in Figure 22. The resampler ratio for two samples per symbol (2.4576MHz) is 0x03000000, for four samples per symbol (4.9152MHz) it is 0x01800000, and for eight samples per symbol (9.8304MHz) it is 0x00C00000. Note that the resampler can only handle two channels at eight samples per symbol. Sample rates other than 6*N*B can be accepted. To use these rates one needs to customize the PFIR filter to match the bandwidth when the sample rate has been decimated by 4*N, and then the resampling ratio needs to be adjusted to match the desired output rate. Call Graychip for details. 7.11.3 Gain The example configuration assumes a CIC decimation of N=8, which corresponds to an ADC clock rate (CK) of 58.9824MHz. The values of SCALE and BIG_SCALE must be chosen to satisfy: ( SHIFT + SCALE + 6 × BIG_SCALE ) ≤ ( 62 – 5log2 N ) . N is 8 and SHIFT=4, so ( SCALE + 6 × BIG_SCALE ) ≤ 43 , which is satisfied by setting SCALE=1 and BIG_SCALE=7. If other values of N are chosen, then SCALE and BIG_SCALE need to be modified as necessary. The overall gain is adjusted using FINE_GAIN and FINAL_SHIFT. The overall gain is:  5 ( SHIFT + SCALE + 6 × BIG_SCALE – 62 )  COARSE CFIR_SUM PFIR_SUM FINE_GAIN FINAL_SHIFT 1 RES_SUM -)(2 - ) ( -------------------GAIN =  ( --------------------) ( ------------------) )N 2 ) ( -----------------) ( --------------------------------------------( 2 32768 × NDELAY NZEROS + 1 65536 65536 1024   where NZEROS=0, N=8, SHIFT=4, SCALE=1, BIG_SCALE=7, COARSE=0, CFIR_SUM=83001, PFIR_SUM=89373, RES_SUM=134786 and NDELAY=64. Because of the loss of 1/2 when converting real data to complex, the desired gain is 2.0. This can be achieved by setting FINE_GAIN to 1153 and FINAL_SHIFT equal to 4.  GRAYCHIP,INC. - 67 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 7.11.4 IS95 NB-CDMA Configuration The control register settings for this example are shown in table 34. It is assumed that output pin SO is tied to input pin SIA. Table 34: Example IS95 NB-CDMA Configuration Global Registers Address 0 1 2 3 4 5 6 7 F8 00 00 - 27 DC 00 00 After configuration set address 0 to 08, then set address 5 to 5C Paged Registers Address CH A CH B CH C CH D RES OUT 16 17 18 19 20 21 Pages 0,1 Load CFIR coefficients: cfir_68.taps Pages 2-5 Load PFIR coefficients: pfir_is95_1.5x.taps Page 6 00 00 FREQ Page 7 0C 77 22 Pages 8.9 Load CFIR coefficients: cfir_68.taps Pages 10-13 Load PFIR coefficients pfir_is95_1.5x.taps 22 23 24 25 26 27 28 29 30 31 79 00 00 00 00 1D - 81 04 79 00 00 00 00 1D - 81 04 79 00 00 00 00 1D - 81 04 79 00 00 00 00 1D - 81 04 00 80 01 unused 20 22 07 Page 14 00 00 FREQ Page 15 0C 77 22 Pages 16,17 Load CFIR coefficients: cfir_68.taps Pages 18-21 Load PFIR coefficients: pfir_is95_1.5x.taps 70 unused 20 22 07 Page 22 00 00 FREQ Page 23 0C 77 22 Pages 24,25 Load CFIR coefficients: cfir_68.taps Pages26-29 Load PFIR coefficients: pfir_is95_1.5x.taps 70 unused 20 22 07 70 Page 30 00 00 FREQ Page 31 0C 77 22 unused Page 32-63 Load resampler coefficients: res_6x64_60.taps 20 22 07 70 Page 64 23 05 00 14 E4 70 00 E4 unused Page 65 00 00 80 01 00 00 80 01 00 00 80 01 00 Page 98 FF 40 6C 87 EF 00 E4 10 32 54 76 02 unused 7.12 UMTS WB-CDMA APPLICATION This section describes how to configure the chip to downconvert UMTS WB-CDMA signals and output samples at two times or four times the UMTS symbol rate. The desired UMTS Specifications are: Table 35: Desired UMTS Specifications Specification Value Comment Clock (CK) 61.44MHz =16*3.84MHz Can be any value greater than this, does not need to be a multiple of 3.84MHz. Input Sample Rate Same as clock rate May be an integer division of the clock rate (30.72MHz, 20.48MHz, etc.) Input Format A port, 14 Bit, 2’s Complement Can be modified as desired Spur free dynamic range > -80dB The GC4016 NCO provides more than 115 dB of spur free dynamic range Output Sample Rate 15.36MSPS, complex data (4X) Can be 2X or 4X multiple of the symbol rate by changing the resampler ratio. Can do two channels at 2X if the clock rate is greater than 92.16MHz. Passband Width 4.6848MHz RRC filter with alpha=0.22 give a bandwidth of 1.22*3.84MHz Passband Ripple 0.1 dB Filter gives 0.05dB passband ripple Stopband Rejection 60 dB at 5MHz, 80dB at > 5MHz offset Rejection > 80dB at 2.6MHz offset Output Format Parallel output, 16 bit I and Q data Can be modified as desired, allows simple AGC in an FPGA to 4 or 6 bits.  GRAYCHIP,INC. - 68 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 7.12.1 UMTS Filter Response Figure 23 shows the overall response using specially tuned CFIR and PFIR filters., The PFIR filter is a specially optimized root-raised-cosine 63 tap filter with an alpha of 0.22. The filter is designed to have less than -50dB of inter symbol interference (ISI) noise. 2.5MHz Figure 23. Frequency Response for the Example UMTS Application These coefficients are available by e-mail or over the web as cfir_umts.taps and pfir_umts.taps. The CFIR_SUM for cfir_umts.taps is 58827. The PFIR_SUM for pfir_umts.taps is 61821. 7.12.2 Oversampling Using the Resampler This example assumes the input sample rate is equal to 4*N*B, where N is the decimation in the CIC filter (See Section 5.6) and B is the UMTS symbol rate (3.84 MHz). The outputs are two complex samples per symbol (7.68MHz) with the resampler set to interpolate by unity (no interpolation). The output rate can be doubled or quadrupled as desired by changing the resampler ratio. The resampler uses the configuration res_8x64_60. (See Section 7.7). This configuration introduces 0.03dB of passband ripple and -62dB inband noise, neither being large enough to effect UMTS demodulation. The resampler ratio for two samples per symbol (7.68MHz) is 0x04000000 and for four samples per symbol (15.36MHz) it is 0x02000000. Sample rates other than 4*N*B can be accepted by adjusting the PFIR filter to match the desired RRC filter and by using the resampler to adjust the final sample rate to be exactly 2X or 4X the symbol rate. 7.12.3 Gain The example configuration assumes a CIC decimation of N=4, which corresponds to an ADC clock rate (CK) of 61.44 MHz. The values of SCALE and BIG_SCALE must be chosen to satisfy: ( SHIFT + SCALE + 6 × BIG_SCALE ) ≤ ( 62 – 5log2 N ) . N is 4 and SHIFT=4, so ( SCALE + 6 × BIG_SCALE ) ≤ 48 , which is satisfied by setting SCALE=5 and BIG_SCALE=7, which are their maximum values. If other values of N are chosen, then SCALE and BIG_SCALE need to be modified as necessary. The overall gain is adjusted using COARSE, FINE_GAIN and FINAL_SHIFT. The overall gain is:  5 ( SHIFT + SCALE + 6 × BIG_SCALE – 62 )  COARSE CFIR_SUM PFIR_SUM FINE_GAIN FINAL_SHIFT 1 RES_SUM -)(2 - ) ( -------------------GAIN =  ( --------------------) ( ------------------) )N 2 ) ( -----------------) ( --------------------------------------------( 2 32768 × NDELAY NZEROS + 1 65536 65536 1024   where NZEROS=0, N=4, SHIFT=4, SCALE=5, BIG_SCALE=7, COARSE=1, CFIR_SUM=58827, PFIR_SUM=61821,  GRAYCHIP,INC. - 69 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 RES_SUM=134782 and NDELAY=64. Because of the loss of 1/2 when converting real data to complex, the desired gain is 2.0. This can be achieved by setting FINE_GAIN to 2352 and FINAL_SHIFT equal to 4. 7.12.4 UMTS Configuration The control register settings for this example are shown in table 36. It is assumed that output pin SO is tied to input pin SIA. Table 36: Example UMTS Configuration Global Registers Address 0 1 2 3 4 5 6 7 F8 00 00 - 27 DC 00 00 After configuration set address 0 to 08, then set address 5 to 5C Paged Registers Address CH A CH B CH C CH D RES OUT 16 17 18 19 20 Pages 0,1 Load CFIR coefficients: cfir_umts.taps Pages 2-5 Load PFIR coefficients: pfir_umts.taps Page 6 00 00 FREQ Page 7 0C 77 22 Pages 8.9 Load CFIR coefficients: cfir_umts.taps Pages 10-13 Load PFIR coefficients pfir_umts.taps 21 22 07 70 07 70 07 70 07 70 23 24 25 26 27 28 29 30 31 7D 30 10 06 00 1D - 30 09 7D 50 10 06 00 1D - 30 09 7D 30 10 00 00 1D - 30 09 7D 50 10 00 00 1D - 30 09 00 00 02 unused 20 22 Page 14 00 C0 FREQ Page 15 0C 77 22 unused Pages 16,17 Load CFIR coefficients: cfir_umts.taps Pages 18-21 Load PFIR coefficients: pfir_umts.taps 20 22 Page 22 00 00 FREQ Page 23 0C 77 22 unused Pages 24,25 Load CFIR coefficients: cfir_umts.taps Pages26-29 Load PFIR coefficients: pfir_umts.taps 20 22 Page 30 00 C0 FREQ Page 31 0C 77 22 unused Page 32-63 Load resampler coefficients: res_8x64_60.taps 20 22 Page 64 20 07 00 14 00 70 00 00 unused Page 65 00 00 00 02 00 00 00 2 00 00 00 02 00 Page 98 FF 40 6C 80 29 01 00 10 32 54 76 02 unused  GRAYCHIP,INC. - 70 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP 7.13 DATA SHEET REV 1.0 DIAGNOSTICS The following four tables contain the diagnostic test configurations. To run the diagnostics, load the GC4016 with the configuration, set address 0 to 00 in order to clear the resets, set address 5 to 00 to release the counter, wait for the checksum to stabilize (approximately 220 clock cycles) and then read the checksum, which should match the expected value. Table 37: Diagnostic Test 1, Expected Checksum = E0 GLOBAL REGISTERS ADDRESS VALUE 0 F0 1 00 2 00 3 00 4 2D 5 1C 6 FF 7 01 PAGED REGISTERS PAGE ADDRESS 16 17 20 21 22 23 24 25 26 27 28 29 30 31 CFIR COEFFICIENT PAGES: 0,1,8,9,16,17,24,25 0,8,16,24 FF 7F 00 00 00 18 19 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1,9,17,25 00 00 00 00 00 00 PFIR COEFFICIENT PAGES: 2,3,4,5,10,11,12,13,18,19,20,21,26,27,28,29 2 3,4,5 FF 00 7F 00 00 00 FREQUENCY TUNING PAGES: 6 AA AA 56 00 00 00 00 00 00 34 12 00 67 78 45 56 23 34 00 00 30 AA AA 89 GENERAL CONTROL PAGES: 67 45 00 14 22 55 55 55 55 00 00 00 00 7,15,23,31 0C 77 55 50 55 07 70 78 00 01 RESAMPLER COEFFICIENT PAGES: 01 07 00 - 00 20 32 33-63 FF 00 07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 53 46 00 14 E4 RESAMPLER CONTROL PAGE: 50 00 E4 65 00 00 00 04 00 RESAMPLER RATIO PAGE: 00 00 04 00 00 00 04 00 00 00 04 D9 OUTPUT PAGE: E4 21 65 87 00 02 98 00 A1 6C C1 00 00 00 00 00 00 00 00 00 43 . Table 38: Diagnostic Test 2, Expected Checksum = 4C PAGED REGISTERS PAGE ADDRESS 16 17 18 19 20 CFIR COEFFICIENT PAGES: 0,1,8,9,16,17,24,25 0,8,16,24 1,9,17,25 42 2A 00 27 2C FD 01 39 93 91 21 22 23 24 25 26 27 28 29 30 31 01 41 6C FE 0B F8 A0 F5 2E FE CA 10 PFIR COEFFICIENT PAGES: 2,3,4,5,10,11,12,13,18,19,20,21,26,27,28,29 2 1C 00 AD 00 0D 00 4C FF 2A FF 51 00 9D 01 2B 01 58 B2 FD 04 CA EE FE 04 25 9E 02 FF 8B C3 03 F9 D5 9A 00 F9 A1 69 FC 00 CD 8A FB 08 5 A1 09 23 FREQUENCY TUNING PAGES: 00 6C F2 57 EE 23 FF 88 22 E2 46 4A 56 70 71 00 00 00 07 00 - 00 08 3 4 EA D5 FE FF 6 14 AA 55 AA 55 67 78 45 56 23 34 00 00 22 30 55 AA 55 AA 89 9A 67 78 45 56 00 00 GENERAL CONTROL PAGES: 7,15,23,31 0C 77 55 50 55 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 00 04 43 65 87 00 02 32 FF 07 00 00 RESAMPLER COEFFICIENT PAGES: 00 00 00 00 00 00 33-63 00 00 00 00 00 00 00 00 00 RESAMPLER CONTROL PAGE: 64 53 46 00 14 E4 50 00 E4 RESAMPLER RATIO PAGE: 65 00 00 00 04 00 00 98 00 A1 6C C1 D9 00  GRAYCHIP,INC. 00 04 OUTPUT PAGE: E4 21 - 71 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 . Table 39: Diagnostic Test 3, Expected Checksum = EF PAGED REGISTERS PAGE ADDRESS 16 17 20 21 22 23 24 25 26 27 28 29 30 31 CFIR COEFFICIENT PAGES: 0,1,8,9,16,17,24,25 0,8,16,24 0C 00 A3 FF C2 18 19 FF 24 03 03 05 07 FB B3 EB 48 F2 1,9,17,25 8C 20 F7 60 FF 7F PFIR COEFFICIENT PAGES: 2,3,4,5,10,11,12,13,18,19,20,21,26,27,28,29 2 3 02 8B 00 FF 01 F8 00 FF F5 BF FF 00 E9 9B FF 00 FE 43 FF FF 2D 89 00 FE 2B 1A 00 00 D0 43 FF 02 4 5 66 50 01 04 A7 6A FD 0E 6A 4D FC 03 F8 16 00 EB BD 7E 05 EA 6A AE 02 19 70 D5 F9 5E 35 FF F8 7F FREQUENCY TUNING PAGES: 6 AA AA 89 67 45 FF 94 45 78 89 56 67 FF FF 30 AA AA 56 GENERAL CONTROL PAGES: 94 78 FF 14 22 55 55 55 55 7,15,23,31 0C 77 55 50 55 1F 70 6A 00 00 RESAMPLER COEFFICIENT PAGES: 00 07 00 - 55 05 32 33 F7 F4 0F 0F F6 F3 0F 0F F6 F2 0F 0F F6 F1 0F 0F F5 F1 0F 0F F5 F0 0F 0F F4 EF 0F 0F F4 EE 0F 0F 34 35 EE E8 0F 0F ED E8 0F 0F EC E7 0F 0F EB E7 0F 0F EB E6 0F 0F EA E6 0F 0F E9 E6 0F 0F E9 E6 0F 0F 36 37 E5 E7 0F 0F E5 E8 0F 0F E5 E9 0F 0F E6 EA 0F 0F E6 EB 0F 0F E6 EC 0F 0F E6 ED 0F 0F E7 EE 0F 0F 38 39 F0 FF 0F 0F F1 02 0F 00 F3 04 0F 00 F5 07 0F 00 F6 9 0F 00 F8 0C 0F 00 FB 0F 0F 00 FD 12 0F 00 40 41 15 30 00 00 19 34 00 00 1C 37 00 00 1F 3B 00 00 22 3E 00 00 26 42 00 00 29 45 00 00 2D 48 00 00 42 43 4C 62 00 00 4F 65 00 00 52 67 00 00 55 69 00 00 58 6A 00 00 5B 6C 00 00 5E 6D 00 00 60 6E 00 00 44 45 6E 69 00 00 6F 67 00 00 6F 65 00 00 6F 62 00 00 6E 5F 00 00 6D 5B 00 00 6C 57 00 00 6B 53 00 00 46 47 4F 1D 00 00 4A 15 00 00 44 0D 00 00 3F 05 00 00 39 FC 00 0F 32 F3 00 0F 2C EA 00 0F 24 E0 00 0F 48 49 D7 83 0F 0F CD 78 0F 0F C3 6D 0F 0F B8 62 0F 0F AE 57 0F 0F A3 4C 0F 0F 98 41 0F 0F 8D 36 0F 0F 50 51 2C E2 0F 0E 22 DA 0F 0E 17 D3 0F 0E 0E CD 0F 0E 4 C7 0F 0E FB C1 0E 0E F2 BD 0E 0E EA B9 0E 0E 52 53 B5 B7 0E 0E B3 BB 0E 0E B1 C1 0E 0E B0 C7 0E 0E AF CE 0E 0E B0 D6 0E 0E B1 E0 0E 0E B4 EA 0E 0E 54 55 F5 79 0E 0F 02 8E 0F 0F 10 A5 0F 0F 1E BD 0F 0F 2E D6 0F 0F 3F EF 0F 0F 51 0A 0F 00 65 26 0F 00 56 57 43 4D 00 01 61 72 00 01 80 98 00 01 A0 BE 00 01 C1 E5 00 01 E3 0D 00 02 05 35 01 02 29 5D 01 02 58 59 86 D8 02 03 B0 02 02 04 D9 2D 02 04 03 57 03 04 2E 81 03 04 58 AB 03 04 83 D4 03 04 AD FD 03 04 60 61 25 50 05 06 4D 72 05 06 74 92 05 06 9B B1 05 06 C1 CF 05 06 E6 EC 05 06 0A 08 06 07 2E 23 06 07 62 63 3C D0 07 07 53 DC 07 07 6A E6 07 07 7F EE 07 07 92 F5 07 07 A4 FA 07 07 B4 FD 07 07 C3 FF 07 07 64 53 7 00 14 E4 RESAMPLER CONTROL PAGE: 50 00 E4 65 56 34 12 04 89 RESAMPLER RATIO PAGE: 67 45 02 00 89 67 05 90 68 47 04 65 87 00 02 98  GRAYCHIP,INC. 00 A1 6C C1 19 OUTPUT PAGE: 00 E4 21 - 72 - 43 August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 . Table 40: Diagnostic Test 4, Expected Checksum = 18 PAGED REGISTERS PAGE ADDRESS 16 17 20 21 22 23 24 25 26 27 28 29 30 31 CFIR COEFFICIENT PAGES: 0,1,8,9,16,17,24,25 0,8,16,24 2F 00 9A FF 60 18 19 FB 06 FB CF 05 AB 0C FA F8 B0 E1 1,9,17,25 0F 00 CB 51 FF 7F PFIR COEFFICIENT PAGES: 2,3,4,5,10,11,12,13,18,19,20,21,26,27,28,29 2 3 E0 0D FF 00 16 3A FF FF 62 49 00 01 E8 BD FF FE B6 95 FF 00 A5 91 00 00 39 4B FF FE 8A 41 00 02 4 5 38 0E FE F9 49 AA 00 06 BD 6D 01 FD 9D CD FC FA BB 45 03 0F C0 B6 FD E6 2B A8 FF 20 72 FF 04 7F 70 70 64 64 30 50 00 00 02 02 07 07 00 00 - 00 00 04 04 FREQUENCY TUNING PAGES: 6 00 00 67 45 23 01 45 56 23 34 01 02 30 00 C0 71 56 GENERAL CONTROL PAGES: 7,15,23,31 34 02 7F 7F 14 22 00 00 C0 00 67 71 7,23 15,31 0C 0C 77 77 55 55 50 50 55 55 32 FF 07 00 00 RESAMPLER COEFFICIENT PAGES: 00 00 00 00 00 00 00 00 00 00 00 00 33-63 00 00 00 00 00 00 00 00 00 RESAMPLER CONTROL PAGE: 00 00 00 00 00 00 00 64 53 46 00 14 E4 50 00 E4 RESAMPLER RATIO PAGE: 65 00 00 00 04 00 00 00 00 00 04 00 00 00 04 98 0F A8 28 C1 19 00 43 65 87 00 02 00 04 OUTPUT PAGE: E4 21 Electronic versions of these tables are available by email or from the web as diag_tests.txt. 7.14 OUTPUT TEST CONFIGURATION The output test takes advantage of the tag modes. To perform the output tests, first configure the chip according to the desired mode, and then change the configuration so that: TAG_EN=1 and FLUSH_SYNC=7 (always) in all four channels. TAG_EN turns on the tag mode, and FLUSH_SYNC clears the channels, but allows the channels to continue to operate and output zeroes. Then follow the suggested initialization sequence described in Section 3.12. This will force the output words to be zeroes with the tag bits (see addresses 23-26 in the output page) in the LSBs.  GRAYCHIP,INC. - 73 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 Graychip reserves the right to make changes in circuit design and/or specifications at any time without notice. The user is cautioned to verify that datasheets are current before placing orders. Information provided by Graychip is believed to be accurate and reliable. No responsibility is assumed by Graychip for its use, nor for any infringement of patents or other rights of third parties which may arise from its use. No license is granted by implication or otherwise under any patent rights of Graychip.  GRAYCHIP,INC. - 74 - August 27, 2001 This document contains information which may be changed at any time without notice GC4016 REGISTER ASSIGNMENT QUICK REFERENCE GUIDE. Address Global 0 Global Reset 1 Status 2 Page 3 Checksum 4 General Syncs 5 Count Sync 6 Counter Byte 0 CNT[0:7] 00 7 Counter Byte 1 CNT[7:15] 00 0,1 16-31 Name CFIR Coef 7(MSB) 6 GLOBAL_ RESET OUT_BLK_ RESET 5 4 PAD_RESET ZERO 3 RESAMPLER_ RESET CHECK_DONE EDGE_WRITE 2 1 CK_2X_EN RES_QOV CK_2X_TEST RES_IOV C H LVDS 4_BIT_ADDR ONE_SHOT OS_MODE DIAG_SYNC COUNTER_SYNC C H C H - DITHER_SYNC ZPAD_EN ZPAD_SYNC - FLUSH_SYNC A Control 20 (0x14) Dec and Flush 21 (0x15) Dec Byte 0 22 (0x16) Dec Byte 1 - 23 (0x17) CIC Scale - 24 (0x18) SplitIQ 25 (0x19) CFIR 26 (0x1A) PFIR 27 (0x1B) Input 28 (0x1C) Peak Control 29 (0x1D) Peak Count PEAK_COUNT 30 (0x1E) Fine Gain Byte 0 FINE_GAIN[0:7] 31 (0x1F) Fine Gain Byte 1 77 NCO_SYNC 22 20 22 07 MIX20B QONLY TEST DEC[8:11] BIG_SCALE IONLY SPLITIQ MSB_POL - - - PEAK_SELECT IN_FMT PEAK_MODE 79 NEG_CTL COARSE - 70 SCALE QDLY_CFIR NO_SYM_CFIR 00 IDLY_PFIR QDLY_PFIR NO_SYM_PFIR 00 PEAK_THRESHOLD - 00 IDLY_CFIR AB_SEL INPUT_SEL 00 PEAK_SYNC 1D read only 00 FINE_GAIN[8:13] 10-13 16-31 PFIR Coef 32 PFIR Coefficients for Channel B, Load LSBs in even addresses, MSBs in odd addresses 14 16,17 PHASE 16 bit channel B phase, LSBs in 16, MSBs in 17, PHASE=216P/2π 04 0000 32 bit channel B tuning frequency, LSBs in 18, MSBs in 20, FREQ = 232F/FCK 15 16-31 Channel Control See above 16,17 16-31 CFIR Coef 11 CFIR Coefficients for Channel C, Load LSBs in even addresses, MSBs in odd addresses 18-21 16-31 PFIR Coef 32 PFIR Coefficients for Channel C, Load LSBs in even addresses, MSBs in odd addresses 22 16,17 PHASE 16 bit channel C phase, LSBs in 16, MSBs in 17, PHASE=216P/2 π 00000000 0000 32 bit channel C tuning frequency, LSBs in 18, MSBs in 20, FREQ = 2 32F/FCK 23 16-31 Channel Control See above 24,25 16-31 CFIR Coef 11 CFIR Coefficients for Channel D, Load LSBs in even addresses, MSBs in odd addresses 26-29 16-31 PFIR Coef 32 PFIR Coefficients for Channel D, Load LSBs in even addresses, MSBs in odd addresses 30 16,17 PHASE 16 bit channel D phase, LSBs in 16, MSBs in 17, PHASE=216P/2 π 16-31 0C DEC_SYNC GAIN_SYNC 11 CFIR Coefficients for Channel B, Load LSBs in even addresses, MSBs in odd addresses 31 SHIFT PHASE_SYNC DEC[0:7] CFIR Coef 18,19,20,21 FREQ 0000 - 16-31 D D0 then 50 00000000 NZEROS 8,9 18,19,20,21 FREQ 00 27 DIAG_SOURCE - Zero Pad C 00 11 CFIR Coefficients for Channel A, Load LSBs in even addresses, MSBs in odd addresses 19 (0x13) 18,19,20,21 FREQ F8 then 08 See below read only OUTPUT_SYNC COUNT_TEST NCO Sync B READY CHECKSUM[0:7] 18 (0x12) Page CK_LOSS_ DETECT A3 C 32 PFIR Coefficients for Channel A, Load LSBs in even addresses, MSBs in odd addresses 2,3,4,5 16-31 PFIR Coef H 16 bit channel A phase, LSBs in 16, MSBs in 17, PHASE=216P/2π A 6 16,17 PHASE N 32 bit channel A tuning frequency, LSBs in 18, MSBs in 21, FREQ = 232F/FCK 18,19,20,21 FREQ N CH_RESET USE_SHIFT E 7 16 (0x10) Channel Reset L FREQ_SYNC 17 (0x11) Frequency Sync A Channel MISSED PAGE[0:6] 0(LSB) Suggested Default Page 00000000 0000 32 bit channel D tuning frequency, LSBs in 18, MSBs in 20, FREQ = 2 32F/FCK 00000000 Channel Control See above Power up initialization: (Assumes SO is tied to SIA) (1) Set address 0 to F8; (2) Write to all registers and coefficients; (3) Set address 5 to D0; (4) Set address 0 to 08; (5) Set address 5 to 50. SYNC MODE SYNC SOURCE 0,1 off (never asserted) 2 SIA 3 SIB 4 ONE_SHOT 5 TC (terminal count of internal counter) 6,7 on (always active) REV 1.0 August 27, 2001 GC4016 REGISTER ASSIGNMENT QUICK REFERENCE GUIDE Page R 32-63 E 64 S (0x40) A M P L E R Address 16-31 Filter Taps 7(MSB) N-Channels - 17 (0x11) N-Multiplies - 18 (0x12) Filter Select 19 (0x13) Final Shift 20 (0x14) Channel Map 21 (0x15) Add To 22 (0x16) Clock Divide 23 (0x17) Ratio Map 16-19 96,97 6 5 4 3 2 1 0(LSB) Suggested Default Resampler Coefficients, 8 LSBs in even addresses, 4 MSBs in odd addresses. (Must be loaded in the blocks 16-23 and 24-31) 16 (0x10) 65 (0x41) O 98 U (0x62) T P U T Name RES_SYNC NF=(NFILTER-1) NO_SYM_RES FILTER_SEL_2 TAG_22 CHAN_MAP_D FILTER_SEL_0 00 CHAN_MAP_A E4 FINAL_SHIFT CHAN_MAP_C RATIO_SYNC 46 FILTER_SEL_1 ROUND (12B,16B, 20B,24B) - 23 NM=(NMULT-1) FILTER_SEL_3 - Bypass NC =(NCHAN-1) CHAN_MAP_B (must be 0) ADD_C_TO_D 35 ADD_B_TO_C ADD_A_TO_B 70 RES_CLK_DIV (The resampler clock rate is 2*F CK/(RES_CLK_DIV+1)) RATIO_MAP_3 RATIO_MAP_2 00 RATIO_MAP_1 RATIO_MAP_0 00 Res Ratio 0 RATIO_0, Resampler ratio 0. RATIO = 226 (Resampler input sample rate)/(Resampler output sample rate) 04000000 20-23 Res Ratio 1 RATIO_1, Resampler ratio 1. 04000000 24-27 Res Ratio 2 RATIO_2, Resampler ratio 2. 04000000 28-31 Res Ratio 3 RATIO_3, Resampler ratio 3. 04000000 16-31 Output Data See Tables 4,5, and 6 for details EN_PAR EN_P3 EN_P2 EN_P1 EN_P0 EN_SFS EN_RDY EN_SCK RDY_WIDTH TAG_EN INV_SFS INV_RDY INV_SCK REAL_ONLY MASTER PARALLEL NIBBLE LINK 16 (0x10) Tristate Controls 17 (0x11) Output Format 18 (0x12) Output Mode 19 (0x13) Frame Control 20 (0x14) Word Sizes 21 (0x15) Clock Control 22 (0x16) Serial Mux 23 (0x17) Output Tag A TAG_AQ TAG_AI 10 24 (0x18) Output Tag B TAG_BQ TAG_BI 32 25 (0x19) Output Tag C TAG_CQ TAG_CI 54 26 (0x1A) Output Tag D TAG_DQ TAG_DI 27 (0x1B) Revision 28 (0x1C) Miscellaneous OUT_BLK_SYNC REVERSE_IQ OUTPUT_MODE SFS_MODE See Table 3 FRAME_LENGTH BLOCK_SIZE BITS_PER_WORD OUTPUT_ORDER WORDS_PER_FRAME NSERIAL SMUX_3 SCK_RATE SMUX_2 SMUX_1 SMUX_0 76 Mask Revision Number read only - EN_SO EN_4_FS 02 . Global Syncs (Addresses 4 and 5) Channel Syncs (Pages 7, 15, 23 and 31) Sync Value Description Sync Value Description DIAG_SYNC 7 (always) Only used during diagnostics PHASE_SYNC 7 (always) Use phase settings as they are loaded OUTPUT_SYNC 4 (OS) The SO output is used during initialization FREQ_SYNC 7 (always) Use frequency settings as they are loaded COUNTER_SYNC 4 (OS) Sync counter with one shot pulse NCO_SYNC 2 (SIA) Sync the phase accumulator during initialization. Set to SIB for frequncy hopping. DITHER_SYNC 0 (never) or 2 (SIA) Can free run except during diagnostics, or reset during initialization ZPAD_SYNC 2 (SIA) Sync the zero pad circuit during initialization DEC_SYNC 2 (SIA) Sync the channel decimation during initialization Outout Circuit Sync (Page 98) OUT_BLK_SYNC 2 (SIA) Sync the output block during initialization Resampler syncs (Page 64) RES_SYNC 2 (SIA) Sync the Resampler during initialization FLUSH_SYNC 2 (SIA) Flush the channels during initialization RATIO_SYNC 7(always) Set to always except when synchronously changing ratios GAIN_SYNC 7 (always) Use fine gain settings as they are loaded PEAK_SYNC 5 (TC) Periodically capture peak count data  5 ( SHIFT + SCALE + 6 × BIG_SCALE – 62 )  COARSE CFIR_SUM PFIR_SUM FINE_GAIN FINAL_SHIFT 1 RES_SUM GAIN =  ( --------------------)N 2 ) ( ------------------) ( ------------------ ) ( -------------------) ( --------------------------------------------)(2 ) ( 2 32768 × NDELAY NZEROS + 1 65536 65536 1024   REV 1.0 August 27, 2001 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third–party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright  2001, Texas Instruments Incorporated