HD3SS0001
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SLAS827 – SEPTEMBER 2013
10.3Gbps Thunderbolt™ Port and DisplayPort™ Switch
Check for Samples: HD3SS0001
FEATURES
1
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23
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•
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Compatible with Thunderbolt™ Technology
Electrical Standards and DisplayPort ™1.2a
Wide –3dB Differential Bandwidth of Over
10GHz on 10G Path
Supports DP and DP++ Configurations
Handles HPD (5V tolerant) and Cable Detect
Supports AUX and DDC MUX
Excellent Dynamic Characteristics (on 10G
path, typical values at 5GHz):
– Crosstalk = –35dB
– Off-Isolation = –24dB
– Insertion Loss = –1.5dB
– Return Loss = –20dB
– Intra-pair Skew Added < 4ps
Single 3.3V Power Supply
Small 3x3mm 24-Pin QFN Package
Low Power Consumption
– 3.3mW Typical Active Power
– 80 µW Typical Detect Mode
DESCRIPTION
The HD3SS0001 is a high-speed passive-switch
device with integrated buffers and resistors, designed
to support Thunderbolt™ technology, DisplayPort,
and Dual Mode DisplayPort. The 10G path supports a
high 10GHz bandwidth and excellent loss
characteristics, while the DisplayPort path supports
5.4Gbps.
The integrated 3-pairs to 1-pair multiplexer (3:1 MUX)
switches between DDC, AUX, and 10.3Gbps signals.
The integrated 2-pairs to 1-pair multiplexer (2:1 MUX)
switches between the Thunderbolt™ technology Low
Speed UART transmit/receive pair and DisplayPort
Main Link 1.
The MUXs are controlled by 4 input pins: TRI#,
DP_EN#, 10G_EN, and CAD_IN (cable detect from
the connector). The HD3SS0001 is packaged in a
small 3x3mm 24-pin QFN, operates from a single
3.3V supply, and supports an ambient temperature
range of –40°C to 85°C.
sp
FUNCTIONAL DIAGRAM
VDD
AUX(n)
R1
AUX(p)
DDC_SDA
10G(n)
3:1 pair
MUX
DDC_SCL
10G(p)
R2
10G_RX1(n)
10G_RX1(p)
Control
Logic
TRI#
DP_EN#
10G_EN
ML1(p)_IN
ML1(n)_IN
VDD
RPU
2:1 pair
MUX
ML1(p)_OUT
ML1(n)_OUT
LSTX
LSRX
RPD
CAD_OUT
CAD_IN
HPD_OUT
HPD_IN
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Thunderbolt is a trademark of Intel Corp.
DisplayPort is a trademark of VESA Standards Association.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
HD3SS0001
SLAS827 – SEPTEMBER 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
TYPICAL APPLICATION
DDC_SCL
Thunderbolt™
Controller
mDP /
Thunderbolt™
Connector
DDC_SDA
AUX(p)
AUX
AUX(n)
10G_RX1(p)
10G_RX1
10G_RX1(n)
Pin 16
10G(n)
Pin 18
HD3SS0001
ML1(p)_IN
DP ML1
10G(p)
ML1(p)_OUT
ML1(n)_IN
Thunderbolt™ Port
and DisplayPort™
Switch
LSTX
LSRX
ML1(n)_OUT
Pin 9
Pin 11
TRI#
DP_EN#
10G_EN
Interface
Controller
CAD_OUT
CAD_IN
HPD_OUT
HPD_IN
Pin 4
Pin 2
TRUTH TABLE
LOGICAL INPUT TO SET (1)
MODE
Thunderbolt™
Protocol
DisplayPort
TMDS
(1)
(2)
2
EFFECT
TRI#
DP_EN#
10G_EN
CAD_IN
2:1 MUX
SELECTION (2)
3:1 MUX
SELECTION (2)
PULL-UP RESISTOR
on 10G(n)
1
1
1
X
LS
10G
Disconnected
0
1
1
X
LS
Tri-stated
Disconnected
1
0
0
0
ML
AUX
Connected
0
0
0
0
Tri-Stated
Tri-stated
Connected
1
0
0
1
ML
DDC
Connected
Connected
0
0
0
1
Tri-Stated
Tri-stated
Detect Mode
X
1
0
X
LS
Tri-Stated
Connected
[Invalid]
X
0
1
X
Tri-Stated
Tri-Stated
Disconnected
“X” = Don’t Care.
MUX Selection names are abbreviated.
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SLAS827 – SEPTEMBER 2013
GND
ML1(n)_OUT
ML1(p)_OUT
24
10G(p)
TRI#
10G(n)
PACKAGE PINOUT
(TOP VIEW)
23
22
21
20
19
3:1
2:1
18
CAD_IN
17
HPD_IN
16
CAD_OUT
15
10G_EN
AUX(n)
1
AUX(p)
2
VDD
3
DDC_SDA
4
14
LSTX
DDC_SCL
5
13
LSRX
DP_EN#
6
12
HPD_OUT
10
11
ML1(p)_IN
9
ML1(n)_IN
8
GND
10G_RX1(n)
7
10G_RX1(p)
GND
MUX PIN MAPPING (1)
CONTROLLER-SIDE PIN
Connector-Side Pin
AUX(n)
DDC_SDA
10G(n)
10G_RX1(n)
AUX(p)
DDC_SCL
10G(p)
10G_RX1(p)
ML1(p)_IN
LSTX
ML1(n)_IN
LSRX
(1)
ML1(p)_OUT
ML1(n)_OUT
NOTE: The HD3SS0001 can tolerate polarity inversions for the
differential signals denoted by the (p) and (n) terminology, to ease
potential board routing issues. LSTX/LSRX cannot be swapped,
since LSRX is buffered and therefore unidirectional. Also, note that
the integrated pullup on 10G(n) and the integrated pulldown on
10G(p) cannot be swapped.
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PIN FUNCTIONS
PIN
NO.
SYSTEM
SIDE
I/O
NAME
DESCRIPTION
11
ML1(p)_IN
DisplayPort MainLink1(p) input
10
ML1(n)_IN
DisplayPort MainLink1(n) input
24
TRI#
6
DP_EN#
15
10G_EN
18
CAD_IN
17
HPD_IN
2
AUX(p)
AUX Positive Signal
1
AUX(n)
AUX Negative Signal
5
DDC_SCL
4
DDC_SDA
14
LSTX
13
LSRX
22
10G(p)
23
10G(n)
19
ML1(p)_OUT
20
ML1(n)_OUT
DisplayPort MainLink1(n) output or LSRX
8
10G_RX1(p)
10.3Gbps Positive Signal
7
10G_RX1(n)
16
CAD_OUT
12
HPD_OUT
3
VDD
9, 21,
Center Pad
GND
Controller
I
Tri-State control (see TRUTH TABLE)
DisplayPort Enable, active-low (see TRUTH TABLE)
10.3Gbps Mode Enable (see TRUTH TABLE)
Connector
Controller
Cable Detect
Hot Plug Detect
DDC Clock
DDC Data
UART TX Signal
I/O
UART RX Signal
10G_RX1(p) or AUX(p) or DDC_SCL, with pull-down
Connector
10G_RX1(n) or AUX(n) or DDC_SDA, with pull-up
DisplayPort MainLink1(p) output or LSTX
10.3Gbps Negative Signal
O
Cable Detect
Controller
Hot Plug Detect
Power supply
Power
Supply
Reference ground
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted)
VALUE
Supply voltage range (2)
Voltage range
Electrostatic discharge
MAX
VDD
–0.5
4
Differential I/O
–0.5
4
Control pin/buffers
–0.5
VDD+0.5
Human body model (3)
Charged-device model (4)
Continuous power dissipation
(1)
(2)
(3)
(4)
4
UNIT
MIN
±1,500
±500
V
V
V
See Power Characteristics
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC/ESDA JS-001-2011
Tested in accordance with JEDEC JESD22 C101-E
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SLAS827 – SEPTEMBER 2013
THERMAL INFORMATION
over operating free-air temperature range (unless otherwise noted)
HD3SS0001
THERMAL METRIC (1)
θJA
Junction-to-ambient thermal resistance
41.5
θJCtop
Junction-to-case (top) thermal resistance
43.1
θJCbot
Junction-to-case (bottom) thermal resistance
6.3
θJB
Junction-to-board thermal resistance
11.2
ψJT
Junction-to-top characterization parameter
1.2
ψJB
Junction-to-board characterization parameter
11.2
(1)
UNITS
24-PIN VQFN (RLL)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
POWER CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX (1)
1.0
1.3
UNIT
IDD
Supply Current in Active Mode
Outputs Floating
IDETECT
Supply Current in Detect Mode
DP_EN# = 1, 10G_EN = 0
26
50
µA
PD
Power Dissipation in Active Mode
3.3
4.7
mW
PDetect
Power Dissipation in Detect Mode
80
150
µW
(1)
mA
The maximum ratings are simulated for VDD = 3.6V.
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RECOMMENDED OPERATING CONDITIONS
Typical values for all parameters are at VDD = 3.3V and TA = 25°C. (Temperature limits are specified by design)
PARAMETER
NOTES/CONDITIONS
MIN
TYP
MAX
3.3
(1)
V
°C
VDD
Supply voltage
3.0
TA
Operating free-air
temperature
–40
85
VIH
Input high voltage
CAD_IN, HPD_IN (2), TRI#, DP_EN#, and 10G_EN
2.0
VDD
ML1(n)_OUT (when 2:1 MUX selects LS)
2.0
VDD
VIL
Input low voltage
CAD_IN, HPD_IN (2), TRI#, DP_EN#, and 10G_EN
–0.1
0.8
ML1(n)_OUT (when 2:1 MUX selects LS)
–0.1
0.8
VOH
Output high voltage
VOL
Output low voltage
IIH
High-level input current
IIL
Low-level input current
3.6
CAD_OUT, HPD_OUT
2.7
VDD
LSRX (when 2:1 MUX selects LS)
2.7
VDD (1)
CAD_OUT, HPD_OUT
0.0
0.1
LSRX (when 2:1 MUX selects LS)
0.0
0.1
TRI#, DP_EN#, 10G_EN, CAD_IN, and HPD_IN;
VDD = 3.6V, VIN = VDD
UNIT
V
V
V
V
5
µA
ML1(n)_OUT; VDD = 3.6V; VIN = VDD (when 2:1 MUX
selects LS)
3.75
TRI#, DP_EN#, 10G_EN, CAD_IN, and HPD_IN;
VDD = 3.6V, VIN = GND
100
ML1(n)_OUT; VDD = 3.6V, VIN = GND (when 2:1 MUX
selects LS)
100
nA
VI/O_Diff
Differential I/O voltage
AUX(p)/AUX(n), 10G_RX1(p)/ 10G_RX1(n),
ML1(p)_IN/ML1(n)_IN, 10G(p)/10G(n), and
ML1(p)_OUT/ML1(n)_OUT when MUX’s are connected to
Differential Signals.
0
1.8
Vpp
VI/O_CM
Common mode I/O
voltage
AUX(p)/AUX(n), 10G_RX1(p)/10G_RX1(n),
ML1(p)_IN/ML1(n)_IN, 10G(p)/ 10G(n), and
ML1(p)_OUT/ML1(n)_OUT when MUX’s are connected to
Differential Signals.
0
2.0
V
(1)
(2)
VDD range supports 3.0V to 3.6V, but for Thunderbolt products it is anticipated that the VDD must be maintained at less than or equal to
3.4V to ensure that the VOH on the LSRx do not exceed 3.4V.
HPD_IN is 5V tolerant.
ELECTRICAL CHARACTERISTICS
(under recommended operation conditions)
PARAMETER
CONDITIONS
Thunderbolt™ Technology 10.3Gbps Link: 10G_RX1(p), 10G_RX1(n)
MIN
TYP
MAX
UNIT
(1)
RL
Differential Return Loss
f = 5.0 GHz
–20
dB
IL
Differential Insertion Loss
f = 5.0 GHz
–1.5
dB
OIRR
Differential Off Isolation
f = 5.0GHz (see Figure 3)
–24
dB
XTALK
Differential Crosstalk
f = 5.0 GHz
–35
dB
BW
Bandwidth
–3 dB
10
GHz
tPD
Propagation Delay(from input to
output)
Rsc and RL = 50 Ω (see Figure 2)
200
ps
TSKEW
Intra-Pair Skew Added
Rsc and RL = 50 Ω (see Figure 2)
4
ps
CON
Outputs ON Capacitance
VI = 0 V, Outputs Open, Switch ON
1.5
pF
COFF
Outputs OFF Capacitance
VI
= 0 V, Outputs Open Switch OFF
1
pF
RON
Output ON resistance
VDD = 3.3 V, IO = –15 µA
7.5
Ω
ΔRON
On resistance match between pairs of
the same channel
VDD = 3.3V; IO = –15 µA
Control Line Change to MUX Output
Switched
See Figure 1
TON
TOFF
(1)
6
1
400
10
Ω
µs
These values apply for CAD_IN tri-stated, unless otherwise noted.
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ELECTRICAL CHARACTERISTICS (continued)
(under recommended operation conditions)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
DisplayPort Link: ML1(p)_IN, ML1(n)_IN
RL
Differential Return Loss
f = 2.7 GHz
–16
dB
IL
Differential Insertion Loss
f = 2.7 GHz; VCM = 0 V
–0.8
dB
OIRR
Differential Off-Isolation
f = 2.7 GHz (see Figure 3)
–20
dB
XTALK
Differential Crosstalk
f = 2.7 GHz
–35
BW
Differential Bandwidth
–3 dB
tPD
Propagation Delay(from input to
output)
RSC and RL = 50 Ω (see Figure 2)
TSKEW
Intra-pair Skew Added
RSC and RL = 50 Ω (see Figure 2)
CON
Outputs ON Capacitance
VI = 0 V; Outputs Open; Switch ON
COFF
Outputs OFF Capacitance
RON
ΔRON
TON
TOFF
dB
7
GHz
200
4
ps
ps
1.5
pF
VI = 0 V; Outputs Open; Switch OFF
1
pF
Output ON resistance
VDD = 3.3 V; IO = –15 mA; VCM = 0.5 V to 1.5 V;
CAD_IN = 0 V
6
On resistance match between pairs of
the same channel
VDD = 3.3 V; IO = -15 mA; VCM = 0.5 V to 1.5 V
Control Line Change to MUX Output
Switched
See Figure 1
8
Ω
1
Ω
400
10
µs
Thunderbolt™ Technology Low Speed UART : LSTX
CON
Outputs ON capacitance
VI = 0 V , Outputs Open, Switch ON
8
pF
COFF
Outputs OFF capacitance
VI = 0 V, Outputs Open, Switch OFF
3
pF
RON
Output ON resistance
VDD = 3 V, VCM = 0 V to 3 V, IO = –1 mA
CAD_IN = 0 V
tPD
Propagation Delay
LSTX to ML1(p)_OUT
12
19
Ω
200
ps
DisplayPort: AUX(p), AUX(n)
CON
Outputs ON Capacitance
VI = 0 V; Outputs Open; Switch ON
6
pF
COFF
Outputs OFF Capacitance
VI = 0 V; Outputs Open; Switch OFF
3
pF
RON
Output ON resistance
VDD = 3.3V; IO = –10 mA; AUX(p) = 0.3 V;
AUX(n) = 3.0 V; CAD_IN = 0 V
12
Ω
ΔRON
On resistance match between pairs of
the same channel
VDD = 3.3 V; IO = –10 mA;
VCM = 0.5 V to 1.5 V
Control line change to Mux output
switched
See Figure 2
TON
TOFF
1
Ω
40
ms
10
µs
Thunderbolt Technology Low Speed UART : LSRX
CON
Outputs capacitance
ZO
Output impedance
VDD = 3.3 V
tPD
Propagation delay
ML1(n)_OUT to LSRX
tr
Rise Time
VDD = 3 V
3
ns
tf
Fall Time
VDD = 3 V
3
ns
TON
Control line change to MUX Output
Switched
See Figure 1
TOFF
3
pF
60
Ω
3.2
ns
400
µs
10
µs
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ELECTRICAL CHARACTERISTICS (continued)
(under recommended operation conditions)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
DisplayPort : DDC_SCL, DDC_SDA
CON
Outputs ON capacitance
VI = 0 V, Outputs Open, Switch ON
9
pF
COFF
Outputs OFF capacitance
VI = 0 V, Outputs Open, Switch OFF
3
pF
RON
Output ON resistance
VDD = 3.3 V, IO = –10 mA, VCM = 0.4 V,
CAD_IN = 3.3 V
TON
Control line change to MUX output
switched
See Figure 1
TOFF
80
150
400
10
Ω
µs
UART and 10G MUX Outputs : LSTX/LSRX/10G(p)/10G(n)
R1
Integrated Pullup Resistance
10G(n) pin when in DP, TMDS, or Detect Mode
87
105
kΩ
R2
Integrated Pulldown Resistance
10G(p) pin when in DP, TMDS, or Detect Mode, or
VDD = 0V
87
105
kΩ
RPU
Integrated pullup resistance
LSTX
8.7
kΩ
RPD
Integrated pulldown resistance
LSRX
1.2
MΩ
TEST DIAGRAMS
50%
TRI# / DP_EN# / 10G_EN / CAD_IN
90%
10%
Muxed/Buffered Output Pins
T OFF
TON
Figure 1. Control Line Change to Switched Signals
8
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Vcc
R SC = 50Ω
R SC = 50Ω
ML1(n)_IN /
10G_RX1(n)
ML1(p)_OUT /
10G(p)
HD3SS0001
ML1(p)_IN /
10G_RX1(p)
R L = 50Ω
ML1(n)_OUT /
10G(n)
RL = 50Ω
SEL
VDD
VIN+
50%
50%
50%
50%
0V
VDD
VIN0V
VDD
VOUT+
50%
50%
50%
50%
0V
VDD
VOUT0V
tP1
tP2
t PD = Max(tp1, t p2)
tSK(O) = Difference between t PD for any
two pairs of outputs
t SK(b-b) = Difference between t P1
and tP2 of same pair
Figure 2. Propagation Delay and Skew
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Network
Analyzer
P1
P2
VDD
AUX(p)
10G_RX1(p) /
AUX(p) /
DDC_SCL
RL
AUX(n)
10G_RX1(n) /
AUX(n) /
DDC_SDA
VDD
HD3SS0001
TRI#
10G(p)
CAD_IN
10G_EN
DP_EN#
10G(n)
Figure 3. Off-Isolation Measurement Setup
10
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
HD3SS0001RLLR
ACTIVE
VQFN
RLL
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
3SS001
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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