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HD3SS3212-Q1
SLASEQ6A – SEPTMEBER 2018 – REVISED JUNE 2019
HD3SS3212-Q1 Two-Channel Differential 2:1/1:2 USB3.2 Mux/Demux
1 Features
3 Description
•
The HD3SS3212-Q1 is a high-speed bidirectional
passive switch in mux or demux configurations. It is
suited for USB Type-C™ application that supports
USB 3.2 Gen 1 and Gen 2 data rates. The SEL
control pin provides switching on differential channels
between Port B or Port C to Port A.
1
•
•
•
•
•
•
•
•
•
AEC-Q100 Qualified for automotive applications
– Temperature grade 2: –40°C to +105°C, TA
Provides MUX/DEMUX solution for USB Type-C™
ecosystem for USB 3.2 Gen 1 and Gen 2 data
rates
Compatible with MIPI DSI/CSI, FPD-Link III,
LVDS, and PCIe Gen II, III
Operates up to 10 Gbps
Wide –3-dB Differential BW of over 8 GHz
Excellent dynamic characteristics (at 5 GHz)
– Crosstalk = –28 dB
– Off isolation = –19 dB
– Insertion loss = –2 dB
– Return loss = –8 dB
Bidirectional "Mux/De-Mux" differential switch
Supports common mode voltage 0 V to 2 V
Single supply voltage VCC of 3.3 V
Available in automotive friendly QFN package
(2.5 mm x 4.5 mm at 0.5 mm pitch)
The HD3SS3212-Q1 is a generic analog differential
passive switch. It works for any high-speed interface
application requiring a common mode voltage range
of 0 V to 2 V and differential signaling with differential
amplitude up to 1800 mVpp. Adaptive tracking
ensures the channel remains unchanged for the
entire common mode voltage range.
Excellent dynamic characteristics of the device allows
high-speed switching, minimum attenuation to the
signal eye diagram, and with little added jitter. It
consumes less than 1.65 mW of power when
operational. The OEn pin has a shutdown mode
resulting in less than 0.02 µW.
Device Information(1)
PART NUMBER
HD3SS3212-Q1
2 Applications
•
•
•
•
•
•
PACKAGE
VQFN (20)
BODY SIZE (NOM)
2.50 mm × 4.50 mm ×
0.5-mm pitch
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
USB Type-C™ ecosystem
Automotive media interface
Head unit
Rear seat entertainment
FPD-Link II and FPD-Link III switching
MIPI DSI/CSI-2 switching
SPACE
Simplified Schematic
B0p
TXp1
SSTXp
A0p
B0n
TXn1
SSTXn
A0n
C0p
TXp2
C0n
TXn2
SEL
B1p
RXp1
SSRXp
A1p
B1n
RXn1
SSRXn
A1n
C1p
RXp2
C1n
RXn2
OEn
USB-C Receptacle
HD3SS3212-Q1
USB3.1 Host
VCC
CC1
TP
GND
CC2
3.3V
CC
Controller
Copyright © 2018, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
HD3SS3212-Q1
SLASEQ6A – SEPTMEBER 2018 – REVISED JUNE 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
High-Speed Performance Parameters ......................
Switching Characteristics ..........................................
Parameter Measurement Information .................. 6
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 10
9
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Applications ................................................ 14
9.3 Systems Examples.................................................. 16
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 18
12 Device and Documentation Support ................. 19
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
13 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September 2018) to Revision A
•
2
Page
Changed the document From: Advanced Information To: Production data .......................................................................... 1
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SLASEQ6A – SEPTMEBER 2018 – REVISED JUNE 2019
5 Pin Configuration and Functions
NC1
GND
1
20
RKS Package
20-Pin VQFN
Top View
OEn
2
19
B0p
A0p
3
18
B0n
A0n
4
17
B1p
Thermal
GND
5
16
B1n
VCC
6
15
C0p
A1p
7
14
C0n
A1n
8
13
C1p
SEL
9
12
C1n
11
GND
NC2
10
Pad
Not to scale
Pin Functions
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
VCC
6
P
3.3-V power
OEn
2
I
Active-low chip enable
L: Normal operation
H: Shutdown
A0p
3
I/O
Port A, channel 0, high-speed positive signal
A0n
4
I/O
Port A, channel 0, high-speed negative signal
GND
5, 11, 20
G
Ground
A1p
7
I/O
Port A, channel 1, high-speed positive signal
A1n
8
I/O
Port A, channel 1, high-speed negative signal
SEL
9
I
C1n
12
I/O
Port C, channel 1, high-speed negative signal (connector side)
C1p
13
I/O
Port C, channel 1, high-speed positive signal (connector side)
C0n
14
I/O
Port C, channel 0, high-speed negative signal (connector side)
C0p
15
I/O
Port C, channel 0, high-speed positive signal (connector side)
B1n
16
I/O
Port B, channel 1, high-speed negative signal (connector side)
B1p
17
I/O
Port B, channel 1, high-speed positive signal (connector side)
B0n
18
I/O
Port B, channel 0, high-speed negative signal (connector side)
B0p
19
I/O
Port B, channel 0, high-speed positive signal (connector side)
NC1
1
NA
NC2
10
NA
(1)
Port select pin.
L: Port A to Port B
H: Port A to Port C
Can be left not connected or can be fed to VCC or tied to GND.
The high-speed data ports incorporate 20-kΩ pulldown resistors that are switched in when a port is not selected and switched out when
the port is selected.
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HD3SS3212-Q1
SLASEQ6A – SEPTMEBER 2018 – REVISED JUNE 2019
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Voltage
Tstg
(1)
MIN
MAX
–0.5
4
Differential I/O
–0.5
2.5
Control pins
–0.5
VCC+ 0.5
–65
150
Supply voltage
Storage temperature
UNIT
V
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended
OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
HBM ESD Classification Level 2
±2000
Charged-device model (CDM), per AEC Q100- 011
CDM ESD Classification Level C6
±500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage
2.7
3.6
V
Vih
Input high voltage (SEL, OEn pins)
1.7
VCC
V
Vil
Input low voltage (SEL, OEn pins)
–0.1
0.8
V
Vdiff
High-speed signal pins differential voltage
0
1.8
Vpp
Vcm
High speed signal pins common mode voltage
TA
Operating free-air/ambient temperature
HD3SS3212-Q1
UNIT
0
2
V
-40
105
°C
6.4 Thermal Information
HD3SS3212-Q1
THERMAL METRIC (1)
RKS (VQFN)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
58.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
59.9
°C/W
RθJB
Junction-to-board thermal resistance
32.1
°C/W
ψJT
Junction-to-top characterization parameter
5.9
°C/W
ψJB
Junction-to-board characterization parameter
32
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
16.7
°C/W
(1)
4
For more information about traditional and new thermalmetrics, see the Semiconductor and IC Package ThermalMetrics application
report.
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SLASEQ6A – SEPTMEBER 2018 – REVISED JUNE 2019
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.5
0.8
UNIT
mA
0.005
1
µA
ICC
Device active current
VCC = 3.3 V, OEn = 0
ISTDN
Device shutdown current
VCC = 3.3 V, OEn = VCC
CON
Output ON capacitance to GND
0.6
pF
COFF
Output OFF capacitance to GND
0.8
pF
RON
Output ON resistance
VCC = 3.3 V; VCM = 0 to 2 V;
IO = –8 mA
ΔRON
On-resistance match between pairs of the same
channel
VCC = 3.3 V; –0.35 V ≤ VIN ≤ 2.35 V; IO =
–8 mA
RFLAT_ON
On-resistance flatness RON(MAX) – RON(MIN)
VCC = 3.3 V; –0.35 V ≤ VIN ≤ 2.35 V
IIH,CTRL
Input high current, control pins (SEL, OEn)
IIL,CTRL
Input low current, control pins (SEL, OEn)
5
IIH,HS
Input high current, high-speed pins [Ax/Bx/Cx][p/n]
VIN = 2 V for selected port, A and B with
SEL = 0, and A and C with
SEL = VCC
IIH,HS
Input high current, high-speed pins [Ax/Bx/Cx][p/n]
VIN = 2 V for non-selected port, C with
SEL = 0, and B with
SEL = VCC (1)
IIL,HS
Input low current, high-speed pins [Ax/Bx/Cx][p/n]
(1)
100
8
Ω
0.7
Ω
1
Ω
1
µA
1
µA
1
µA
140
µA
1
µA
There is a 20-kΩ pull-down in non-selected port.
6.6 High-Speed Performance Parameters
PARAMETER
IL
BW
RL
Differential insertion loss
TEST CONDITION
MIN
-0.4
ƒ = 0.625 MHz
-0.4
ƒ = 2.5 GHz
-1.8
ƒ = 5 GHz
-2.0
ƒ = 0.3 MHz
-25
ƒ = 2.5 GHz
-11
9
ƒ = 4 GHz
ƒ = 5 GHz
OIRR
XTALK
Differential OFF isolation
Differential crosstalk
-1
ƒ = 4 GHz
–3-dB bandwidth
Differential return loss
TYP
ƒ = 0.3 MHz
-9
MAX
UNIT
dB
GHz
dB
-8
ƒ = 0.3 MHz
-75
ƒ = 2.5 GHz
-23
ƒ = 4 GHz
-21
ƒ = 5 GHz
-19
ƒ = 0.3 MHz
-70
ƒ = 2.5 GHz
-35
ƒ = 4 GHz
-30
ƒ = 5 GHz
-28
dB
dB
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HD3SS3212-Q1
SLASEQ6A – SEPTMEBER 2018 – REVISED JUNE 2019
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6.7 Switching Characteristics
PARAMETER
tPD
Switch propagation delay (see Figure 3)
tSW_ON
MIN
TYP
ƒ > 1 GHz
MAX
UNIT
80
ps
Switching time SEL-to-Switch ON (see Figure 2)
0.5
µs
tSW_OFF
Switching time SEL-to-Switch OFF (see Figure 2)
0.5
µs
tSW_OEn_ON
Switching time OEn-to-Switch ON
2
µs
tSW_OEn_OFF
Switching time OEn-to-Switch OFF
0.1
µs
tSK_INTRA_A0B0
Intra-pair output skew for path A0 to B0. (see Figure 3)
Intra-pair Skew = P N
tSK_INTRA_A0C0
Intra-pair output skew for path A0 to C0. (see Figure 3)
Intra-pair Skew = P N
1.25
ps
tSK_INTRA_A1B1
Intra-pair output skew for path A1 to B1. (see Figure 3)
Intra-pair Skew = P N
-0.75
ps
tSK_INTRA_A1C1
Intra-pair output skew for path A1 to C1. (see Figure 3)
Intra-pair Skew = P N
-4
ps
tSK_INTER
Inter-pair output skew (see Figure 3)
4.5
ps
20
ps
7 Parameter Measurement Information
VCC
RSC = 50 Ÿ
Bxp/Cxp
Axp
RL = 50 Ÿ
RSC = 50 Ÿ
Axn
RL = 50 Ÿ
Bxn/Cxn
SEL
Figure 1. Test Setup
6
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SLASEQ6A – SEPTMEBER 2018 – REVISED JUNE 2019
Parameter Measurement Information (continued)
50%
50%
SEL
90%
10%
VOUT
tSW_ON
tSW_OFF
Figure 2. Switch On and Off Timing Diagram
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Parameter Measurement Information (continued)
2.6-V Max
50%
VIN
50%
0V
2.6-V Max
50%
VOUT
0V
50%
tPD
VOUTp
50%
VOUTn
TSK_INTRA
B0/C0
VOUT
50%
50%
50%
B1/C1
VOUT
50%
tSK_INTER
Figure 3. Timing Diagrams and Test Setup
8
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SLASEQ6A – SEPTMEBER 2018 – REVISED JUNE 2019
8 Detailed Description
8.1 Overview
The HD3SS3212-Q1 is a generic analog differential passive switch that can work for any high-speed interface
applications requiring a common mode voltage range of 0 V to 2 V and differential signaling with differential
amplitude up to 1800 mVpp. It employs adaptive tracking that ensures the channel remains unchanged for the
entire common mode voltage range.
Excellent dynamic characteristics of the device allow high-speed switching with minimum attenuation to the
signal eye diagram with very little added jitter. It consumes less than 1.65 mW of power when operational and
has a shutdown mode exercisable by OEn pin resulting less than 0.02 µW.
8.2 Functional Block Diagram
B0+
B0±
A0+
A0±
C0+
C0±
SEL
B1+
B1±
A1+
A1±
C1+
C1±
8.3 Feature Description
8.3.1 Output Enable and Power Savings
The HD3SS3212-Q1 has two power modes, active/normal operating mode and standby/shutdown mode. During
standby mode, the device consumes very-little current to save the maximum power. To enter standby mode, the
OEn control pin is pulled high through a resistor and must remain high. For active/normal operation, the OEn
control pin should be pulled low to GND or dynamically controlled to switch between H or L.
HD3SS3212-Q1 consumes < 1.65 mW of power when operational and has a shutdown mode exercisable by the
EN pin resulting < 0.02 µW.
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HD3SS3212-Q1
SLASEQ6A – SEPTMEBER 2018 – REVISED JUNE 2019
www.ti.com
8.4 Device Functional Modes
Table 1. Port Select Control Logic (1)
PORT A CHANNEL
(1)
10
PORT B OR PORT C CHANNEL CONNECTED TO PORT A CHANNEL
SEL = L
SEL = H
A0p
B0p
C0p
A0n
B0n
C0n
A1p
B1p
C1p
A1n
B1n
C1n
The HD3SS3212 can tolerate polarity inversions for all differential signals on Ports A, B, and C. Take
care to ensure the same polarity is maintained on Port A versus Ports B/C.
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SLASEQ6A – SEPTMEBER 2018 – REVISED JUNE 2019
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The HD3SS3212-Q1 is a generic 2-channel high-speed mux/demux type of switch that can be used for routing
high-speed signals between two different locations on a circuit board. The HD3SS3212-Q1 supports several
high-speed data protocols with a differential amplitude of
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