HD3SS3415RUAT

Sample & Buy Product Folder Technical Documents Support & Community Tools & Software HD3SS3415 SLAS840C – MARCH 2012 – REVISED OCTOBER 2015 HD3SS3415 4-Channel High-Performance Differential Switch 1 Features 3 Description • The HD3SS3415 is a high-speed passive switch capable of switching four differential channels, including applications such as two full PCI Express x1 lanes from one source to one of two target locations in a PC/server application. With its bidirectional capability the HD3SS3415 will also support applications that allow connections between one target and two source devices, such as a shared peripheral between two platforms. The HD3SS3415 has a single control line (SEL Pin) which can be used to control the signal path between Port A and either Port B or Port C. 1 • • • • • Compatible with Multiple Interface Standards Operating up to 12 Gbps Including PCI Express Gen III and USB 3.0 Wide –3-dB Differential BW of over 8 GHz Excellent Dynamic Characteristics (at 4 GHz) – Crosstalk = –35 dB – Off Isolation = –19 dB – Insertion Loss = –1.5 dB – Return Loss = –11 dB VDD Operating Range 3.3 V ±10% Small 3.5 mm × 9 mm, 42-Pin WQFN Package Common Industry Standard Pinout 2 Applications • • • • Desktop and Notebook PCs Server/Storage Area Networks PCI Express Backplanes Shared I/O Ports Device Information(1) PART NUMBER HD3SS3415 1 B0NC VDD B1+ B1NC GND Top View RUA Package A2- SEL GND B2+ C2+ B2- C2- VDD NC A3+ A3- B3+ 22 17 21 GND 18 GND VDD B3GND NC C3+ C3- HD3SS3415 Switch Flow Through Routing NC GND VDD GND 38 39 42 B0+ C0+ C0A1+ VDD A2+ BODY SIZE (NOM) 9.00 mm × 3.50 mm GND A0- A1C1+ C1- PACKAGE WQFN (42) (1) For all available packages, see the orderable addendum at the end of the datasheet. HD3SS3415 Pinout A0+ The HD3SS3415 is offered in an industry standard 42-pin WQFN package available in a common footprint shared by several other vendors. The device is specified to operate from a single supply voltage of 3.3 V over the full temperature range of 0°C to 70°C 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. HD3SS3415 SLAS840C – MARCH 2012 – REVISED OCTOBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 9 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description continued ........................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6 7.1 7.2 7.3 7.4 7.5 7.6 7.7 6 6 6 6 7 7 9 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Dissipation Ratings ................................................... Typical Characteristics .............................................. Parameter Measurement Information ................ 10 Detailed Description ............................................ 12 9.1 Overview ................................................................. 12 9.2 Functional Block Diagram ....................................... 12 9.3 Feature Description................................................. 13 9.4 Device Functional Modes........................................ 13 10 Application and Implementation........................ 14 10.1 Application Information.......................................... 14 10.2 Typical Application ............................................... 15 11 Power Supply Recommendations ..................... 17 12 Layout................................................................... 17 12.1 Layout Guidelines ................................................. 17 12.2 Layout Example .................................................... 17 13 Device and Documentation Support ................. 18 13.1 13.2 13.3 13.4 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 18 18 18 18 14 Mechanical, Packaging, and Orderable Information ........................................................... 18 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (August 2015) to Revision C Page • Changed the HD3SS3415 Pinout and HD3SS3415 Switch Flow Through Routing images.................................................. 1 • Changed temperature From: industrial temperature range of –40°C to 85°C To: industrial temperature range of 0°C to 70°C in the Overview section ........................................................................................................................................... 12 Changes from Revision A (July 2015) to Revision B • Page Changed the Storage temperature MIN value From: 65 To: –65 in the Absolute Maximum Ratings (1) (2) table ................... 6 Changes from Original (February 2012 ) to Revision A Page • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 • Deleted the word "industrial" from Description section........................................................................................................... 1 • Changed the second paragraph of the Description -40 to 0 and 85 to 70°C ......................................................................... 1 • Changed TA spec values from –40°C MIN and 85°C MAX to 0°C MIN and 70°C MAX in the Recommended Operating Conditions table. .................................................................................................................................................... 6 2 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: HD3SS3415 HD3SS3415 www.ti.com SLAS840C – MARCH 2012 – REVISED OCTOBER 2015 5 Description continued The HD3SS3415 is a generic 4-CH high-speed mux/demux type of switch that can be used for routing highspeed signals between two different locations on a circuit board. Although it was designed specifically to address PCI Express Gen III applications, the HD3SS3415 will also support several other high-speed data protocols with a differential amplitude of < 1800 mVpp and a common mode voltage of < 2 V, as with USB 3.0 and DisplayPort 1.2. The one select input (SEL) pin of the device can easily be controlled by an available GPIO pin within a system or from a microcontroller. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: HD3SS3415 3 HD3SS3415 SLAS840C – MARCH 2012 – REVISED OCTOBER 2015 www.ti.com 6 Pin Configuration and Functions 38 39 42 1 A0+ NC GND VDD GND RUA Package 42-Pin WQFN Top View GND A0- B0+ C0+ C0A1+ B0NC VDD B1+ B1- A1C1+ C1- NC GND Top View RUA Package VDD A2+ A2- SEL GND B2+ C2+ B2- C2- VDD NC A3+ A3- B3+ 22 17 21 GND 18 GND VDD B3GND NC C3+ C3- Pin Functions PIN NAME NO. I/O DESCRIPTION SWITCH PORT A A0+ 1 Port A, Channel 0, High Speed Positive Signal A0– 2 Port A, Channel 0, High Speed Negative Signal A1+ 5 Port A, Channel 1, High Speed Positive Signal A1– 6 A2+ 10 A2– 11 Port A, Channel 2, High Speed Negative Signal A3+ 14 Port A, Channel 3, High Speed Positive Signal A3– 15 Port A, Channel 3, High Speed Negative Signal B0+ 37 Port B, Channel 0, High Speed Positive Signal B0– 36 lPort B, Channel 0, High Speed Negative Signal B1+ 33 Port B, Channel 1, High Speed Positive Signal B1– 32 B2+ 28 B2– 27 Port B, Channel 2, High Speed Negative Signal B3+ 24 Port B, Channel 3, High Speed Positive Signal B3– 23 Port B, Channel 3, High Speed Negative Signal I/O Port A, Channel 1, High Speed Negative Signal Port A, Channel 2, High Speed Positive Signal SWITCH PORT B 4 I/O Port B, Channel 1, High Speed Negative Signal Port B, Channel 2, High Speed Positive Signal Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: HD3SS3415 HD3SS3415 www.ti.com SLAS840C – MARCH 2012 – REVISED OCTOBER 2015 Pin Functions (continued) PIN NAME NO. I/O DESCRIPTION SWITCH PORT C C0+ 3 Port C, Channel 0, High Speed Positive Signal C0– 4 Port C, Channel 0, High Speed Negative Signal C1+ 7 Port C, Channel 1, High Speed Positive Signal C1– 8 C2+ 12 C2– 13 Port C, Channel 2, High Speed Negative Signal C3+ 16 Port C, Channel 3, High Speed Positive Signal C3– 17 Port C, Channel 3, High Speed Negative Signal I/O Port C, Channel 1, High Speed Negative Signal Port C, Channel 2, High Speed Positive Signal CONTROL, SUPPLY, AND NO CONNECT 18, 20, 22, 29, 38, 40, 42, Center Pad Supply NC 21, 25, 31, 35, 39 – Electrically not connected SEL 30 I Select between port B or port C. Internally tied to GND via 100kΩ resistor VDD 9, 19, 26, 34, 41 Supply GND Negative power supply voltage Positive power supply voltage Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: HD3SS3415 5 HD3SS3415 SLAS840C – MARCH 2012 – REVISED OCTOBER 2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings (1) (2) Over operating free-air temperature range (unless otherwise noted) Supply voltage (VDD) Voltage MIN MAX UNIT Absolute minimum/maximum supply voltage range –0.5 4 V Differential I/O –0.5 4 Control pin (SEL) –0.5 VDD+0.5 –65 150 Storage temperature (Tstg) (1) (2) V ºC Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to network ground terminal. 7.2 ESD Ratings VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) Electrostatic discharge (1) UNIT ±4000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) V ±1500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions Typical values for all parameters are at VDD = 3.3V and TA = 25°C. (Temperature limits are specified by design) MIN TYP 3.3 MAX UNIT VDD Supply voltage 3.0 3.6 V VIH Input high voltage (SEL Pin) 2.0 VDD V VIL Input low voltage (SEL Pin) –0.1 0.8 V VI/O_Diff Differential voltage (differential pins) Switch I/O diff voltage 0 1.8 VPP VI/O_CM Common voltage (differential pins) Switch I/O common mode voltage 0 2.0 V TA Operating free-air temperature Ambient temperature 0 70 °C 7.4 Thermal Information HD3SS3415 THERMAL METRIC (1) TQFN (RUA) UNIT 42 PINS RθJA Junction-to-ambient thermal resistance 53.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 38.2 °C/W RθJB Junction-to-board thermal resistance 21.9 °C/W ψJT Junction-to-top characterization parameter 27.4 °C/W ψJB Junction-to-board characterization parameter 5.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 27.3 °C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: HD3SS3415 HD3SS3415 www.ti.com SLAS840C – MARCH 2012 – REVISED OCTOBER 2015 7.5 Electrical Characteristics RSC and RLOAD = 50 Ω and CL = 50 pF, over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DEVICE PARAMETERS IIH Input High Voltage (SEL) VDD = 3.6 V; VIN = VDD 95 µA IIL Input Low Voltage (SEL) VDD = 3.6 V; VIN = GND 1 µA Leakage Current (Differential I/O pins) ILK VDD = 3.6 V; VIN = 0 V; VOUT = 2 V (ILK On OPEN outputs) [Ports B and C] 130 µA VDD = 3.6 V, VIN = 2 V; VOUT = 0 V (ILK On OPEN outputs) [Port A] 4 IDD Supply Current VDD = 3.6 V; SEL = VDD/GND; Outputs Floating 4.7 CON Outputs ON Capacitance VIN = 0 V; Outputs Open; Switch ON 1.5 COFF Outputs OFF Capacitance VIN = 0 V; Outputs Open, Switch OFF 1 RON Output ON resistance VDD = 3.3 V; VCM = 0.5 V to 1.5 V ; IO = –8 mA 5 On resistance match between channels 6 mA pF pF 8 Ω VDD = 3.3 V ; –0.35 V ≤ VIN ≤ 1.2 V; IO = –8 mA 2 Ω On resistance match between pairs of the same channel VDD = 3.3 V; –0.35 V ≤ VIN ≤ 1.2 V; IO = –8 mA 0.7 Ω RFLAT_ON On resistance flatness (RON(MAX) – RON(MAIN) VDD = 3.3 V; –0.35 V ≤ VIN ≤ 1.2 V 1.15 Ω tPD Switch propagation delay Rsc and RLOAD = 50 Ω 85 ps ΔRON SEL-to-switch Ton SEL-to-switch Toff TSKEW_Inter Inter-pair output skew (CH-CH) TSKEW_Intra Intra-pair output skew (bit-bit) Differential return loss (VCM = 0 V) See Typical Characteristics RL XTALK OIRR Differential Crosstalk(VCM = 0 V) See Typical Characteristics Differential Off-Isolation(VCM = 0 V) See Typical Characteristics Differential Insertion Loss (VCM = 0 V) See Typical Characteristics IL BW Band Width Rsc and RLOAD = 50 Ω 70 250 70 250 Rsc and RLOAD = 50 Ω f = 0.3 MHz –28 f = 2500 MHz –12 f = 4000 MHz –11 f = 0.3 MHz –90 f = 2500 MHz –39 f = 4000 MHz –35 f = 0.3 MHz –75 f = 2500 MHz –22 f = 4000 MHz –19 f = 0.3 MHz –0.5 f = 2500 MHz –1.1 f = 4000 MHz –1.5 At –3 dB ns 20 ps 8 ps dB dB dB dB 8 GHz 7.6 Dissipation Ratings PD Power Dissipation MIN MAX UNIT 15.5 21.6 mW Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: HD3SS3415 7 HD3SS3415 SLAS840C – MARCH 2012 – REVISED OCTOBER 2015 www.ti.com 50% SEL 90% VOUT 10% Toff Ton Figure 1. Select to Switch Output On (TON) and Off (TOFF) Timing Diagram VDD RSC = 50W An+ RSC = 50W HD3SS3415 Bn+/Cn+ RL = 50W An- Bn-/CnRL = 50W SEL VDD VIN+ 50% 50% 50% 50% 0V VDD VIN- 0V VDD VOUT+ 50% 50% 50% 50% 0V VDD VOUT+ 0V tP1 tP1 TSKEWInter = Difference between tPD for any two pairs of outputs TSKEWIntra = Difference between tP1 and tP2 of same pair Figure 2. Propagation Delay Timing Diagram and Test Setup 8 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: HD3SS3415 HD3SS3415 www.ti.com SLAS840C – MARCH 2012 – REVISED OCTOBER 2015 7.7 Typical Characteristics m1 5 m2m3 m1 freq= 300.0kHz dB(SDD21)=-0.361 d B (SD D 2 1 ) m4 -5 m2 freq= 2.514GHz dB(SDD21)=-0.951 -10 m3 freq= 3.985GHz dB(SDD21)=-1.413 -15 -20 -5 m7 m6 -10 m7 freq= 3.985GHz dB(SDD11)=-10.275 -20 -25 m5 -30 freq, Hz Figure 4. Differential Return Loss 0 0 m1 freq= 300.0kHz dB(SDD21)=-86.588 -40 m2 freq= 2.514GHz dB(SDD21)=-33.793 -60 m1 m3 freq= 3.985GHz dB(SDD21)=-29.900 -100 m1 freq= 300.0kHz dB(SDD21)=-78.265 m2m3 -20 d B ( S D D 2 1) m2m3 -20 d B ( S D D 2 1) 1E 10 2E 10 1E 9 1E 8 1 E7 freq, Hz Figure 3. Differential Insertion Loss -80 m6 freq= 2.514GHz dB(SDD11)=-13.591 -15 1E 6 1E 10 2E 10 1E 9 1E 8 1E 7 1E 6 m4 freq= 8.724GHz dB(SDD21)=-3.019 m5 freq= 300.0kHz dB(SDD11)=-28.295 0 d B(S D D 1 1 ) 0 m2 freq= 2.514GHz dB(SDD21)=-22.547 -40 -60 m3 freq= 3.985GHz dB(SDD21)=-19.244 m1 -80 -100 -120 1E 10 2E 10 1E 9 1E 8 1 E7 1E 6 1E 10 2E 10 1E 9 1E 8 1 E7 1E 6 freq, Hz freq, Hz Figure 5. Differential Crosstalk Figure 6. Differential Off Isolation Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: HD3SS3415 9 HD3SS3415 SLAS840C – MARCH 2012 – REVISED OCTOBER 2015 www.ti.com 8 Parameter Measurement Information Network Analyzer P2 P1 VDD B0+ A0+ 100 W A0B0HD3SS3415 SEL B1+ A1+ 100 W A1B1- Figure 7. Cross Talk Measurement Setup Network Analyzer P2 P1 VDD A0+ B0+ A0- 100 W B0- HD3SS3415 SEL B1+ B1- Figure 8. Off Isolation Measurement Setup 10 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: HD3SS3415 HD3SS3415 www.ti.com SLAS840C – MARCH 2012 – REVISED OCTOBER 2015 Parameter Measurement Information (continued) A 3.1 Inches Rogers Microstrip Oscilloscope 10Gbps PRBS 2 7- 1 Vi=0.8Vpp ; Vcm =0V Figure 9. Source Eye Diagram Test Setup A 1.4 Inches Rogers Microstrip 1.7 Inches Rogers Microstrip 7 10Gbps PRBS 2 - 1 Vi=0.8Vpp ; Vcm =0V Oscilloscope Figure 10. Output Eye Diagram Test Setup Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: HD3SS3415 11 HD3SS3415 SLAS840C – MARCH 2012 – REVISED OCTOBER 2015 www.ti.com 9 Detailed Description 9.1 Overview The HD3SS3415 is a high-speed passive switch offered in an industry standard 42-pin WQFN package available in a common footprint shared by several other vendors. The device is specified to operate from a single supply voltage of 3.3 V over the full industrial temperature range of 0°C to 70°C. The HD3SS3415 is a generic 4-CH high-speed mux/demux type of switch that can be used for routing high-speed signals between two different locations on a circuit board. Although it was designed specifically to address PCI Express Gen III applications, the HD3SS3415 will also support several other high-speed data protocols with a differential amplitude of < 1800 mVpp and a common-mode voltage of < 2.0 V, as with USB 3.0 and DisplayPort 1.2. 9.2 Functional Block Diagram VDD MUX 0 B0+ B0C0+ C0- A0+ A0SEL SEL 100kO C1+ C1- SEL MUX 1 B1+ B1- A1+ A1- SEL C2+ C2- MUX 2 B2+ B2A2+ A2- C3+ C3- MUX 3 SEL B3+ B3- A3+ A3- GND 12 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: HD3SS3415 HD3SS3415 www.ti.com SLAS840C – MARCH 2012 – REVISED OCTOBER 2015 9.3 Feature Description The HD3SS3415 has a single control line (SEL Pin) which can be used to control the signal path between Port A and either Port B or Port C. Theone select input (SEL) pin of the device can easily be controlled by an available GPIO pin within a system or from a microcontroller. Table 1. MUX Pin Connections (1) PORT B OR PORT C CHANNEL CONNECTED TO PORT A CHANNEL PORT A CHANNEL SEL = L SEL = H B0+ C0+ A0+ (1) A0– B0– C0– A1+ B1+ C1+ A1– B1– C1– A2+ B2+ C2+ A2– B2– C2– A3+ B3+ C3+ A3– B3– C3– The HD3SS3415 can tolerate polarity inversions for all differential signals on Ports A, B and C. Care should be taken to ensure the same polarity is maintained on Port A vs. Port B/C. 9.4 Device Functional Modes Table 2 lists the functional modes for the HD3SS3415. Table 2. HD3SS3415 Control Logic CONTROL PIN (SEL) PORT A TO PORT B CONNECTION STATUS PORT A TO PORT C CONNECTION STATUS L (Default State) Connected Disconnected H Disconnected Connected Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: HD3SS3415 13 HD3SS3415 SLAS840C – MARCH 2012 – REVISED OCTOBER 2015 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information 10.1.1 AC Coupling Caps Many interfaces require AC coupling between the transmitter and receiver. The 0402 capacitors are the preferred option to provide AC coupling, and the 0603 size capacitors also work. The 0805 size capacitors and C-packs should be avoided. When placing AC coupling capacitors symmetric placement is best. A capacitor value of 0.1 µF is best and the value should be match for the ± signal pair. The placement should be along the TX pairs on the system board, which are usually routed on the top layer of the board. There are several placement options for the AC coupling capacitors. Because the switch requires a bias voltage, the capacitors must only be placed on one side of the switch. If they are placed on both sides of the switch, a biasing voltage should be provided. A few placement options are shown below. In Figure 11, the coupling capacitors are placed between the switch and endpoint. In this situation, the switch is biased by the system/host controller. Figure 11. AC Coupling Capacitors Between Switch Tx and Endpoint Tx In Figure 12, the coupling capacitors are placed on the host transmit pair and endpoint transmit pair. In this situation, the switch on the top is biased by the endpoint and the lower switch is biased by the host controller. Figure 12. AC Coupling Capacitors on Host Tx and Endpoint Tx 14 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: HD3SS3415 HD3SS3415 www.ti.com SLAS840C – MARCH 2012 – REVISED OCTOBER 2015 Application Information (continued) If the common-mode voltage in the system is higher than 2 V, the coupling capacitors are placed on both sides of the switch (shown in Figure 13). A biasing voltage of less than 2 V is required in this case. Figure 13. AC Coupling Capacitors on Both Sides of Switch HD3SS3415 Chipset Memory/GPU Hub Port B x2 Port C x2 Port B x2 Port C x2 x8 x16 HD3SS3415 Chipset I/O Hub HD3SS3415 iGPU GPIO Port B x2 Port C x2 x8 Graphics Card Slot Port A x2 x16 Graphics Card Slot Microprocessor HD3SS3415 10.2 Typical Application Port B x2 Port C x2 SEL Pins Figure 14. Typical Application Schematic Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: HD3SS3415 15 HD3SS3415 SLAS840C – MARCH 2012 – REVISED OCTOBER 2015 www.ti.com Typical Application (continued) 10.2.1 Design Requirements Table 3 lists the design parameters of this example. Table 3. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage range 3.3 V Decoupling capacitors 0.1 µF AC Capacitors 75 nF - 200 nF (100 nF shown) USBSS TX p and n lines require AC capacotprs. Alternate mode signals may or may not require AC capacitors 10.2.2 Detailed Design Procedure • Connect VDD and GND pins to the power and ground planes of the printed circuit board, with a 0.1-uF bypass capacitor. • Use +3.3-V TTL/CMOS logic level at SEL • Use controlled-impedance transmission media for all the differential signals • Ensure the received complimentary signals are with a differential amplitude of