INA116PAG4

® INA116 INA 116 INA 116 Ultra Low Input Bias Current INSTRUMENTATION AMPLIFIER FEATURES DESCRIPTION ● LOW INPUT BIAS CURRENT: 3fA typ The INA116 is a complete monolithic FET-input instrumentation amplifier with extremely low input bias current. Difet ® inputs and special guarding techniques yield input bias currents of 3fA at 25°C, and only 25fA at 85°C. Its 3-op amp topology allows gains to be set from 1 to 1000 by connecting a single external resistor. ● BUFFERED GUARD DRIVE PINS ● LOW OFFSET VOLTAGE: 2mV max ● HIGH COMMON-MODE REJECTION: 84dB (G = 10) ● LOW QUIESCENT CURRENT: 1mA Guard pins adjacent to both input connections can be used to drive circuit board and input cable guards to maintain extremely low input bias current. ● INPUT OVER-VOLTAGE PROTECTION: ±40V The INA116 is available in 16-pin plastic DIP and SOL-16 surface-mount packages, specified for the –40°C to +85°C temperature range. APPLICATIONS ● LABORATORY INSTRUMENTATION ● pH MEASUREMENT ● ION–SPECIFIC PROBES ● LEAKAGE CURRENT MEASUREMENT V+ 13 2 Guard INA116 – VIN 3 Over-Voltage Protection +1 A1 4 Guard 60kΩ 1 60kΩ G=1+ 50kΩ RG 25kΩ A3 RG 16 Guard + VIN Guard 11 VO 25kΩ 5 6 Over-Voltage Protection A2 60kΩ +1 60kΩ 9 Ref 7 8 V– Difet®; Burr-Brown Corporation International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ©1994 Burr-Brown Corporation SBOS034 PDS-1242B Printed in U.S.A. May, 1995 SPECIFICATIONS AT TA = +25°C, VS = ±15V, RL = 10kΩ, unless otherwise noted. INA116P, U PARAMETER CONDITIONS INPUT Offset Voltage, RTI Initial vs Temperature vs Power Supply Long-Term Stability Bias Current vs Temperature Offset Current vs Temperature Impedance, Differential Common-Mode Common-Mode Voltage Range Safe Input Voltage Common-Mode Rejection TA = +25°C TA = TMIN to TMAX VS = ±4.5V to ±18V VCM = ±11V, ∆RS = 1kΩ G=1 G = 10 G = 100 VCM = ±5V, G = 1000 NOISE Voltage Noise, RTI f = 1kHz fB = 0.1Hz to 10Hz Current Noise f = 1kHz GAIN Gain Equation Range of Gain Gain Error MIN TYP INA116PA, UA MAX ±0.5 ±0.5/G ±2 ±2/G See Typical Curve ±10 ±15/G ±50 ±100/G ±1 ±5/G ±3 ±25 See Typical Curve ±1 ±25 See Typical Curve >1015/0.2 >1015/7 (V+)–4 (V+)–2 (V–)+4 (V–)+2.4 ±40 80 84 86 86 MIN ✻ ✻ ✻ G=1 G = 10 G = 100 G = 1000 G=1 G=1 G = 10 G = 100 G = 1000 GUARD OUTPUTS Offset Voltage Output Impedance Current Drive FREQUENCY RESPONSE Bandwidth, –3dB Slew Rate Settling Time, 0.01% Output Overload Recovery POWER SUPPLY Voltage Range Current RL = 10kΩ RL = 10kΩ (V+) –1 (V–) +0.35 G=1 G = 10 G = 100 G = 1000 G = 10 to 200 10V Step, G = 1 G = 10 G = 100 G = 1000 50% Overdrive ±5 ±5/G mV ±100 ±200/G ±100 µV/V µV/mo fA ±100 fA Ω/pF Ω/pF V V V 28 2 ✻ ✻ nV/√Hz µVp-p 0.1 ✻ fA/√Hz 73 78 80 80 ✻ ±0.01 ±0.25 ±0.35 ±1.25 ±5 ±25 ±0.0005 ±0.001 ±0.001 ±0.005 1000 ±0.05 ±0.4 ±0.5 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ±10 ±100 ±0.005 ±0.005 ±0.005 ±50 ✻ ✻ ✻ ✻ ✻ (V+) –0.7 (V–) +0.2 1000 +5/–12 800 500 70 7 0.8 22 25 145 400 20 ±4.5 ±15 ±1 –40 –40 ±18 ±1.4 ✻ 85 125 ✻ ✻ 80 ✻ Specification same as INA116P NOTE: (1) Guaranteed by wafer test. (2) Temperature coefficient of the “50kΩ” term in the gain equation. ® INA116 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ dB dB dB dB ±15 650 +2/–0.05 VIN = 0V TEMPERATURE RANGE Specification Operating θJA UNITS ✻ ✻ ✻ ✻ 89 92 94 94 1+(50kΩ/RG) OUTPUT Voltage Positive Negative Load Capacitance Stability Short-Circuit Current MAX G = 1000, RS = 0Ω 1 Gain vs Temperature(1) 50kΩ Resistance(1)(2) Nonlinearity TYP 2 ✻ 0.1 ±0.5 ±0.7 ±20 ±100 ±0.01 ±0.01 ±0.01 ✻ V/V V/V % % % % ppm/°C ppm/°C % of FSR % of FSR % of FSR % of FSR mV Ω mA ✻ ✻ ✻ ✻ V V pF mA ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ kHz kHz kHz kHz V/µs µs µs µs µs µs ✻ ✻ ✻ ✻ ✻ V mA ✻ ✻ °C °C °C/W ELECTROSTATIC DISCHARGE SENSITIVITY PIN CONFIGURATION Top View DIP SOL-16 RG 1 16 RG Guard – 2 15 NC – VIN 3 14 NC Guard – 4 13 V+ Guard + 5 12 NC + VIN 6 11 VO Guard + 7 10 NC V– 8 9 This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE INFORMATION Ref NC: No Internal Connection. ABSOLUTE MAXIMUM RATINGS PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) INA116PA INA116P INA116UA INA116U 16-Pin Plastic DIP 16-Pin Plastic DIP SOL-16 Surface-Mount SOL-16 Surface-Mount 180 180 211 211 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. Supply Voltage .................................................................................. ±18V Input Voltage Range .......................................................................... ±40V Output Short-Circuit (to ground) .............................................. Continuous Operating Temperature ................................................. –40°C to +125°C Storage Temperature ..................................................... –40°C to +125°C Junction Temperature .................................................................... +150°C Lead Temperature (soldering, 10s) ............................................... +300°C The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 INA116 TYPICAL PERFORMANCE CURVES At TA = +25°C, VS = ±15V, RL = 10kΩ, unless otherwise noted. COMMON-MODE REJECTION vs FREQUENCY GAIN vs FREQUENCY 100 60 G = 1000 40 G = 100 Gain (dB) 30 20 G = 10 10 0 G=1 –10 G = 100V/V 80 70 60 G = 10V/V 50 40 30 G = 1V/V 20 10 0 –20 1k 10k 100k 1M 10 10M 100 1k 10k 100k Frequency (Hz) Frequency (Hz) POSITIVE POWER SUPPLY REJECTION vs FREQUENCY NEGATIVE POWER SUPPLY REJECTION vs FREQUENCY 120 120 100 G = 1000V/V 80 60 G = 100V/V G = 10V/V 40 G = 1V/V 20 100 Power Supply Rejection (dB) Power Supply Rejection (dB) G = 1000V/V 90 Common-Mode Rejection (dB) 50 G = 1k 80 60 G = 10 < 100 G=1 40 20 0 0 1 10 100 1k 10k 1 100k 10 100 1k 10k 100k Frequency (Hz) Frequency (Hz) INPUT BIAS CURRENT vs TEMPERATURE INPUT BIAS CURRENT vs INPUT VOLTAGE 15 1000 Input Bias Current (fA) Input Bias Current (fA) 10 5 0 –5 100 IOS IB 10 –10 –15 –15 Measurement Limit 1 –10 –5 0 5 10 –75 15 Input Voltage (V) ® INA116 4 –50 –25 0 25 50 75 100 125 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = ±15V, RL = 10kΩ, unless otherwise noted. INPUT COMMON-MODE RANGE vs OUTPUT VOLTAGE G ≥ 10 INPUT REFERRED NOISE vs FREQUENCY 10k G ≥ 10 Voltage Noise Density (nV/√ Hz) 15 G=1 G=1 5 – VD/2 0 + – VD/2 VO INA116 Ref + VCM –5 +15V G=1 –15V G=1 –10 –15 –15 G = 1V/V 1k 100 G = 1000V/V G = 10V/V Bandwidth Limit 10 –10 –5 0 5 10 15 1 10 100 Output Voltage (V) INPUT OVER-VOLTAGE V/I CHARACTERISTICS 15 G ≥ 10 2 Offset Voltage Change (µV) 3 Input Current (mA) 10k OFFSET VOLTAGE WARM-UP 4 G = 1000V/V G = 1V/V 1 0 –1 G = 1V/V G = 1000V/V –2 –3 10 G=1 5 0 –5 G=1 –10 G ≥ 10 –4 –15 –40 –30 –20 –10 0 10 20 30 40 0 5 10 15 20 25 Input Voltage (V) Time After Power Supply Turn-On (s) INPUT OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION QUIESCENT CURRENT AND SLEW RATE vs TEMPERATURE 1.6 40 26 G = 100 19 0.5 7 1.4 6 24 0.5 Quiescent Current (µA) Production Distribution (%) 1k Frequency (Hz) 38 20 G = 10 9 5 2 G=1 0.5 2 3 9 12 1 1 18 15 17 14 1.4 IQ 1.2 1.2 1.0 1.0 0.8 0.8 SR 0.6 4 4 0.6 0.5 0.4 –80 –60 –40 –20 0 20 40 Slew Rate (V/µs) Common-Mode Voltage (V) 10 60 80 –75 Offset Voltage Drift (µV/°C) –50 –25 0 25 50 75 100 0.4 125 Temperature (°C) ® 5 INA116 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = ±15V, RL = 10kΩ, unless otherwise noted. VOLTAGE NOISE, 0.1 TO 10Hz INPUT-REFERRED, G ≥ 100 32 G = 10, 100 28 G=1 24 20 16 500nV/div Peak-to-Peak Output Voltage (V) MAXIMUM OUTPUT VOLTAGE vs FREQUENCY G = 1000 12 8 4 0 100 1k 10k 100k 1M 1s/div Frequency (Hz) SMALL SIGNAL RESPONSE SMALL SIGNAL RESPONSE G=1 G=100 20mV/div 20mV/div G=10 G=1000 10µs/div 100µs/div LARGE SIGNAL RESPONSE LARGE SIGNAL RESPONSE G=1 G=100 5V/div 5V/div G=10 G=1000 100µs/div 100µs/div ® INA116 6 APPLICATIONS INFORMATION The 50kΩ term in equation 1 is the sum of the two feedback resistors of A1 and A2. These on-chip metal film resistors are laser trimmed to accurate absolute values. The accuracy and temperature coefficient of these resistors are included in the gain accuracy and drift specifications of the INA116. Figure 1 shows the connections required for basic operation of the INA116. Applications with noisy or high impedance power supplies may require decoupling capacitors close to the supply pins as shown. The stability and temperature drift of RG also affect gain. RG’s contribution to gain accuracy and drift can be directly inferred from the gain equation (1). Low resistor values required for high gain make wiring resistance important. Sockets add to the wiring resistance that will contribute additional gain error in gains of approximately 100 or greater. The output is referred to the output reference (Ref) terminal which is normally grounded. This must be a low impedance connection to assure good common-mode rejection. A resistance of 30Ω in series with this connection will cause a typical device to degrade to approximately 72dB CMR at G = 1. SETTING THE GAIN Gain of the INA116 is set by connecting a single external resistor, RG, as shown. The gain is— G = 1+ 50kΩ RG OFFSET TRIMMING The INA116 is laser trimmed for low offset voltage and offset voltage drift; most applications require no external offset adjustment. Figure 2 shows an optional circuit for trimming the output offset voltage. A voltage applied to the Ref terminal is summed at the output. Op amp A1 provides a low source impedance for the Ref terminal, assuring good common-mode rejection. (1) Commonly used gains and resistor values are shown in Figure 1. V+ 0.1µF 13 4 INA116 3 – VIN Over-Voltage Protection +1 A1 2 RFB 25kΩ 1 Input Guards See Text. R2 60kΩ R1 60kΩ A3 RG 16 6 Over-Voltage Protection Ref R3 60kΩ 8 1 2 5 10 20 50 100 200 500 1000 2000 5000 10000 VO 11 A2 +1 7 DESIRED GAIN 50kΩ RG RFB 25kΩ 5 + VIN G=1+ RG (Ω) NEAREST 1% RG (Ω) NC 50.00k 12.50k 5.556k 2.632k 1.02k 505.1 251.3 100.2 50.05 25.01 10.00 5.001 NC 49.9k 12.4k 5.62k 2.61k 1.02k 511 249 100 49.9 24.9 10 4.99 R4 60kΩ 9 0.1µF V– Also drawn in simplified form: V– IN RG V+ IN INA116 VO Ref NC: No Connection. FIGURE 1. Basic Connections. ® 7 INA116 – VIN V+ VO INA116 RG + VIN CIRCUIT BOARD LAYOUT AND ASSEMBLY Careful circuit board layout and assembly techniques are required to achieve the exceptionally low input bias current performance of the INA116. Guard terminals adjacent to both inputs make it easy to properly guard the critical input terminal layout. Since traces are not required to run between device pins, this layout is easily accomplished, even with the surface mount package. The guards should completely encircle their respective input connections—see Figure 4. Both sides of the circuit board should be guarded, even if only one side has an input terminal conductor. Route any timevarying signals away from the input terminals. Solder mask should not cover the input and guard traces since this can increase leakage. 100µA 1/2 REF200 Ref 100Ω(1) OPA131 ±10mV Adjustment Range 10kΩ(1) 100Ω(1) 100µA 1/2 REF200 NOTE: (1) For wider trim range required in high gains, scale resistor values larger V– FIGURE 2. Optional Trimming of Output Offset Voltage. INPUT BIAS CURRENT RETURN PATH Input circuitry must provide an input bias current path for proper operation. Figure 3 shows resistors R1 and R2 to provide an input current path. Without these resistors, the inputs would eventually float to a potential that exceeds the common-mode range of the INA116 and the input amplifiers would saturate. Because of its exceedingly low input bias current, improperly biased inputs may operate normally for a period of time after power is first applied, or operate intermittently. Guard Top and Bottom of Circuit Board. FIGURE 4. Circuit Board Guard Layout. After assembly, the circuit board should be cleaned. Commercial solvents should be chosen according to the soldering method and flux used. Solvents should be cleaned and replaced often. Solvent cleaning should be followed by a deionized water rinse and 85°C bake out. Crystal or Ceramic Transducer INA116 Sockets can be used, but select and evaluate them carefully for best results. Use caution when installing the INA116 in a socket. Careless handling can contaminate the plastic near the input pins, dramatically increasing leakage current. VO 100MΩ R1 100MΩ R2 A proven low leakage current assembly method is to bend the input pins outward so they do not contact the circuit board. Input connections are made in air and soldered directly to the input pin. This technique is often not practical or production-worthy. It is, however, a useful technique for evaluation and testing and provides a benchmark with which to compare other wiring techniques. The circuit board guarding techniques discussed normally reduce leakage to acceptable levels. Polarizing Voltage 100MΩ Capacitive Sensor INA116 A solid mechanical assembly is required for good results. Nearby plastic parts can be especially troublesome since a static charge can develop and the slightest motion or vibration will couple charge to the inputs. Place a Faraday shield around the whole amplifier and input connection assembly to eliminate stray fields. VO 100MΩ 100MΩ R1 100MΩ R2 FIGURE 3. Providing An Input Bias Current Path. ® INA116 8 INPUT CONNECTIONS Some applications must make high impedance input connections to external sensors or input connectors. To assure low leakage, the input should be guarded all the way to the signal source—see Figure 5. Coaxial cable can be used with the shield driven by the guard. A separate connection is required to provide a ground reference at the signal source. Triaxial cable may reduce noise pickup and provides the ground reference at the source. Drive the inner shield at guard potential and ground the outer shield. Two separate guarded lines are required if both the inverting and non-inverting inputs are brought to the source. The guard drive output current is limited to approximately +2mA/–50µA. For slow input signals the internal guard output can directly drive a cable shield. With fast input signals, however, the guard may not provide sufficient output current to rapidly charge the cable capacitance. An op amp buffer may be required as shown in Figure 6. High-Z Source Two coaxial cables and ground – VIN V + VIN 1MΩ High-Z Source Two triaxial cables – VIN V + VIN 1MΩ FIGURE 5. Input Cable Guarding Circuits. +15 Circuit Board Guard Cable 3 VIN 13 G = 10 1 150Ω INA116 5.62kΩ 11 16 VO 9 Op amp buffer helps guard cables with fast input signals— see text. 6 OPA131 8 –15 FIGURE 6. Buffered Guard Drive. Solution Ground Sample Electrode Reference Electrode FIGURE 7. pH or Ion Measurement System. ® 9 INA116 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) INA116PA NRND PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type INA116UA NRND SOIC DW 16 40 RoHS & Green NIPDAU-DCC Level-3-260C-168 HR -40 to 85 INA116PA INA116UA INA116UAG4 NRND SOIC DW 16 40 RoHS & Green NIPDAU-DCC Level-3-260C-168 HR INA116UA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of