INA118PBG4

INA118 SBOS027C – SEPTEMBER 2000 – REVISED SEPTEMBER 2022 INA118 Precision, Low-Power Instrumentation Amplifier A single external resistor sets any gain from 1 to 10000. Internal input protection can withstand up to ±40 V without damage. 1 Features • • • • • • • • • A newer version of this device is now available: INA818 Low offset voltage: 50 µV, maximum Low drift: 0.5 µV/°C, maximum Low input bias current: 5 nA, maximum High CMR: 110 dB, minimum Inputs protected to ±40 V Wide supply range: ±2.25 to ±18 V Low quiescent current: 350 µA Packages: 8-Pin plastic DIP, SO-8 The INA118 is laser-trimmed for low offset voltage (50 µV), drift (0.5 µV/°C), and high common-mode rejection (110 dB at G = 1000). The INA118 operates with power supplies as low as ±2.25 V, and quiescent current is only 350 µA, making this device an excellent choice for battery-operated systems. The INA118 is available in 8-pin plastic DIP and SO-8 surface-mount packages, and specified for the –40°C to +85°C temperature range. 2 Applications • • • • • • The upgraded INA818 offers a lower input stage offset voltage (35 µV, maximum), lower input bias current (0.5 nA maximum) and lower noise (8 nV/√Hz) at the same quiescent current. See the Device Comparison Table for a selection of precision instrumentation amplifiers from Texas Instruments. Pressure transmitter Temperature transmitter Weigh scale Electrocardiogram (ECG) Analog input module Data acquisition (DAQ) Package Information 3 Description PACKAGE(1) PART NUMBER The INA118 is a low-power, general-purpose instrumentation amplifier offering excellent accuracy. The versatile, three op amp design and small size make this device an excellent choice for a wide range of applications. Current-feedback input circuitry provides wide bandwidth, even at high gain (70 kHz at G = 100). INA118 (1) BODY SIZE (NOM) SOIC (8) 3.91 mm × 4.90 mm PDIP (8) 6.35 mm × 9.81 mm For all available packages, see the package option addendum at the end of the data sheet. V+ 7 INA118 2 – VIN Overvoltage Protection A1 1 25 k 40 k A3 RG VIN 3 6 50 k RG VO 25 k 8 + G=1+ 40 k Overvoltage Protection 5 A2 40 k 40 k
Ref 4 V– Simplified Schematic An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. INA118 www.ti.com SBOS027C – SEPTEMBER 2000 – REVISED SEPTEMBER 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Device Comparison Table...............................................4 6 Pin Configuration and Functions...................................4 7 Specifications.................................................................. 5 7.1 Absolute Maximum Ratings........................................ 5 7.2 ESD Ratings............................................................... 5 7.3 Recommended Operating Conditions.........................5 7.4 Thermal Information....................................................5 7.5 Electrical Characteristics.............................................6 7.6 Typical Characteristics................................................ 8 8 Detailed Description......................................................12 8.1 Overview................................................................... 12 8.2 Functional Block Diagram......................................... 12 8.3 Feature Description...................................................13 8.4 Device Functional Modes..........................................13 9 Application and Implementation.................................. 14 9.1 Application Information............................................. 14 9.2 Typical Application.................................................... 14 9.3 Power Supply Recommendations.............................17 9.4 Layout....................................................................... 19 10 Device and Documentation Support..........................21 10.1 Device Support....................................................... 21 10.2 Receiving Notification of Documentation Updates..21 10.3 Support Resources................................................. 21 10.4 Trademarks............................................................. 21 10.5 Electrostatic Discharge Caution..............................21 10.6 Glossary..................................................................21 11 Mechanical, Packaging, and Orderable Information.................................................................... 21 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (April 2019) to Revision C (September 2022) Page • Changed minimum supply voltage from ±1.35 V to ±2.25 V and from 2.7 V to 4.5 V throughout document......1 • Changed Applications to link to latest end-equipment on ti.com........................................................................ 1 • Changed resistors in Simplified Schematic from 60 kΩ to 40 kΩ....................................................................... 1 • Changed minimum and maximum input common-mode voltage from V– + 1.1 V and V+ – 1 V to V– + 2 V and V+ – 2 V respectively in Recommended Operating Conditions ......................................................................... 5 • Changed minimum and maximum ambient temperature from –55°C and +150°C to –40°C and +125°C respectively in Recommended Operating Conditions ........................................................................................5 • Added VCM = 0 V to test conditions below title in Electrical Characteristics ...................................................... 6 • Changed input offset voltage vs temperature test condition from TA = TMIN to TMAX to TA = –40°C to +85°C in Electrical Characteristics ................................................................................................................................... 6 • Changed input offset voltage vs power supply test condition from VS = ±1.35 V to ±18 V to VS = ±2.25 V to ±18 V in Electrical Characteristics ..................................................................................................................... 6 • Changed high-side linear input voltage range from (V+) – 1 V minimum and (V+) – 0.65 V typical to (V+) – 2 V minimum and (V+) – 1.4 V typical in Electrical Characteristics .......................................................................... 6 • Changed low-side linear input voltage range from (V–) + 1.1 V minimum and (V–) + 0.95 V typical to (V–) + 2 V minimum and (V–) + 1.2 V typical in Electrical Characteristics .......................................................................6 • Added test condition of TA = –40°C to +85°C to bias current vs temperature and offset current vs temperature in Electrical Characteristics ................................................................................................................................6 • Added test condition of TA = –40°C to +85°C to gain vs temperature and 50-kΩ resistance vs temperature in Electrical Characteristics ................................................................................................................................... 6 • Changed single supply output voltage test condition from VS = 2.7 V/0 V to V+ = 4.5 V, V– = 0 V in Electrical Characteristics ................................................................................................................................................... 6 • Deleted power supply voltage range specification from Electrical Characteristics ............................................ 6 • Deleted temperature range specifications from Electrical Characteristics .........................................................6 • Changed Figures 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-11, 7-12, 7-18, 7-19, and 7-20 in Typical Characteristics ........8 • Changed FET transistor input current limit from approximately 1.5-5 mA to 6 mA in Overview ......................12 • Deleted internal node equations in Overview and Functional Block Diagram ................................................. 12 • Changed schematic in Functional Block Diagram ........................................................................................... 12 • Changed linear input voltage range in Input Common-Mode Range and Single-Supply Operation ................13 • Changed FET transistor input current limit from approximately 1.5-5 mA to 6 mA in Input Protection ............13 • Changed resistors in Figure 9-1 from 60 kΩ to 40 kΩ in Typical Application ...................................................14 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA118 www.ti.com • INA118 SBOS027C – SEPTEMBER 2000 – REVISED SEPTEMBER 2022 Changed Figure 10-5 to use a 5-V supply voltage........................................................................................... 19 Changes from Revision A (January 2016) to Revision B (April 2019) Page • Added information about the newer, upgraded INA818 .....................................................................................1 • Added Device Comparison Table ...................................................................................................................... 4 Changes from Revision * (September 2000) to Revision A (January 2016) Page • Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................. 1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA118 3 INA118 www.ti.com SBOS027C – SEPTEMBER 2000 – REVISED SEPTEMBER 2022 5 Device Comparison Table DEVICE GAIN EQUATION RG PINS AT PIN INA818 35-µV Offset, 0.4-µV/°C VOS Drift, 8-nV/√Hz Noise, Low-Power, Precision Instrumentation Amplifier DESCRIPTION G = 1 + 50 kΩ / RG 1, 8 INA819 35-µV Offset, 0.4-µV/°C VOS Drift, 8-nV/√Hz Noise, Low-Power, Precision Instrumentation Amplifier G = 1 + 50 kΩ / RG 2, 3 INA821 35-µV Offset, 0.4-µV/°C VOS Drift, 7-nV/√Hz Noise, High-Bandwidth, Precision Instrumentation Amplifier G = 1 + 49.4 kΩ / RG 2, 3 INA828 50-µV Offset, 0.5-µV/°C VOS Drift, 7-nV/√Hz Noise, Low-Power, Precision Instrumentation Amplifier G = 1 + 50 kΩ / RG 1, 8 INA333 25-µV VOS, 0.1-µV/°C VOS Drift, 1.8-V to 5-V, RRO, 50-µA IQ, chopperstabilized INA G = 1 + 100 kΩ / RG 1, 8 PGA280 20-mV to ±10-V Programmable Gain IA With 3-V or 5-V Differential Output; Analog Supply up to ±18 V Digital programmable N/A INA159 G = 0.2 V Differential Amplifier for ±10-V to 3-V and 5-V Conversion G = 0.2 V/V N/A PGA112 Precision Programmable Gain Op Amp With SPI Digital programmable N/A 6 Pin Configuration and Functions RG 1 8 RG V–IN 2 7 V+ + IN 3 6 VO V– 4 5 Ref V Figure 6-1. P (8-Pin PDIP) and D (8-Pin SOIC) Packages, Top View Table 6-1. Pin Functions PIN NO. 4 NAME TYPE DESCRIPTION 1 RG — 2 V– IN Input Negative input 3 V+ Input Positive input IN Gain setting pin. For gains greater than 1, place a gain resistor between pin 1 and pin 8. 4 V– 5 Ref Input 6 VO Output Output 7 V+ Power Positive supply 8 RG — Power Negative supply Reference input. This pin must be driven by low impedance or connected to ground. Gain setting pin. For gains greater than 1, place a gain resistor between pin 1 and pin 8. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA118 INA118 www.ti.com SBOS027C – SEPTEMBER 2000 – REVISED SEPTEMBER 2022 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT ±18 V ±40 V 125 °C 150 °C 300 °C 125 °C Supply voltage Analog input voltage Output short-circuit (to ground) Continuous Operating temperature –40 Junction temperature Lead temperature (soldering, 10 s) Tstg (1) Storage temperature –40 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Section 7.3. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VS TA MIN NOM MAX UNIT Power supply ±2.25 ±15 ±18 V Input common-mode voltage (for VO = 0 V) V– Ambient temperature V+ +2 –40 –2 V 125 °C 7.4 Thermal Information INA118 THERMAL METRIC(1) D (SOIC) P (PDIP) UNIT 8 PINS 8 PINS RθJA Junction-to-ambient thermal resistance 115 48 °C/W RθJC(top) Junction-to-case (top) thermal resistance 62 37 °C/W RθJB Junction-to-board thermal resistance 59 25 °C/W ψJT Junction-to-top characterization parameter 14 14 °C/W ψJB Junction-to-board characterization parameter 58 25 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA118 5 INA118 www.ti.com SBOS027C – SEPTEMBER 2000 – REVISED SEPTEMBER 2022 7.5 Electrical Characteristics at TA = 25°C, VS = ±15 V, VCM = 0 V, and RL = 10 kΩ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT Offset voltage, RTI Initial TA = 25°C vs Temperature TA = –40°C to +85°C vs Power supply VS = ±2.25 V to ±18 V INA118PB, UB ±10 ± 50 / G ±50 ± 500 / G INA118P, U ±25 ±100 / G ±125 ±1000 / G INA118PB, UB ±0.2 ± 2 / G ±0.5 ± 20 / G INA118P, U ±0.2 ± 5 / G ±1 ± 20 / G INA118PB, UB ±1 ±10 / G ±5 ± 100 / G INA118P, U ±1 ±10 / G ±10 ±100 / G Long-term stability Impedance ±0.4 ±5 / G Differential 1010 Common-mode 1010 || 4 Linear input voltage (V+) – 1.4 (V–) + 2 (V–) + 1.2 Safe input voltage INA118PB, UB 80 INA118P, U 73 90 VCM = ±10 V, ΔRS = 1 kΩ, G = 10 INA118PB, UB 97 110 VCM = ±10 V, ΔRS = 1 kΩ, G = 100 INA118PB, UB VCM = ±10 V, ΔRS = 1 kΩ, G = 1000 Common-mode rejection Bias current Bias current drift Noise voltage, RTI V 89 110 120 98 120 INA118PB, UB 110 125 INA118P, U 100 125 INA118P, U G = 1000, RS = 0 Ω ±1 ±5 INA118P, U ±1 ±10 ±40 nA pA/°C INA118PB, UB ±1 ±5 INA118P, U ±1 ±10 ±40 nA pA/°C f = 10 Hz 11 nV/√Hz f = 100 Hz 10 nV/√Hz 10 nV/√Hz 0.28 µVp-p f = 1 kHz fB = 0.1 Hz to 10 Hz Noise current dB INA118PB, UB TA = –40°C to +85°C V 90 107 TA = –40°C to +85°C Offset current Offset current drift INA118P, U µV/V Ω || pF ±40 VCM = ±10 V, ΔRS = 1 kΩ, G=1 µV/°C µV/mo || 1 (V+) – 2 µV f = 10 Hz 2 f = 1 kHz 0.3 fB = 0.1 Hz to 10 Hz 80 pA/√Hz pAp-p GAIN Gain equation 1 + (50 kΩ / RG) Gain 1 Gain error 6 G=1 ±0.01% ±0.024% G = 10 ±0.02% ±0.4% G = 100 ±0.05% ±0.5% G = 1000 ±0.5% ±1% Gain drift G = 1, TA = –40°C to +85°C 50-kΩ resistance drift(1) TA = –40°C to +85°C Nonlinearity V/V 10000 V/V ±1 ±10 ppm/°C ±25 ±100 ppm/°C G=1 ±0.0003 ±0.001 G = 10 ±0.0005 ±0.002 G = 100 ±0.0005 ±0.002 G = 1000 ±0.002 ±0.01 Submit Document Feedback % of FSR Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA118 INA118 www.ti.com SBOS027C – SEPTEMBER 2000 – REVISED SEPTEMBER 2022 7.5 Electrical Characteristics (continued) at TA = 25°C, VS = ±15 V, VCM = 0 V, and RL = 10 kΩ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT Voltage: Positive RL = 10 kΩ (V+) – 1 (V+) – 0.8 Negative RL = 10 kΩ (V–) + 0.35 (V–) + 0.2 Single supply high V+ = 4.5 V, V– = 0 V(2), RL = 10 kΩ 1.8 2 Single supply low V+ = 4.5 V, V– = 0 V(2), RL = 10 kΩ 60 Load capacitance stability Short circuit current V 35 mV 1000 pF +5/–12 mA FREQUENCY RESPONSE Bandwidth, –3 dB G=1 800 G = 10 500 G = 100 70 G = 1000 Slew rate Settling time, 0.01% Overload recovery kHz 7 VO = ±10 V, G = 10 0.9 G=1 15 G = 10 15 G = 100 21 G = 1000 210 50% overdrive V/µs µs 20 µs POWER SUPPLY Current (1) (2) VIN = 0 V ±350 ±385 µA Temperature coefficient of the 50-kΩ term in the gain equation. Common-mode input voltage range is limited. See text for discussion of low power supply and single power supply operation. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA118 7 INA118 www.ti.com SBOS027C – SEPTEMBER 2000 – REVISED SEPTEMBER 2022 7.6 Typical Characteristics at TA = 25°C, VS = ±15 V (unless otherwise noted) 140 60 G = 1000 40 Common-Mode Rejection (dB) 50 G = 100 Gain (dB) 30 20 G = 10 10 0 G=1 –10 120 G=1000 100 G=100 80 G=10 60 G=1 40 20 0 –20 1k 10k 100k 1M 1 10M 10 Figure 7-1. Gain vs Frequency Input Common-Mode Voltage (V) Input Common-Mode Voltage (V) G=1 G = 100 12 8 4 0 -4 -8 -12 -15 -10 -5 0 5 Output Voltage (V) 10 15 100k G=1 G = 100 4 3 2 1 0 -1 -2 -3 -4 -5 -7.5 20 -5 -2.5 0 2.5 Output Voltage (V) 5 7.5 VS = ±5 V Figure 7-3. Input Common-Mode Range vs Output Voltage Figure 7-4. Input Common-Mode Range vs Output Voltage 5 5 VREF = 0 V VREF = 2.5 V Input Common-Mode Voltage (V) Input Common-Mode Voltage (V) 10k Figure 7-2. Common-Mode Rejection vs Frequency VS = ±15 V 4 3 2 1 0 VREF = 0V VREF = 2.5 V 4 3 2 1 0 0 1 2 3 Output Voltage (V) 4 5 0 VS = 5 V G=1 1 2 3 Output Voltage (V) 4 5 VS = 5 V G = 100 Figure 7-5. Input Common-Mode Range vs Output Voltage 8 1k 5 16 -16 -20 100 Frequency (Hz) Frequency (Hz) Figure 7-6. Input Common-Mode Range vs Output Voltage Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA118 INA118 www.ti.com SBOS027C – SEPTEMBER 2000 – REVISED SEPTEMBER 2022 7.6 Typical Characteristics (continued) 160 160 140 140 120 120 Negative Power Supply Rejection Ratio (dB) Positive Power Supply Rejection Ratio (dB) at TA = 25°C, VS = ±15 V (unless otherwise noted) 100 80 60 40 G=1 G = 10 G = 100 G = 1000 20 100 80 60 40 20 0 0 1 10 100 1k Frequency (Hz) 10k 100k Figure 7-7. Positive Power Supply Rejection vs Frequency 1 100 G=1 10 100 G = 10 G = 100, 1000 G = 1000 BW Limit 10 1 Current Noise (All Gains) 1 1 10 100 1k 10k 100k RL = 10kΩ CL = 100pF 100 0.01% 0.1% 10 0.1 1 10k 10 100 1000 Gain (V/V) Frequency (Hz) Figure 7-10. Settling Time vs Gain Figure 7-9. Input-Referred Noise Voltage vs Frequency 8 0.5 6 0.45 4 Input Current (mA) Quiescent Current (mA) 100 1k Frequency (Hz) 1000 Settling Time (µs) 1k 10 Figure 7-8. Negative Power Supply Rejection vs Frequency Input Bias Current Noise (pA/√ Hz) Input-Referred Noise Voltage (nV/√ Hz) G=1 G = 10 G = 100 G = 1000 0.4 0.35 0.3 2 0 -2 -4 0.25 0.2 -40 Unit 1 Unit 2 -20 0 20 40 60 80 Temperature ( C) 100 120 140 Figure 7-11. Quiescent Current and Slew Rate vs Temperature -6 -8 -40 -30 -20 -10 0 10 Input Voltage (V) 20 30 40 Figure 7-12. Input Bias Current vs Input Overload Voltage Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA118 9 INA118 www.ti.com SBOS027C – SEPTEMBER 2000 – REVISED SEPTEMBER 2022 7.6 Typical Characteristics (continued) at TA = 25°C, VS = ±15 V (unless otherwise noted) 5 Input Bias and Offset Current (nA) 10 Offset Voltage Change (µV) 8 6 4 G = 1000 2 0 –2 –4 –6 –8 –10 IOS 3 2 ±I b 1 0 –1 –2 –3 –4 –5 3.0 2.5 2.0 1.5 1.0 0.5 0 4 –75 –50 –25 0 Time from Power Supply Turn On (ms) Figure 7-13. Offset Voltage vs Warm-Up Time Output Voltage Swing (V) Output Voltage Swing (V) Positive VS £ ±5V (V+) –0.8 VS = ±15V (V–)+0.8 Single Power Supply, V– = 0V Ground-Referred Load (V–)+0.4 50 75 100 125 Figure 7-14. Input Bias and Offset Current vs Temperature V+ (V+) –0.4 25 Temperature (°C) Negative V+ (V+) –0.2 (V+) –0.4 (V+) –0.6 (V+) –0.8 (V+) –1 Positive +85°C +25°C –40°C RL = 10kΩ +85°C (V–) +0.4 Negative +25°C (V–) +0.2 –40°C V– V– 0 1 2 3 4 0 ±5 Output Current (mA) Figure 7-15. Output Voltage Swing vs Output Current ±15 ±20 Figure 7-16. Output Voltage Swing vs Power Supply Voltage 16 16 14 14 –|ICL| 12 10 8 6 +|ICL| 4 2 Output Amplitude (Vp) Short Circuit Current (mA) ±10 Power Supply Voltage (V) VS = 15 V VS = 5 V 12 10 8 6 4 2 0 –75 –50 –25 0 25 50 75 100 125 0 100 Temperature (°C) Figure 7-17. Output Current Limit vs Temperature 10 1k 10k Frequency (Hz) 100k 1M Figure 7-18. Maximum Output Swing vs Frequency Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA118 INA118 www.ti.com SBOS027C – SEPTEMBER 2000 – REVISED SEPTEMBER 2022 7.6 Typical Characteristics (continued) at TA = 25°C, VS = ±15 V (unless otherwise noted) -40 0.1 -60 0.01 0.001 10 -80 100 1k Frequency (Hz) 10k 0.2 -100 100k 0.1 Noise (0.1 V/div) G=1 G = 10 Total Harmonic Distortion + Noise (dB) Total Harmonic Distortion + Noise (%) 1 0 -0.1 -0.2 -5 D040 -4 -3 -2 -1 0 1 Time (1 s/div) 2 3 4 5 G = 1000 Figure 7-20. Input-Referred Noise, 0.1 Hz to 10 Hz Figure 7-19. THD + N vs Frequency G=1 G = 100 20mV/div G = 10 20mV/div G = 1000 10µs/div 100µs/div Figure 7-21. Small-Signal Response Figure 7-22. Small-Signal Response G=1 G = 100 5V/div 5V/div G = 1000 G = 10 100µs/div 100µs/div Figure 7-23. Large-Signal Response Figure 7-24. Large-Signal Response Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA118 11 INA118 www.ti.com SBOS027C – SEPTEMBER 2000 – REVISED SEPTEMBER 2022 8 Detailed Description 8.1 Overview Section 8.2 shows a simplified representation of the INA118 and provides insight into device operation. Each input is protected by two FET transistors that provide a low series resistance under normal signal conditions, thus preserving excellent noise performance. When excessive voltage is applied, these transistors limit input current to approximately 6 mA. The differential input voltage is buffered by Q1 and Q2 and impressed across RG, causing a signal current to flow through RG, R1, and R2. The output difference amp, A3, removes the common-mode component of the input signal and refers the output signal to the Ref pin. 8.2 Functional Block Diagram 10 µA V 10 µA B + – VO = G • (VIN – VIN) Input Bias Current Compensation Output Swing Range: (V+) – 0.8 V to (V–) + 0.35 V A2 A1 C1 40 k C2 40 k
40 k A3 VO 40 k – Ref VIN Q1 R1 25 k R2 25 k Q2 RG VD/2 (External) VCM VD/2 + VIN 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA118 www.ti.com INA118 SBOS027C – SEPTEMBER 2000 – REVISED SEPTEMBER 2022 8.3 Feature Description The INA118 input sections use junction field effect transistors (JFET) connected to provide protection up to ±40 V. The current-feedback architecture provides maximum bandwidth over the full range of gain settings. 8.4 Device Functional Modes 8.4.1 Noise Performance The INA118 provides low noise in most applications. For differential source impedances less than 1 kΩ, the INA103 may provide lower noise. For source impedances greater than 50 kΩ, the INA111 FET-input instrumentation amplifier may provide lower noise. The low-frequency noise of the INA118 is approximately 0.28 µVPP, measured from 0.1 Hz to 10 Hz (G ≥ 100). The INA118 provides dramatically improved noise performance when compared to state-of-the-art, chopperstabilized amplifiers. 8.4.2 Input Common-Mode Range The linear input voltage range of the input circuitry of the INA118 is from approximately 1.4-V less than the positive supply voltage to 1.2-V greater than the negative supply. As a differential input voltage causes the output voltage to increase, however, the linear input range is limited by the output voltage swing of amplifiers A1 and A2. Thus, the linear common-mode input range is related to the output voltage of the complete amplifier. This behavior also depends on supply voltage; see also Figure 7-6. Input-overload can produce an output voltage that appears normal. For example, if an input overload condition drives both input amplifiers to their positive output swing limit, the difference voltage measured by the output amplifier is near zero. In this case, the output of the INA118 is near 0 V even though both inputs are overloaded. 8.4.3 Input Protection The inputs of the INA118 are individually protected for voltages up to ±40 V. For example, a condition of –40 V on one input and +40 V on the other input does not cause damage. Internal circuitry on each input provides low series impedance under normal signal conditions. To provide equivalent protection, series input resistors contribute excessive noise. If the input is overloaded, the protection circuitry limits the input current to a safe value of approximately 6 mA. Figure 7-12 shows this input current limit behavior. The inputs are protected even if the power supplies are disconnected or turned off. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA118 13 INA118 www.ti.com SBOS027C – SEPTEMBER 2000 – REVISED SEPTEMBER 2022 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information The INA118 measures a small differential voltage with a high common-mode voltage developed between the noninverting and inverting input. The high common-mode rejection makes the INA118 an excellent choice for a wide range of applications. The ability to set the reference pin to adjust the functionality of the output signal offers additional flexibility that is practical for multiple configurations. 9.2 Typical Application Figure 9-1 shows the basic connections required for operation of the INA118. Applications with noisy or high impedance power supplies can require decoupling capacitors close to the device pins, as shown. The output is referred to the output reference (Ref) pin, which is normally grounded. This connection must be low-impedance to maintain good common-mode rejection. A resistance of 12 Ω in series with the Ref pin causes a typical device to degrade to approximately 80-dB CMR (G = 1). Figure 9-1 depicts an input signal with a 5-mV, 1-kHz signal with a 1-VPP common-mode signal, a condition often observed in process-control systems. Figure 9-2 depicts the output of the INA118 (G = 250) depicting the clean recovered 1-kHz waveform. V+ 0.1 µF 7 INA118 – VIN DESIRED GAIN RG ( ) NEAREST 1% RG (
) 1 2 5 10 20 50 100 200 500 1000 2000 5000 10000 NC 50.00k 12.50k 5.556k 2.632k 1.02k 505.1 251.3 100.2 50.05 25.01 10.00 5.001 NC 49.9k 12.4k 5.62k 2.61k 1.02k 511 249 100 49.9 24.9 10 4.99 2 Overvoltage Protection A1 W 1 25 k 40 k 40 k – + – VIN ) VO = G • (VIN G=1+ A3 RG 6 + 25 k 8 50 k RG Load VO – + VIN 3 5 A2 Overvoltage Protection 40 k 4 40 k Ref 0.1 µF NC: No Connection. V– Also drawn in simplified form: – VIN RG + VIN INA118 VO Ref Figure 9-1. Basic Connections 14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA118 INA118 www.ti.com SBOS027C – SEPTEMBER 2000 – REVISED SEPTEMBER 2022 9.2.1 Design Requirements Figure 9-5 and Figure 9-4 depict the performance of a typical application of the INA118 in a shop floor-vibration sensing application. Industrial process control systems often involve the interconnecting of multiple subsystems; therefore, ground loops are frequently encountered, and often are not easily solved. The inherent common-mode rejection of instrumentation amplifiers enables accurate measurements even in the presence of ground-loop potentials. The typical application was tested in a system with these requirements: • Transducer signal ≈ 5 mVPP • Transducer center frequency = 1 kHz • Common-mode signal (required to be rejected): 1 VPP at 60 Hz 9.2.2 Detailed Design Procedure 9.2.2.1 Setting the Gain As shown in Equation 1, the gain of the INA118 is set by connecting a single external resistor, RG, connected between pins 1 and 8. G = 1 + 50R kΩ (1) G Commonly used gains and resistor values are shown in Figure 9-1. The 50-kΩ term in Equation 1 comes from the sum of the two internal feedback resistors of A1 and A2. These on-chip metal film resistors are laser-trimmed to accurate absolute values. The accuracy and temperature coefficient of these resistors are included in the gain accuracy and drift specifications of the INA118. The stability and temperature drift of the external gain setting resistor, RG, also affects gain. The contribution of RG to gain accuracy and drift can be directly inferred from Equation 1. Low resistor values required for high gain can make wiring resistance important. Sockets add to the wiring resistance, which contributes additional gain error (possibly an unstable gain error) in gains of approximately 100 or greater. 9.2.2.2 Dynamic Performance Figure 7-1 shows that, despite a low quiescent current, the INA118 achieves wide bandwidth, even at high gain. This achievement is due to the current-feedback topology of the INA118. Settling time also remains excellent at high gain. The INA118 exhibits approximately 3-dB peaking at 500 kHz in unity gain. This peaking is a result of the current-feedback topology and is not an indication of instability. Unlike an op amp with poor phase margin, the rise in response is a predictable 6-dB/octave due to a zero in the amplifier response. A simple pole at 300 kHz or less produces a flat pass-band unity gain response. 9.2.2.3 Offset Trimming The INA118 is laser-trimmed for low offset voltage and drift. Most applications require no external offset adjustment. Figure 9-2 shows an optional circuit for trimming the output offset voltage. The voltage applied to the Ref pin is summed at the output. The op amp buffer provides low impedance at the Ref pin to preserve good common-mode rejection. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA118 15 INA118 www.ti.com SBOS027C – SEPTEMBER 2000 – REVISED SEPTEMBER 2022 – VIN V+ RG INA118 VO 100µA 1/2 REF200 Ref + VIN OPA177 ±10mV Adjustment Range 100Ω 10kΩ 100Ω 100µA 1/2 REF200 V– Figure 9-2. Optional Trimming of Output Offset Voltage 9.2.2.4 Input Bias Current Return Path The input impedance of the INA118 is extremely high at approximately 1010 Ω. However, a path must be provided for the input bias current of both inputs. This input bias current is approximately ±5 nA. High input impedance means that this input bias current changes very little with varying input voltage. Input circuitry must provide a path for this input bias current for proper operation. Figure 9-3 shows various provisions for an input bias current path. Without a bias current path, the inputs float to a potential which exceeds the common-mode range of the INA118, and the input amplifiers saturates. If the differential source resistance is low, the bias current return path can be connected to one input (see the thermocouple example in Figure 9-3). With higher source impedance, using two equal resistors provides a balanced input, with the possible advantages of lower input offset voltage due to bias current, and better high-frequency common-mode rejection. Microphone, Hydrophone etc. INA118 47kΩ 47kΩ Thermocouple INA118 10kΩ INA118 Center-tap provides bias current return. Figure 9-3. Providing an Input Common-Mode Current Path 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA118 INA118 www.ti.com SBOS027C – SEPTEMBER 2000 – REVISED SEPTEMBER 2022 9.2.3 Application Curves 1-kHz differential signal is also present but cannot be seen in this waveform. Figure 9-4. Input of Typical Application Showing 60-Hz Common-Mode Signal Figure 9-5. Output of Typical Application Shows Desired 1-kHz Waveform With Common-Mode Interference Rejected 9.3 Power Supply Recommendations 9.3.1 Low-Voltage Operation The INA118 operates on power supplies as low as ±2.25 V. Performance of the INA118 remains excellent with power supplies ranging from ±2.25 V to ±18 V. Most parameters vary only slightly throughout this supply voltage range; see also Section 7.6. Operation at low supply voltage requires careful attention to make sure that the input voltages remain within the respective linear range. Voltage swing requirements of internal nodes limit the input common-mode range with low power supply voltage. Figure 7-3 shows the range of linear operation for a various supply voltages and gains. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA118 17 INA118 www.ti.com SBOS027C – SEPTEMBER 2000 – REVISED SEPTEMBER 2022 V+ – VIN + RG VO INA118 10.0V 6 REF102 Ref R1 1MΩ C1 0.1µF R1 2 R2 4 Pt100 1 f–3dB = 2πR1C1 OPA602 Cu K = 1.59Hz Cu Figure 9-6. AC-Coupled Instrumentation Amplifier RG Ref R3 100Ω = RTD at 0°C ISA TYPE MATERIAL VO INA118 COEFFICIENT (µV/°C) R1 , R 2 E + Chromel – Constantan 58.5 66.5kΩ J + Iron – Constantan 50.2 76.8kΩ K + Chromel – Alumel 39.4 97.6kΩ T + Copper – Constantan 38.0 102kΩ Figure 9-7. Thermocouple Amplifier With Cold Junction Compensation – VIN R1 RG IO = INA118 VIN •G R1 2.8kΩ LA RG/2 RA + VO INA118 Ref Ref 2.8kΩ IB G = 10 390kΩ A1 IO 1/2 OPA2604 RL 1/2 OPA2604 10kΩ 390kΩ Load A1 IB Error OPA177 OPA602 OPA128 –1.5nA –1pA –75fA Figure 9-9. ECG Amplifier With Right-Leg Drive Figure 9-8. Differential Voltage to Current Converter 18 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA118 INA118 www.ti.com SBOS027C – SEPTEMBER 2000 – REVISED SEPTEMBER 2022 9.3.2 Single-Supply Operation The INA118 can be used on single power supplies of 4.5 V to 36 V. Figure 9-10 shows a basic single-supply circuit. The output Ref pin is connected to ground. Zero differential input voltage demands an output voltage of 0 V (ground). The actual output voltage swing is limited to approximately 35-mV above ground, when the load is referred to ground as shown. Figure 7-15 shows how the output voltage swing varies with output current. With single supply operation, V+ IN and V – IN must be 1.2-V greater than ground for linear operation. Connecting the inverting input to ground and measuring a voltage connected to the noninverting input is not possible. To illustrate the issues affecting low-voltage operation, consider the circuit in Figure 9-10, which shows the INA118 operating from a single 5-V supply. Depending on the desired gain, a resistor in series with the high side of the bridge can be required to make sure that the bridge output voltage is within the common-mode range of the amplifier inputs. See Figure 7-5 for 5-V single supply operation. 5V 5V R1(1) 2.5V – DV 300
RG VO INA118 Ref 2.5V + DV NOTE: (1) R1 may be required to create proper common-mode voltage, for low voltage operation with certain gains — see text. Figure 9-10. Single-Supply Bridge Amplifier 9.4 Layout 9.4.1 Layout Guidelines TI always recommends paying attention to good layout practices. For best operational performance of the device, use good printed-circuit-board (PCB) layout practices, including: • Make sure that both input paths are well-matched for source impedance and capacitance to avoid converting common-mode signals into differential signals. In addition, parasitic capacitance at the gain-setting pins can also affect CMRR over frequency. For example, in applications that implement gain switching using switches or PhotoMOS® relays to change the value of RG, select the component so that the switch capacitance is as small as possible. • Noise can propagate into analog circuitry through the power pins of the circuit as a whole, and of the individual device. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply applications. • Separate grounding for analog and digital portions of the circuitry is one of the simplest and most effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current. • To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in parallel with the noisy trace. • Keep the traces as short as possible. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA118 19 INA118 www.ti.com SBOS027C – SEPTEMBER 2000 – REVISED SEPTEMBER 2022 9.4.2 Layout Example Gain Resistor Bypass Capacitor RG RG VIN V-IN V+ VIN V+IN VO V- Ref - + V+ VOUT GND Bypass Capacitor V- GND Figure 9-11. Layout Recommendation 20 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA118 INA118 www.ti.com SBOS027C – SEPTEMBER 2000 – REVISED SEPTEMBER 2022 10 Device and Documentation Support 10.1 Device Support 10.1.1 Development Support Table 10-1. Design Kits and Evaluation Modules NAME PART NUMBER TYPE DIP adapter evaluation module DIP-ADAPTER-EVM Evaluation modules and boards Universal instrumentation amplifier evaluation module INAEVM Evaluation modules and boards Table 10-2. Development Tools DESCRIPTION PART NUMBER TYPE Analog engineer's calculator ANALOG-ENGINEER-CALC Calculation tool TINA-TI™ software: SPICE-based analog simulation program TINA-TI Circuit design and simulation PSpice® for TI design and simulation tool PSPICE-FOR-TI Circuit design and simulation 10.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.4 Trademarks TINA-TI™ and TI E2E™ are trademarks of Texas Instruments. PhotoMOS® is a registered trademark of Panasonic Corporation. PSpice® is a registered trademark of Cadence Design Systems, Inc. All trademarks are the property of their respective owners. 10.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA118 21 PACKAGE OPTION ADDENDUM www.ti.com 11-Feb-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) INA118P ACTIVE PDIP P 8 50 RoHS & Green Call TI N / A for Pkg Type -40 to 85 INA118P INA118PB ACTIVE PDIP P 8 50 RoHS & Green Call TI N / A for Pkg Type INA118U ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR INA 118U INA118U/2K5 ACTIVE SOIC D 8 2500 RoHS & Green Call TI Level-3-260C-168 HR INA 118U INA118U/2K5G4 ACTIVE SOIC D 8 2500 RoHS & Green Call TI Level-3-260C-168 HR INA 118U INA118UB ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR INA 118U B INA118UB/2K5 ACTIVE SOIC D 8 2500 RoHS & Green Call TI Level-3-260C-168 HR INA 118U B INA118UBG4 ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR INA 118U B INA118UG4 ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR INA 118U INA118P B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of