INA118UB

Product Folder Order Now Support & Community Tools & Software Technical Documents INA118 SBOS027B – SEPTEMBER 2000 – REVISED APRIL 2019 INA118 Precision, Low-Power Instrumentation Amplifier A newer version of this device is now available: INA818 1 Features 3 Description • The INA118 is a low-power, general-purpose instrumentation amplifier offering excellent accuracy. The versatile, three op amp design and small size make this device an excellent choice for a wide range of applications. Current-feedback input circuitry provides wide bandwidth, even at high gain (70 kHz at G = 100). 1 • • • • • • • • A newer version of this device is now available: INA818 Low offset voltage: 50 µV, maximum Low drift: 0.5 µV/°C, maximum Low input bias current: 5 nA, maximum High CMR: 110 dB, minimum Inputs protected to ±40 V Wide supply range: ±1.35 to ±18 V Low quiescent current: 350 µA Packages: 8-Pin plastic DIP, SO-8 A single external resistor sets any gain from 1 to 10000. Internal input protection can withstand up to ±40 V without damage. The INA118 is laser-trimmed for low offset voltage (50 µV), drift (0.5 µV/°C), and high common-mode rejection (110 dB at G = 1000). The INA118 operates with power supplies as low as ±1.35 V, and quiescent current is only 350 µA, making this device an excellent choice for battery-operated systems. 2 Applications • • • • • Bridge amplifiers Thermocouple amplifiers RTD Sensor amplifiers Medical instrumentation Data acquisition The INA118 is available in 8-pin plastic DIP and SO-8 surface-mount packages, and specified for the –40°C to +85°C temperature range. The upgraded INA818 offers a lower input stage offset voltage (35 µV, maximum), lower input bias current (0.5 nA maximum) and lower noise (8 nV/√Hz) at the same quiescent current. See the Device Comparison Table for a selection of precision instrumentation amplifiers from Texas Instruments. Device Information(1) PART NUMBER INA118 PACKAGE BODY SIZE (NOM) SOIC (8) 3.91 mm × 4.90 mm PDIP (8) 6.35 mm × 9.81 mm (1) For all available packages, see the package option addendum at the end of the data sheet. Simplified Schematic V+ 7 2 – VIN Over-Voltage Protection INA118 A1 60kΩ 1 G=1+ 60kΩ 50kΩ RG 25kΩ A3 RG 8 + VIN 3 6 VO 25kΩ Over-Voltage Protection 5 A2 60kΩ Ref 60kΩ 4 V– 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. A newer version of this device is now available: INA818 INA118 SBOS027B – SEPTEMBER 2000 – REVISED APRIL 2019 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 5 7.1 7.2 7.3 7.4 7.5 7.6 5 5 5 5 6 8 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 12 8.1 8.2 8.3 8.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 12 12 13 13 9 Application and Implementation ........................ 14 9.1 Application Information............................................ 14 9.2 Typical Application ................................................. 14 10 Power Supply Recommendations ..................... 18 10.1 Low-Voltage Operation ......................................... 18 10.2 Single-Supply Operation ....................................... 19 11 Layout................................................................... 20 11.1 Layout Guidelines ................................................. 20 11.2 Layout Example .................................................... 21 12 Device and Documentation Support ................. 22 12.1 12.2 12.3 12.4 12.5 12.6 Device Support .................................................... Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 22 22 22 22 22 22 13 Mechanical, Packaging, and Orderable Information ........................................................... 22 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (January 2016) to Revision B Page • Added information about the newer, upgraded INA818 ........................................................................................................ 1 • Added Device Comparison Table........................................................................................................................................... 3 Changes from Original (September 2000) to Revision A • 2 Page Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .............................................................. 1 Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated Product Folder Links: INA118 A newer version of this device is now available: INA818 INA118 www.ti.com SBOS027B – SEPTEMBER 2000 – REVISED APRIL 2019 5 Device Comparison Table DEVICE GAIN EQUATION RG PINS AT PIN INA818 35-µV Offset, 0.4 µV/°C VOS Drift, 8-nV/√Hz Noise, Low-Power, Precision Instrumentation Amplifier DESCRIPTION G = 1 + 50 kΩ / RG 1, 8 INA819 35-µV Offset, 0.4 µV/°C VOS Drift, 8-nV/√Hz Noise, Low-Power, Precision Instrumentation Amplifier G = 1 + 50 kΩ / RG 2, 3 INA821 35-µV Offset, 0.4 µV/°C VOS Drift, 7-nV/√Hz Noise, HighBandwidth, Precision Instrumentation Amplifier G = 1 + 49.4 kΩ / RG 2, 3 INA828 50-µV Offset, 0.5 µV/°C VOS Drift, 7-nV/√Hz Noise, Low-Power, Precision Instrumentation Amplifier G = 1 + 50 kΩ / RG 1, 8 INA333 25-µV VOS, 0.1 µV/°C VOS Drift, 1.8-V to 5-V, RRO, 50-µA IQ, chopper-stabilized INA G = 1 + 100 kΩ / RG 1, 8 PGA280 20-mV to ±10-V Programmable Gain IA With 3-V or 5-V Differential Output; Analog Supply up to ±18 V Digital programmable N/A INA159 G = 0.2 V Differential Amplifier for ±10-V to 3-V and 5-V Conversion G = 0.2 V/V N/A PGA112 Precision Programmable Gain Op Amp With SPI Digital programmable N/A Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated Product Folder Links: INA118 3 A newer version of this device is now available: INA818 INA118 SBOS027B – SEPTEMBER 2000 – REVISED APRIL 2019 www.ti.com 6 Pin Configuration and Functions P and D Packages 8-Pin PDIP and SOIC Top View RG 1 8 RG V–IN 2 7 V+ + IN 3 6 VO V– 4 5 Ref V Pin Functions PIN NO. NAME I/O DESCRIPTION 1 RG — 2 V–IN I Negative input 3 + I Positive input V IN Gain setting pin. For gains greater than 1, place a gain resistor between pin 1 and pin 8. 4 V– — 5 Ref I Reference input. This pin must be driven by low impedance or connected to ground. 6 VO O Output 7 V+ — Positive supply 8 RG — Gain setting pin. For gains greater than 1, place a gain resistor between pin 1 and pin 8. 4 Negative supply Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated Product Folder Links: INA118 A newer version of this device is now available: INA818 INA118 www.ti.com SBOS027B – SEPTEMBER 2000 – REVISED APRIL 2019 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT ±18 V ±40 V 125 °C Junction temperature 150 °C Lead temperature (soldering, 10 s) 300 °C 125 °C Supply voltage Analog input voltage Output short-circuit (to ground) Continuous Operating temperature Tstg (1) –40 Storage temperature –40 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) V Power supply VO = 0 Input common-mode voltage TA Ambient temperature MIN NOM MAX UNIT ±2.25 ±15 ±18 V V– + 1.1 V+ – 1 V –55 150 °C 7.4 Thermal Information INA118 THERMAL METRIC (1) D (SOIC) P (PDIP) 8 PINS 8 PINS UNIT RθJA Junction-to-ambient thermal resistance 115 48 °C/W RθJC(top) Junction-to-case (top) thermal resistance 62 37 °C/W RθJB Junction-to-board thermal resistance 59 25 °C/W ψJT Junction-to-top characterization parameter 14 14 °C/W ψJB Junction-to-board characterization parameter 58 25 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated Product Folder Links: INA118 5 A newer version of this device is now available: INA818 INA118 SBOS027B – SEPTEMBER 2000 – REVISED APRIL 2019 www.ti.com 7.5 Electrical Characteristics at TA = 25°C, VS = ±15 V, and RL = 10 kΩ (unless otherwise noted_ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT Offset voltage, RTI Initial TA = 25°C vs Temperature TA = TMIN to TMAX vs Power supply VS = ±1.35 V to ±18 V INA118PB, UB ±10 ± 50/G ±50 ± 500/G INA118P, U ±25 ±100/G ±125±1000/G INA118PB, UB ±0.2 ± 2/G ±0.5 ± 20/G INA118P, U ±0.2 ± 5/G ±1 ± 20/G INA118PB, UB ±1 ±10/G ±5 ± 100/G INA118P, U ±1 ±10/G ±10 ±100/G Long-term stability ±0.4 ±5/G 10 Differential 10 Common-mode 1010 || 4 Impedance Linear input voltage range (V+) – 0.65 – (V ) + 1.1 (V–) + 0.95 90 Safe input voltage INA118PB, UB 80 INA118P, U 73 90 VCM = ±10 V, ΔRS = 1 kΩ, G = 10 INA118PB, UB 97 110 VCM = ±10 V, ΔRS = 1 kΩ, G = 100 INA118PB, UB VCM = ±10 V, ΔRS = 1 kΩ, G = 1000 INA118PB, UB INA118P, U 100 125 Common-mode rejection Bias current INA118P, U INA118P, U 89 110 107 120 98 120 110 125 ±1 ±5 INA118P, U ±1 ±10 ±1 ±5 INA118P, U ±1 ±10 f = 10 Hz f = 100 Hz f = 1 kHz G = 1000, RS = 0 Ω fB = 0.1 Hz to 10 Hz Noise current nA pA/°C INA118PB, UB vs Temperature V dB ±40 Offset current Noise voltage, RTI V INA118PB, UB vs Temperature µV/V Ω || pF ±40 VCM = ±10 V, ΔRS = 1 kΩ, G=1 µV/°C µV/mo || 1 (V+) – 1 µV nA ±40 pA/°C 11 nV/√Hz 10 nV/√Hz 10 nV/√Hz 0.28 µVp-p f = 10 Hz 2 f = 1 kHz 0.3 fB = 0.1 Hz to 10 Hz 80 pA/√Hz pAp-p GAIN Gain equation 1 + (50 kΩ/RG) Range of gain Gain error Gain vs temperature 1 G=1 ±0.01% ±0.024% G = 10 ±0.02% ±0.4% G = 100 ±0.05% ±0.5% G = 1000 ±0.5% ±1% G=1 (1) 6 V/V ±1 ±10 ppm/°C ±25 ±100 ppm/°C G=1 ±0.0003 ±0.001 G = 10 ±0.0005 ±0.002 G = 100 ±0.0005 ±0.002 G = 1000 ±0.002 ±0.01 50-kΩ resistance (1) Nonlinearity V/V 10000 % of FSR Temperature coefficient of the 50-kΩ term in the gain equation. Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated Product Folder Links: INA118 A newer version of this device is now available: INA818 INA118 www.ti.com SBOS027B – SEPTEMBER 2000 – REVISED APRIL 2019 Electrical Characteristics (continued) at TA = 25°C, VS = ±15 V, and RL = 10 kΩ (unless otherwise noted_ PARAMETER TEST CONDITIONS MIN TYP (V+) – 1 (V+) – 0.8 (V ) + 0.35 (V–) + 0.2 MAX UNIT OUTPUT Positive Voltage: Negative Single supply high Single supply low RL = 10 kΩ – VS = 2.7 V/0 V (2), RL = 10 kΩ 1.8 2 60 35 Load capacitance stability Short circuit current V mV 1000 pF +5/–12 mA FREQUENCY RESPONSE Bandwidth, –3 dB G=1 800 G = 10 500 G = 100 70 G = 1000 Slew rate Settling time, 0.01% Overload recovery kHz 7 VO = ±10 V, G = 10 0.9 G=1 15 G = 10 15 G = 100 21 G = 1000 210 50% Overdrive V/µs µs 20 µs POWER SUPPLY Voltage range Current ±1.35 VIN = 0 V ±15 ±18 V ±350 ±385 µA TEMPERATURE RANGE Specification –40 85 °C Operating –40 125 °C (2) Common-mode input voltage range is limited. See text for discussion of low power supply and single power supply operation. Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated Product Folder Links: INA118 7 A newer version of this device is now available: INA818 INA118 SBOS027B – SEPTEMBER 2000 – REVISED APRIL 2019 www.ti.com 7.6 Typical Characteristics at TA = 25°C, VS = ±15 V (unless otherwise noted) 140 60 G = 1000 Gain (dB) 40 Common-Mode Rejection (dB) 50 G = 100 30 20 G = 10 10 0 G=1 –10 120 G=1000 100 G=100 80 G=10 60 G=1 40 20 0 –20 1k 10k 100k 1M 1 10M 10 100 Figure 1. Gain vs Frequency G ‡ 10 10 G=1 G=1 5 VD/2 VD/2 –5 + – –15 –15 VO INA118 Ref + VCM –10 +15V – –15V All Gains –10 All Gains –5 0 5 G=1 2 15 G=1 +5V 1 VD/2 0 VD/2 –1 – + – VO INA118 Ref + VCM –2 –5V –3 –5 –5 All Gains –4 –3 All Gains –2 –1 0 1 2 3 4 5 Output Voltage (V) Output Voltage (V) Figure 3. Input Common-Mode Range vs Output Voltage Figure 4. Input Common-Mode Range vs Output Voltage 3 G ‡ 10 4 G=2 3 G=1 Single Supply 2 +5V VD/2 VD/2 1 – + – VO INA118 Ref + Common-Mode Voltage (V) 5 Common-Mode Voltage (V) 3 –4 10 G ‡ 10 G ‡ 10 4 Common-Mode Voltage (V) Common-Mode Voltage (V) G ‡ 10 0 100k Figure 2. Common-Mode Rejection vs Frequency 5 15 G ‡ 10 2 G=1 Single Supply +3V VD/2 1 VD/2 – + – + VO INA118 Ref VCM VCM 0 0 0 8 10k 1k Frequency (Hz) Frequency (Hz) 1 2 3 4 5 0 1 2 3 Output Voltage (V) Output Voltage (V) Figure 5. Input Common-Mode Range vs Output Voltage Figure 6. Input Common-Mode Range vs Output Voltage Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated Product Folder Links: INA118 A newer version of this device is now available: INA818 INA118 www.ti.com SBOS027B – SEPTEMBER 2000 – REVISED APRIL 2019 Typical Characteristics (continued) 160 160 140 140 120 100 G = 1000 80 G = 100 60 G = 10 40 G = 1000 Power Supply Rejection (dB) Power Supply Rejection (dB) at TA = 25°C, VS = ±15 V (unless otherwise noted) G=1 120 G = 100 100 G = 10 80 G=1 60 40 20 20 0 0 1 10 100 1k 10k 10 100k 100 1k 100 10 G = 10 G = 100, 1000 G = 1000 BW Limit 1 Current Noise (All Gains) 1 10 100 Figure 8. Negative Power Supply Rejection vs Frequency Settling Time (µs) G=1 100 1 100k 1000 Input Bias Current Noise (pA/√ Hz) Input-Referred Noise Voltage (nV/√ Hz) Figure 7. Positive Power Supply Rejection vs Frequency 1k 10 10k Frequency (Hz) Frequency (Hz) RL = 10kΩ CL = 100pF 100 0.1% 0.1 1k 0.01% 10 10k 1 10 100 1000 Gain (V/V) Frequency (Hz) Figure 9. Input-Referred Noise Voltage vs Frequency 500 Figure 10. Settling Time vs Gain 1.5 10 S 400 IQ 1 VS = ±15V 300 0.5 VS = ±1.35V Input Bias Current (mA) ate lew R Slew Rate (V/µs) Quiescent Current (µA) 8 6 4 2 G = 1000 G=1 0 –2 G=1 –4 G = 1000 –6 –8 200 –75 –50 –25 0 25 50 75 100 0 125 –10 –40 0 40 Overload Voltage (V) Temperature (°C) Figure 11. Quiescent Current and Slew Rate vs Temperature Figure 12. Input Bias Current vs Input Overload Voltage Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated Product Folder Links: INA118 9 A newer version of this device is now available: INA818 INA118 SBOS027B – SEPTEMBER 2000 – REVISED APRIL 2019 www.ti.com Typical Characteristics (continued) at TA = 25°C, VS = ±15 V (unless otherwise noted) 5 Input Bias and Offset Current (nA) 10 Offset Voltage Change (µV) 8 6 4 G = 1000 2 0 –2 –4 –6 –8 –10 1.0 0.5 0 IOS 3 2 ±I b 1 0 –1 –2 –3 –4 –5 3.0 2.5 2.0 1.5 4 –75 –50 –25 0 Time from Power Supply Turn On (ms) Figure 13. Offset Voltage vs Warm-Up Time Output Voltage Swing (V) Output Voltage Swing (V) Positive VS £ ±5V (V+) –0.8 VS = ±15V (V–)+0.8 Single Power Supply, V– = 0V Ground-Referred Load (V–)+0.4 Negative V+ (V+) –0.2 (V+) –0.4 (V+) –0.6 (V+) –0.8 (V+) –1 100 125 +85°C +25°C –40°C RL = 10kΩ +85°C Negative +25°C (V–) +0.2 –40°C V– 0 1 2 3 4 0 ±5 Output Current (mA) 10 8 6 +|ICL| 2 0 Peak-to-Peak Output Voltage (V) –|ICL| 12 4 ±15 ±20 Figure 16. Output Voltage Swing vs Power Supply Voltage 16 14 ±10 Power Supply Voltage (V) Figure 15. Output Voltage Swing vs Output Current Short Circuit Current (mA) 75 Positive (V–) +0.4 V– 32 G = 10, 100 28 G=1 24 20 16 G = 1000 12 8 4 0 –75 10 50 Figure 14. Input Bias and Offset Current vs Temperature V+ (V+) –0.4 25 Temperature (°C) –50 –25 0 25 50 75 100 125 100 1k 10k 100k 1M Temperature (°C) Frequency (Hz) Figure 17. Output Current Limit vs Temperature Figure 18. Maximum Output Swing vs Frequency Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated Product Folder Links: INA118 A newer version of this device is now available: INA818 INA118 www.ti.com SBOS027B – SEPTEMBER 2000 – REVISED APRIL 2019 Typical Characteristics (continued) at TA = 25°C, VS = ±15 V (unless otherwise noted) 1 THD + N (%) G = 10 0.1 RL =1 0k Ω 0.1µV/div 0.01 RL = ∞ (Noise Floor) 0.001 20 100 1k 10k 20k 1s/div Frequency (Hz) Figure 19. THD + N vs Frequency Figure 20. Input-Referred Noise, 0.1 Hz to 10 Hz G=1 G = 100 20mV/div G = 10 20mV/div G = 1000 10µs/div 100µs/div \ Figure 22. Small-Signal Response Figure 21. Small-Signal Response G=1 G = 100 5V/div 5V/div G = 1000 G = 10 100µs/div 100µs/div Figure 23. Large-Signal Response Figure 24. Large-Signal Response Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated Product Folder Links: INA118 11 A newer version of this device is now available: INA818 INA118 SBOS027B – SEPTEMBER 2000 – REVISED APRIL 2019 www.ti.com 8 Detailed Description 8.1 Overview Figure 25 shows a simplified representation of the INA118 and provides insight into its operation. Each input is protected by two FET transistors that provide a low series resistance under normal signal conditions, preserving excellent noise performance. When excessive voltage is applied, these transistors limit input current to approximately 1.5 to 5 mA. The differential input voltage is buffered by Q1 and Q2 and impressed across RG, causing a signal current to flow through RG, R1 and R2. The output difference amp, A3, removes the common-mode component of the input signal and refers the output signal to the Ref terminal. The equations in Figure 25 describe the output voltages of A1 and A2. The VBE and IR drop across R1 and R2 produce output voltages on A1 and A2 that are approximately 1-V lower than the input voltages. 8.2 Functional Block Diagram A1 Out = VCM – VBE – (10µA • 25kΩ) – V O/2 A2 Out = VCM – VBE – (10µA • 25kΩ) + V O/2 Output Swing Range A 1, A 2; (V+) – 0.65V to (V–) + 0.06V Amplifier Linear Input Range: (V+) – 0.65V to (V–) + 0.98V 10µA VB 10µA + – VO = G • (VIN – VIN) Input Bias Current Compensation Output Swing Range: (V+) – 0.8V to (V–) + 0.35V A2 A1 C1 C2 60kΩ 60kΩ 60kΩ A3 VO 60kΩ – VIN Ref Q1 R1 25kΩ R2 25kΩ Q2 RG VD/2 (External) VCM VD/2 + VIN Figure 25. INA118 Simplified Circuit Diagram 12 Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated Product Folder Links: INA118 A newer version of this device is now available: INA818 INA118 www.ti.com SBOS027B – SEPTEMBER 2000 – REVISED APRIL 2019 8.3 Feature Description The INA118 input sections use junction field effect transistors (JFET) connected to provide protection up to ±40 V. The current-feedback architecture provides maximum bandwidth over the full range of gain settings. 8.4 Device Functional Modes 8.4.1 Noise Performance The INA118 provides low noise in most applications. For differential source impedances less than 1 kΩ, the INA103 may provide lower noise. For source impedances greater than 50 kΩ, the INA111 FET-Input Instrumentation Amplifier may provide lower noise. Low-frequency noise of the INA118 is approximately 0.28 µVp-p, measured from 0.1 to 10 Hz (G≥100). This provides dramatically improved noise when compared to state-of-the-art chopper-stabilized amplifiers. 8.4.2 Input Common-Mode Range The linear input voltage range of the input circuitry of the INA118 is from approximately 0.6-V less than the positive supply voltage to 1-V greater than the negative supply. As a differential input voltage causes the output voltage to increase, however, the linear input range is limited by the output voltage swing of amplifiers A1 and A2. Thus, the linear common-mode input range is related to the output voltage of the complete amplifier. This behavior also depends on supply voltage; see Figure 6. Input-overload can produce an output voltage that appears normal. For example, if an input overload condition drives both input amplifiers to their positive output swing limit, the difference voltage measured by the output amplifier is near zero. The output of the INA118 is near 0 V even though both inputs are overloaded. 8.4.3 Input Protection The inputs of the INA118 are individually protected for voltages up to ±40 V. For example, a condition of –40 V on one input and +40 V on the other input does not cause damage. Internal circuitry on each input provides low series impedance under normal signal conditions. To provide equivalent protection, series input resistors would contribute excessive noise. If the input is overloaded, the protection circuitry limits the input current to a safe value of approximately 1.5 to 5 mA. Figure 12 shows this input current limit behavior. The inputs are protected even if the power supplies are disconnected or turned off. Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated Product Folder Links: INA118 13 A newer version of this device is now available: INA818 INA118 SBOS027B – SEPTEMBER 2000 – REVISED APRIL 2019 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The INA118 measures a small differential voltage with a high common-mode voltage developed between the noninverting and inverting input. The high common-mode rejection makes the INA118 suitable for a wide range of applications. The ability to set the reference pin to adjust the functionality of the output signal offers additional flexibility that is practical for multiple configurations 9.2 Typical Application Figure 26 shows the basic connections required for operation of the INA118. Applications with noisy or high impedance power supplies may require decoupling capacitors close to the device pins as shown. The output is referred to the output reference (Ref) terminal, which is normally grounded. This must be a low-impedance connection to assure good common-mode rejection. A resistance of 12 Ω in series with the Ref pin causes a typical device to degrade to approximately 80-dB CMR (G = 1). Figure 26 depicts an input signal with a 5-mV, 1-kHz signal with a 1-Vp-p common-mode signal, a condition often observed in process control systems. Figure 27 depicts the output of the INA118 (gain = 250) depicting the clean recovered 1-kHz waveform. V+ 0.1µF 7 – VIN DESIRED GAIN RG ( Ω) NEAREST 1% RG (Ω) 1 2 5 10 20 50 100 200 500 1000 2000 5000 10000 NC 50.00k 12.50k 5.556k 2.632k 1.02k 505.1 251.3 100.2 50.05 25.01 10.00 5.001 NC 49.9k 12.4k 5.62k 2.61k 1.02k 511 249 100 49.9 24.9 10 4.99 2 INA118 Over-Voltage Protection A1 W 60kΩ 1 + – ) VO = G • (VIN – VIN 60kΩ 25kΩ G=1+ A3 RG 3 6 + 8 + VIN 50kΩ RG 25kΩ Load VO 5 A2 Over-Voltage Protection 60kΩ 4 60kΩ – Ref 0.1µF NC: No Connection. V– Also drawn in simplified form: – VIN RG + VIN INA118 VO Ref Figure 26. Basic Connections 14 Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated Product Folder Links: INA118 A newer version of this device is now available: INA818 INA118 www.ti.com SBOS027B – SEPTEMBER 2000 – REVISED APRIL 2019 Typical Application (continued) 9.2.1 Design Requirements Figure 30 and Figure 29 depict the performance of a typical application of the INA118 in a shop floor vibration sensing application. Because industrial process control systems often involve the interconnecting of multiple subsystems, ground loops are frequently encountered and often are not easily solved. The inherent commonmode rejection of instrumentation amplifiers enables accurate measurements even in the presence of ground loop potentials. The typical application was tested in a system with these requirements: • Transducer signal ≈ 5 mVp-p • Transducer center frequency = 1 kHz • Common-Mode signal (required to be rejected): 1 Vp-p at 60 Hz 9.2.2 Detailed Design Procedure 9.2.2.1 Setting the Gain As shown in Equation 1, the gain of the INA118 is set by connecting a single external resistor, RG, connected between pins 1 and 8. 50kΩ G=1+ RG (1) Commonly used gains and resistor values are shown in Figure 26. The 50-kΩ term in Equation 1 comes from the sum of the two internal feedback resistors of A1 and A2. These onchip metal film resistors are laser-trimmed to accurate absolute values. The accuracy and temperature coefficient of these resistors are included in the gain accuracy and drift specifications of the INA118. The stability and temperature drift of the external gain setting resistor, RG, also affects gain. The contribution of RG to gain accuracy and drift can be directly inferred from Equation 1. Low resistor values required for high gain can make wiring resistance important. Sockets add to the wiring resistance, which contributes additional gain error (possibly an unstable gain error) in gains of approximately 100 or greater. 9.2.2.2 Dynamic Performance The Figure 1 shows that, despite its low quiescent current, the INA118 achieves wide bandwidth, even at high gain. This is due to the current-feedback topology of the INA118. Settling time also remains excellent at high gain. The INA118 exhibits approximately 3-dB peaking at 500 kHz in unity gain. This is a result of its current-feedback topology and is not an indication of instability. Unlike an op amp with poor phase margin, the rise in response is a predictable 6-dB/octave due to a response zero. A simple pole at 300 kHz or lower produces a flat passband unity gain response. 9.2.2.3 Offset Trimming The INA118 is laser-trimmed for low offset voltage and drift. Most applications require no external offset adjustment. Figure 27 shows an optional circuit for trimming the output offset voltage. The voltage applied to the Ref terminal is summed at the output. The op amp buffer provides low impedance at the Ref terminal to preserve good common-mode rejection. Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated Product Folder Links: INA118 15 A newer version of this device is now available: INA818 INA118 SBOS027B – SEPTEMBER 2000 – REVISED APRIL 2019 www.ti.com Typical Application (continued) – VIN V+ RG INA118 VO 100µA 1/2 REF200 Ref + VIN OPA177 ±10mV Adjustment Range 100Ω 10kΩ 100Ω 100µA 1/2 REF200 V– Figure 27. Optional Trimming of Output Offset Voltage 9.2.2.4 Input Bias Current Return Path The input impedance of the INA118 is extremely high at approximately 1010 Ω. However, a path must be provided for the input bias current of both inputs. This input bias current is approximately ±5 nA. High input impedance means that this input bias current changes very little with varying input voltage. Input circuitry must provide a path for this input bias current for proper operation. Figure 28 shows various provisions for an input bias current path. Without a bias current path, the inputs float to a potential which exceeds the common-mode range of the INA118, and the input amplifiers saturates. If the differential source resistance is low, the bias current return path can be connected to one input (see the thermocouple example in Figure 28). With higher source impedance, using two equal resistors provides a balanced input, with the possible advantages of lower input offset voltage due to bias current, and better highfrequency common-mode rejection. 16 Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated Product Folder Links: INA118 A newer version of this device is now available: INA818 INA118 www.ti.com SBOS027B – SEPTEMBER 2000 – REVISED APRIL 2019 Typical Application (continued) Microphone, Hydrophone etc. INA118 47kΩ 47kΩ Thermocouple INA118 10kΩ INA118 Center-tap provides bias current return. Figure 28. Providing an Input Common-Mode Current Path 9.2.3 Application Curves 1-kHz differential signal is also present but cannot be seen in this waveform. Figure 29. Input of Typical Application Showing 60-Hz Common-Mode Signal Figure 30. Output of Typical Application Shows Desired 1-kHz Waveform With Common-Mode Interference Rejected Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated Product Folder Links: INA118 17 A newer version of this device is now available: INA818 INA118 SBOS027B – SEPTEMBER 2000 – REVISED APRIL 2019 www.ti.com 10 Power Supply Recommendations 10.1 Low-Voltage Operation The INA118 can be operated on power supplies as low as ±1.35 V. Performance of the INA118 remains excellent with power supplies ranging from ±1.35 V to ±18 V. Most parameters vary only slightly throughout this supply voltage range; see Typical Characteristics. Operation at low supply voltage requires careful attention to assure that the input voltages remain within their linear range. Voltage swing requirements of internal nodes limit the input common-mode range with low power supply voltage. Figure 3 shows the range of linear operation for a various supply voltages and gains. V+ – VIN + RG VO INA118 10.0V 6 REF102 Ref R1 1MΩ C1 0.1µF R1 2 R2 4 Pt100 1 f–3dB = 2πR1C1 OPA602 Cu K = 1.59Hz Cu RG Ref R3 100Ω = RTD at 0°C ISA TYPE Figure 31. AC-Coupled Instrumentation Amplifier – VIN R1 RG IO = INA118 MATERIAL COEFFICIENT (µV/°C) R1 , R 2 E + Chromel – Constantan 58.5 66.5kΩ J + Iron – Constantan 50.2 76.8kΩ K + Chromel – Alumel 39.4 97.6kΩ T + Copper – Constantan 38.0 102kΩ Figure 32. Thermocouple Amplifier With Cold Junction Compensation VIN •G R1 2.8kΩ LA + RG/2 RA Ref VO INA118 VO INA118 Ref IB 2.8kΩ G = 10 390kΩ A1 IO Load A1 IB Error OPA177 OPA602 OPA128 –1.5nA –1pA –75fA Figure 33. Differential Voltage to Current Converter 18 1/2 OPA2604 RL 1/2 OPA2604 10kΩ 390kΩ Figure 34. ECG Amplifier With Right-Leg Drive Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated Product Folder Links: INA118 A newer version of this device is now available: INA818 INA118 www.ti.com SBOS027B – SEPTEMBER 2000 – REVISED APRIL 2019 10.2 Single-Supply Operation The INA118 can be used on single power supplies of 2.7 V to 36 V. Figure 35 shows a basic single supply circuit. The output Ref terminal is connected to ground. Zero differential input voltage demands an output voltage of 0 V (ground). Actual output voltage swing is limited to approximately 35-mV above ground, when the load is referred to ground as shown. Figure 15 shows how the output voltage swing varies with output current. With single supply operation, V+IN and V–IN must both be 0.98-V above ground for linear operation. It is not possible, for example, to connect the inverting input to ground and measure a voltage connected to the noninverting input. To illustrate the issues affecting low voltage operation, consider the circuit in Figure 35, which shows the INA118 operating from a single 3-V supply. A resistor in series with the low side of the bridge assures that the bridge output voltage is within the common-mode range of the amplifier’s inputs. See Figure 3 for 3-V single supply operation. +3V 3V 2V – DV RG 300Ω VO INA118 Ref 2V + DV 150Ω R1 (1) NOTE: (1) R1 required to create proper common-mode voltage, only for low voltage operation — see text. Figure 35. Single-Supply Bridge Amplifier Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated Product Folder Links: INA118 19 A newer version of this device is now available: INA818 INA118 SBOS027B – SEPTEMBER 2000 – REVISED APRIL 2019 www.ti.com 11 Layout 11.1 Layout Guidelines TI always recommends paying attention to good layout practices. For best operational performance of the device, use good printed-circuit-board (PCB) layout practices, including: • Take care to ensure that both input paths are well-matched for source impedance and capacitance to avoid converting common-mode signals into differential signals. In addition, parasitic capacitance at the gain-setting pins can also affect CMRR over frequency. For example, in applications that implement gain switching using switches or PhotoMOS® relays to change the value of RG, select the component so that the switch capacitance is as small as possible. • Noise can propagate into analog circuitry through the power pins of the circuit as a whole, and of the device itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply applications. • Separate grounding for analog and digital portions of the circuitry is one of the simplest and most effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, see Circuit Board Layout Techniques (SLOA089). • To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in parallel with the noisy trace. • Keep the traces as short as possible. 20 Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated Product Folder Links: INA118 A newer version of this device is now available: INA818 INA118 www.ti.com SBOS027B – SEPTEMBER 2000 – REVISED APRIL 2019 11.2 Layout Example Gain Resistor Bypass Capacitor RG RG VIN V-IN V+ VIN V+IN VO V- Ref - + V+ VOUT GND Bypass Capacitor V- GND Figure 36. Layout Recommendation Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated Product Folder Links: INA118 21 A newer version of this device is now available: INA818 INA118 SBOS027B – SEPTEMBER 2000 – REVISED APRIL 2019 www.ti.com 12 Device and Documentation Support 12.1 Device Support 12.1.1 Development Support Table 1. Design Kits and Evaluation Modules NAME PART NUMBER TYPE DIP Adapter Evaluation Module DIP-ADAPTER-EVM Evaluation Modules and Boards Universal Instrumentation Amplifier Evaluation Module INAEVM Evaluation Modules and Boards Table 2. Development Tools NAME PART NUMBER TYPE Calculate Input Common-Mode Range of Instrumentation Amplifiers INA-CMV-CALC Calculation Tools SPICE-Based Analog Simulation Program TINA-TI Circuit Design and Simulation 12.2 Documentation Support 12.2.1 Related Documentation For related documentation, refer to the following: Circuit Board Layout Techniques 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 22 Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated Product Folder Links: INA118 PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) INA118P ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) NIPDAU N / A for Pkg Type -40 to 85 INA118P INA118PB ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) NIPDAU N / A for Pkg Type INA118U ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) NIPDAU Level-3-260C-168 HR INA 118U INA118U/2K5 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) NIPDAU Level-3-260C-168 HR INA 118U INA118U/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) NIPDAU Level-3-260C-168 HR INA 118U INA118UB ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) NIPDAU Level-3-260C-168 HR INA 118U B INA118UB/2K5 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) NIPDAU Level-3-260C-168 HR INA 118U B INA118UBG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) NIPDAU Level-3-260C-168 HR INA 118U B INA118UG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) NIPDAU Level-3-260C-168 HR INA 118U INA118P B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of