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INA148-Q1
SBOS472B – MARCH 2009 – REVISED JUNE 2016
INA148-Q1 ±200-V Common-Mode Voltage Difference Amplifier
1 Features
3 Description
•
•
The INA148-Q1 is a precision, low-power, unity-gain
difference amplifier with a high common-mode input
voltage range. The device consists of a monolithic,
precision, bipolar operational amplifier with a thin-film
resistor network.
1
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 1C
– Device CDM ESD Classification Level C6
– Device MM ESD Classification Level M2
High Common-Mode Voltage
– 75 V at VS = 5 V
– ±200 V at VS = ±15 V
Fixed Differential Gain = 1 V/V
Low Quiescent Current: 260 µA
Wide Supply Range
– Single Supply: 2.7 V to 36 V
– Dual Supplies: ±1.35 V to ±18 V
Low Gain Error: 0.075% (Maximum)
Low Nonlinearity: 0.002% (Maximum)
High CMR: 86 dB
Surface-Mount 8-pin SOIC Package
The INA148-Q1 is available in an 8-pin SOIC,
surface-mount package, and is specified for operation
over the temperature range of –40°C to 125°C.
Device Information(1)
PART NUMBER
INA148-Q1
PACKAGE
SOIC (8)
BODY SIZE (NOM)
3.91 mm × 4.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
.
2 Applications
•
•
•
•
•
•
•
•
The on-chip resistors are laser trimmed for an
accurate 1-V/V differential gain and high commonmode rejection. Excellent temperature tracking of the
resistor network maintains high gain accuracy and
common-mode rejection over temperature. The
INA148-Q1 operates on single or dual supplies.
These features make the INA148-Q1 suitable for
HEV/EV and Powertrain applications, specifically in
battery management systems.
HEV/EV and Powertrain
HEV Battery Management
Automotive Instrumentation
Current-Shunt Measurements
Differential Sensor Amplifiers
Line Receivers
Battery-Powered Systems
Stacked-Cell Monitors
Input Common-Mode Voltage vs Output Voltage
250
Common Mode Voltage (V)
200
150
100
50
0
-50
-100
-150
-200
-250
-20
-15
-10
-5
0
5
Output Voltage (V)
10
15
20
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA148-Q1
SBOS472B – MARCH 2009 – REVISED JUNE 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
3
3
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics Dual Supply ......................
Electrical Characteristics Single Supply....................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 13
8
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Applications ................................................ 14
9 Power Supply Recommendations...................... 19
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 Device and Documentation Support ................. 20
11.1
11.2
11.3
11.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (October 2011) to Revision B
Page
•
Added Device Information table, Table of Contents, Pin Configuration and Functions section, Specifications section,
ESD Ratings table, Thermal Information table, Detailed Description section, Application and Implementation section,
Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Deleted Ordering Information Table; see POA at the end of the datasheet .......................................................................... 1
Changes from Original (March 2009) to Revision A
•
2
Page
Features Bullet From: Low Quiescent Current: 260 mA To: Low Quiescent Current: 260 µA .............................................. 1
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SBOS472B – MARCH 2009 – REVISED JUNE 2016
5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
REF
1
8
NC
–IN
2
7
V+
+IN
3
6
OUT
V–
4
5
NC
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
+IN
3
I
Noninverting input
–IN
2
I
Inverting input
NC
5, 8
—
No connection
OUT
6
O
Output voltage
REF
1
I
Reference voltage input
V+
7
I
Positive supply voltage
V–
4
I
Negative supply voltage
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage
V+ to V–
Input voltage
MAX
UNIT
36
V
Continuous
±200
Peak (0.1 s)
±500
Short circuit to ground duration
V
Continuous
Package thermal impedance, junction to free air
Operating free-air temperature
–40
97.1
°C/W
125
°C
Maximum operating virtual-junction temperature
150
°C
Lead temperature (soldering, 10 s)
300
°C
150
°C
Storage temperature, Tstg
(1)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002
V(ESD)
(1)
Electrostatic discharge
(1)
UNIT
±1500
Charged-device model (CDM), per AEC Q100-011
±2000
Machine model
±150
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
Supply voltage
TA
Operating free-air temperature
Single supply
Dual supply
MAX
2.7
36
±1.35
±18
–40
125
UNIT
V
°C
6.4 Thermal Information
INA148-Q1
THERMAL METRIC (1)
D (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
100.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
44.9
°C/W
RθJB
Junction-to-board thermal resistance
42.2
°C/W
ψJT
Junction-to-top characterization parameter
6.3
°C/W
ψJB
Junction-to-board characterization parameter
41.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics Dual Supply
VS = ±5 V to ±15 V (dual supply), RL = 10 kΩ to ground, VREF = 0 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VS = ±15 V
±1
±5
VS = ±5 V
±1
±5
VOS
Input offset voltage (1) (2)
VCM = 0 V
ΔVOS/ΔT
Input offset voltage drift (1)
TA = –40°C to 125°C
±10
PSRR
Power supply ripple rejection (1)
VS = ±1.35 V to ±18 V, VCM = 0 V
±50
VCM
Common-mode voltage range
V+IN – V–IN = 0
CMRR
Common-mode rejection ratio
Vn
–200
200
VS = ±5 V
–100
80
70
86
VS = ±5 V, VCM = –100 V to 80 V, RS = 0 Ω
70
86
MΩ
1
MΩ
Voltage noise
(1) (3)
f = 0.1 Hz to 10 Hz
f = 1 kHz
Gain nonlinearity
μVp-p
nV/√Hz
±0.01%
VO = (V– + 0.5) to (V+ – 1.5)
±3
±10
±0.001
±0.002
VS = ±5 V
±0.001
Slew rate
VS = ±15 V, 10-V step
Settling time
VS = ±5 V, 6-V step
V/V
±0.075%
VS = ±15 V
Small-signal bandwidth
frequency response
Overload recovery
17
880
1
VO = (V– + 0.5) to (V+ – 1.5)
Gain error over temperature
4
dB
2
Gain error
(1)
(2)
(3)
V
Common-mode input impedance
Initial gain (1)
ts
μV/V
Differential input impedance
Voltage noise density (1) (3)
SR
mV
μV/°C
±400
VS = ±15 V
VS = ±15 V, VCM = –200 V to 200 V, RS = 0 Ω
UNIT
%FSR
100
kHz
1
V/μs
0.1%
21
0.01%
25
0.1%
21
0.01%
25
50% input overload
ppm/°C
24
μs
μs
Overall difference amplifier configuration. Referred to input pins (V+IN and V–IN ), gain = 1 V/V.
Includes effects of amplifier's input bias and offset currents.
Includes effects of input current noise and thermal noise contribution of resistor network.
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Electrical Characteristics Dual Supply (continued)
VS = ±5 V to ±15 V (dual supply), RL = 10 kΩ to ground, VREF = 0 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
RL = 100 kΩ
V– + 0.25
V+ – 1
RL = 10 kΩ
V– + 0.5
V+ – 1.5
VO
Output voltage
IO
Output current
Short-circuit current, continuous to common
CL
Load capacitance
Stable operation
IS
Supply current
VIN = 0, IO = 0
UNIT
V
±13
mA
10
nF
±260
±300
μA
TYP
MAX
UNIT
±1
±5
6.6 Electrical Characteristics Single Supply
VS = 5 V (single supply), RL = 10 kΩ to VS / 2, VREF = VS / 2, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1) (2)
MIN
VOS
Input offset voltage
ΔVOS/ΔT
Input offset voltage drift (1)
VCM = VS / 2
TA = –40°C to 125°C
±10
PSRR
Power supply ripple rejection (1)
VS = 2.7 V to 36 V, VCM = VS / 2
±50
VCM
Common-mode voltage range
V+IN – V–IN = 0
CMRR
Common-mode rejection ratio
VCM = –47.5 V to 32.5 V, RS = 0 Ω
VREF = 0.25 V
VREF = VS / 2
–4
75
32.5
70
Common-mode input impedance
Vn
Voltage noise (1) (3)
f = 0.1 Hz to 10 Hz
Voltage noise density (1) (3)
f = 1 kHz
Initial gain
(1)
Gain error
V
86
dB
2
MΩ
1
MΩ
17
μVp-p
880
nV/√Hz
1
VO = 0.5 V to 3.5 V
Gain error over temperature
Gain nonlinearity
μV/V
±400
–47.5
Differential input impedance
mV
μV/°C
VO = 0.5 V to 3.5 V
Slew rate
ts
Settling time
VS = 5 V, 3-V step
Overload recovery
50% input overload
±0.075%
±3
±10
±0.001
Small-signal bandwidth
SR
V/V
±0.01%
ppm/°C
%FSR
100
kHz
1
V/μs
0.1%
21
0.01%
25
μs
μs
13
RL = 100 kΩ
V– + 0.25
V+ – 1
RL = 10 kΩ
V– + 0.5
V+ – 1.5
VO
Output voltage
IO
Output current
Short-circuit current, continuous to common
±8
mA
CL
Load capacitance
Stable operation
10
nF
IQ
Quiescent current
VIN = 0, IO = 0
(1)
(2)
(3)
260
300
V
μA
Overall difference amplifier configuration. Referred to input pins (V+IN and V–IN ), gain = 1 V/V.
Includes effects of amplifier's input bias and offset currents.
Includes effects of input current noise and thermal noise contribution of resistor network.
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6.7 Typical Characteristics
VS = ±15 V, RL = 10 kΩ to common, VREF = 0 V, TA = 25°C (unless otherwise noted)
5
100
= VS = ±15 V
VS= ±1.35 V
0
= VS = ±1.35 V
VS = ±15 V
Voltage Gain (dB)
Voltage Gain (dB)
80
–5
–10
–20
–25
60
40
20
–30
0
–35
10
100
10k
1k
100k
100
10
1M
Figure 1. Gain vs Frequency
100k
1M
Figure 2. Common-Mode Rejection vs Frequency
1000
Input Noise Spectral Density (nV/ÖHz)
110
PSR+
(VS = ±18 V)
100
Power Supply Rejection (dB)
10k
1k
Frequency (Hz)
Frequency (Hz)
90
PSR+
(VS = ±1.35 V)
80
PSR–
(VS = ±18 V)
70
60
PSR–
(VS = ±1.35 V)
50
40
30
20
800
600
400
200
100
10
1
10
1k
100
Frequency (Hz)
10k
10
100k
Figure 3. Power Supply Rejection vs Frequency
100
1k
Frequency (Hz)
10k
100k
Figure 4. Input Voltage Noise Spectral Density
290
280
VS = ±15 V
270
IQ (µA)
5 µV/div
260
250
VS = ±2.5 V
240
230
220
1 s/div
210
–60 –40 –20
0
20
40
60
80
100 120 140
Temperature (°C)
Figure 5. Voltage Noise (RTI)
6
Figure 6. Quiescent Current vs Temperature
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Typical Characteristics (continued)
VS = ±15 V, RL = 10 kΩ to common, VREF = 0 V, TA = 25°C (unless otherwise noted)
20
+SC
125°C
10
5
125°C
–55°C
–55°C
5 V/div
Short-Circuit Current (mA)
15
0
–5
–10
–SC
–15
–20
–60
–40
–20
0
20
40
60
80
100
120
140
25 µs/div
Temperature (°C)
Figure 7. Short-Circuit Current vs Temperature
Figure 8. Large-Signal Step Response vs Temperature
RL = 1 kW
RL = 1 kW
RL = 10 kW
5 V/div
5 V/div
RL = 100 kW
RL = 10 kW
RL = 100 kW
25 µs/div
1 ms/div
RL = 10 kΩ
Figure 9. Output Voltage Swings vs RL
CL = 10 pF
Figure 10. Large-Signal Step Response
CL = 1 nF
CL = 10 nF
G = +1 V/V
5 V/div
50 mV/div
VIN
100 µs/div
10 µs/div
RL = 10 kΩ
CL = 10 pF
CL = 1 nF and 10 nF
Figure 11. Small-Signal Step Response
Figure 12. Large-Signal Capacitive Load Response
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Typical Characteristics (continued)
VS = ±15 V, RL = 10 kΩ to common, VREF = 0 V, TA = 25°C (unless otherwise noted)
24
24
VS = ±2.5 V
Percent of Amplifiers (%)
Percent of Amplifiers (%)
VS = ±15 V
18
12
6
20
16
12
8
4
0
Figure 14. Offset Voltage Production Distribution
Figure 13. Offset Voltage Production Distribution
20
20
VS = ±2.5 V
Percent of Amplifiers (%)
15
10
5
15
10
5
30.0
18.0
24.0
12.0
6.0
0.0
–6.0
–12.0
–30.0
30.0
18.0
24.0
12.0
6.0
0.0
–6.0
–12.0
–18.0
–24.0
–30.0
Offset Voltage Drift, RTI (µV/°C)
–18.0
0
0
–24.0
Offset Voltage Drift, RTI (µV/°C)
Figure 15. Offset Voltage Drift Production Distribution
Figure 16. Offset Voltage Drift Production Distribution
40
40
VS = ±2.5 V
Percent of Amplifiers (%)
VS = ±15 V
30
20
10
0
30
20
10
Gain Drift (ppm/°C)
10.0
8.0
4.0
2.0
0.0
–2.0
–4.0
–6.0
–8.0
–10.0
10.0
6.0
8.0
4.0
2.0
0.0
–2.0
–4.0
–6.0
–8.0
–10.0
0
6.0
Percent of Amplifiers (%)
VS = ±15 V
Percent of Amplifiers (%)
5.0
3.0
Offset Voltage, RTI (mV)
Offset Voltage, RTI (mV)
Gain Drift (ppm/°C)
Figure 17. Gain Drift Production Distribution
8
4.0
2.0
1.0
0.0
–1.0
–2.0
–3.0
–4.0
–5.0
5.0
3.0
4.0
2.0
1.0
0.0
–1.0
–2.0
–3.0
–4.0
–5.0
0
Figure 18. Gain Drift Production Distribution
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Typical Characteristics (continued)
VS = ±15 V, RL = 10 kΩ to common, VREF = 0 V, TA = 25°C (unless otherwise noted)
VS = ±15 V
VS = ±15V
V+IN
0V
V–IN
VOUT
5 V/div
5 V/div
VOUT
0V
0V
5 µs/div
5 µs/div
Figure 19. Inverting Input 50% Overload Recovery Time
Figure 20. Noninverting Input 50% Overload Recovery Time
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7 Detailed Description
7.1 Overview
The INA148-Q1 is a unity-gain difference amplifier with a high common-mode input voltage range. To achieve its
high common-mode voltage range, the INA148-Q1 features a precision, laser-trimmed, thin-film resistor network
with a 20:1 input voltage divider ratio. High input voltages are thereby reduced in amplitude, delivering input
voltages to the op amp that are within its linear operating range. A Tee network in the op amp feedback network
places the amplifier in a gain of 20 V/V, restoring the overall circuit gain to unity (1 V/V).
External voltages can be summed into the amplifier's output by using the REF pin, making the differential
amplifier a highly versatile design tool. Voltages on the REF pin also influence the INA148-Q1's common-mode
voltage range.
In accordance with good engineering practice for linear integrated circuits, the INA148-Q1's power-supply bypass
capacitors must be connected as close to the supply pins (V+ and V–) as practical. TI recommends ceramic or
tantalum capacitors for use as bypass capacitors.
The input impedances are unusually high for a difference amplifier and this must be considered when routing
input signal traces on a PCB. Avoid placing digital signal traces near the difference amplifier's input traces to
minimize noise pickup.
7.2 Functional Block Diagram
+VS
0.1 µF
7
V–IN
2
1 MW
50 kW
50 kW
VO = (V+IN – V–IN)
2.7778 kW
6
A1
V+IN
3
1 MW
VO
52.6316 kW
INA148-Q1
4
–VS
0.1 µF
1
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7.3 Feature Description
7.3.1 Operating Voltage
The INA148-Q1 is specified for ±15-V and ±5-V dual supplies and 5-V single supplies. The INA148-Q1 can be
operated with single or dual supplies with excellent performance.
The INA148-Q1 is fully characterized for supply voltages from ±1.35 V to ±18 V and over temperatures of –40°C
to 125°C. Parameters that vary significantly with operating voltage, load conditions, or temperature are shown in
Typical Characteristics.
7.3.2 Gain Equation
An internal on-chip resistor network sets the overall differential gain of the INA148-Q1 to precisely 1 V/V.
Equation 1 shows the output.
VO = (V+IN – V–IN) + VREF
10
(1)
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Feature Description (continued)
7.3.3 Common-Mode Range
The 20:1 input resistor ratio of the INA148-Q1 provides an input common-mode range that extends well beyond
its power supply rails.
The exact input voltage range depends on the amplifier's power-supply voltage and the voltage applied to the
REF pin. See Typical Applications for typical input voltage ranges at different power supply voltages.
7.3.4 Offset Trim
The INA148-Q1 is laser-trimmed for low offset voltage and drift. Most applications require no external offset
adjustment.
Because a voltage applied to the reference (REF) pin is summed directly into the amplifier's output signal, this
technique can be used to null the amplifier's input offset voltage. Figure 21 shows an optional circuit for trimming
the offset voltage.
+VS
7
2
V–IN
1 MW
50 kW
50 kW
VO = (V+IN – V–IN)
2.7778 kW
6
A1
190 W
V+IN
3
VO
52.6316 kW
1 MW
INA148
4
–VS
VREF 1
+15 V
10 kW
10 kW
10 W
±15-mV Offset Trim Range, RTI
–15 V
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Figure 21. Optional Offset Trim Circuit
To maintain high common-mode rejection (CMR), the source impedance of any signal applied to the REF pin
must be very low (≤5 Ω).
A source impedance of only 10 Ω at the REF pin reduces the INA148-Q1's CMR to approximately 74 dB. High
CMR can be restored if a resistor is added in series with the amplifier's positive input pin. This resistor must be
19 times the source impedance that drives the REF pin. For example, if there is a source impedance of 10 Ω to
the REF pin, a 190-Ω resistor must be added in series with the +IN pin.
Preferably, the offset trim voltage applied to the REF pin must be buffered with an amplifier such as an OPA171Q1 (see Figure 22). In this case, the op amp output impedance is low enough that no external resistor is needed
to maintain the INA148-Q1's excellent CMR.
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Feature Description (continued)
+15 V
7
2
V–IN
1 MW
50 kW
50 kW
VO = (V+IN – V–IN)
2.7778 kW
6
A1
3
V+IN
VO
52.6316 kW
1 MW
INA148
4
VREF 1
+15 V
–15 V
100 kW
±15-mV Offset Trim Range, RTI
100 kW
OPA171-Q1
100 W
–15 V
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Figure 22. Preferred Offset Trim Circuit
7.3.5 Input Impedance
The input resistor network determines the impedance of each of the INA148-Q1 inputs. The impedance is
approximately 1 MΩ. Unlike an instrumentation amplifier, signal source impedances at the two input pins must be
nearly equal to maintain good common-mode rejection.
A mismatch between the two input source impedances causes a differential amplifier's common-mode rejection
to be degraded. With a source impedance imbalance of only 500 Ω, CMR can fall to approximately 66 dB.
Figure 23 shows a common application, measuring power supply current through a shunt resistor (RS). A shunt
resistor creates an unbalanced source resistance condition that can degrade a differential amplifier's commonmode rejection.
+15 V
7
Load
2
1 MW
50 kW
50 kW
IL
VO = I L × R S
2.7778 kW
6
A1
RS
RC
3
VO
52.6316 kW
1 MW
INA148
VCM
200 V
4
1
–15 V
Copyright © 2016, Texas Instruments Incorporated
Figure 23. Shunt-Resistor Current Measurement Circuit
Unless the shunt resistor is less than approximately 100 Ω, TI recommends an additional equal compensating
resistor (RC) to maintain input balance and high CMR.
12
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Feature Description (continued)
Source impedances (or shunts) greater than 5 kΩ are not recommended, even if they are perfectly compensated.
This is because the internal resistor network is laser-trimmed for accurate voltage divider ratios, but not
necessarily to absolute values. Input resistors are shown as 1 MΩ; however, this is only their nominal value.
In practice, the input resistors' absolute values may vary by as much as 30%. The two input resistors match to
about 5%, so adding compensating resistors greater than 5 kΩ can cause a serious mismatch in the resulting
resistor network voltage divider ratios, thus degrading CMR.
TI recommends not attempting to extend the INA148-Q1 input voltage range by adding external resistors for the
reasons described in the previous paragraph. CMR suffers serious degradation unless the resistors are carefully
trimmed for CMR and gain. This is an iterative adjustment and can be tedious and time consuming.
7.4 Device Functional Modes
The INA148-Q1 is a unity-gain, differential to single-ended amplifier that can reject high common-mode signals
up to ±200 V with ±15-V supply voltage. This high common-mode rejection is achieved by internal trimmed
resistive divider network. The resistive network provides an attenuation factor of 20:1.
Equation 2 shows the transfer function output to input.
VO = V+IN – V–IN
(2)
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
INA148-Q1 is a unity-gain difference amplifier with a high common-mode input voltage range. It is suitable to be
used in many different applications that need bidirectional measurments in a high input common-mode
environment.
8.2 Typical Applications
8.2.1 Battery Monitor Circuit
IC
RS
0.01 W
+
0.1 µF
–
28-V
Supply
7
2
1 MW
50 kW
50 kW
2.7778 kW
VO = 1.235 V + (IC × RS)
6
VO
A1
3
52.6316 kW
1 MW
271 kW
INA148
4
1
10 µF
5W
+
LM4041-N-Q1
Copyright © 2016, Texas Instruments Incorporated
Figure 24. Battery Monitor Circuit Diagram
8.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the input parameters.
Table 1. Design Parameters
14
PARAMETER
EXAMPLE VALUE
Battery voltage
28 V
Sense resistor
0.01 Ω
Load current bidirectional
–50 A to 50 A
Reference voltage (LM4041-N-Q1)
1.235 V ± 0.1%
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8.2.1.2 Detailed Design Procedure
This circuit is designed for measuring the high-side current bidirectional in automotive battery monitor such as
charging or body control modules with a 28-V battery or similar applications. The voltage difference amplifier
REF pin is set at 1.235 V for bidirectional current measurement.
The LM4041-V-Q1 supply current is around 100 µA. It is provided from the 28-V battery through 271-kΩ resistor.
The INA148-Q1 has a gain of 1 and output voltage as shown in Equation 3:
VO = RS × IC + 1.235 V
(3)
The sense resistor value can be changed according to measured current range. TI recommends choosing the
right value for minimizing the error and the dissipating power. The measured differential voltage is given as
Equation 4 and the dissipated power is given as Equation 5.
RS × IC
RS × IC2
(4)
(5)
1.35
1.8
1.33
1.7
1.31
1.6
1.29
1.5
Output Voltage (V)
Output Voltage (V)
8.2.1.3 Application Curves
1.27
1.25
1.23
1.21
1.19
1.4
1.3
1.2
1.1
1
0.9
1.17
1.15
0.8
1.13
-10
0.7
-50
-8
-6
-4
-2
0
2
Load Current (A)
4
6
8
10
-40
-30
-20
D001
Figure 25. Output Voltage vs Load Current –10 A to 10 A
-10
0
10
Load Current (A)
20
30
40
50
D001
Figure 26. Output Voltage vs Load Current –50 A to 50 A
8.2.2 Quasi-AC-Coupled Differential Amplifier
+VS
fC » 0.75 Hz HPF
7
V–IN
2
U1
1 MW
50 kW
50 kW
VO = (V+IN – V–IN) + VREF
2.7778 kW
6
VO
A1
V+IN
3
1 MW
52.6316 kW
1 MW
INA148
4
1
0.22 µF
–VS
+VS
7
6
U2
Copyright © 2016, Texas Instruments Incorporated
2
OPA171-Q1
4
3
VREF
–VS
Figure 27. Quasi-AC-Coupled Differential Amplifier Diagram
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8.2.2.1 Design Requirements
For this design example, use the parameters listed in Table 2 as the input parameters.
Table 2. Design Parameters
PARAMETER
EXAMPLE VALUE
Common-mode supply voltage (–200 V to 200 V)
15 V
Common-mode supply voltage (–100 V to 750 V)
5V
U2
OPA171-Q1
External resistor
1 MΩ
External capacitor
0.22 µF
8.2.2.2 Detailed Design Procedure
A quasi-AC coupled differential amplifier can be simply made by adding a general-purpose op amp configured as
an integrator externally to the device. Equation 6 shows the output of OPA171-Q1.
Z ö
Z
æ
VO 1 = ç 1 + C ÷ ´ VREF - C ´ VO
R ø
R
è
where
•
•
ZC is the impedance of the external capacitor
R is the value of the external resistor
(6)
Equation 7 shows the output of INA148-Q1.
VO = VO1 + V+IN – V–IN
(7)
Equation 8 is the result of combining the previous two equations.
VO =
R´C´S
´ (V+IN - V-IN ) + VREF
1+ R ´ C ´ S
where
•
S = j × 2π × ƒ
(8)
R´C´S
The transfer function 1 + R ´ C ´ S has a zero and a pole at
cutoff frequncy and flat 0 dB above.
1
2p ´ R ´ C .
Making a gain slope of 20 dB/decade below the
VREF can be set to 0 V in case of dual supply.
8.2.3 Single-Supply Differential Amplifier
+5 V
0.1 µF
7
V–IN
2
1 MW
50 kW
50 kW
VO = (V+IN – V–IN) + 1.235V
2.7778 kW
6
VCM = –23 V to +56 V
V+IN
3
A1
1 MW
VO
52.6316 kW
INA148
4
1
34 kW
5W
+5 V
10 µF
+
LM4041-N-Q1
Copyright © 2016, Texas Instruments Incorporated
Figure 28. Single-Supply Differential Amplifier Diagram
16
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8.2.3.1 Design Requirements
For this design example, use the parameters listed in Table 3 as the input parameters.
Table 3. Design Parameters
PARAMETER
EXAMPLE VALUE
Common-mode voltage
–23 V to 56 V
Load current
Bidirectional
Reference voltage (LM4041-N-Q1)
1.235 V ± 0.1%
Supply voltage (INA148-Q1)
5V
8.2.3.2 Detailed Design Procedure
For applications that have –23-V to 56-V common-mode voltage and a single 5-V supply, the common-mode
rejection ratio is in the order of 80 dB. The INA148-Q1 is not a rail-to-rail output. An external reference voltage is
necessary for bidirectional measurment or low differential output. The external resistor is necessary to provide a
100-µA supply to LM4041-N-Q1.
8.2.4 AC-Coupled Difference Amplifier
+15 V
C1
7
(1)
4.7 µF
250 V
V–IN
2
1 MW
50 kW
50 kW
2.7778 kW
VO = (V+IN – V–IN)
6
VCM = 200 Vpk
A1
VO
C2
(1)
4.7 µF
250 V
V+IN
3
52.6316 kW
1 MW
INA148
4
1
–15 V
Copyright © 2016, Texas Instruments Incorporated
(1)
Metallized polypropylene, ±5% tolerance
Figure 29. AC-Coupled Difference Amplifier Circuit Diagram
8.2.4.1 Design Requirements
For this design example, use the parameters listed in Table 4 as the input parameters.
Table 4. Design Parameters
PARAMETER
EXAMPLE VALUE
Decoupling capacitors
4.7 µF, 250 V ± 5%
Differential input voltage range
–14 V to 14 V
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8.2.4.2 Detailed Design Procedure
An AC-coupled voltage difference amplifier requires 2 series capacitors. These capacitors must be high quality
with tolerance of less than 5% and a rated voltage of 250 V at 200-V common-mode.
8.2.5 50-mV Current-Shunt Amplifier With ±200-V Common-Mode Voltage Range
0.47 µF ceramic (all)
RS
50 mV
shunt
I
6 +15
+VISO
+VS
IN5245
VCM = –200V max
5
1 kW
200 kW
0.1 µF
+VISO
2
O
7
–VISO
2
–15
7
6
OPA171-Q1
3
C
IN5245
+15 V
+15 V
1
1 MW
2
4
±15 V Isolated
Power Supply
7
50 kW
50k W
–VISO
2.7778 kW
6 VO
A1
–50-mV Input = –10-V Output
52.6316 kW
1 MW
3
INA148
4
0.1 µF
–15 V
1
Copyright © 2016, Texas Instruments Incorporated
Figure 30. 50-mV Current-Shunt Amplifier With ±200-V Common-Mode Voltage Range Diagram
8.2.5.1 Design Requirements
For this design example, use the parameters listed in Table 5 as the input parameters.
Table 5. Design Parameters
PARAMETER
EXAMPLE VALUE
Common-mode voltage
±200 V
Differential input voltage
–50 mV to 50 mV
Gain (OPA171-Q1)
200
Isolated power supply
±15 V
8.2.5.2 Detailed Design Procedure
The OPA171-Q1 gain is 200, set by 1 kΩ and 200 kΩ resistors. The OPA171-Q1 positive input and the
INA148‑Q1 are both tied to the isolated power supply common ground. The OPA171-Q1 output is calculated by
Equation 9.
VO = –200 × VSENSE
where
•
VSENSE is the voltage across the shunt resistor
(9)
The INA148-Q1 output is calculated by Equation 10.
VO = –(–200 × VSENSE) = 200 × VSENSE
18
(10)
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9 Power Supply Recommendations
Supply voltage is 2.7 V to 36 V for single supply and ±1.35 V to ±18 V for dual supplies. The input commonmode voltage range is higher at higher supply voltage, 75 V at VS = 5 V and ±200 V at VS = ±15 V.
10 Layout
10.1 Layout Guidelines
The INA148-Q1 is a precision voltage difference amplifier. To realize the full operational performance of the
device, good high-frequency printed-circuit-board (PCB) layout practices are required. Low-loss 0.1-µF bypass
capacitors must be connected between each supply pin and ground as close to the device as possible. The
bypass capacitor traces must be designed for minimum inductance.
10.2 Layout Example
1
8
2
7
3
6
4
5
10 µF
0.1 µF
0.1 µF
GND
Figure 31. INA148-Q1 Layout Diagram
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11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
INA148QDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
148Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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