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INA1650, INA1651
SBOS818B – DECEMBER 2016 – REVISED NOVEMBER 2018
INA165x SoundPlus™ High Common-Mode Rejection Line Receivers
1 Features
3 Description
•
The dual-channel INA1650 and single-channel
INA1651 (INA165x) SoundPlus™ audio line receivers
achieve an extremely-high common-mode rejection
ratio (CMRR) of 91 dB while maintaining an ultra-low
THD+N of –120 dB at 1 kHz for 22-dBu signal levels.
Precision matching of on-chip resistors give the
INA165x devices excellent CMRR performance.
These resistors have matching that is far superior
compared to external components, and are immune
to mismatches introduced by printed circuit board
(PCB) layout. Unlike other line receiver products, the
INA165x CMRR is characterized over temperature
and tested in production to deliver consistent
performance in a wide variety of applications.
1
•
•
•
•
•
•
•
•
•
High Common-Mode Rejection:
91 dB (Typical)
High Input Impedance: 1-MΩ Differential
Ultra-Low Noise: –104.7 dBu, Unweighted
Ultra-Low Total Harmonic Distortion + Noise:
–120 dB THD+N (22 dBu, 22-kHz Bandwidth)
Wide Bandwidth: 2.7 MHz
Low Quiescent Current: 6 mA (INA1651, Typical)
Short-Circuit Protection
Integrated EMI Filters
Wide Supply Range: ±2.25 V to ±18 V
Available in Small 14-Pin TSSOP Package
2 Applications
•
•
•
•
•
•
Differential Audio Interfaces
Audio Input Circuitry
Line Drivers
Audio Power Amplifiers
Audio Analyzers
High-End Audio and Video (A/V) Receivers
The INA165x devices operate over a very-widesupply range of ±2.25 V to ±18 V, on 10.5 mA of
supply current. In addition to the line-receiver
channels, a buffered mid-supply reference output is
included, making the INA165x configurable for dualor single-supply applications. The mid-supply output
can be used as a bias voltage for other analog
circuitry in the signal chain. These devices are
specified from –40°C to +125°C.
Device Information(1)
PART NUMBER
INA165x Simplified Internal Schematic
PACKAGE
BODY SIZE (NOM)
INA1650
TSSOP (14)
4.40 mm × 5.00 mm
INA1651
TSSOP (14)
4.40 mm × 5.00 mm
VEE
VCC
(1) For all available packages, see the package option addendum
at the end of the data sheet.
IN+ A
+
OUT A
COM A
±
CMRR Histogram (5746 Channels)
IN± A
REF A
25
VCC
±
20
+
Channels (%)
VMID(IN)
VEE
INA1650 ONLY
REF B
IN± B
15
10
5
50
45
40
35
30
25
20
15
10
0
5
OUT B
+
0
±
COM B
CMRR ( V/V)
IN+ B
C001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA1650, INA1651
SBOS818B – DECEMBER 2016 – REVISED NOVEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
5
6
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: ........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 15
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
15
15
15
17
8
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Applications ................................................ 22
9 Power Supply Recommendations...................... 29
10 Layout................................................................... 29
10.1 Layout Guidelines ................................................. 29
10.2 Layout Examples................................................... 30
11 Device and Documentation Support ................. 32
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
32
32
32
33
33
33
33
33
12 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2018) to Revision B
•
Changed INA1651 device from product preview to production data (active) ......................................................................... 1
Changes from Original (September 2018) to Revision A
•
2
Page
Page
Added new INA1651 as advance information ........................................................................................................................ 1
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SBOS818B – DECEMBER 2016 – REVISED NOVEMBER 2018
5 Pin Configuration and Functions
INA1650 PW Package
14-Pin TSSOP
Top View
VCC
1
14
VEE
IN+ A
2
13
OUT A
COM A
3
12
REF A
IN± A
4
11
VMID(IN)
IN± B
5
10
VMID(OUT)
COM B
6
9
REF B
IN+ B
7
8
OUT B
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
COM A
3
I
Input common, channel A
COM B
6
I
Input common, channel B
IN+ A
2
I
Noninverting input, channel A
IN– A
4
I
Inverting input, channel A
IN+ B
7
I
Noninverting input, channel B
IN– B
5
I
Inverting input, channel B
OUT A
13
O
Output, channel A
OUT B
8
O
Output, channel B
REF A
12
I
Reference input, channel A. This pin must be driven from a low impedance.
REF B
9
I
Reference input, channel B. This pin must be driven from a low impedance.
VCC
1
—
Positive (highest) power supply
VEE
14
—
Negative (lowest) power supply
VMID(IN)
11
I
Input node of internal supply divider. Connect a capacitor to this pin to reduce noise from the
supply divider circuit.
VMID(OUT)
10
O
Buffered output of internal supply divider.
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SBOS818B – DECEMBER 2016 – REVISED NOVEMBER 2018
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INA1651 PW Package
14-Pin TSSOP
Top View
VCC
1
14
VEE
IN+ A
2
13
OUT A
COM A
3
12
REF A
IN± A
4
11
VMID(IN)
NC
5
10
VMID(OUT)
NC
6
9
NC
NC
7
8
NC
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
COM A
3
I
Input common, channel A
IN+ A
2
I
Noninverting input, channel A
IN– A
4
I
Inverting input, channel A
NC
5
—
No internal connection
NC
6
—
No internal connection
NC
7
—
No internal connection
NC
8
—
No internal connection
NC
9
—
No internal connection
OUT A
13
O
Output, channel A
REF A
12
I
Reference input, channel A. This pin must be driven from a low impedance.
VCC
1
—
Positive (highest) power supply
VEE
14
—
Negative (lowest) power supply
VMID(IN)
11
I
Input node of internal supply divider. Connect a capacitor to this pin to reduce noise from the
supply divider circuit.
VMID(OUT)
10
O
Buffered output of internal supply divider.
4
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SBOS818B – DECEMBER 2016 – REVISED NOVEMBER 2018
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply voltage, VS = (V+) – (V–)
Voltage
40
Input voltage (Signal inputs, enable, ground)
(V–) – 0.5
(V+) + 0.5
Input differential voltage
Input current (all pins except power-supply pins)
Current
Output short-circuit
±10
(2)
–55
(2)
125
Junction, TJ
150
Storage, Tstg
(1)
mA
Continuous
Operating, TA
Temperature
V
(V+) – (V–)
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Short-circuit to VS / 2 (ground in symmetrical dual supply setups), one amplifier per package.
6.2 ESD Ratings
VALUE
UNIT
INA1650
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±750
V
INA1651
V(ESD)
(1)
(2)
Electrostatic discharge
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage (V+ – V–)
Specified temperature
NOM
MAX
UNIT
4.5 (±2.25)
36 (±18)
V
–40
125
°C
6.4 Thermal Information
THERMAL METRIC (1)
INA1650
INA1651
PW (TSSOP)
PW (TSSOP)
UNIT
14 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
97.0
99.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
22.6
29.9
°C/W
RθJB
Junction-to-board thermal resistance
40.4
42.6
°C/W
ψJT
Junction-to-top characterization parameter
0.9
1.5
°C/W
ψJB
Junction-to-board characterization parameter
39.6
42.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS818B – DECEMBER 2016 – REVISED NOVEMBER 2018
6.5
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Electrical Characteristics:
at TA = 25°C, VS = ±2.25 V to ±18 V, VCM = VOUT = midsupply, and RL = 2 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO PERFORMANCE
THD+N
Total harmonic distortion +
noise
0.00039%
VO = 3 VRMS, f = 1kHz, 90-kHz measurement bandwidth,
VS = ±18 V
–108.1
VIN = 22 dBu (9.7516 VRMS) , FIN = 1 kHz, VS = ±18 V,
90-kHz measurement bandwidth
–115.2
dB
0.0005%
SMPTE and DIN two-tone, 4:1 (60 Hz and 7 kHz)
VO = 3 VRMS, 90-kHz measurement bandwidth
IMD
dB
0.000174%
–106.1
Intermodulation distortion
dB
0.00066%
CCIF twin-tone (19 kHz and 20 kHz),
VO = 3 VRMS, 90-kHz measurement bandwidth
–103.6
dB
AC PERFORMANCE
BW
Small-signal bandwidth
2.7
SR
Slew rate
10
V/μs
VO = 1 VP
1.59
MHz
CL = 20 pF
71°
CL = 200 pF
54°
Full-power bandwidth (1)
PM
Phase margin
ts
Settling time
To 0.01%, Vs = ±18 V, 10-V step
2.2
μs
330
ns
f = 1 kHz, REF and COM pins connected to ground
140
dB
f = 1 kHz, REF and COM pins connected to VMID(OUT)
130
dB
80
MHz
4.5
μVRMS
Overload recovery time
Channel separation
MHz
EMI/RFI filter corner frequency
NOISE
Output voltage noise
Output voltage noise density (2)
en
f = 20 Hz to 20 kHz, no weighting
–104.7
f = 100 Hz
47
f = 1 kHz
31
dBu
nV/√Hz
OFFSET VOLTAGE
VOS
Output offset voltage
dVOS/dT
Output offset voltage drift (2)
PSRR
Power-supply rejection ratio
±1
TA = –40°C to +125°C (2)
±3
±4
TA = –40°C to +125°C
2
7
2
mV
μV/°C
μV/V
GAIN
Gain
Gain error
Gain nonlinearity
1
TA = –40°C to +125°C (2)
VS = ±18 V, –10 V < VO < 10 V
(2)
V/V
0.04%
0.05%
0.05%
0.06%
1
5
ppm
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
(V–) + 0.25
(V–) + 0.25 V ≤ VCM ≤ (V+) – 2 V, REF and COM pins
connected to ground, VS = ±18 V
CMRR
Common-mode rejection ratio
TA = –40°C to +125°C
(V–) + 0.25 V ≤ VCM ≤ (V+) – 2 V, REF and COM pins
connected to VMID(OUT), VS = ±18 V
TA = –40°C to +125°C
CMRR
(1)
(2)
6
Common-mode rejection ratio
(2)
(2)
(V–) + 0.25 V ≤ VCM ≤ (V+) – 2 V, REF and COM pins
connected to ground, VS = ±18 V, RS mismatch = 20 Ω
(V+) – 2
85
91
82
89
82
86
76
84
84
V
dB
dB
Full-power bandwidth = SR / (2π × VP), where SR = slew rate.
Specified by design and characterization.
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Electrical Characteristics: (continued)
at TA = 25°C, VS = ±2.25 V to ±18 V, VCM = VOUT = midsupply, and RL = 2 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
850
212.5
1000
1150
kΩ
250
287.5
kΩ
0.01%
0.25%
INPUT IMPEDANCE
Differential
Common-mode
Input resistance mismatch
SUPPLY DIVIDER CIRCUIT
Nominal output voltage
[ (V+) + (V–) ] / 2
2
V
Output voltage offset
VMID(IN) = ((V+) + (V–) / 2
4
mV
Input impedance
VMID(IN) pin, f = 1 kHz
250
Output resistance
VMID(OUT) pin
0.35
Ω
Output voltage noise
20 Hz to 20 kHz, CMID = 1 µF
1.56
µVRMS
Output capacitive load limit
Phase margin > 45°, RISO = 0 Ω
150
pF
kΩ
OUTPUT
Positive rail
VO
Voltage output swing from rail
Negative rail
RL = 2 kΩ
350
RL = 600 Ω
1100
RL = 2 kΩ
mV
430
RL = 600 Ω
1300
ZOUT
Output impedance
f ≤ 100 kHz, IOUT = 0 A
80 dB at 1 kHz
THD+N: < –100 dB (4-dBu input signal, 1-kHz fundamental, 90-kHz measurement bandwidth)
8.2.1.2 Detailed Design Procedure
The passive components shown in Figure 51 are selected using the information given in the Application
Information and Layout Guidelines sections. All 10-µF input AC-coupling capacitors (C1, C2, C3, and C4)
maximize the CMRR performance at low frequency, as shown in Figure 48. The high-pass corner frequency for
input signals meets the design requirement for frequency response, as Equation 6 shows:
1
1
FC
0.032 Hz
2 ˜ S ˜ RIN ˜ CIN 2 ˜ S ˜ (500 k:) ˜ (10 PF)
(6)
1-MΩ RCOM resistors (R3 and R4) further improve CMRR performance at low frequency. Resistors R1, R2, R4,
and R5 provide a discharge pathway for the AC-coupling capacitors in the event that audio equipment with a DC
offset voltage is connected to the inputs of the circuit. These resistors are optional and may degrade the CMRR
performance with mismatches in source impedance. Finally, capacitors C5, C6, C7, and C8 provide a lowimpedance pathway for power supply noise to pass to ground rather than interfering with the audio signal. No
connection is necessary on the VMID(IN) and VMID(OUT) pins because the supply-divider circuit is not used in this
particular application.
8.2.1.3 Application Curves
Figure 52 through Figure 57 illustrate the measured performance of the line receiver circuit. Figure 52 shows the
measured frequency response. The gain of the circuit is 0 dB as expected with 0.1-dB magnitude variation at 10
Hz. The measured CMRR of the circuit (Figure 53) at 1 kHz equals 94 dB without any source impedance
mismatch. Adding a 10-Ω source impedance mismatch degrades the CMRR at 1 kHz to 92 dB. The highfrequency degradation of CMRR shown in Figure 53 for the 10-Ω source impedance mismatch cases is due to
the capacitance of the cables used for the measurement. The total harmonic distortion plus noise (THD+N) is
plotted over frequency in Figure 54. For a 4-dBu (1.23 VRMS) input signal level, the THD+N remains flat at –101.6
dB (0.0008%) over the measured frequency range. Increasing the signal level to 22 dBu further decreases the
THD+N to –115.2 dB (0.00017%) at 1 kHz, but the THD+N rises above 7 kHz. Measuring the THD+N vs Output
Amplitude (Figure 55) at 1 kHz shows a constant downward slope until the noise floor of the audio analyzer is
reached at 5 VRMS. The constant downward slope indicates that noise from the device dominates THD+N at this
frequency instead of distortion harmonics. Figure 56 and Figure 57 confirm this conclusion. For a 4–dBu signal
level, the second harmonic is barely visible above the noise floor at –140 dBu. Increasing the signal level to 22
dBu produces distortion harmonics above the noise floor. The largest harmonic in this case is the second at
–111.2 dBu, or –133.2 dB relative to the fundamental.
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Typical Applications (continued)
1
±40
No Mismatch
10- Mismatch, XLR Pin 2
10- Mismatch, XLR Pin 3
0.8
±50
0.6
±60
0.2
Gain (dB)
Gain (dB)
0.4
0
-0.2
±70
±80
-0.4
-0.6
±90
-0.8
-1
±100
10
100
1k
10k
10
100k
Frequency (Hz)
100
1k
10k
100k
Frequency (Hz)
C001
C001
1-VRMS Common-Mode Signal
-100
0.001
-120
0.0001
-140
0.00001
10
100
1k
10k
Frequency (Hz)
0.1
-60
0.01
-80
0.001
-100
0.0001
-120
-140
0.00001
0.01
0.1
C014
Figure 55. THD+N vs Amplitude
20
40
0
20
0
Amplitude (dBu)
±20
Amplitude (dBu)
10
22-kHz Measurement Bandwidth
Figure 54. THD+N vs Frequency
±40
±60
±80
±100
±20
±40
±60
HD2: -111.2 dBu (-133.2 dBc)
±80
±100
HD3: -120.1 dBu (-142.1 dBc)
±120
±120
HD4: -130.7 dBu (-152.7 dBc)
±140
±140
±160
±160
0
5k
10k
15k
Frequency (Hz)
24
1
Output Voltage (VRMS)
C001
90-kHz Measurement Bandwidth
Total Harmonic Distortion + Noise (dB)
-80
22 dBu (9.75 VRMS)
4 dBu (1.23 VRMS)
Total Harmonic Distortion + Noise (%)
0.01
Figure 53. Common-Mode Rejection Ratio vs Frequency
Total Harmonic Distortion + Noise (dB)
Total Harmonic Distortion + Noise (%)
Figure 52. Frequency Response
20k
0
C004
5k
10k
15k
Frequency (Hz)
4–dBu Output Amplitude
22–dBu Output Amplitude
Figure 56. Output Spectrum
Figure 57. Output Spectrum
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20k
C004
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Typical Applications (continued)
8.2.2 Differential Line Receiver for Single-Supply Applications
The INA1650 can simply operate in single-supply applications by connecting the COM and REF pins to the
output of the internal supply divider.
(VMID(OUT). Adding a 1-µF capacitor to the VMID(IN) pin to filters noise from the power supply and the internal
voltage divider.
12 V
C7 1 F
Input Differential
Audio Signals
C1
10 F
C6 0.1 F
1 VCC
R1
100 k
2
3
1
R2
100 k
C2
10 F
XLR Connector
R4
100 k
3
2
1
R5
100 k
C3
10 F
C4
10 F
VEE 14
2 IN+ A
OUT A 13
3 COM A
REF A 12
4 IN- A
VMID(IN) 11
5 IN- B
VMID(OUT) 10
6 COM B
REF B 9
7 IN+ B
OUT B 8
C5 1 F
Output Single-Ended
Audio Signals
INA1650
XLR Connector
Copyright © 2016, Texas Instruments Incorporated
Figure 58. Differential Line Receiver for Single-Supply Applications
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Typical Applications (continued)
8.2.3 Floating Single-Ended Input Line Receiver for Ground Loop Noise Reduction
Ground loops commonly form in audio systems where the equipment is interconnected with coaxial cables, which
introduces significant common-mode noise. If the sheath of the coaxial cable is connected to the equipment
chassis and safety ground, a ground loop forms, which includes the main electrical wiring and the audio signal
path. The INA165x can break these ground loops by floating the sheath of the coaxial cable through resistors
(R3 and R4 in Figure 59) so ground noise appears at the inputs of the INA165x as a common-mode signal.
Capacitors C8 and C9 provide a high-frequency pathway to ground for radio frequency interference (RFI). A
transient voltage suppressor (TVS) connected between the coaxial sheath and the chassis ground is shown in
Figure 59. This TVS protects the inputs of the INA165x in the event of an electrostatic discharge to the signal
input.
12 V
C7 1 F
C6 0.1 F
C1
10 F
RCA Input
R1
10 k
R3
33
C9
10 nF
C8
10 nF
R2
10 k
R4
33
RCA Input
1 VCC
C2
10 F
C3
10 F
C4
10 F
VEE 14
2 IN+ A
OUT A 13
3 COM A
REF A 12
4 IN- A
VMID(IN) 11
5 IN- B
VMID(OUT) 10
6 COM B
REF B 9
7 IN+ B
OUT B 8
C5 1 F
INA1650
TPD2E007
Copyright © 2016, Texas Instruments Incorporated
Figure 59. Ground Loop Isolation in Single-Ended Systems
26
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Typical Applications (continued)
8.2.4 Floating Single-Ended Input Line Receiver With Differential Outputs
The application in Figure 59 can be further extended to include differential outputs, which are necessary for audio
ADCs and many Class-D amplifier devices. Figure 60 shows the addition of an OPA1688 audio operational
amplifier to the outputs of the INA1650 that convert the single-ended outputs to differential outputs.
12 V
C7 1 F
R5
10 k
C8 0.1 F
Differential
Output
+12V
C2
10 F
3 COM A
REF A 12
4 IN- A
VMID(IN) 11
5 IN- B
VMID(OUT) 10
VS+
R1
10 k
OUT A 13
VS±
C5 10 nF
VEE 14
2 IN+ A
±
1 VCC
C1
10 F
RCA Input
+
R3 33
½
OPA1688
R6
10 k
C11
10 pF
R7
10 k
C10
10 pF
C9 1 F
TPD2E007
C6 10 nF
RCA Input
C4
10 F
6 COM B
REF B 9
7 IN+ B
OUT B 8
½
OPA1688
INA1650
+
R4 33
C3
10 F
±
R2
10 k
Differential
Output
R8
10 k
Copyright © 2016, Texas Instruments Incorporated
Figure 60. Single-Ended Line-Receiver Circuit With Differential Outputs
8.2.5 TRS Audio Interface in Single-Supply Applications
The INA1650 can be used for auxiliary audio inputs which may use a tip-ring-sleeve (TRS) connector where both
audio channels share a common ground connection. Figure 61 shows the INA1650 configured as a line receiver
for a TRS interface to remove common-mode noise on the sleeve connection.
12 V
C7 1 F
C6 0.1 F
TRS Jack
C1
10 F
Ring
Tip
R1
100 k
C2
10 F
R2
100 k
C8 10 nF
R3 33
Sleeve
C3
10 F
C4
10 F
1
VCC
2
IN+ A
OUT A 13
3
COM A
REF A 12
4
IN- A
VMID(IN) 11
5
IN- B
VMID(OUT) 10
6
COM B
VEE 14
7 IN+ B
REF B
9
OUT B
8
Right
Output
C5 1 F
Left
Output
INA1650
Copyright © 2016, Texas Instruments Incorporated
Figure 61. TRS Audio Interface in Single-Supply Applications
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Typical Applications (continued)
8.2.6 Differential Line Driver With Single-Ended Input
The INA1650 can be employed in line-driver applications (Figure 62) where the precision matched internal
resistor networks are useful in converting a single-ended signal to a balanced signal. Resistors R1 and R4
(shown in Figure 62) isolate the large cable capacitance from the outputs of the INA1650 to maintain stability. TI
recommends AC-coupling capacitors C1 and C2 since the DC voltages of the connected equipment may be
unknown. Resistors R2 and R3 dissipate any charge collected on the capacitors due to connecting equipment
with a DC voltage present.
18 V
-18 V
C5 1 F
C3 1 F
C6 0.1 F
C4 0.1 F
1 VCC
Single-Ended
Input Signal
VEE 14
2 IN+ A
OUT A 13
3 COM A
REF A 12
4 IN- A
VMID(IN) 11
5 IN- B
VMID(OUT) 10
R1
49.9
C1
10 F
Differential
Output Signal
R2
100 k
2
XLR Connector
6 COM B
REF B 9
7 IN+ B
OUT B 8
INA1650
1
R3
100 k
R4
49.9
3
C2
10 F
Copyright © 2016, Texas Instruments Incorporated
Figure 62. INA1650 Used as a Balanced Audio Line Driver
28
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SBOS818B – DECEMBER 2016 – REVISED NOVEMBER 2018
9 Power Supply Recommendations
The INA165x operates from ±2.25-V to ±18-V supplies while maintaining excellent performance. However, some
applications do not require equal positive and negative output voltage swing. With the INA165x, power-supply
voltages do not need to be equal. For example, the positive supply can be set to 25 V with the negative supply at
–5 V.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Connect low-ESR, 1.0-µF and 0.1-µF ceramic bypass capacitors between each supply pin and ground,
placed as close to the device as possible. Connecting bypass capacitors only from V+ to ground is
acceptable in single-supply applications. Noise can propagate into analog circuitry through the power pins of
this device. The bypass capacitors reduce the coupled noise by providing low-impedance pathways to
ground.
• Connect the device REF pins to a low-impedance, low-noise, system reference point (such as an analog
ground or the VMID(OUT) pin) with the shortest trace possible.
• Place the external components as close to the device as possible, as shown in Figure 63 and Figure 64.
• Use ground pours and planes to shield input signal traces and minimize additional noise introduced into the
signal path.
• Keep the length of input traces equal and as short as possible. Route the input traces as a differential pair
with as minimal spacing between them as possible.
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10.2 Layout Examples
+V
C1
-V
C5
C7
C6
C8
IN+ A
R1
Input reference /
shield
1 VCC
VEE 14
R3
R2
2 IN+ A
OUT A 13
3 COM A
REF A 12
IN- A
C2
4 IN- A
VMID(IN) 11
C3
5 IN- B
VMID(OUT) 10
IN+ B
R4
6 COM B
REF B 9
7 IN+ B
OUT B 8
R4
Input reference /
shield
R5
INA1650
IN- B
C4
+V
GND
C5
C7
Place bypass
capacitors as close to
IC as possible
-V
GND
GND
Connect COM pins to
input signal reference
C6
IN+ A
R3
R2
R1
Input reference /
shield
C1
IN- A
C2
C8
1 VCC
VEE 14
2 IN+ A
OUT A 13
3 COM A
REF A 12
4 IN- A
VMID(IN) 11
5 IN- B
VMID(OUT) 10
GND
C3
Input reference /
shield
R4
R4
IN- B
C4
R5
IN+ B
Input pairs routed
adjacent to each
other
6 COM B
REF B 9
7 IN+ B
OUT B 8
INA1650
Use ground pours for
shielding the input
signal pairs
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 63. Layout Example for a Dual-Supply Line Receiver
30
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SBOS818B – DECEMBER 2016 – REVISED NOVEMBER 2018
Layout Examples (continued)
+V
C7
C6
C1
1 VCC
IN+
R1
Input reference /
shield
R2
IN-
C3
Input reference /
shield
R5
REF A 12
3 COM A
C2
IN-
R4
VEE 14
OUT A 13
2 IN+ A
C4
4 IN- A
VMID(IN) 11
5 IN- B
VMID(OUT) 10
6 COM B
REF B 9
7 IN+ B
OUT B 8
C5
INA1650
IN+
+V
GND
C7
C6
IN+
C1
R2
R1
Input reference /
shield
IN-
IN-
C2
C3
R5
R4
Input reference /
shield
IN+
1 VCC
Connect VEE to lowimpedance ground
GND
Place VMID(IN) filter
capacitor as close to
IC as possible
VEE 14
2 IN+ A
OUT A 13
3 COM A
REF A 12
4 IN- A
VMID(IN) 11
5 IN- B
VMID(OUT) 10
6 COM B
REF B 9
7 IN+ B
OUT B 8
GND
C5
Use a low-impedance
connection to
connect reference
pins to VMID(OUT)
C4
GND
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 64. Layout Example for a Single-Supply Line Receiver
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www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the WEBENCH® Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 TI Precision Designs
TI Precision Designs are available online at http://www.ti.com/ww/en/analog/precision-designs/. TI Precision
Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of
operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured
performance of many useful circuits.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
Circuit Board Layout Techniques
11.3 Related Links
Table 1 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to order now.
Table 1. Related Links
32
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
INA1650
Click here
Click here
Click here
Click here
Click here
INA1651
Click here
Click here
Click here
Click here
Click here
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Copyright © 2016–2018, Texas Instruments Incorporated
Product Folder Links: INA1650 INA1651
INA1650, INA1651
www.ti.com
SBOS818B – DECEMBER 2016 – REVISED NOVEMBER 2018
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.6 Trademarks
SoundPlus, E2E are trademarks of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: INA1650 INA1651
33
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
INA1650IPW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
IN1650C
INA1650IPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
IN1650C
INA1651IPW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA1651
INA1651IPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA1651
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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