INA203, INA204, INA205
SBOS393F – MARCH 2007 – REVISED JUNE 2021
INA20x –16-V to 80-V, 500-kHz Current Sense Amplifier With Dual Comparators
1 Features
3 Description
•
•
The INA203, INA204, and INA205 are a family
of unidirectional current-shunt monitors with voltage
output, dual comparators, and voltage reference. The
INA203, INA204, and INA205 can sense drops across
shunts at common-mode voltages from –16 V to 80 V.
The INA203, INA204, and INA205 are available with
three output voltage scales: 20 V/V, 50 V/V, and 100
V/V, with up to 500-kHz bandwidth.
•
•
•
•
•
•
Complete current sense solution
Three gain options available:
– INA203 = 20 V/V
– INA204 = 50 V/V
– INA205 = 100 V/V
Dual comparators:
– Comparator 1 with latch
– Comparator 2 with optional delay
Common-mode range: –16 V to 80 V
High accuracy: 3.5% (maximum) over temperature
Bandwidth: 500 kHz
Quiescent current: 1.8 mA
Packages: SO-14, TSSOP-14, VSSOP-10
2 Applications
•
•
•
•
•
•
•
Notebook computers
Cell phones
Telecom equipment
Automotive
Power management
Battery chargers
Welding equipment
The INA203, INA204, and INA205 also incorporate
two open-drain comparators with internal 0.6-V
references. On 14-pin versions, the comparator
references can be overridden by external inputs.
Comparator 1 includes a latching capability, and
Comparator 2 has a user-programmable delay. 14-pin
versions also provide a 1.2-V reference output.
The INA203, INA204, and INA205 operate from a
single 2.7-V to 18-V supply. They are specified over
the extended operating temperature range of –40°C to
125°C.
Device Information (1)
PART NUMBER
PACKAGE
INA203,
INA204,
INA205
(1)
BODY SIZE (NOM)
SOIC (14)
8.65 mm × 3.91 mm
VSSOP (10)
3.00 mm × 3.00 mm
TSSOP (14)
5.00 mm × 4.40 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
VS
1
OUT
2
14 VIN+
13 VIN1.2V REF
CMP1 IN-/0.6V REF
3
12 1.2V REF OUT
CMP1 IN+
4
11 CMP1 OUT
CMP2 IN+
5
10 CMP2 OUT
CMP2 IN-/0.6V REF
6
9
CMP2 DELAY
GND
7
8
CMP1 RESET
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA203, INA204, INA205
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SBOS393F – MARCH 2007 – REVISED JUNE 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics: Current-Shunt Monitor....... 6
6.6 Electrical Characteristics: Comparator........................7
6.7 Electrical Characteristics: Reference.......................... 9
6.8 Electrical Characteristics: General..............................9
6.9 Typical Characteristics.............................................. 10
7 Detailed Description......................................................14
7.1 Overview................................................................... 14
7.2 Functional Block Diagrams....................................... 14
7.3 Feature Description...................................................14
7.4 Device Functional Modes..........................................18
8 Application and Implementation.................................. 22
8.1 Application Information............................................. 22
8.2 Typical Application.................................................... 22
9 Power Supply Recommendations................................23
10 Layout...........................................................................24
10.1 Layout Guidelines................................................... 24
10.2 Layout Example...................................................... 24
11 Device and Documentation Support..........................25
11.1 Related Links.......................................................... 25
11.2 Receiving Notification of Documentation Updates.. 25
11.3 Support Resources................................................. 25
11.4 Trademarks............................................................. 25
11.5 Electrostatic Discharge Caution.............................. 25
11.6 Glossary.................................................................. 25
12 Mechanical, Packaging, and Orderable
Information.................................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (November 2015) to Revision F (June 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Changed maximum input voltage for accurate measurements from: (VSHUNT – 0.25) / Gain to: (VOUT – 0.25) /
Gain.................................................................................................................................................................. 15
Changes from Revision D (May 2009) to Revision E (November 2015)
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 1
• Moved thermal values from Electrical Characteristics: General to Thermal Information table. Removed
duplicate storage temperature parameter...........................................................................................................9
Changes from Revision C (October 2007) to Revision D (May 2009)
Page
• Changed Figure 6-1 ...........................................................................................................................................7
2
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Device Comparison
Table 5-1. Device Gain
DEVICE
GAIN
INA203
20 V/V
INA204
50 V/V
INA205
100 V/V
Table 5-2. Related Products
FEATURES
PRODUCT
Variant of INA203–INA205 Comparator 2 polarity
INA206–INA208
Current-shunt monitor with single Comparator and VREF
INA200–INA202
Current-shunt monitor only
INA193–INA198
Current-shunt monitor with split stages for filter options
INA270–INA271
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5 Pin Configuration and Functions
VS
1
OUT
2
14 VIN+
13 VIN1.2V REF
CMP1 IN-/0.6V REF
3
12 1.2V REF OUT
CMP1 IN+
4
11 CMP1 OUT
CMP2 IN+
5
10 CMP2 OUT
CMP2 IN-/0.6V REF
6
9
CMP2 DELAY
GND
7
8
CMP1 RESET
Figure 5-1. D and PW Packages 14-Pin SOIC and TSSOP Top View
VS
1
10 VIN+
OUT
2
9
VIN-
CMP1 IN+
3
8
CMP1 OUT
CMP2 IN+
4
7
CMP2 OUT
GND
5
6
CMP1 RESET
0.6V REF
Figure 5-2. DGS Package 10-Pin VSSOP Top View
Table 5-1. Pin Functions
PIN
NAME
4
I/O
DESCRIPTION
SOIC, TSSOP
VSSOP
VS
1
1
I
Power Supply
OUT
2
2
O
Output voltage
CMP1 IN-/0.6-V Ref
3
—
I
Comparator 1 negative input, can be used to override the internal
0.6-V reference
CMP1 IN+
4
3
I
Comparator 1 positive input
CMP2 IN+
5
—
I
Comparator 2 positive input
CMP2 IN–
—
4
I
Comparator 2 negative input
CMP2 IN–/0.6-V Ref
6
—
I
Comparator 2 negative input, can be used to override the internal
0.6-V reference
GND
7
5
I
Ground
CMP1 RESET
8
6
I
Comparator 1 output reset, active low
CMP2 DELAY
9
—
I
Connect an optional capacitor to adjust comparator 2 delay
CMP2 OUT
10
7
O
Comparator 2 output
CMP1 OUT
11
8
O
Comparator 1 output
1.2-V REF OUT
12
—
O
1.2-V reference output
VIN–
13
9
I
Connect to shunt low side
VIN+
14
10
I
Connect to shunt high side
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6 Specifications
6.1 Absolute Maximum Ratings
See (1)
MIN
Supply Voltage, VS
MAX
UNIT
18
V
Differential (VIN+) – (VIN–)
–18
18
V
Common-Mode
–16
80
V
Comparator Analog Input and Reset Pins
GND – 0.3
(VS) + 0.3
V
Analog Output, Out Pin
GND – 0.3
(VS) + 0.3
V
Comparator Output, Out Pin
GND – 0.3
18
V
VREF and CMP2 Delay Pin
GND – 0.3
10
V
5
mA
Operating Temperature
–55
150
°C
Junction Temperature
–65
150
°C
Storage temperature, Tstg
–65
150
°C
Current-Shunt Monitor Analog
Inputs, VIN+ and VIN–
Input Current Into Any Pin
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±4000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
–16
12
80
Operating supply voltage
2.7
12
18
V
Operating free-air temperature
–40
25
125
°C
VCM
Common-mode input voltage
VS
TA
UNIT
V
6.4 Thermal Information
INA20x
THERMAL METRIC
(1)
UNIT
D (SOIC)
DGS (VSSOP)
PW (TSSOP)
14 PINS
10 PINS
14 PINS
84.9
161.3
112.6
°C/W
44
36.8
37.2
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
39.4
82.3
55.4
°C/W
ψJT
Junction-to-top characterization parameter
10.3
1.3
2.7
°C/W
ψJB
Junction-to-board characterization parameter
39.1
80.8
54.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
150
200
150
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics: Current-Shunt Monitor
At TA = 25°C, VS = 12 V, VCM = 12 V, VSENSE = 100 mV, RL = 10 kΩ to GND, Rpullup = 5.1 kΩ each connected from CMP1
OUT and CMP2 OUT to VS, and CMP1 IN+ = 1 V and CMP2 IN– = GND, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.15
(VS – 0.25)/
Gain
V
80
V
INPUT
VSENSE
Full-Scale Sense Input
Voltage
VSENSE = VIN+ – VIN–
VCM
Common-Mode Input
Range
TA = –40°C to 125°C
–16
CMRR
Common-Mode Rejection
Ratio
VCM = –16 V to 80 V
80
100
dB
CMRR over Temperature
VCM = 12 V to 80 V
100
123
dB
TA = –40°C to
125°C
±0.5
VOS
Offset Voltage, RTI
dVOS/dT
Offset Voltage, RTI
Temperature
PSR
IB
(1)
(1)
vs.
±2.5
mV
25°C to 125°C
±3
mV
–40°C to 25°C
±3.5
mV
TMIN to TMAX
TA = –40°C to
125°C
5
Offset Voltage, RTI (1) vs.
Power Supply
VOUT = 2 V,
VCM = 18 V, 2.7 V
TA = –40°C to
125°C
2.5
100
μV/V
Input Bias Current,
VIN– Pin
TA = –40°C to 125°C
±9
±16
μA
INA203
20
V/V
INA204
50
V/V
μV/°C
OUTPUT (VSENSE ≥ 20 mV)
G
Gain
INA205
RO
100
Gain Error
VSENSE = 20 mV to 100 mV
Gain Error over
Temperature
VSENSE = 20 mV to TA = –40°C to
100 mV
125°C
Total Output Error (2)
VSENSE = 120 mV,
VS = 16 V
Total Output Error (2) over
Temperature
VSENSE = 120 mV,
VS = 16 V
Nonlinearity Error (3)
VSENSE = 20 mV to 100 mV
TA = –40°C to
125°C
No Sustained Oscillation
V/V
±1%
±2%
±0.75%
Output Impedance, Pin 2
Maximum Capacitive Load
±0.2%
±2.2%
±3.5%
±0.002%
1.5
Ω
10
nF
300
mV
OUTPUT (VSENSE < 20 mV) (4)
INA203, INA204, INA205
output
–16 V ≤ VCM < 0 V
INA203 output
0 V ≤ VCM ≤ VS, VS = 5 V
0.4
V
INA204 output
0 V ≤ VCM ≤ VS, VS = 5 V
1
V
INA205 output
0 V ≤ VCM ≤ VS, VS = 5 V
2
V
INA203, INA204, INA205
output
VS < VCM ≤ 80 V
300
mV
VOLTAGE OUTPUT (5)
6
Output Swing to the
Positive Rail
VIN– = 11 V,
VIN+ = 12 V
TA = –40°C to
125°C
(Vs) – 0.15
(Vs) – 0.25
V
Output Swing to GND (6)
VIN– = 0 V,
VIN+ = –0.5 V
TA = –40°C to
125°C
(VGND) + 0.004
(VGND) + 0.05
V
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At TA = 25°C, VS = 12 V, VCM = 12 V, VSENSE = 100 mV, RL = 10 kΩ to GND, Rpullup = 5.1 kΩ each connected from CMP1
OUT and CMP2 OUT to VS, and CMP1 IN+ = 1 V and CMP2 IN– = GND, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
BW
Bandwidth
Phase Margin
SR
INA203; CLOAD = 5 pF
500
kHz
INA204; CLOAD = 5 pF
300
kHz
INA205; CLOAD = 5 pF
200
kHz
CLOAD < 10 nF
40
Slew Rate
VSENSE = 10 mVPP to 100 mVPP,
CLOAD = 5 pF
Settling Time (1%)
1
V/μs
2
μs
40
nV/√ Hz
NOISE, RTI
Output Voltage Noise
Density
(1)
(2)
(3)
(4)
(5)
(6)
Offset is extrapolated from measurements of the output at 20 mV and 100 mV VSENSE.
Total output error includes effects of gain error and VOS.
Linearity is best fit to a straight line.
For details on this region of operation, see the Accuracy Variations as a Result Of VSENSE and Common-Mode Voltage section in the
Application and Implementation.
See Typical Characteristic curve Positive Output Voltage Swing vs. Output Current (Positive Output Voltage Swing vs. Output Current).
Specified by design; not production tested.
6.6 Electrical Characteristics: Comparator
At TA = 25°C, VS = 12 V, VCM = 12 V, VSENSE = 100 mV, RL = 10 kΩ to GND, and Rpullup = 5.1 kΩ each connected from CMP1
OUT and CMP2 OUT to VS, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
Offset Voltage
Comparator Common-Mode Voltage =
Threshold Voltage
Offset Voltage Drift,
Comparator 1
2
mV
TA = –40°C to 125°C
±2
μV/°C
Offset Voltage Drift,
Comparator 2
TA = –40°C to 125°C
5.4
μV/°C
Threshold
TA = 25°C
590
Threshold over
Temperature
TA = –40°C to 125°C
586
Hysteresis (1), CMP1
TA = –40°C to 85°C
–8
mV
Hysteresis (1), CMP2
TA = –40°C to 85°C
8
mV
INPUT BIAS CURRENT
608
620
mV
625
mV
(2)
CMP1 IN+, CMP2 IN+
0.005
CMP1 IN+, CMP2 IN+ vs.
TA = –40°C to 125°C
Temperature
10
nA
15
nA
INPUT IMPEDANCE
Pins 3 and 6 (14-pin
packages only)
10
kΩ
INPUT RANGE
CMP1 IN+ and CMP2
IN+
0 V to VS – 1.5 V
V
Pins 3 and 6 (14-pin
packages only) (3)
0 V to VS – 1.5 V
V
OUTPUT
Large-Signal Differential
Voltage Gain
CMP VOUT 1 V to 4 V, RL ≥ 15 kΩ
Connected to 5 V
200
V/mV
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At TA = 25°C, VS = 12 V, VCM = 12 V, VSENSE = 100 mV, RL = 10 kΩ to GND, and Rpullup = 5.1 kΩ each connected from CMP1
OUT and CMP2 OUT to VS, unless otherwise noted.
PARAMETER
TEST CONDITIONS
High-Level Output
Current
MIN
VID = 0.4 V, VOH = VS
TYP
MAX
0.0001
1
μA
220
300
mV
Low-Level Output Voltage VID = –0.6 V, IOL = 2.35 mA
UNIT
RESPONSE TIME (4)
Comparator 1
RL to 5 V, CL = 15 pF, 100-mV Input Step
with 5-mV Overdrive
1.3
μs
Comparator 2
RL to 5 V, CL = 15 pF, 100-mV Input Step
with 5-mV Overdrive, CDELAY Pin Open
1.3
μs
RESET
RESET Threshold (5)
1.1
Logic Input Impedance
MΩ
1.5
μs
RESET Propagation
Delay
3
μs
Comparator 2 Delay
Equation (6)
CDELAY = tD/5
μF
Minimum RESET Pulse
Width
tD
(1)
(2)
(3)
(4)
(5)
(6)
V
2
Comparator 2 Delay
CDELAY = 0.1 μF
0.5
s
Hysteresis refers to the threshold (the threshold specification applies to a rising edge of a noninverting input) of a falling edge on the
noninverting input of the comparator; refer to Figure 6-1.
Specified by design; not production tested.
See the Comparator Maximum Input Voltage Range section in the Application and Implementation.
The comparator response time specified is the interval between the input step function and the instant when the output crosses 1.4 V.
The CMP1 RESET input has an internal 2-MΩ (typical) pulldown. Leaving the CMP1 RESET open results in a LOW state, with
transparent comparator operation.
The Comparator 2 delay applies to both rising and falling edges of the comparator output.
VTHRESHOLD
0.592
VTHRESHOLD
0.6
0.6
0.608
Input Voltage
Input Voltage
Hysteresis = VTHRESHOLD - 8mV
Hysteresis = VTHRESHOLD - 8mV
a) CMP1
b) CMP2
Figure 6-1. Comparator Hysteresis
8
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6.7 Electrical Characteristics: Reference
At TA = 25°C, VS = 12 V, VCM = 12 V, VSENSE = 100 mV, RL = 10 kΩ to GND, and Rpullup = 5.1 kΩ each connected from CMP1
OUT and CMP2 OUT to VS, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.188
1.2
1.212
40
100
UNIT
REFERENCE VOLTAGE
1.2-VREFOUT Output
Voltage
dVOUT/dT
dVOUT/dT
Reference Drift
TA = –40°C to 85°C
0.6-VREF Output
Voltage
Pins 3 and 6 of 14-pin packages only
Reference Drift
TA = –40°C to 85°C
LOAD REGULATION
0.6
V
ppm/°C
v
40
100
ppm/°C
2
mV/mA
dVOUT/dILOAD
Sourcing
0mA < ISOURCE < 0.5mA
0.4
Sinking
0mA < ISINK < 0.5mA
0.4
ILOAD
Load Current
dVOUT/dVS
Line Regulation
2.7 V < VS < 18 V
mV/mA
1
mA
30
μV/V
CAPACITIVE LOAD
Reference Output
Maximum Capacitive
Load
10
No Sustained Oscillations
nF
OUTPUT IMPEDANCE
Output Impedance
Pins 3 and 6 of 14-Pin Packages Only
10
kΩ
6.8 Electrical Characteristics: General
All specifications at TA = 25°C, VS = 12 V, VCM = 12 V, VSENSE = 100 mV, RL = 10 kΩ to GND, Rpullup = 5.1 kΩ each
connected from CMP1 OUT and CMP2 OUT to VS, and CMP1 IN+ = 1 V and CMP2 IN– = GND, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
18
V
1.8
2.2
mA
2.8
mA
POWER SUPPLY
VS
Operating power supply
TA = –40°C to 125°C
IQ
Quiescent current
VOUT = 2 V
Quiescent current over
temperature
VSENSE = 0 mV
2.7
Comparator power-on
reset threshold (1)
1.5
V
TEMPERATURE
(1)
Specified temperature
–40
125
°C
Operating temperature
–55
150
°C
The INA203, INA204, and INA205 are designed to power-up with the comparator in a defined reset state as long as CMP1 RESET
is open or grounded. The comparator will be in reset as long as the power supply is below the voltage shown here. The comparator
assumes a state based on the comparator input above this supply voltage. If CMP1 RESET is high at power-up, the comparator output
comes up high and requires a reset to assume a low state, if appropriate.
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6.9 Typical Characteristics
All specifications at TA = 25°C, VS = 12 V, VCM = 12 V, and VSENSE = 100 mV, unless otherwise noted.
45
40
G = 50
35
Gain (dB)
30
G = 100
40
G = 50
35
Gain (dB)
45
CLOAD = 1000pF
G = 100
G = 20
25
20
30
20
15
15
10
10
5
G = 20
25
5
10k
100k
10k
1M
100k
Frequency (Hz)
Figure 6-2. Gain vs. Frequency
Figure 6-3. Gain vs. Frequency
20
140
18
130
Common-Mode and
Power-Supply Rejection (dB)
100V/V
16
VOUT (V)
14
50V/V
12
10
8
20V/V
6
4
CMR
110
100
90
PSR
80
70
60
40
0
20
100
200
300
400
500
600
700
800
10
900
100
1k
10k
100k
Frequency (Hz)
VDIFFERENTIAL (mV)
Figure 6-4. Gain Plot
Figure 6-5. Common-Mode and Power-Supply
Rejection vs. Frequency
4.0
0.1
3.5
0.09
0.08
3.0
Output Error (% )
Output Error
(% error of the ideal output value)
120
50
2
2.5
2.0
1.5
1.0
0.07
0.06
0.05
0.04
0.03
0.02
0.5
0.01
0
0
50
100 150
200
250 300
350 400 450 500
0
-16 -12 -8 -4
VSENSE (mV)
0
4
8
12 16 20
...
76 80
Common-Mode Voltage (V)
Figure 6-6. Total Output Error vs. VSENSE
10
1M
Frequency (Hz)
Figure 6-7. Total Output Error vs. Common-Mode
Voltage
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3.5
12
11
VS = 12V
10
9
2.5
+25°C
8
-40°C
+125°C
7
6
VS = 3V
5
Sourcing Current
+25°C
4
-40°C
Output stage is designed
to source current. Current
sinking capability is
approximately 400mA.
3
2
1
+125°C
0
0
IQ (mA)
Output Voltage (V)
3.0
Sourcing Current
2.0
1.5
1.0
0.5
0
5
10
20
15
25
30
0
1
2
Output Current (mA)
Output Short-Circuit Current (mA)
VS = 2.7V
IQ (mA)
1.50
1.25
VS = 12V
1.00
VS = 2.7V
VSENSE = 0mV
7
6
34
VS = 12V
0.75
0.50
-16 -12 -8 -4
5
8
9
10
Figure 6-9. Quiescent Current vs. Output Voltage
VSENSE = 100mV
1.75
4
Output Voltage (V)
Figure 6-8. Positive Output Voltage Swing vs.
Output Current
2.00
3
-40°C
30
+25°C
26
+125°C
22
18
14
10
6
0
4
8
12 16 20 24 28 32 36
2.5 3.5
4.5
VCM (V)
5.5 6.5
7.5
8.5
9.5 10.5 11.5 17
18
Supply Voltage (V)
Figure 6-10. Quiescent Current vs. Common-Mode
Voltage
Figure 6-11. Output Short-Circuit Current vs.
Supply Voltage
G = 20
Output Voltage (50mV/div)
Output Voltage (500mV/div)
G = 20
VSENSE = 20mV to 30mV
VSENSE = 20mV to 110mV
Time (2ms/div)
Time (2ms/div)
Figure 6-12. Step Response
Figure 6-13. Step Response
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G = 50
Output Voltage (50mV/div)
Output Voltage (100mV/div)
G = 20
VSENSE = 20mV to 30mV
VSENSE = 90mV to 100mV
Time (5ms/div)
Time (2ms/div)
Figure 6-15. Step Response
Figure 6-14. Step Response
G = 50
Output Voltage (1V/div)
Output Voltage (100mV/div)
G = 50
VSENSE = 20mV to 110mV
VSENSE = 90mV to 100mV
Time (5ms/div)
Time (5ms/div)
Figure 6-16. Step Response
Figure 6-17. Step Response
600
G = 100
Output Voltage (2V/div)
500
VOL (mV)
400
300
200
100
VSENSE = 20mV to 110mV
0
Time (10ms/div)
0
1
.
Figure 6-18. Step Response
12
2
3
4
5
6
ISINK (mA)
Figure 6-19. Comparator VOL vs. ISINK
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SBOS393F – MARCH 2007 – REVISED JUNE 2021
600
602
599
601
Comparator Trip Point (mV)
Reset Voltage (mV)
598
597
596
595
594
593
592
600
599
598
597
591
596
590
2
4
6
8
10
12
14
16
18
-50
0
-25
Supply Voltage (V)
Figure 6-20. Comparator Trip Point vs. Supply
Voltage
50
75
100
125
Figure 6-21. Comparator Trip Point vs.
Temperature
200
1.2
175
1.0
Reset Voltage (V)
Propagation Delay (ns)
25
Temperature (°C)
150
125
100
75
0.8
0.6
0.4
0.2
50
0
0
20
40
60
80
100 120 140
160 180
2
200
4
6
Overdrive Voltage (mV)
8
10
12
14
16
18
Supply Voltage (V)
Figure 6-22. Comparator 1 Propagation Delay vs.
Overdrive Voltage
Figure 6-23. Comparator Reset Voltage vs. supply
Voltage
300
Propagation Delay (ns)
275
Input
200mV/div
250
225
200
Output
2V/div
175
150
VOD = 5mV
125
-50
-25
0
25
50
75
100
2ms/div
125
.
Temperature (°C)
Figure 6-24. Comparator Propagation Delay vs.
Temperature
Figure 6-25. Comparator Propagation Delay
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7 Detailed Description
7.1 Overview
The INA203, INA204, and INA205 are a family of unidirectional current-shunt monitors with voltage output,
dual comparators, and voltage reference. The INA203, INA204, and INA205 can sense drops across shunts
at common-mode voltages from –16 V to 80 V. The INA203, INA204, and INA205 are available with three
output voltage scales: 20 V/V, 50 V/V, and 100 V/V, with up to 500-kHz bandwidth. The INA203, INA204, and
INA205 also incorporate two open-drain comparators with internal 0.6-V references. On 14-pin versions, the
comparator references can be overridden by external inputs. Comparator 1 includes a latching capability, and
Comparator 2 has a user-programmable delay. 14-pin versions also provide a 1.2-V reference output. The
INA203, INA204, and INA205 operate from a single 2.7-V to 18-V supply. They are specified over the extended
operating temperature range of –40°C to 125°C.
7.2 Functional Block Diagrams
VS
1
OUT
2
14 VIN+
13 VIN1.2V REF
CMP1 IN-/0.6V REF
3
12 1.2V REF OUT
CMP1 IN+
4
11 CMP1 OUT
CMP2 IN+
5
10 CMP2 OUT
CMP2 IN-/0.6V REF
6
9
CMP2 DELAY
GND
7
8
CMP1 RESET
Figure 7-1. SO-14, TSSOP-14 Functional Block Diagram
VS
1
10 VIN+
OUT
2
9
VIN-
CMP1 IN+
3
8
CMP1 OUT
CMP2 IN+
4
7
CMP2 OUT
GND
5
6
CMP1 RESET
0.6V REF
Figure 7-2. VSSOP-10 Functional Block Diagram
7.3 Feature Description
7.3.1 Basic Connections
Figure 7-3 shows the basic connections of the INA203, INA204, and INA205. The input pins, VIN+ and VIN–,
should be connected as closely as possible to the shunt resistor to minimize any resistance in series with the
shunt resistance.
Power-supply bypass capacitors are required for stability. Applications with noisy or high-impedance power
supplies may require additional decoupling capacitors to reject power-supply noise. Connect bypass capacitors
close to the device pins.
14
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SBOS393F – MARCH 2007 – REVISED JUNE 2021
RSHUNT
3mW
Load Supply
-18V to +80V
Load
5V Supply
VS
Current Shunt
Monitor Output
CBYPASS
0.01mF
INA203
x20
OUT
CMP1 IN-/0.6 REF
1.2V REF
VIN+
VIN-
RPULL-UP
4.7kW
RPULL-UP
4.7kW
1.2V REF OUT
CMP1 OUT
CMP1 IN+
CMP2 IN+
CMP2 IN-/0.6 REF
CMP2 OUT
CMP2 DELAY
GND
CMP1 RESET
Optional Delay
Capacitor
0.2mF
Transparent/Reset
Latch
Figure 7-3. INA20x Basic Connection
7.3.2 Selecting RSHUNT
The value chosen for the shunt resistor, RSHUNT, depends on the application and is a compromise between
small-signal accuracy and maximum permissible voltage loss in the measurement line. High values of RSHUNT
provide better accuracy at lower currents by minimizing the effects of offset, while low values of RSHUNT
minimize voltage loss in the supply line. For most applications, best performance is attained with an RSHUNT
value that provides a full-scale shunt voltage range of 50 mV to 100 mV. Maximum input voltage for accurate
measurements is (VOUT – 0.25) / Gain.
7.3.3 Comparator
The INA203, INA204, and INA205 devices incorporate two open-drain comparators. These comparators typically
have 2 mV of offset and a 1.3-μs (typical) response time. The output of Comparator 1 latches and is reset
through the CMP1 RESET pin, as shown in Figure 7-5. This configuration applies to both the 10- and 14-pin
versions. Figure 7-4 illustrates the comparator delay.
The 14-pin versions of the INA203, INA204, and INA205 devices include additional features for comparator
functions. The comparator reference voltage of both Comparator 1 and Comparator 2 can be overridden by
external inputs for increased design flexibility. Comparator 2 has a programmable delay.
7.3.4 Comparator Delay (14-Pin Version Only)
The Comparator 2 programmable delay is controlled by a capacitor connected to the CMP2 Delay Pin; see
Figure 7-3. The capacitor value (in μF) is selected by using Equation 1:
CDELAY (in mF) =
tD
5
(1)
A simplified version of the delay circuit for Comparator 2 is shown in Figure 7-4. The delay comparator consists
of two comparator stages with the delay between them. I1 and I2 cannot be turned on simultaneously; I1
corresponds to a U1 low output and I2 corresponds to a U1 high output. Using an initial assumption that the U1
output is low, I1 is on, then U2 +IN is zero. If U1 goes high, I2 supplies 120 nA to CDELAY. The voltage at U2 +IN
begins to ramp toward a 0.6-V threshold. When the voltage crosses this threshold, the U2 output goes high while
the voltage at U2 +IN continues to ramp up to a maximum of 1.2 V when given sufficient time (twice the value
of the delay specified for CDELAY). This entire sequence is reversed when the comparator outputs go low, so that
returning to low exhibits the same delay.
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1.2V
I2
120nA
U1
U2
I1
120nA
0.6V
CDELAY
Figure 7-4. Simplified Model of the Comparator 2 Delay Circuit
0.6V
VIN
0V
CMP Out
RESET
Figure 7-5. Comparator Latching Capability
Take care to note what will happen if events occur more rapidly than the delay timeout; for example, when the
U1 output goes high (turning on I2), but returns low (turning I1 back on) prior to reaching the 0.6-V transition for
U2. The voltage at U2 +IN ramps back down at a rate determined by the value of CDELAY, and only returns to
zero if given sufficient time.
In essence, when analyzing Comparator 2 for behavior with events more rapid than its delay setting, use the
model shown in Figure 7-4.
7.3.5 Comparator Maximum Input Voltage Range
The maximum voltage at the comparator input for normal operation is up to (Vs) – 1.5 V. There are special
considerations when overdriving the reference inputs (pins 3 and 6). Driving either or both inputs high enough
to drive 1 mA back into the reference introduces errors into the reference. Figure 7-6 shows the basic input
structure. A general guideline is to limit the voltage on both inputs to a total of 20 V. The exact limit depends
on the available voltage and whether either or both inputs are subject to the large voltage. When making this
determination, consider the 20 kΩ from each input back to the comparator. Figure 7-7 shows the maximum input
voltage that avoids creating a reference error when driving both inputs (an equivalent resistance back into the
reference of 10 kΩ).
£ 1mA
1.2V
20kW
20kW
CMP1 IN-
CMP2 IN+
Figure 7-6. Limit Current Into Reference ≤ 1 mA
16
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SBOS393F – MARCH 2007 – REVISED JUNE 2021
RSHUNT
3mW
Load Supply
-18V to +80V
Load
5V Supply
VS
Current Shunt Monitor Output
CMP1 IN-/0.6 REF
CBYPASS
0.01mF
V < 11.2
VIN+
VIN-
INA203
x20
OUT
1.2V REF
RPULL-UP
4.7kW
RPULL-UP
4.7kW
1.2V REF OUT
CMP1 IN+
CMP1 OUT
CMP2 IN+
CMP2 IN-
CMP2 OUT
CMP2 DELAY
GND
CMP1 RESET
Optional Delay
Capacitor
0.2mF
Transparent/Reset
Latch
Figure 7-7. Overdriving Comparator Inputs Without Generating a Reference Error
Raychem
Polyswitch
Load
< 18V
Battery
+5V Supply
VS+
CMP1 IN-
x20
1.2V REF
3.3kW
Pull-Up
Resistors
VIN+
INA203
OUT
VIN1.2V REF OUT
CMP1 IN+
CMP1 OUT
CMP2 IN+
CMP2 IN-
CMP2 OUT
CMP2 DELAY
GND
CMP1 RESET
CBYPASS
0.01mF
Overlimit
Warning
(1)
(1)
Reset
Latch
Optional
CDELAY
0.01mF
NOTE: (1) Warning at half current (with optional delay). Overlimit latches when Polyswitch opens.
Figure 7-8. Polyswitch Warning and Fault Detection Circuit
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SBOS393F – MARCH 2007 – REVISED JUNE 2021
RSHUNT
0.02W
Load
Q2
NDS8434A
R1
100kW
+5V Supply
R7
1kW
VS+
R5
100kW
R6
6.04kW
CMP1 IN-
R3
14kW
R4
6.04kW
VIN+
INA203
x20
OUT
1.2V REF
Q1
2N3904
VIN-
CMP1 IN+
CMP1 OUT
CMP2 IN+
CMP2 IN-
CMP2 OUT
CMP2 DELAY
GND
CMP1 RESET
CBYPASS
0.01mF
R2
1kW
1.2V REF OUT
Reset
Latch
Figure 7-9. Lead-Acid Battery Protection Circuit
7.4 Device Functional Modes
7.4.1 Input Filtering
An obvious and straightforward location for filtering is at the output of the INA203, INA204, and INA205 series;
however, this location negates the advantage of the low output impedance of the internal buffer. The only other
option for filtering is at the input pins of the INA203, INA204, and INA205, which is complicated by the internal
5 kΩ + 30% input impedance; this configuration is illustrated in Figure 7-10. Using the lowest possible resistor
values minimizes both the initial shift in gain and effects of tolerance. Use Equation 2 to calculate the effect on
initial gain.
Gain Error % = 100 - 100 ´
5kW
5kW + RFILT
(2)
Total effect on gain error can be calculated by replacing the 5-kΩ term with 5 kΩ – 30%, (or 3.5 kΩ) or 5 kΩ +
30% (or 6.5 kΩ). The tolerance extremes of RFILT can also be inserted into the equation. If a pair of 100 Ω 1%
resistors are used on the inputs, the initial gain error will be 1.96%. Worst-case tolerance conditions will always
occur at the lower excursion of the internal 5-kΩ resistor (3.5 kΩ), and the higher excursion of RFILT – 3% in this
case.
18
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SBOS393F – MARCH 2007 – REVISED JUNE 2021
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