INA232AIDDFR

INA232 SBOSAA2 – DECEMBER 2022 INA232 48-V, 16-Bit, Current, Voltage, and Power Monitor With an I2C Interface 1 Features 3 Description • • • • • • The INA232 device is a 16-bit digital current monitor with an I2C/SMBus-compatible interface that is compliant with a wide range of digital bus voltages such as 1.2 V, 1.8 V, 3.3 V, and 5.0 V. The device monitors the voltage across an external sense resistor and reports values for current, bus voltage, and power. • • • • • • • • High-side or low-side current sensing Operates from a 1.7-V to 5.5-V power supply Reports current, voltage and power Programmable full scale range: 20mV / 80mV Input common mode range: –0.3 V to 48 V Current monitoring accuracy: – 16-bit ADC resolution – 0.3% gain error (maximum) – 50-µV offset (maximum) Low input bias current: 10 nA (maximum) Configurable averaging options General call addressing allows conversion synchronization among devices Alert limits for over and under current events 1.2-V compliant I2C, SMBus interface Two device address options with four pin selectable address SOT23-8 Package Operating temperature: –40°C and +125°C The INA232 features programmable ADC conversion times and averaging. The device also has a programmable calibration value with an internal multiplier that enables direct readouts of current in amperes and power in watts. The device monitors the bus voltage present on the IN– pin and can alert on over/under current as well as over/under voltage conditions. High input impedance while in current measurement mode allows use of larger current sense resistors needed to measure small value system currents. The INA232 senses current on common-mode bus voltages that can vary from –0.3 V to 48 V, independent of the supply voltage. The device operates from a single 1.7-V to 5.5-V supply, drawing a typical supply current of 300 µA in normal operation. The device can be placed in a low-power standby mode where the typical operating current is 2.2 µA. 2 Applications • • • • • Smart speakers Battery chargers Power management Battery cell monitors and balancers Rack servers Package Information(1) PART NUMBER(2) PACKAGE INA232 (1) (2) SOT-23 (8) BODY SIZE (NOM) 1.60 mm × 2.90 mm For all available packages, see the package option addendum at the end of the data sheet. The INA232 is available in A and B device address options. See Table 7-1 for address differences between the A and B devices. Supply Voltage (1.7 V to 5.5 V) C BYPASS 0.1 µF Bus Voltage (-0.3 V to 48 V) TI Device HighSide Shunt VS SDA x Load SCL Power Register V IN+ LowSide Shunt Current Register ADC I IN- I2C-, SMBus-, Compatible Interface Voltage Register ALERT A0 Alert Register GND High-Side or Low-Side Sensing Application An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. INA232 www.ti.com SBOSAA2 – DECEMBER 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................4 6.4 Thermal Information....................................................4 6.5 Electrical Characteristics.............................................5 6.6 Timing Requirements (I2C)......................................... 7 6.7 Timing Diagram ..........................................................7 6.8 Typical Characteristics................................................ 8 7 Detailed Description...................................................... 11 7.1 Overview................................................................... 11 7.2 Functional Block Diagram......................................... 11 7.3 Feature Description...................................................11 7.4 Device Functional Modes..........................................13 7.5 Programming............................................................ 15 7.6 Register Maps...........................................................18 8 Application and Implementation.................................. 23 8.1 Application Information............................................. 23 8.2 Typical Application.................................................... 27 8.3 Power Supply Recommendations.............................30 8.4 Layout....................................................................... 30 9 Device and Documentation Support............................31 9.1 Device Support......................................................... 31 9.2 Documentation Support............................................ 31 9.3 Receiving Notification of Documentation Updates....31 9.4 Support Resources................................................... 31 9.5 Trademarks............................................................... 31 9.6 Electrostatic Discharge Caution................................31 9.7 Glossary....................................................................31 10 Mechanical, Packaging, and Orderable Information.................................................................... 31 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 2 DATE REVISION NOTES December 2022 * Initial Release Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA232 INA232 www.ti.com SBOSAA2 – DECEMBER 2022 5 Pin Configuration and Functions IN+ 1 8 ALERT IN– 2 7 A0 GND 3 6 SDA VS 4 5 SCL Not to scale Figure 5-1. DDF Package 8-Pin SOT-23 (Top View) Table 5-1. Pin Functions PIN NAME DDF (SOT23-8) TYPE DESCRIPTION Address pin. Connect to GND, SCL, SDA, or VS. Table 7-1 lists the pin settings and corresponding addresses. A0 7 Digital input ALERT 8 Digital output GND 3 Ground IN– 2 Analog input Current sensing negative input. For high-side applications, connect to load side of sense resistor. For low-side applications, connect to ground side of sense resistor. Bus voltage measurements are made with respect to this pin. IN+ 1 Analog input Current sensing positive input. For high-side applications, connect to bus voltage side of sense resistor. For low-side applications, connect to load side of sense resistor. SCL 5 Digital input Serial bus clock line, open-drain input. SDA 6 Digital input/output Serial bus data line, open-drain input/output VS 4 Power Supply Multifunctional alert, open-drain output. This pin alerts to report fault conditions or can be configured to notify host when a conversion is complete. Ground for both analog and digital. Power supply, 1.7 V to 5.5 V Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA232 3 INA232 www.ti.com SBOSAA2 – DECEMBER 2022 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) Vs MIN MAX 6 V –26 26 V Common - mode GND – 0.3 50 V SDA, SCL, ALERT, A0 GND – 0.3 6 V Supply Voltage VIN+, VINVIO Differential (VIN+) - (VIN-) Input current into any pin Open-drain digital output current (SDA, ALERT) TA Operating Temperature TJ Junction temperature Tstg Storage temperature (1) –55 –65 UNIT 5 mA 10 mA 150 °C 150 °C 150 °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. 6.2 ESD Ratings VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all V(ESD) (1) (2) Electrostatic discharge pins(1) Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2) UNIT ±2000 V ±1000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VCM Common-mode input range GND – 0.3 48 V VS Operating supply range 1.7 5.5 V TA Ambient temperature –40 125 °C 6.4 Thermal Information INA232 THERMAL METRIC(1) DDF (SOT-23) UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 146.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 70.5 °C/W RθJB Junction-to-board thermal resistance 67.1 °C/W ΨJT Junction-to-top characterization parameter 4.1 °C/W YJB Junction-to-board characterization parameter 66.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA232 INA232 www.ti.com SBOSAA2 – DECEMBER 2022 6.5 Electrical Characteristics at TA = 25°C, VS = 3.3 V, VSENSE = VIN+ – VIN– = 0 mV, VIN- = VBUS = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP 120 150 MAX UNIT INPUT CMRR Common-mode rejection Shunt voltage input range VCM = –0.3 V to 48 V, TA = –40°C to 125°C dB ADCRANGE = 0 –81.9175 81.92 mV ADCRANGE = 1 –20.4794 20.48 mV Vos Shunt offset voltage VCM = 12 V ±50 µV dVos/dT Shunt offset voltage drift TA = –40°C to +125°C ±0.1 µV/°C Vos_b IN– bus offset Voltage ±10 mV dVos_b/dT IN– bus offset voltage drift TA = –40°C to +125°C ±50 µV/°C PSRRSHUNT Power supply rejection ratio (Current measurements) VS = 1.7 V to 5.5 V, TA = –40°C to 125°C ±10 µV/V PSRRBUS Power supply rejection ratio (Voltage measurements) VS = 1.7 V to 5.5 V, TA = –40°C to 125°C, VIN– = 50 mV ±5 mV/V ZIN– IN– input impedance Bus Voltage Measurement Mode IB_SHDWN Input Leakage IN+, IN–, Shutdown Mode 0.1 5 nA IB Input bias current IN+, IN–, Current Measurement Mode 0.1 10 nA Differential Input Impedance (IN+ to IN–) Shunt or Current Measurement Modes, VIN+ – VIN– < 82 mV 140 kΩ ADC Resolution TA = –40°C to 125°C 16 Bits Shunt Voltage, ADCRANGE = 0 2.5 µV Shunt Voltage, ADCRANGE = 1 625 nV 1.05 MΩ DC ACCURACY RDIFF 1 LSB step size Bus Voltage ADC Conversion-time (TA = –40°C to 125°C) GSERR Shunt voltage gain error GS_DRFT Shunt voltage gain error drift GBERR VIN– voltage gain error GB_DRFT VIN– voltage gain error drift INL Integral Non-Linearity DNL Differential Non-Linearity 1.6 mV CT bit = 000 133 140 147 µs CT bit = 001 194 204 214 µs CT bit = 010 315 332 349 µs CT bit = 011 559 588 617 µs CT bit = 100 1.045 1.100 1.155 ms CT bit = 101 2.01 2.116 2.222 ms CT bit = 110 3.948 4.156 4.364 ms CT bit = 111 7.832 8.244 8.656 ms ±0.3 % TA = –40°C to +125°C 30 ppm/°C ±0.5 TA = –40°C to +125°C % 50 ppm/°C ±2 m% ±0.1 LSB POWER SUPPLY VSENSE = 0 mV IQ Quiescent current VPOR Power-on reset threshold 300 IQ vs temperature, TA = –40°C to +125°C Shutdown 2.2 VS falling 0.95 380 µA 500 µA 3 µA V Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA232 5 INA232 www.ti.com SBOSAA2 – DECEMBER 2022 at TA = 25°C, VS = 3.3 V, VSENSE = VIN+ – VIN– = 0 mV, VIN- = VBUS = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 28 35 UNIT SMBUS SMBUS timeout ms DIGITAL INPUT / OUTPUT Input capacitance pF Logic input level, high VS = 1.7 V to 5.5 V, TA = –40°C to +125°C 0.9 5.5 V VIL Logic input level, low VS = 1.7 V to 5.5 V, TA = –40°C to +125°C 0 0.4 V VHYS Hysteresis VOL 6 3 VIH 130 Logic output level, low IOL = 3 mA, VS = 1.7 V to 5.5 V, TA = –40°C to +125°C Digital leakage input current 0 ≤ VINPUT ≤ VS Submit Document Feedback mV 0 0.3 V –1 1 µA Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA232 INA232 www.ti.com SBOSAA2 – DECEMBER 2022 6.6 Timing Requirements (I2C) MIN I2C NOM MAX UNIT 400 kHz BUS (FAST MODE) F(SCL) I2C clock frequency t(BUF) Bus free time between STOP and START conditions 600 ns t(HDSTA) Hold time after a repeated START condition. After this period, the first clock is generated. 100 ns t(SUSTA) Repeated START condition setup time 100 ns t(SUSTO) STOP condition setup time 100 ns t(HDDAT) Data hold time 10 t(SUDAT) Data setup time 100 ns t(LOW) SCL clock low period 1300 ns t(HIGH) SCL clock high period 600 ns tF Data fall time 300 ns tF Clock fall time 300 ns tR Clock rise time tR Clock rise time (SCLK ≤ 100 kHz) I2C 1 900 ns 300 ns 1000 ns 2940 kHz BUS (HIGH-SPEED MODE) F(SCL) I2C clock frequency t(BUF) Bus free time between STOP and START conditions 160 ns t(HDSTA) Hold time after a repeated START condition. After this period, the first clock is generated. 100 ns t(SUSTA) Repeated START condition setup time 100 ns t(SUSTO) STOP condition setup time 100 t(HDDAT) Data hold time t(SUDAT) Data setup time 20 ns t(LOW) SCL clock low period 200 ns t(HIGH) SCL clock high period 60 tF Data fall time 80 ns tF Clock fall time 40 ns tR Clock rise time 40 ns 10 ns 10 125 ns ns 6.7 Timing Diagram t(LOW) tF tR t(HDSTA) SCL t(HDSTA) t(HIGH) t(HDDAT) t(SUSTO) t(SUSTA) t(SUDAT) SDA t(BUF) P S S P Figure 6-1. I2C Timing Diagram Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA232 7 INA232 www.ti.com SBOSAA2 – DECEMBER 2022 6.8 Typical Characteristics at TA = 25°C, VVS = 3.3 V, VCM = 12 V, and VSENSE = (VIN+ – VIN–) = 0 mV (unless otherwise noted) 0 −10 Gain (dB) −20 −30 −40 −50 −60 1 10 100 1k Frequency (Hz) 10k 100k G001 . Figure 6-3. Shunt Input Offset Voltage vs Temperature Figure 6-2. Frequency Response 8 Figure 6-4. Shunt Input CMRR vs Temperature Figure 6-5. Shunt Gain Error vs Temperature Figure 6-6. Shunt Gain Error vs Common-Mode Voltage Figure 6-7. Bus Offset Voltage (VIN-) vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA232 INA232 www.ti.com SBOSAA2 – DECEMBER 2022 6.8 Typical Characteristics (continued) at TA = 25°C, VVS = 3.3 V, VCM = 12 V, and VSENSE = (VIN+ – VIN–) = 0 mV (unless otherwise noted) Figure 6-8. Bus Voltage (VIN-) Gain Error vs Temperature Figure 6-9. Input Bias Current vs Differential Voltage Figure 6-10. Input Bias Current vs Common-Mode Voltage (IB+, IB-) Figure 6-11. Input Bias Current vs Temperature Figure 6-12. Input Bias Current vs Temperature (Shutdown) Figure 6-13. Quiescent Current vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA232 9 INA232 www.ti.com SBOSAA2 – DECEMBER 2022 6.8 Typical Characteristics (continued) at TA = 25°C, VVS = 3.3 V, VCM = 12 V, and VSENSE = (VIN+ – VIN–) = 0 mV (unless otherwise noted) Figure 6-14. Quiescent Current vs Supply Voltage Figure 6-15. Quiescent Current - Shutdown vs Supply Voltage Figure 6-16. Quiescent Current - Shutdown vs Temperature Figure 6-17. Quiescent Current vs Clock (SCL) Frequency Figure 6-18. Quiescent Current - Shutdown vs SCL Frequency 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA232 INA232 www.ti.com SBOSAA2 – DECEMBER 2022 7 Detailed Description 7.1 Overview The INA232 is a digital current-sense amplifier with an I2C- and SMBus-compatible interface. The device reports the sensed current and features programmable out-of-range limits to issue alerts when the current is outside the normal range of operation. The integrated analog-to-digital converter (ADC) can be set to different averaging modes and configured for continuous-versus-triggered operation. Device Registers provides detailed register information for the INA232. 7.2 Functional Block Diagram Supply Voltage (1.7 V to 5.5 V) C BYPASS 0.1 µF Bus Voltage (-0.3 V to 48 V) TI Device HighSide Shunt VS SDA x Load SCL Power Register V IN+ LowSide Shunt Current Register ADC Interface I IN- I2C-, SMBus-, Compatible Voltage Register ALERT A0 Alert Register GND 7.3 Feature Description 7.3.1 Integrated Analog-to-Digital Convertor (ADC) The INA232 integrates a low offset 16-bit delta-sigma (ΔΣ) ADC. This ADC is multiplexed to process both the shunt voltage and bus voltage measurements. Bus voltage measurements are made with respect to IN– and GND. The shunt voltage measurement is a differential measurement of the voltage developed when the load current flows through a shunt resistor as measured between the IN+ and IN– pins. The shunt voltage measurement has an maximum offset voltage of only 50 µV and a maximum gain error of 0.3%. The low offset voltage of the shunt voltage measurement allows for increased accuracy at light load conditions for a given shunt resistor value. Another advantage of low offset is the ability to sense a lower voltage drop across the sense resistor accurately, thus allowing for a lower-value shunt resistor. Lower-value shunt resistors reduce power loss in the current-sense circuit and help improve the power efficiency of the end application. There are no special considerations for power-supply sequencing because the bus common-mode at the IN+ and IN– pins and power-supply voltage at the vs. pin are independent of each other; therefore, the bus commonmode voltage can be present with the supply voltage off, and vice-versa. 7.3.2 Power Calculation Figure 7-1 shows that the current and power are calculated after a shunt voltage and bus voltage measurement. Power is calculated based on the previous current calculation and the latest bus voltage measurement. If the value loaded into the calibration register is zero, the power value reported is also zero. The current and power values are considered intermediate results (unless the averaging is set to 1) and are stored in an internal accumulation register. Following every measured sample, the newly-calculated values for current and power are appended to this accumulation register until all of the samples have been measured and averaged. After all Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA232 11 INA232 www.ti.com SBOSAA2 – DECEMBER 2022 of the samples have been measured and the corresponding current and power calculations have been made, the accumulated average for each of these parameters is then loaded to the corresponding output registers where they can then be read. These calculations are performed in the background and do not add to the overall conversion time. Bus and Power Limit Detect Following Every Bus Voltage Conversion Current Limit Detect Following Every Shunt Voltage Conversion I V I V P I P V I V P I P V I P V I P V I P V I P V I V P I P V I P V I P V I P V I P V I P V P Power Average Bus Voltage Average Shunt Voltage Average Figure 7-1. Power Calculation Scheme 7.3.3 Low Bias Current When performing a current measurement, the INA232 features very low input bias current which provides several benefits. The low input bias current of the INA232 reduces the current consumed by the device in both active and shutdown state. Another benefit of low bias current is that it allows the use of input filters to reject high-frequency noise before the signal is converted to digital data. In traditional digital current-sense monitors, the addition of input filters comes at the cost of reduced accuracy. However, as a result of the low bias current, the reduction in accuracy due to input filters is minimized. An additional benefit of low bias current is the ability to use a larger shunt resistor to accurately sense smaller currents. Use of a larger value for the shunt resistor allows the device to accurately monitor currents in the sub-mA range. The bias current in the INA232 is the smallest when the sensed current is zero. As the current starts to increase, the differential voltage drop across the shunt resistor increases which results in an increase in the bias current (see Figure 6-9). The INA232 has low bias current only when making a current measurement, when bus voltage measurements are made the impedance of the IN– will decrease. During bus voltage measurements the IN– pin will be connected to an internal resistor divider with an impedance of approximately 1 MΩ. Configuring the ADC to perform only current measurements will allow the device to always have low bias current. 7.3.4 Low Voltage Supply and Wide Common-Mode Voltage Range The supply voltage range of the INA232 is 1.7 V to 5.5 V. The ability to operate at 1.7 V enables the device to be used in 1.8-V supply rails. Even with a supply voltage of 1.7 V, the device can monitor currents on voltage rails as high as 48 V. This wide common-mode range of operation allows the device to be used in many applications where the common-mode voltage exceeds the supply voltage rail. 7.3.5 ALERT Pin The INA232 has a single Mask/Enable register (06h) that allows the ALERT pin to be programmed to respond to a single user-defined event or to a conversion ready notification if desired. The Mask/Enable register allows the selection from one of the five available functions to monitor and set the conversion ready bit (CNVR, Mask/ Enable register) to control the response of the ALERT pin. Based on the function being monitored, a value would then be entered into the Alert Limit register (07h) to set the corresponding threshold value that asserts the ALERT pin. The ALERT pin allows for one of several available alert functions to be monitored to determine if a user-defined threshold has been exceeded. The five alert functions that can be monitored are: • Shunt voltage overlimit (SOL) 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA232 INA232 www.ti.com • • • • SBOSAA2 – DECEMBER 2022 Shunt voltage underlimit (SUL) Bus voltage overlimit (BOL) Bus voltage underlimit (BUL) Power overlimit (POL) The ALERT pin is an open-drain output. This pin is asserted when the alert function selected in the Mask/Enable register exceeds the value programmed into the Alert Limit register. Only one of these alert functions can be enabled and monitored at a time. If multiple alert functions are enabled, the selected function in the highest significant bit position takes priority and responds to the Alert Limit register value. For example, if the SOL and the SUL are both selected, the ALERT pin asserts when the Shunt Voltage Over Limit register exceeds the value in the Alert Limit register. The conversion-ready state of the device can also be monitored at the ALERT pin to inform the user when the device has completed the previous conversion and is ready to begin a new conversion. The conversion ready flag (CVRF) bit can be monitored at the ALERT pin along with one of the alert functions. If an alert function and the CNVR bit are both enabled for monitoring at the ALERT pin, then after the ALERT pin is asserted, the CVRF bit (D3) and the AFF bit (D4) in the Mask/Enable register must be read following the alert to determine the source of the alert. If the conversion ready feature is not desired, and the CNVR bit is not set, the ALERT pin only responds to an exceeded alert limit based on the alert function enabled. If the alert function is not used, the ALERT pin can be left floating without impacting the operation of the device. Refer to Figure 7-1 to see the relative timing of when the value in the Alert Limit register is compared to the corresponding converted value. For example, if the alert function that is enabled is Shunt Voltage Over Limit (SOL), following every shunt voltage conversion the value in the Alert Limit register is compared to the measured shunt voltage to determine if the measurements have exceeded the programmed limit. The AFF bit (D4, Mask/ Enable register) asserts high any time the measured voltage exceeds the value programmed into the Alert Limit register. In addition to the AFF bit being asserted, the ALERT pin is asserted based on the Alert Polarity bit (APOL, D1, Mask/Enable register). If the Alert Latch is enabled, the AFF bit and ALERT pin remain asserted until either the Configuration register is written to or the Mask/Enable register is read. The bus voltage alert functions (BOL and BUL, Mask/Enable register) compare the measured bus voltage to the Alert Limit register following every bus voltage conversion and assert the AFF bit and ALERT pin if the limit threshold is exceeded. The power overlimit alert function (POL, Mask/Enable register) is also compared to the calculated power value following every bus voltage measurement conversion and asserts the AFF bit and ALERT pin if the limit threshold is exceeded. The alert function compares the programmed alert limit value to the result of each corresponding conversion. Therefore, an alert can be issued during a conversion cycle where the averaged value of the signal does not exceed the alert limit. Triggering an alert based on this intermediate conversion allows for out-of-range events to be detected faster than the averaged output data registers are updated. This fast detection can be used to create alert limits for quickly changing conditions through the use of the alert function, as well as to create limits to longer-duration conditions through software monitoring of the averaged output values. 7.4 Device Functional Modes 7.4.1 Continuous Verses Triggered Operation The INA232 has two operating modes, continuous and triggered, that determine how the ADC operates after these conversions. When the INA232 is in the normal operating mode (that is, the MODE bits of the Configuration register are set to '111'), it continuously converts a shunt voltage reading followed by a bus voltage reading. In triggered mode, writing any of the triggered convert modes into the Configuration register (0h) (that is, the MODE bits of the Configuration register are set to 001) triggers a single-shot conversion. This action produces a single set of measurements. To trigger another single-shot conversion, the Configuration register must be written to again, even if the mode does not change. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA232 13 INA232 www.ti.com SBOSAA2 – DECEMBER 2022 Although the INA232 can be read at any time, and the data from the last conversion remain available, the conversion ready flag bit (CVRF bit, Mask/Enable register) is provided to help coordinate single-shot or triggered conversions. The CVRF bit is set after all conversions, averaging, and multiplication operations are complete for a single cycle. The CVRF bit clears under these conditions: 1. Writing to the Configuration register, except when configuring the MODE bits for power-down mode; or 2. Reading the Mask/Enable register. 7.4.2 Device Shutdown In addition to the two operating modes (continuous and triggered), the INA232 also has a power-down mode that reduces the quiescent current and input bias current. The power-down mode reduces supply drain when the device is not being used. Full recovery from power-down mode requires 100 µs. The device remains in power-down mode until one of the active modes settings are written into the Configuration register. 7.4.3 Power-On Reset Power-on reset (POR) is asserted when VS drops below 0.95 V (typical) at which all of the registers are reset to their default values. The default power-up register values are shown in the reset column for each register description. Table 7-2 provides links to the register descriptions. 7.4.4 Averaging and Conversion Time Considerations The INA232 has programmable conversion times for both the shunt voltage and bus voltage measurements. The conversion times for these measurements can be selected from as fast as 140 μs to as long as 8.244 ms. The conversion time settings, along with the programmable averaging mode, allow the INA232 to be configured to optimize the available timing requirements in a given application. For example, if a system requires that data be read every 5 ms, the INA232 can be configured with the conversion times set to 588 μs and the averaging mode set to 4. This configuration results in the data updating approximately every 4.7 ms. The INA232 can also be configured with a different conversion time setting for the shunt and bus voltage measurements. This type of approach is common in applications where the bus voltage tends to be relatively stable. This situation allows for the time spent measuring the bus voltage to be reduced relative to the shunt voltage measurement. The shunt voltage conversion time can be set to 4.156 ms with the bus voltage conversion time set to 588 μs, and the averaging mode set to 1. This configuration also results in data updating approximately every 4.7 ms. There are trade-offs associated with the conversion time settings and the averaging mode used. The averaging feature can significantly improve the measurement accuracy by effectively filtering the signal. This approach allows the INA232 to reduce noise in the measurement that may be caused by noise coupling into the signal. A greater number of averages enables the INA232 to be more effective in reducing the noise component of the measurement. The conversion times selected can also have an effect on the measurement accuracy. Figure 7-2 shows multiple conversion times to illustrate the effect of noise on the measurement. To achieve the highest accuracy measurement possible, use a combination of the longest allowable conversion times and highest number of averages, based on the timing requirements of the system. 14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA232 INA232 www.ti.com SBOSAA2 – DECEMBER 2022 Figure 7-2. Noise vs Conversion Time 7.5 Programming 7.5.1 I2C Serial Interface The INA232 operates only as a target on both the SMBus and I2C interfaces. Connections to the bus are made through the open-drain SDA and SCL lines. The SDA and SCL pins feature integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. Although the device integrates spike suppression into the digital I/O lines, proper layout techniques help minimize the amount of coupling into the communication lines. This noise introduction could occur from capacitive coupling signal edges between the two communication lines themselves or from other switching noise sources present in the system. Routing traces in parallel with ground in between layers on a printed circuit board (PCB) typically reduces the effects of coupling between the communication lines. Shielded communication lines reduce the possibility of unintended noise coupling into the digital I/O lines that could be incorrectly interpreted as start or stop commands. The INA232 supports the transmission protocol for fast mode up to 400 kHz and high-speed mode up to 2.94 MHz. All data bytes are transmitted most significant byte first and follow the SMBus 3.0 transfer protocol. To communicate with the INA232, the controller must first address targets through a target address byte. The target address byte consists of seven address bits and a direction bit that indicates whether the action is to be a read or write operation. The INA232 uses a single address pin, A0. Table 7-1 shows possible configurations for A0 and the corresponding address for both the A and B versions of the device. The INA232 samples the state of the A0 pin on every bus communication. The pin state for A0 must be established before any activity on the interface occurs. When connecting the SDA pin to A0 to set the device address, make sure to add an additional hold time of 100 ns on the MSB of the I2C address to ensure correct device addressing. The A and B device options, each with four unique addresses, allows users to connect up to eight devices in a system without I2C address conflicts. Table 7-1. Address Pins and Target Addresses A0 INA232A DEVICE OPTION INA232B DEVICE OPTION GND 1000000 1001000 VS 1000001 1001001 SDA 1000010 1001010 SCL 1000011 1001011 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA232 15 INA232 www.ti.com SBOSAA2 – DECEMBER 2022 7.5.2 Writing to and Reading Through the I2C Serial Interface Accessing a specific register on the INA232 is accomplished by writing the appropriate value to the register pointer. Refer to Register Maps for a complete list of registers and corresponding addresses. The value for the register pointer (see Figure 7-5) is the first byte transferred after the target address byte with the R/W bit low. Every write operation to the device requires a value for the register pointer. Writing to a register begins with the first byte transmitted by the controller. This byte is the target address, with the R/W bit low. The device then acknowledges receipt of a valid address. The next byte transmitted by the controller is the address of the register to be accessed. This register address value updates the register pointer to the desired internal device register. The next two bytes are written to the register addressed by the register pointer. The device acknowledges receipt of each data byte. The controller may terminate data transfer by generating a start or stop condition. When reading from the device, the last value stored in the register pointer by a write operation determines which register is read during a read operation. To change the register pointer for a read operation, a new value must be written to the register pointer. This write is accomplished by issuing a target address byte with the R/ W bit low, followed by the register pointer byte. No additional data are required. The controller then generates a start condition and sends the address byte for the target with the R/W bit high to initiate the read command. The next byte is transmitted by the target and is the most significant byte of the register indicated by the register pointer. This byte is followed by an Acknowledge from the controller; then the target transmits the least significant byte. The controller may or may not acknowledge receipt of the second data byte. The controller may terminate data transfer by generating a Not-Acknowledge after receiving any data byte, or generating a start or stop condition. If repeated reads from the same register are desired, it is not necessary to continually send the register pointer bytes; the device retains the register pointer value until it is changed by the next write operation. Figure 7-3 shows the write operation timing diagram. Figure 7-4 shows the read operation timing diagram. These diagrams are shown for reading/writing to 16 bit registers. Register bytes are sent most-significant byte first, followed by the least significant byte. 1 9 9 1 1 9 1 9 SCL SDA 1 0 0 A3 A2 A1 A0 R/W Start By Controller Frame 1 Two-Wire Target Address Byte A. B. P7 P6 P5 P4 P3 P2 P1 ACK By Target D15 D14 D13 D12 D11 D10 P0 D9 D8 (1) D7 D6 D5 D4 D3 D2 D1 D0 ACK By Target ACK By Target Frame 2 Register Pointer Byte ACK By Target Frame 3 Data MSByte Stop By Controller Frame 4 Data LSByte The value of the Target Address byte is determined by the setting of the A0 address pin. Refer to Table 7-1. The device does not support packet error checking (PEC) or perform clock stretching. Figure 7-3. Timing Diagram for Write Word Format 1 9 1 9 1 9 SCL SDA 1 0 0 A3 A2 A1 A0 Start By Controller ACK By Target Frame 1 Two-Wire Target Address Byte A. B. C. D. D15 D14 D13 R/W (1) D12 D11 D10 D9 D8 From Target Frame 2 Data MSByte D7 D6 D5 D4 D3 D2 D1 From Target ACK By Controller (2) Frame 3 Data LSByte D0 No ACK By Controller (3) Stop (2) The value of the Target Address byte is determined by the setting of the A0 address pin. Refer to Table 7-1. Read data is from the last register pointer location. If a new register is desired, the register pointer must be updated. See Figure 7-5. ACK by the controller can also be sent. The device does not support packet error checking (PEC) or perform clock stretching. Figure 7-4. Timing Diagram for Read Word Format 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA232 INA232 www.ti.com SBOSAA2 – DECEMBER 2022 1 9 1 9 SCL SDA 1 0 0 A3 A2 A1 A0 R/W Start By Controller P7 P6 P5 (1) Frame 1 Two-Wire Target Address Byte A. P4 P3 P2 P1 ACK By Target P0 Stop ACK By Target Frame 2 Register Pointer Byte The value of the Target Address byte is determined by the setting of the A0 address pin. Refer to Table 7-1. Figure 7-5. Typical Register Pointer Set 7.5.3 High-Speed I2C Mode When the bus is idle, both the SDA and SCL lines are pulled high by the pullup resistors. The controller generates a start condition followed by a valid serial byte containing high-speed (HS) controller code 00001XXX. This transmission is made in fast (400 kHz) or standard (100 kHz) (F/S) mode at no more than 400 kHz. The device does not acknowledge the HS controller code, but does recognize it and switches its internal filters to support 2.94-MHz operation. The controller then generates a repeated start condition (a repeated start condition has the same timing as the start condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission speeds up to 2.94 MHz are allowed. Instead of using a stop condition, use repeated start conditions to maintain the bus in HS-mode. A stop condition ends the HS-mode and switches all the internal filters of the device to support the F/S mode. 7.5.4 General Call Reset A general call reset to multiple devices is implemented by addressing the general call address 0000 000, with the last R/W bit set to 0. This is then followed by the following data byte 0000 0110 (06h). On receiving this 2-byte sequence, all devices designed to respond to the general call address will reset. All INA232 devices on the bus will do a soft reset operation and return to the default power-up conditions 7.5.5 General Call Start Byte A general call ADC conversion start command to multiple INA232 devices is implemented by addressing the general call address 0000 000, with the last R/W bit set to 1. No other data bytes are required. Be aware that other devices in the bus that use general call start commands on the bus will also trigger a start of conversion. 7.5.6 SMBus Alert Response The INA232 is designed to respond to the SMBus Alert Response address. The SMBus Alert Response provides a quick fault identification for simple targets. When an Alert occurs, the controller can broadcast the Alert Response target address (0001 100) with the Read/Write bit set high. Following this Alert Response, any target that generates an alert identifies itself by acknowledging the Alert Response and sending its address on the bus. The Alert Response can activate several different target devices simultaneously, similar to the I2C General Call. If more than one target attempts to respond, bus arbitration rules apply. The losing device does not generate an Acknowledge and continues to hold the Alert line low until that device wins arbitration. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA232 17 INA232 www.ti.com SBOSAA2 – DECEMBER 2022 7.6 Register Maps 7.6.1 Device Registers Table 7-2 lists the INA232 registers. All register locations not listed in Table 7-2 should be considered as reserved locations and the register contents should not be modified. Table 7-2. INA232 Registers Address Register Size (bits) Reset Value Section 0h Configuration Register 16 4127h Go 1h Shunt Voltage Register 16 0000h Go 2h Bus Voltage Register 16 0000h Go 3h Power Register 16 0000h Go 4h Current Register 16 0000h Go 5h Calibration Register 16 0000h Go 6h Mask/Enable Register 16 0000h Go 7h Alert Limit Register 16 0000h Go Manufacturer ID Register 16 5449h Go 3Eh Register Name Complex bit access types are encoded to fit into small table cells. Table 7-3 shows the codes that are used for access types in this section. Table 7-3. Device Access Type Codes Access Type Code Description R Read W Write Read Type R Write Type W 7.6.1.1 Configuration Register (Address = 0h) [reset = 4127h] The configuration register is shown in Table 7-4. Table 7-4. Configuration Register Field Descriptions Bit Field Type Reset Description 15 RST R/W 0b Set this bit to '1' to generate a system reset that is the same as poweron reset. Resets all registers to default values and then self-clears. 0b = Normal Operation 1b = System Reset self clears registers to default values Reserved R 10b Reserved value always returns 10b ADCRANGE R/W 0b Enables the selection of the shunt full scale input across IN+ and IN–. 0b = ±81.92 mV 1b = ±20.48 mV AVG R/W 000b Sets the number of ADC conversion results to be averaged. The readback registers are updated after averaging is completed. 000b = 1 001b = 4 010b = 16 011b = 64 100b = 128 101b = 256 110b = 512 111b = 1024 14-13 12 11-9 18 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA232 INA232 www.ti.com SBOSAA2 – DECEMBER 2022 Table 7-4. Configuration Register Field Descriptions (continued) Bit Field Type Reset Description 8-6 VBUSCT R/W 100b Sets the conversion time of the VBUS measurement 000b = 140 µs 001b = 204 µs 010b = 332 µs 011b = 588 µs 100b = 1100 µs 101b = 2116 µs 110b = 4156 µs 111b = 8244 µs 5-3 VSHCT R/W 100b Sets the conversion time of the SHUNT measurement 000b = 140 µs 001b = 204 µs 010b = 332 µs 011b = 588 µs 100b = 1100 µs 101b = 2116 µs 110b = 4156 µs 111b = 8244 µs 2-0 MODE R/W 111b Operating mode, modes can be selected to operate the device either in Shutdown mode, continuous mode or triggered mode. The mode also allows user to select mux settings to set continuous or triggered mode on bus voltage, shunt voltage measurement. 000b = Shutdown 001b = Shunt Voltage triggered, single shot 010b = Bus Voltage triggered, single shot 011b = Shunt voltage and Bus voltage triggered, single shot 100b = Shutdown 101b = Continuous Shunt voltage 110b = Continuous Bus voltage 111b = Continuous Shunt and Bus voltage Return to the Summary Table. 7.6.1.2 Shunt Voltage Register (Address = 1h) [reset = 0000h] The Shunt Voltage Register stores the current shunt voltage reading, VSHUNT and is show in Table 7-5. Negative numbers are represented in two's complement format. Generate the two's complement of a negative number by complementing the absolute value binary number and adding 1. An MSB = '1' denotes a negative number. Example: For a value of VSHUNT = –80 mV: 1. Take the absolute value: 80 mV 2. Translate this number to a whole decimal number (80 mV ÷ 2.5 µV) = 32000 3. Convert this number to binary = 0111 1101 0000 0000 4. Complement the binary result = 1000 0010 1111 1111 5. Add '1' to the complement to create the two's complement result = 1000 0011 0000 0000 = 8300h If averaging is enabled, this register displays the averaged value. Table 7-5. Shunt Voltage Register Field Descriptions Bit 15-0 Field Type Reset Description VSHUNT R 0000h Differential voltage measured across the shunt output. Two's complement value. Return to the Summary Table. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA232 19 INA232 www.ti.com SBOSAA2 – DECEMBER 2022 7.6.1.3 Bus Voltage Register (Address = 2h) [reset = 0000h] The bus voltage register is shown in Table 7-6. This register will only return positive values. If averaging is enabled, this register displays the averaged value. Table 7-6. Bus Voltage Register Field Descriptions Bit Field Type Reset Description 15 Reserved R 0b This bit returns Zero as common mode voltage is only positive VBUS R 0000h These bits readout the bus voltage of the system 14-0 Return to the Summary Table. 7.6.1.4 POWER Register (Address = 3h) [reset = 0000h] The power register is shown in Table 7-7. If averaging is enabled, this register displays the averaged value. The Power Register records power in Watts by multiplying the decimal values of the Current Register with the decimal value of the Bus Voltage Register. This is an unsigned result. Table 7-7. POWER Register Field Descriptions Bit 15-0 Field Type Reset Description POWER R 0000h This bit returns a calculated value of power in the system. This is an unsigned result. Return to the Summary Table. 7.6.1.5 CURRENT Register (Address = 4h) [reset = 0000h] CURRENT is shown in Table 7-8. If averaging is enabled, this register displays the averaged value. The value of the Current Register is calculated by multiplying the decimal value in the Shunt Voltage Register with the decimal value of the Calibration Register. Table 7-8. CURRENT Register Field Descriptions Bit 15-0 Field Type Reset Description CURRENT R 0000h Calculated current output in Amperes. Two's complement value. Return to the Summary Table. 7.6.1.6 Calibration Register (Address = 5h) [reset = 0000h] The calibration register shown in Table 7-9 must be programmed to receive valid current and power results after initial power up or power cycle events. This register provides the device with the value of the shunt resistor that was present to create the measured differential voltage. It also sets the resolution of the Current Register. Programming this register sets the Current_LSB and the Power_LSB. Table 7-9. Calibration Register Field Descriptions Bit Field Type Reset 15 Reserved R 0h SHUNT_CAL R/W 0000h 14-0 Description Programmed value needed for doing the shunt voltage to current conversion. Return to the Summary Table. 20 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA232 INA232 www.ti.com SBOSAA2 – DECEMBER 2022 7.6.1.7 Mask/Enable Register (Address = 6h) [reset = 0000h] The Mask/Enable Register is shown in Table 7-10. Table 7-10. Mask/Enable Register Field Descriptions Bit Field 15 SOL (Shunt Over-limit) Type R/W Reset 0b Description Setting this bit high configures the ALERT pin to be asserted if the shunt voltage conversion result exceeds the value programmed in the LIMIT register 14 SUL (Shunt Under-limit) R/W 0b Setting this bit high configures the ALERT pin to be asserted if the shunt voltage conversion result is below the value programmed in the LIMIT register. Cannot be set if Shunt overlimit is set. 13 BOL (Bus Over-limit) R/W 0b Setting this bit high configures the ALERT pin to be asserted if the bus voltage conversion result exceeds the value programmed in the LIMIT register Cannot be set if Shunt overlimit or Shunt underlimit is set. 12 BUL (Bus Under-limit) R/W 0b Setting this bit high configures the ALERT pin to be asserted if the bus voltage conversion result is below the value programmed in the LIMIT register Cannot be set if Shunt over limit, Shunt under limit or Bus over limit is set. 11 POL (Power Over-limit) R/W 0b Setting this bit high configures the ALERT pin to be asserted if the power result exceeds the value programmed in the LIMIT register Cannot be set if Shunt over limit, Shunt under limit, Bus over limit or Bus under limit is set. 10 CNVR (Conversion Ready) R/W 0b Setting this bit high configures the ALERT pin to be asserted when the Conversion Ready Flag, Bit 3, is asserted indicating that the device is ready for the next conversion. 0b = Disable conversion ready flag on ALERT pin 1b = Enables conversion ready flag on ALERT pin 9-6 Reserved R 0000b 5 MemError R 0b CRC or ECC error 4 AFF (Alert Function Flag) R 0b Alert Function Flag -While only one Alert Function can be monitored at the ALERT pin at a time, the Conversion Ready can also be enabled to assert the ALERT pin. Reading the Alert Function Flag following an alert allows the user to determine if the Alert Function was the source of the Alert. When the Alert Latch Enable bit is set to Latch mode, the Alert Function Flag bit clears only when the Mask/Enable Register is read. When the Alert Latch Enable bit is set to Transparent mode, the Alert Function Flag bit is cleared following the next conversion that does not result in an Alert condition. 3 CVRF (Conversion Ready Flag) R 0b Although the device can be read at any time, and the data from the last conversion is available, the Conversion Ready Flag bit is provided to help coordinate one-shot or triggered conversions. The Conversion Ready Flag bit is set after all conversions, averaging, and multiplications are complete. Conversion Ready Flag bit clears under the following conditions: 1.) Writing to the Configuration Register (except for Power-Down selection) 2.) Reading the Mask/Enable Register 2 OVF (Math Over-flow) R 0b This bit is set to '1' if an arithmetic operation resulted in an overflow error. It indicates that current and power data may be invalid. 1 APOL (Alert Polarity) R/W 0b Alert Polarity bit sets the Alert pin polarity. 0b = Normal (Active-low open drain) 1b= Inverted (active-high ) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA232 21 INA232 www.ti.com SBOSAA2 – DECEMBER 2022 Table 7-10. Mask/Enable Register Field Descriptions (continued) Bit 0 Field Type LEN (Alert Latch Enable) Reset R/W Description 0b When the Alert Latch Enable bit is set to Transparent mode, the Alert pin and Alert Function Flag (AFF) bit resets to the idle states when the fault condition has been cleared. When the Alert Latch Enable bit is set to Latch mode, the Alert pin and AFF bit remains active following a fault until this register flag has been read. This bit must be set to use the I2C Alert Response function. 0b = Transparent 1b = Latched Alert pin Return to the Summary Table. 7.6.1.8 Alert Limit Register (Address = 7h) [reset = 0000h] The alert limit register is shown in Table 7-11. Table 7-11. Alert Limit Register Field Descriptions Bit Field Type Reset Description 15-0 LIMIT R/W 0000h The Alert Limit Register contains the value used to compare to the register selected in the Mask/Enable Register to determine if a limit has been exceeded. A two's complement value must be used for the Shunt Over Voltage limit. Limit values entered should match the format of the targeted register Return to the Summary Table. 7.6.1.9 Manufacturer ID Register (Address = 3Eh) [reset = 5449h] The manufacturer ID register is shown in Table 7-12. Table 7-12. MANUFACTURE_ID Register Field Descriptions Bit 15-0 Field Type Reset Description MANUFACTURE_ID R 5449h Reads back TI in ASCII Return to the Summary Table. 22 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA232 INA232 www.ti.com SBOSAA2 – DECEMBER 2022 8 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 8.1 Application Information The INA232 is a current shunt monitor with an I2C- and SMBus-compatible interface. The device monitors a shunt voltage drop to calculate the current and bus voltage at IN– pin to determine power. Programmable calibration value, conversion times, and averaging (combined with an internal multiplier) enable direct readouts of current in amperes and power in watts. 8.1.1 Device Measurement Range and Resolution The INA232 device supports two input ranges for the shunt voltage measurement. The supported full scale differential input across the IN+ and IN– pins can be either ±81.92 mV or ±20.48 mV depending on the ADCRANGE bit in the Configuration Register (0h) register. The range for the bus voltage measurement at the IN- pin is from 0 V to 52.42 V, but is limited by process ratings to the max operating voltage. Table 8-1 provides a description of full scale voltage on shunt and bus voltage measurements, along with their associated resolution. Table 8-1. ADC Full Scale Values PARAMETER FULL SCALE VALUE RESOLUTION ±81.92 mV (ADCRANGE = 0) 2.5 µV/LSB ±20.48 mV (ADCRANGE = 1) 625 nV/LSB 0 V to 52.4 V (Limit usable range to recommended operating voltage) 1.6 mV/LSB Shunt voltage Bus voltage The device shunt voltage and bus voltage measurements are read through the Shunt Voltage register (1h) and Bus Voltage register (2h), respectively. The digital output in shunt voltage and bus voltage registers is 16 bits. The shunt voltage measurement can be positive or negative due to bidirectional currents in the system; therefore the data value in shunt voltage register can be positive or negative. The bus voltage register data value is always positive. The output data can be directly converted into voltage by multiplying the digital value by its respective resolution size. Furthermore, the device provides the flexibility to report calculated current in Amperes, power in Watts, as described in Current and Power Calculations. 8.1.2 Current and Power Calculations For the INA232 to report current values in Amperes, a constant conversion value must be written in the calibration register that is dependent on the selected CURRENT_LSB and the shunt resistance used in the application. The value of the calibration register is calculated based on Equation 1. The term CURRENT_LSB is the chosen LSB step size for the CURRENT register where the current is stored. Equation 2 shows the minimum value of CURRENT_LSB is based on the maximum expected current, and it directly defines the maximum resolution of the CURRENT register. While the smallest CURRENT_LSB value yields highest resolution, it is common to select a higher round-number (no higher than 8x) value for the CURRENT_LSB to simplify the conversion of the CURRENT. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA232 23 INA232 www.ti.com SBOSAA2 – DECEMBER 2022 The RSHUNT term is the resistance value of the external shunt used to develop the differential voltage across the IN+ and IN– pins. Use Equation 1 for ADCRANGE = 0. For ADCRANGE = 1, the value of SHUNT_CAL must be divided by 4. SHUNT_CAL = 0.00512 Current_LSB × RSHUNT (1) where • • • 0.00512 is an internal fixed value used to ensure scaling is maintained properly. CURRENT_LSB is a selected value for the current step size in amperes. Must be greater than or equal to CURRENT_LSB (minimum), but less than 8 x CURRENT_LSB(minimum) to reduce resolution loss. The value of SHUNT_CAL must be divided by 4 for ADCRANGE = 1. (2) Note that the current is calculated following a shunt voltage measurement based on the value set in the SHUNT_CAL register. If the value loaded into the SHUNT_CAL register is zero, the current value reported through the CURRENT register is also zero. After programming the SHUNT_CAL register with the calculated value, the measured current in Amperes can be read from the CURRENT register. Use Equation 3 to calculate the final value scaled by the CURRENT_LSB: Current [A] = CURRENT_LSB x CURRENT (3) where • CURRENT is the value read from the CURRENT register The power value can be read from the POWER register as a 16-bit value. Use Equation 4 to convert the power to Watts: Power [W] = 32 x CURRENT_LSB x POWER (4) where • • POWER is the value read from the POWER register. CURRENT_LSB is selected value for the lsb size of the current calculation used in Equation 1. Refer to Detailed Design Procedure for a design example using these equations. 8.1.3 ADC Output Data Rate and Noise Performance The INA232 noise performance and effective resolution depend on the ADC conversion time. The device also supports digital averaging which can further help decrease digital noise. The flexibility of the device to select ADC conversion time and data averaging offers increased signal-to-noise ratio and achieves the highest dynamic range with lowest offset. The profile of the noise at lower signals levels is dominated by the system noise that is comprised mainly of 1/f noise or white noise. The effective resolution of the ADC can be increased by increasing the conversion time and increasing the number of averages. Table 8-2 summarizes the output data rate conversion settings supported by the device. The fastest conversion setting is 140 µs. Typical noise-free resolution is represented as Effective Number of Bits (ENOB) based on device measured data. The ENOB is calculated based on noise peak-to-peak values, which assures that full noise distribution is taken into consideration. 24 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA232 INA232 www.ti.com SBOSAA2 – DECEMBER 2022 Table 8-2. INA232 Noise Performance ADC CONVERSION TIME PERIOD [µs] OUTPUT SAMPLE AVERAGING [SAMPLES] OUTPUT SAMPLE PERIOD [ms] NOISE-FREE ENOB (±81.92-mV) (ADCRANGE = 0) NOISE-FREE ENOB (±20.48-mV) (ADCRANGE = 1) 140 1 0.14 13.1 11.1 204 1 0.204 13.4 11.1 332 1 0.332 14.1 11.7 588 1 0.588 14.7 12.2 1100 1 1.1 14.7 12.5 2116 1 2.116 15.1 13.4 4156 1 4.156 15.7 14.1 8244 1 8.244 16.0 14.7 140 4 0.56 14.1 12.1 204 4 0.816 14.4 12.4 332 4 1.328 15.1 12.9 588 4 2.352 15.7 13.4 1100 4 4.4 15.7 13.7 2116 4 8.464 16.0 14.7 4156 4 16.624 16.0 14.7 8244 4 32.976 16.0 15.7 140 16 2.24 15.1 13.1 204 16 3.264 15.7 13.4 332 16 5.312 15.7 14.1 588 16 9.408 16.0 14.4 1100 16 17.6 16.0 15.1 2116 16 33.856 16.0 15.7 4156 16 66.496 16.0 15.7 8244 16 131.904 16.0 16.0 140 64 8.96 15.7 13.7 204 64 13.056 16.0 14.4 332 64 21.248 16.0 15.1 588 64 37.632 16.0 15.7 1100 64 70.4 16.0 15.7 2116 64 135.424 16.0 16.0 4156 64 265.984 16.0 16.0 8244 64 527.616 16.0 16.0 140 128 17.92 16.0 14.1 204 128 26.112 16.0 15.1 332 128 42.496 16.0 15.7 588 128 75.264 16.0 15.7 1100 128 140.8 16.0 16.0 2116 128 270.848 16.0 16.0 4156 128 531.968 16.0 16.0 8244 128 1055.232 16.0 16.0 140 256 35.84 16.0 14.7 204 256 52.224 16.0 15.7 332 256 84.992 16.0 15.7 588 256 150.528 16.0 16.0 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA232 25 INA232 www.ti.com SBOSAA2 – DECEMBER 2022 Table 8-2. INA232 Noise Performance (continued) ADC CONVERSION TIME PERIOD [µs] OUTPUT SAMPLE AVERAGING [SAMPLES] OUTPUT SAMPLE PERIOD [ms] NOISE-FREE ENOB (±81.92-mV) (ADCRANGE = 0) NOISE-FREE ENOB (±20.48-mV) (ADCRANGE = 1) 1100 256 281.6 16.0 16.0 2116 256 541.696 16.0 16.0 4156 256 1063.936 16.0 16.0 8244 256 2110.464 16.0 16.0 140 512 71.68 16.0 15.1 204 512 104.448 16.0 15.7 332 512 169.984 16.0 16.0 588 512 301.056 16.0 16.0 1100 512 563.2 16.0 16.0 2116 512 1083.392 16.0 16.0 4156 512 2127.872 16.0 16.0 8244 512 4220.928 16.0 16.0 140 1024 143.36 16.0 15.7 204 1024 208.896 16.0 16.0 332 1024 339.968 16.0 16.0 588 1024 602.112 16.0 16.0 1100 1024 1126.4 16.0 16.0 2116 1024 2166.784 16.0 16.0 4156 1024 4255.744 16.0 16.0 8244 1024 8441.856 16.0 16.0 8.1.4 Filtering and Input Considerations Measuring current is often noisy and such noise can be difficult to define. The INA232 offers several options for filtering by allowing the conversion times and number of averages to be selected independently in the Configuration register (0h). The conversion times can be set independently for the shunt voltage and bus voltage measurements to allow added flexibility when configuring the monitoring of the power-supply bus. The internal ADC is based on a delta-sigma (ΔΣ) front-end with a 500-kHz (±10% maximum) sampling rate. This architecture has good inherent noise rejection; however, transients that occur at or very close to the sampling rate harmonics can cause problems. These signals are at 1 MHz and higher and can be managed by incorporating filtering at the device input. The high frequency enables the use of low-value series resistors on the filter with negligible effects on measurement accuracy. In general, filtering the device input is only necessary if there are transients at exact harmonics of the 500 kHz (±10% maximum) sampling rate (greater than 1 MHz). Filter using the lowest possible series resistance (typically 100 Ω or less) and a ceramic capacitor. Recommended values for this capacitor are between 0.1 µF and 1 µF. Figure 8-1 shows the device with a filter added at the input. 26 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: INA232 INA232 www.ti.com SBOSAA2 – DECEMBER 2022 Load Supply VS = 1.7V± 5.5V 100 nF VS RFILTER