INA237-Q1
SBOSA27A – JUNE 2020 – REVISED JUNE 2021
INA237-Q1 AEC-Q100, 85-V, 16-Bit, Precision Power Monitor With I2C Interface
1 Features
3 Description
•
The INA237-Q1 is an ultra-precise digital power
monitor with a 16-bit delta-sigma ADC specifically
designed for current-sensing applications. The device
can measure a full-scale differential input of ±163.84
mV or ±40.96 mV across a resistive shunt sense
element with common-mode voltage support from –
0.3 V to +85 V.
•
•
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 qualified for automotive applications:
– Temperature grade 1: –40°C to +125°C, TA
Functional Safety-Capable
– Documentation available to aid functional safety
system design
High-resolution, 16-bit delta-sigma ADC
Current monitoring accuracy:
– Offset voltage: ±50 µV (maximum)
– Offset drift: ±0.02 µV/°C (maximum)
– Gain error: ±0.3% (maximum)
– Gain error drift: ±50 ppm/°C (maximum)
– Common mode rejection: 120 dB (minimum)
Power monitoring accuracy:
– 1.6% full scale, –40°C to +125°C (maximum)
Fast alert response: 75 μs
Wide common-mode range: –0.3 V to +85 V
Bus voltage sense input: 0 V to 85 V
Shunt full-scale differential range:
±163.84 mV / ±40.96 mV
Input bias current: 2.5 nA (maximum)
Temperature sensor: ±1°C (maximum at 25°C)
Programmable conversion time and averaging
2.94-MHz high-speed I2C interface with 16 pinselectable addresses
Operates from a 2.7-V to 5.5-V supply:
– Operational current: 640 µA (typical)
– Shutdown current: 5 µA (maximum)
The INA237-Q1 reports current, bus voltage,
temperature, and power, all while performing
the needed calculations in the background. The
integrated temperature sensor is ±1°C accurate
for die temperature measurement and is useful in
monitoring the system ambient temperature.
The low offset and gain drift design of the INA237Q1 allows the device to be used in precise systems
that do not undergo multi-temperature calibration
during manufacturing. Further, the very low offset
voltage and noise allow for use in A to kA sensing
applications and provide a wide dynamic range
without significant power dissipation losses on the
sensing shunt element. The low input bias current
of the device permits the use of larger currentsense resistors, thus providing accurate current
measurements in the micro-amp range.
The device allows for selectable ADC conversion
times from 50 µs to 4.12 ms as well as sample
averaging from 1x to 1024x, which further helps
reduce the noise of the measured data.
2 Applications
•
•
•
•
Automotive battery management systems
EV / HEV A - KA sense applications
DC/DC converters and power inverters
ADAS domain controllers
Device Information(1)
PART NUMBER
INA237-Q1
(1)
PACKAGE
VSSOP (10)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
For all available packages, see the package option
addendum at the end of the data sheet.
VS
Power
Reference
IN+
SCL
INMUX
16 Bit
ADC
VBUS
Voltage
Current
Power
Temp
2
IC
SDA
A0
A1
Oscillator
Out-of-range
Threshold
+
ALERT
±
GND
Simplified Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA237-Q1
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 3
6.1 Absolute Maximum Ratings ....................................... 3
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................4
6.5 Electrical Characteristics ............................................5
6.6 Timing Requirements (I2C) ........................................ 7
6.7 Timing Diagram ..........................................................7
6.8 Typical Characteristics................................................ 8
7 Detailed Description......................................................12
7.1 Overview................................................................... 12
7.2 Functional Block Diagram......................................... 12
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................19
7.5 Programming............................................................ 19
7.6 Register Maps...........................................................22
8 Application and Implementation.................................. 31
8.1 Application Information............................................. 31
8.2 Typical Application.................................................... 35
9 Power Supply Recommendations................................39
10 Layout...........................................................................39
10.1 Layout Guidelines................................................... 39
10.2 Layout Example...................................................... 39
11 Device and Documentation Support..........................40
11.1 Receiving Notification of Documentation Updates.. 40
11.2 Support Resources................................................. 40
11.3 Trademarks............................................................. 40
11.4 Electrostatic Discharge Caution.............................. 40
11.5 Glossary.................................................................. 40
12 Mechanical, Packaging, and Orderable
Information.................................................................... 40
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (June 2020) to Revision A (June 2021)
Page
• Changed data sheet status from: Advanced Information to: Production Data....................................................1
• Added Functional Safety bullets......................................................................................................................... 1
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Updated the figures and equations throughput the document to align with the commercial data sheet.............1
2
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5 Pin Configuration and Functions
A1
1
10
IN+
A0
2
9
IN–
ALERT
3
8
VBUS
SDA
4
7
GND
SCL
5
6
VS
Not to scale
Figure 5-1. DGS Package 10-Pin VSSOP Top View
Table 5-1. Pin Functions
PIN
NO.
TYPE
NAME
1
A1
DESCRIPTION
Digital input
I2C address pin. Connect to GND, SCL, SDA, or VS.
I2C address pin. Connect to GND, SCL, SDA, or VS.
2
A0
Digital input
3
ALERT
Digital output
4
SDA
Digital input/output
5
SCL
Digital input
6
VS
Power supply
7
GND
Ground
8
VBUS
Analog input
Bus voltage input.
9
IN–
Analog input
Negative input to the device. For high-side applications, connect to load side of sense resistor. For
low-side applications, connect to ground side of sense resistor.
10
IN+
Analog input
Positive input to the device. For high-side applications, connect to power supply side of sense
resistor. For low-side applications, connect to load side of sense resistor.
Open-drain alert output, default state is active low.
Open-drain bidirectional I2C data.
I2C clock input.
Power supply, 2.7 V to 5.5 V.
Ground.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
VS
Supply voltage
VIN+, VIN– (2)
MAX
UNIT
6
V
Differential (VIN+) – (VIN–)
–40
40
V
Common-mode
–0.3
85
V
VVBUS
–0.3
85
V
VALERT
ALERT
–0.3
vs. + 0.3
V
VIO
SDA, SCL
–0.3
6
V
IIN
Input current into any pin
5
mA
IOUT
Digital output current
10
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
VIN+ and VIN– are the voltages at the IN+ and IN– pins, respectively.
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6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002, all
ESD Classification Level 2
pins(1)
HBM
Charged device model (CDM), per AEC Q100-011, all pins CDM
ESD Classification Level C6
UNIT
±2000
V
±1000
AEC Q100-002 indicated that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VCM
Common-mode input range
–0.3
85
V
VS
Operating supply range
2.7
5.5
V
TA
Ambient temperature
–40
125
°C
6.4 Thermal Information
INA237-Q1
THERMAL
METRIC(1)
DGS
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
177.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
66.4
°C/W
RθJB
Junction-to-board thermal resistance
99.5
°C/W
ΨJT
Junction-to-top characterization parameter
9.7
°C/W
YJB
Junction-to-board characterization parameter
97.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
at TA = 25 °C, VS = 3.3 V, VSENSE = VIN+ – VIN– = 0 V, VCM = VIN– = 48 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
VCM
Common-mode input range
VVBUS
Bus voltage input range
CMRR
Common-mode rejection
TA = –40 °C to +125 °C
–0.3 V < VCM < 85 V, TA = –40 °C to +125 °C
–0.3
85
V
0
85
V
120
TA = –40 °C to +125 °C, ADCRANGE = 0
–163.84
TA = –40 °C to +125 °C, ADCRANGE = 1
–40.96
140
dB
163.84
mV
VDIFF
Shunt voltage input range
Vos
Shunt offset voltage
VCM = 0 V
dVos/dT
Shunt offset voltage drift
TA = –40 °C to +125 °C
PSRR
Shunt offset voltage vs. power supply
VS = 2.7 V to 5.5 V, TA = –40 °C to +125 °C
Vos_bus
VBUS offset voltage
VBUS = 20 mV
±1
±5
dVos/dT
VBUS offset voltage drift
TA = –40 °C to +125 °C
±20
±100
PSRR
VBUS offset voltage vs. power supply
VS = 2.7 V to 5.5 V
±1.1
IB
Input bias current
Either input, IN+ or IN–, VCM = 85 V
ZVBUS
VBUS pin input impedance
Active mode
IVBUS
VBUS pin leakage current
Shutdown mode, VBUS = 85 V
10
nA
RDIFF
Input differential impedance
Active mode, VIN+ – VIN– < 164 mV
92
kΩ
0.8
40.96
mV
±15
±50
µV
±2
±20
nV/°C
±0.1
±1
µV/V
mV
µV/°C
mV/V
0.1
2.5
nA
1
1.2
MΩ
DC ACCURACY
GSERR
Shunt voltage gain error
GS_DRFT
Shunt voltage gain error drift
GBERR
VBUS voltage gain error
GB_DRFT
VBUS voltage gain error drift
PTME
Power total measurment error (TME)
±0.1
±0.1
TA = –40 °C to +125 °C, at full scale
%
±1.6
%
16
Bits
Shunt voltage, ADCRANGE = 0
5
µV
Shunt voltage, ADCRANGE = 1
1.25
µV
Bus voltage
Conversion time field = 0h
ADC conversion-time(1)
±0.3
±50 ppm/°C
Temperature
TCT
%
±50 ppm/°C
ADC resolution
1 LSB step size
±0.3
3.125
mV
125
m°C
50
Conversion time field = 1h
84
Conversion time field = 2h
150
Conversion time field = 3h
280
Conversion time field = 4h
540
Conversion time field = 5h
1052
Conversion time field = 6h
2074
Conversion time field = 7h
4120
µs
INL
Integral Non-Linearity
±2
m%
DNL
Differential Non-Linearity
0.2
LSB
CLOCK SOURCE
FOSC
Internal oscillator frequency
FOSC_TOL Internal oscillator frequency tolerance
1
TA = 25 °C
TA = –40 °C to +125 °C
MHz
±0.5
%
±1
%
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6.5 Electrical Characteristics (continued)
at TA = 25 °C, VS = 3.3 V, VSENSE = VIN+ – VIN– = 0 V, VCM = VIN– = 48 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEMPERATURE SENSOR
Measurement range
Temperature accuracy
–40
TA = 25 °C
TA = –40 °C to +125 °C
+125
°C
±0.15
±1
°C
±0.2
±2
°C
5.5
V
640
750
µA
1.1
mA
5
µA
POWER SUPPLY
VS
Supply voltage
IQ
Quiescent current
IQSD
Quiescent current, shutdown
TPOR
Device start-up time
2.7
VSENSE = 0 V
VSENSE = 0 V, TA = –40 °C to +125 °C
Shuntdown mode
2.8
Power-up (NPOR)
300
From shutdown mode
µs
60
DIGITAL INPUT / OUTPUT
VIH
Logic input level, high
VIL
Logic input level, low
VOL
Logic output level, low
IOL = 3 mA
IIO_LEAK
Digital leakage input current
0 ≤ VIN ≤ VS
(1)
6
SDA, SCL
1.2
5.5
V
GND
0.4
V
GND
0.4
V
–1
1
µA
Subject to oscillator accuracy and drift
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6.6 Timing Requirements (I2C)
MIN
I2C
NOM
MAX
UNIT
400
kHz
BUS (FAST MODE)
F(SCL)
I2C clock frequency
t(BUF)
Bus free time between STOP and START conditions
600
ns
t(HDSTA)
Hold time after a repeated START condition. After this period, the first
clock is generated.
100
ns
t(SUSTA)
Repeated START condition setup time
100
ns
t(SUSTO)
STOP condition setup time
100
ns
t(HDDAT)
Data hold time
10
t(SUDAT)
Data setup time
100
ns
t(LOW)
SCL clock low period
1300
ns
t(HIGH)
SCL clock high period
600
ns
tF
Data fall time
300
ns
tF
Clock fall time
300
ns
tR
Clock rise time
300
ns
2940
kHz
1
900
ns
I2C BUS (HIGH-SPEED MODE)
F(SCL)
I2C clock frequency
t(BUF)
Bus free time between STOP and START conditions
160
ns
t(HDSTA)
Hold time after a repeated START condition. After this period, the first
clock is generated.
100
ns
t(SUSTA)
Repeated START condition setup time
100
ns
t(SUSTO)
STOP condition setup time
100
ns
t(HDDAT)
Data hold time
10
t(SUDAT)
Data setup time
20
ns
t(LOW)
SCL clock low period
200
ns
t(HIGH)
SCL clock high period
60
ns
tF
Data fall time
80
ns
tF
Clock fall time
40
ns
tR
Clock rise time
40
ns
10
125
ns
6.7 Timing Diagram
t(LOW)
tF
tR
t(HDSTA)
SCL
t(HDSTA)
t(HIGH)
t(HDDAT)
t(SUSTO)
t(SUSTA)
t(SUDAT)
SDA
t(BUF)
P
S
S
P
Figure 6-1. I2C Timing Diagram
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6.8 Typical Characteristics
Population
Population
at TA = 25 °C, VVS = 3.3 V, VCM = 48 V, VSENSE = 0, and VVBUS = 48 V (unless otherwise noted)
-50
-40
-30
-20
-10
0
10
20
30
40
50
-50
-40
-30
Shunt Offset Voltage (PV)
-20
-10
0
10
20
30
40
50
Shunt Offset Voltage (PV)
VCM = 48 V
VCM = 0 V
Figure 6-3. Shunt Input Offset Voltage Production Distribution
Population
Figure 6-2. Shunt Input Offset Voltage Production Distribution
-1
-0.8 -0.6 -0.4 -0.2
0
0.2
0.4
0.6
0.8
1
Common-Mode Rejection Ratio (PV)
Figure 6-5. Common-Mode Rejection Ratio Production
Distribution
Population
Figure 6-4. Shunt Input Offset Voltage vs. Temperature
-300
-200
-100
0
100
200
300
Shunt Gain Error (m%)
Figure 6-6. Shunt Input Common-Mode Rejection Ratio vs.
Temperature
8
VCM = 24 V
Figure 6-7. Shunt Input Gain Error Production Distribution
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6.8 Typical Characteristics (continued)
at TA = 25 °C, VVS = 3.3 V, VCM = 48 V, VSENSE = 0, and VVBUS = 48 V (unless otherwise noted)
Figure 6-9. Shunt Input Gain Error vs. Common-Mode Voltage
VCM = 24 V
Population
Figure 6-8. Shunt Input Gain Error vs. Temperature
-5
-4
-3
-2
-1
0
1
2
3
4
5
Bus Voltage Offset (mV)
VVBUS = 20 mV
VVBUS = 20 mV
Figure 6-10. Bus Input Offset Voltage Production Distribution
Figure 6-11. Bus Input Offset Voltage vs. Temperature
140
120
Population
100
80
60
40
20
0
-300
-200
-100
0
100
200
300
Bus Voltage Gain Error (m%)
Figure 6-12. Bus Input Gain Error Production Distribution
Figure 6-13. Bus Input Gain Error vs. Temperature
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6.8 Typical Characteristics (continued)
at TA = 25 °C, VVS = 3.3 V, VCM = 48 V, VSENSE = 0, and VVBUS = 48 V (unless otherwise noted)
10
Figure 6-14. Input Bias Current vs. Differential Input Voltage
Figure 6-15. Input Bias Current (IB+ or IB–) vs. Common-Mode
Voltage
Figure 6-16. Input Bias Current vs. Temperature
Figure 6-17. Input Bias Current vs. Temperature, Shutdown
Figure 6-18. Active IQ vs. Temperature
Figure 6-19. Active IQ vs. Supply Voltage
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6.8 Typical Characteristics (continued)
at TA = 25 °C, VVS = 3.3 V, VCM = 48 V, VSENSE = 0, and VVBUS = 48 V (unless otherwise noted)
Figure 6-21. Shutdown IQ vs. Temperature
Figure 6-20. Shutdown IQ vs. Supply Voltage
150
680
Quiescent Current - Shutdown (PA)
Quiescent Current (PA)
Continuous I2C Write Commands
660
Idle SDA, Clocking SCL
640
620
600
120
90
60
30
0
1
10
100
Frequency (kHz)
1000
3000
1
10
100
Frequency (kHz)
1000
Figure 6-22. Active IQ vs. Clock Frequency
Figure 6-23. Shutdown IQ vs. Clock Frequency
Figure 6-24. Internal Clock Frequency vs. Power Supply
Figure 6-25. Internal Clock Frequency vs. Temperature
3000
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7 Detailed Description
7.1 Overview
The INA237-Q1 device is a digital current sense amplifier with an I2C digital interface. It measures shunt voltage,
bus voltage and internal temperature while calculating current, power necessary for accurate decision making in
precisely controlled systems. Programmable registers allow flexible configuration for measurement precision as
well as continuous or triggered operation. Detailed register information is found in Section 7.6.
7.2 Functional Block Diagram
VS
Power
Reference
IN+
SCL
IN16 Bit
ADC
MUX
Voltage
Current
Power
Temp
VBUS
I2 C
SDA
A0
A1
Oscillator
+
Out-of-range
Threshold
ALERT
±
GND
7.3 Feature Description
7.3.1 Versatile High Voltage Measurement Capability
The INA237-Q1 operates off a 2.7 V to 5.5 V supply but can measure voltage and current on rails as high as
85 V. The current is measured by sensing the voltage drop across a external shunt resistor at the IN+ and IN–
pins. The input stage of the INA237-Q1 is designed such that the input common-mode voltage can be higher
than the device supply voltage, VS. The supported common-mode voltage range at the input pins is –0.3 V to
+85 V, which makes the device well suited for both high-side and low-side current measurements. There are no
special considerations for power-supply sequencing because the common-mode input range and device supply
voltage are independent of each other; therefore, the bus voltage can be present with the supply voltage off, and
vice-versa without damaging the device.
The device also measures the bus supply voltage through the VBUS pin and temperature through the integrated
temperature sensor. The differential shunt voltage is measured between the IN+ and IN– pins, while the bus
voltage is measured with respect to device ground. Monitored bus voltages can range from 0 V to 85 V, while
monitored temperatures can range from -40 ºC to +125 ºC.
Shunt voltage, bus voltage, and temperature measurements are multiplexed internally to a single ADC as shown
in Figure 7-1.
ADCp ADCn
Bus Voltage
VBUS
Shunt Voltage
Internal Temp.
IN+
ADC_IN+
To ADC Input
IN-
ADC_IN-
Vs
PTAT Temp.
Sensor
MUX digital
Control
Figure 7-1. High-Voltage Input Multiplexer
12
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7.3.2 Power Calculation
The current and power are calculated after a shunt voltage and bus voltage measurement as shown in Figure
7-2. Power is calculated based on the previous current calculation and the latest bus voltage measurement. If
the value loaded into the SHUNT_CAL register is zero, the power value reported is also zero. The current and
power values are considered intermediate results (unless the averaging is set to 1) and are stored in an internal
accumulation register. Following every measured sample, the newly-calculated values for current and power are
appended to this accumulation register until all of the samples have been measured and averaged. After all
of the samples have been measured and the corresponding current and power calculations have been made,
the accumulated average for each of these parameters is then loaded to the corresponding output registers
where they can then be read. These calculations are performed in the background and do not add to the overall
conversion time.
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Bus and Power Limit Detect
Following Every Bus Voltage Conversion
Current Limit Detect Following
Every Shunt Voltage Conversion
I
V
I
P
V
I
P
V
I
P
V
I
P
V
I
P
V
I
P
V
I
P
V
I
P
V
I
V
P
I
V
P
I
P
V
I
P
V
I
P
V
I
P
V
I
P
V
P
Power Average
Bus Voltage Average
Shunt Voltage Average
Figure 7-2. Power Calculation Scheme
14
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7.3.3 Low Bias Current
The INA237-Q1 features very low input bias current which provides several benefits. The low input bias current
of the INA237-Q1 reduces the current consumed by the device in both active and shutdown state. Another
benefit of low bias current is that it allows the use of input filters to reject high-frequency noise before the signal
is converted to digital data. In traditional digital current-sense amplifiers, the addition of input filters comes at
the cost of reduced accuracy. However, as a result of the low bias current, the reduction in accuracy due to
input filters is minimized. An additional benefit of low bias current is the ability to use a larger shunt resistor to
accurately sense smaller currents. Use of a larger value for the shunt resistor allows the device to accurately
monitor currents in the sub-mA range.
The bias current in the INA237-Q1 is the smallest when the sensed current is zero. As the current starts to
increase, the differential voltage drop across the shunt resistor increases which results in an increase in the bias
current as shown in Input Bias Current vs. Differential Input Voltage.
7.3.4 High-Precision Delta-Sigma ADC
The integrated ADC is a high-performance, low-offset, low-drift, delta-sigma ADC designed to support
bidirectional current flow at the shunt voltage measurement channel. The measured inputs are selected through
the high-voltage input multiplexer to the ADC inputs as shown in Figure 7-1. The ADC architecture enables
lower drift measurement across temperature and consistent offset measurements across the common-mode
voltage, temperature, and power supply variations. A low-offset ADC is preferred in current sensing applications
to provide a near 0-V offset voltage that maximizes the useful dynamic range of the system.
The INA237-Q1 can measure the shunt voltage, bus voltage, and die temperature, or a combination of any
based on the selected MODE bits setting in the ADC_CONFIG register. This permits selecting modes to convert
only the shunt voltage or bus voltage to further allow the user to configure the monitoring function to fit the
specific application requirements. When no averaging is selected, once an ADC conversion is completed, the
converted values are independently updated in their corresponding registers where they can be read through
the digital interface at the time of conversion end. The conversion time for shunt voltage, bus voltage, and
temperature inputs are set independently from 50 µs to 4.12ms depending on the values programmed in the
ADC_CONFIG register. Enabled measurement inputs are converted sequentially so the total time to convert
all inputs depends on the conversion time for each input and the number of inputs enabled. When averaging
is used, the intermediate values are subsequently stored in an averaging accumulator, and the conversion
sequence repeats until the number of averages is reached. After all of the averaging has been completed, the
final values are updated in the corresponding registers that can then be read. These values remain in the data
output registers until they are replaced by the next fully completed conversion results. In this case, reading the
data output registers does not affect a conversion in progress.
The ADC has two conversion modes—continuous and triggered—set by the MODE bits in ADC_CONFIG
register. In continuous-conversion mode, the ADC will continuously convert the input measurements and update
the output registers as described above in an indefinite loop. In triggered-conversion mode, the ADC will convert
the input measurements as described above, after which the ADC will go into shutdown mode until another
single-shot trigger is generated by writing to the MODE bits. Writing the MODE bits will interrupt and restart
triggered or continuous conversions that are in progress. Although the device can be read at any time, and
the data from the last conversion remains available, the Conversion Ready flag (CNVRF bit in DIAG_ALRT
register) is provided to help coordinate triggered conversions. This bit is set after all conversions and averaging
is completed.
The Conversion Ready flag (CNVRF) clears under these conditions:
•
•
Writing to the ADC_CONFIG register (except for selecting shutdown mode); or
Reading the DIAG_ALRT Register
While the INA237-Q1 device is used in either one of the conversion modes, a dedicated digital engine is
calculating the current and power values in the background as described in Section 7.3.2. All of the calculations
are performed in the background and do not contribute to conversion time.
For applications that must synchronize with other components in the system, the INA237-Q1 conversion can be
delayed by programming the CONVDLY bits in CONFIG register in the range between 0 (no delay) and 510
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ms. The resolution in programming the conversion delay is 2 ms. The conversion delay is set to 0 by default.
Conversion delay can assist in measurement synchronization when multiple external devices are used for
voltage or current monitoring purposes. In applications where an time aligned voltage and current measurements
are needed, two devices can be used with the current measurement delayed such that the external voltage and
current measurements will occur at approximately the same time. Keep in mind that even though the internal
time base for the ADC is precise, synchronization will be lost over time due to internal and external time base
mismatch.
7.3.4.1 Low Latency Digital Filter
The device integrates a low-pass digital filter that performs both decimation and filtering on the ADC output
data, which helps with noise reduction. The digital filter is automatically adjusted for the different output data
rates and always settles within one conversion cycle. The user has the flexibility to choose different output
conversion time periods TCT from 50 µs to 4.12 ms. With this configuration the first amplitude notch appears
at the Nyquist frequency of the output signal which is determined by the selected conversion time period and
defined as fNOTCH= 1 / (2 x TCT). This means that the filter cut-off frequency will scale proportionally with the data
output rate as described. ADC Frequency Response shows the filter response when the 1.052 ms conversion
time period is selected.
0
−10
Gain (dB)
−20
−30
−40
−50
−60
1
10
100
1k
Frequency (Hz)
10k
100k
G001
Conversion time = 1.052 ms, single
conversion only
Figure 7-3. ADC Frequency Response
7.3.4.2 Flexible Conversion Times and Averaging
ADC conversion times for shunt voltage, bus voltage and temperature can be set independently from 50 μs to
4.12 ms. The flexibility in conversion time allows for robust operation in a variety of noisy environments. The
device also allows for programmable averaging times from a single conversion all the way to an average of
1024 conversions. The amount of averaging selected applies uniformly to all active measurement inputs. The
ADC_CONFIG register shown in Table 7-6 provides additional details on the supported conversion times and
averaging modes. The INA237-Q1 effective resolution of the ADC can be increased by increasing the conversion
time and increasing the number of averages. Figure 7-4 and Figure 7-5 shown below illustrate the effect of
conversion time and averaging on a constant input signal.
16
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Figure 7-4. Noise vs. Conversion Time (Averaging = 1)
Figure 7-5. Noise vs. Conversion Time (Averaging = 128)
Settings for the conversion time and number of conversions averaged impact the effective measurement
resolution. For more detailed information on how averaging reduces noise and increases the effective number of
bits (ENOB) see Section 8.1.3.
7.3.5 Integrated Precision Oscillator
The internal timebase of the device is provided by an internal oscillator that is trimmed to less than 0.5%
tolerance at room temperature. The precision oscillator is the timing source for ADC conversions. The digital
filter response varies with conversion time; therefore, the precise clock ensures filter response and notch
frequency consistency across temperature. On power up, the internal oscillator and ADC take roughly 300 µs
to reach 0h, the output registers are updated after the averaging has
completed.
0h = 1
1h = 4
2h = 16
3h = 64
4h = 128
5h = 256
6h = 512
7h = 1024
7.6.1.3 Shunt Calibration (SHUNT_CAL) Register (Address = 2h) [reset = 1000h]
The SHUNT_CAL register is shown in Table 7-7.
Return to the Summary Table.
Table 7-7. SHUNT_CAL Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
R
0h
Reserved. Always reads 0.
14-0
SHUNT_CAL
R/W
1000h
The register provides the device with a conversion constant value
that represents shunt resistance used to calculate current value in
Amperes.
This also sets the resolution for the CURRENT register.
Value calculation under Section 8.1.2.
7.6.1.4 Shunt Voltage Measurement (VSHUNT) Register (Address = 4h) [reset = 0h]
The VSHUNT register is shown in Table 7-8.
Return to the Summary Table.
Table 7-8. VSHUNT Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
VSHUNT
R
0h
Differential voltage measured across the shunt output. Two's
complement value.
Conversion factor:
5 µV/LSB when ADCRANGE = 0
1.25 µV/LSB when ADCRANGE = 1
7.6.1.5 Bus Voltage Measurement (VBUS) Register (Address = 5h) [reset = 0h]
The VBUS register is shown in Table 7-9.
Return to the Summary Table.
Table 7-9. VBUS Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
VBUS
R
0h
Bus voltage output. Two's complement value, however always
positive.
Conversion factor: 3.125 mV/LSB
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7.6.1.6 Temperature Measurement (DIETEMP) Register (Address = 6h) [reset = 0h]
The DIETEMP register is shown in Table 7-10.
Return to the Summary Table.
Table 7-10. DIETEMP Register Field Descriptions
Bit
Field
Type
Reset
Description
15-4
DIETEMP
R
0h
Internal die temperature measurement. Two's complement value.
Conversion factor: 125 m°C/LSB
3-0
RESERVED
R
0h
Reserved. Always reads 0.
7.6.1.7 Current Result (CURRENT) Register (Address = 7h) [reset = 0h]
The CURRENT register is shown in Table 7-11.
Return to the Summary Table.
Table 7-11. CURRENT Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
CURRENT
R
0h
Calculated current output in Amperes. Two's complement value.
Value description under Section 8.1.2.
7.6.1.8 Power Result (POWER) Register (Address = 8h) [reset = 0h]
The POWER register is shown in Table 7-12.
Return to the Summary Table.
Table 7-12. POWER Register Field Descriptions
Bit
23-0
Field
Type
Reset
Description
POWER
R
0h
Calculated power output.
Output value in watts.
Unsigned representation. Positive value.
Value description under Section 8.1.2.
7.6.1.9 Diagnostic Flags and Alert (DIAG_ALRT) Register (Address = Bh) [reset = 0001h]
The DIAG_ALRT register is shown in Table 7-13.
Return to the Summary Table.
Table 7-13. DIAG_ALRT Register Field Descriptions
26
Bit
Field
Type
Reset
Description
15
ALATCH
R/W
0h
When the Alert Latch Enable bit is set to Transparent mode, the
Alert pin and Flag bit reset to the idle state when the fault has been
cleared.
When the Alert Latch Enable bit is set to Latch mode, the Alert pin
and Alert Flag bit remain active following a fault until the DIAG_ALRT
Register has been read.
0h = Transparent
1h = Latched
14
CNVR
R/W
0h
Setting this bit high configures the Alert pin to be asserted when
the Conversion Ready Flag (bit 1) is asserted, indicating that a
conversion cycle has completed.
0h = Disable conversion ready flag on ALERT pin
1h = Enables conversion ready flag on ALERT pin
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Table 7-13. DIAG_ALRT Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
13
SLOWALERT
R/W
0h
When enabled, ALERT function is asserted on the completed
averaged value.
This gives the flexibility to delay the ALERT until after the averaged
value.
0h = ALERT comparison on non-averaged (ADC) value
1h = ALERT comparison on averaged value
12
APOL
R/W
0h
Alert Polarity bit sets the Alert pin polarity.
0h = Normal (Active-low, open-drain)
1h = Inverted (active-high, open-drain )
11-10
RESERVED
R
0h
Reserved. Always read 0.
9
MATHOF
R
0h
This bit is set to 1 if an arithmetic operation resulted in an overflow
error.
It indicates that current and power data may be invalid.
0h = Normal
1h = Overflow
Must be manually cleared by triggering another conversion.
8
RESERVED
R
0h
Reserved. Always read 0.
7
TMPOL
R/W
0h
This bit is set to 1 if the temperature measurement exceeds the
threshold limit in the temperature over-limit register.
0h = Normal
1h = Over Temp Event
When ALATCH =1 this bit is cleared by reading this register.
6
SHNTOL
R/W
0h
This bit is set to 1 if the shunt voltage measurement exceeds the
threshold limit in the shunt over-limit register.
0h = Normal
1h = Over Shunt Voltage Event
When ALATCH =1 this bit is cleared by reading this register.
5
SHNTUL
R/W
0h
This bit is set to 1 if the shunt voltage measurement falls below the
threshold limit in the shunt under-limit register.
0h = Normal
1h = Under Shunt Voltage Event
When ALATCH =1 this bit is cleared by reading this register.
4
BUSOL
R/W
0h
This bit is set to 1 if the bus voltage measurement exceeds the
threshold limit in the bus over-limit register.
0h = Normal
1h = Bus Over-Limit Event
When ALATCH =1 this bit is cleared by reading this register.
3
BUSUL
R/W
0h
This bit is set to 1 if the bus voltage measurement falls below the
threshold limit in the bus under-limit register.
0h = Normal
1h = Bus Under-Limit Event
When ALATCH =1 this bit is cleared by reading this register.
2
POL
R/W
0h
This bit is set to 1 if the power measurement exceeds the threshold
limit in the power limit register.
0h = Normal
1h = Power Over-Limit Event
When ALATCH =1 this bit is cleared by reading this register.
1
CNVRF
R/W
0h
This bit is set to 1 if the conversion is completed.
0h = Normal
1h = Conversion is complete
When ALATCH =1 this bit is cleared by reading this register or
starting a new triggered conversion.
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Table 7-13. DIAG_ALRT Register Field Descriptions (continued)
Bit
0
28
Field
Type
Reset
Description
MEMSTAT
R/W
1h
This bit is set to 0 if a checksum error is detected in the device trim
memory space.
0h = Memory Checksum Error
1h = Normal Operation
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7.6.1.10 Shunt Overvoltage Threshold (SOVL) Register (Address = Ch) [reset = 7FFFh]
If negative values are entered in this register, then a shunt voltage measurement of 0 V will trip this alarm. When
using negative values for the shunt under and overvoltage thresholds be aware that the over voltage threshold
must be set to the larger (that is, less negative) of the two values. The SOVL register is shown in Table 7-14.
Return to the Summary Table.
Table 7-14. SOVL Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
SOVL
R/W
7FFFh
Sets the threshold for comparison of the value to detect Shunt
Overvoltage (overcurrent protection). Two's complement value.
Conversion Factor: 5 µV/LSB when ADCRANGE = 0
1.25 µV/LSB when ADCRANGE = 1.
7.6.1.11 Shunt Undervoltage Threshold (SUVL) Register (Address = Dh) [reset = 8000h]
The SUVL register is shown in Table 7-15.
Return to the Summary Table.
Table 7-15. SUVL Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
SUVL
R/W
8000h
Sets the threshold for comparison of the value to detect Shunt
Undervoltage (undercurrent protection). Two's complement value.
Conversion Factor: 5 µV/LSB when ADCRANGE = 0
1.25 µV/LSB when ADCRANGE = 1.
7.6.1.12 Bus Overvoltage Threshold (BOVL) Register (Address = Eh) [reset = 7FFFh]
The BOVL register is shown in Table 7-16.
Return to the Summary Table.
Table 7-16. BOVL Register Field Descriptions
Bit
Field
Type
Reset
Description
15
Reserved
R
0h
Reserved. Always reads 0.
BOVL
R/W
7FFFh
Sets the threshold for comparison of the value to detect Bus
Overvoltage (overvoltage protection). Unsigned representation,
positive value only. Conversion factor: 3.125 mV/LSB.
14-0
7.6.1.13 Bus Undervoltage Threshold (BUVL) Register (Address = Fh) [reset = 0h]
The BUVL register is shown in Table 7-17.
Return to the Summary Table.
Table 7-17. BUVL Register Field Descriptions
Bit
Field
Type
Reset
Description
15
Reserved
R
0h
Reserved. Always reads 0.
BUVL
R/W
0h
Sets the threshold for comparison of the value to detect Bus
Undervoltage (undervoltage protection). Unsigned representation,
positive value only. Conversion factor: 3.125 mV/LSB.
14-0
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7.6.1.14 Temperature Over-Limit Threshold (TEMP_LIMIT) Register (Address = 10h) [reset = 7FFFh]
The TEMP_LIMIT register is shown in Table 7-18.
Return to the Summary Table.
Table 7-18. TEMP_LIMIT Register Field Descriptions
Bit
Field
Type
Reset
Description
15-4
TOL
R/W
7FFh
Sets the threshold for comparison of the value to detect over
temperature measurements. Two's complement value.
The value entered in this field compares directly against the value
from the DIETEMP register to determine if an over temperature
condition exists. Conversion factor: 125 m°C/LSB.
3-0
Reserved
R
0
Reserved, always reads 0
7.6.1.15 Power Over-Limit Threshold (PWR_LIMIT) Register (Address = 11h) [reset = FFFFh]
The PWR_LIMIT register is shown in Table 7-19.
Return to the Summary Table.
Table 7-19. PWR_LIMIT Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
POL
R/W
FFFFh
Sets the threshold for comparison of the value to detect power overlimit measurements. Unsigned representation, positive value only.
The value entered in this field compares directly against the value
from the POWER register to determine if an over power condition
exists. Conversion factor: 256 × Power LSB.
7.6.1.16 Manufacturer ID (MANUFACTURER_ID) Register (Address = 3Eh) [reset = 5449h]
The MANUFACTURER_ID register is shown in Table 7-20.
Return to the Summary Table.
Table 7-20. MANUFACTURER_ID Register Field Descriptions
Bit
15-0
30
Field
Type
Reset
Description
MANFID
R
5449h
Reads back TI in ASCII.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 Device Measurement Range and Resolution
The INA237-Q1 device supports two input ranges for the shunt voltage measurement. The supported full scale
differential input across the IN+ and IN– pins can be either ±163.84 mV or ±40.96 mV depending on the
ADCRANGE bit in CONFIG register. The range for the bus voltage measurement is from 0 V to 85 V. The
internal die temperature sensor range extends from –256 °C to +256 °C but is limited by the package to –40 °C
to 125 °C.
Table 8-1 provides a description of full scale voltage on shunt, bus, and temperature measurements, along with
their associated step size.
Table 8-1. ADC Full Scale Values
PARAMETER
Shunt voltage
FULL SCALE VALUE
RESOLUTION
±163.84 mV (ADCRANGE = 0)
5 µV/LSB
±40.96 mV (ADCRANGE = 1)
1.25 µV/LSB
Bus voltage
0 V to 85 V
3.125 mV/LSB
Temperature
–40 °C to +125 °C
125 m°C/LSB
The device shunt voltage measurements, bus voltage, and temperature measurements can be read through the
VSHUNT, VBUS, and DIETEMP registers, respectively. The digital output in VSHUNT and VBUS registers is
16-bits. The shunt voltage measurement can be positive or negative due to bidirectional currents in the system;
therefore the data value in VSHUNT can be positive or negative. The VBUS data value is always positive. The
output data can be directly converted into voltage by multiplying the digital value by its respective resolution size.
The digital output in the DIETEMP register is 12-bit and can be directly converted to °C by multiplying by the
above resolution size. This output value can also be positive or negative.
Furthermore, the device provides the flexibility to report calculated current in Amperes, power in Watts as
described in Section 8.1.2.
8.1.2 Current and Power Calculations
For the INA237-Q1 device to report current values in Ampere units, a constant conversion value must be written
in the SHUNT_CAL register that is dependent on the maximum measured current and the shunt resistance used
in the application. The SHUNT_CAL register is calculated based on Equation 1. The term CURRENT_LSB is the
LSB step size for the CURRENT register where the current in Amperes is stored. The value of CURRENT_LSB
is based on the maximum expected current as shown in Equation 2, and it directly defines the resolution of the
CURRENT register. While the smallest CURRENT_LSB value yields highest resolution, it is common to select a
higher round-number (no higher than 8x) value for the CURRENT_LSB in order to simplify the conversion of the
CURRENT.
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The RSHUNT term is the resistance value of the external shunt used to develop the differential voltage across the
IN+ and IN– pins. Use Equation 1 for ADCRANGE = 0. For ADCRANGE = 1, the value of SHUNT_CAL must be
multiplied by 4.
SHUNT_CAL = 819.2 x 106 x CURRENT_LSB x RSHUNT
(1)
where
•
•
819.2 x 106 is an internal fixed value used to ensure scaling is maintained properly.
the value of SHUNT_CAL must be multiplied by 4 for ADCRANGE = 1.
Current_LSB =
Maximum Expected Current
215
(2)
Note that the current is calculated following a shunt voltage measurement based on the value set in the
SHUNT_CAL register. If the value loaded into the SHUNT_CAL register is zero, the current value reported
through the CURRENT register is also zero.
After programming the SHUNT_CAL register with the calculated value, the measured current in Amperes can be
read from the CURRENT register. The final value is scaled by CURRENT_LSB and calculated in Equation 3:
Current [A] = CURRENT_LSB x CURRENT
(3)
where
•
CURRENT is the value read from the CURRENT register
The power value can be read from the POWER register as a 24-bit value and converted to Watts by using
Equation 4:
Power [W] = 0.2 x CURRENT_LSB x POWER
(4)
where
•
•
POWER is the value read from the POWER register.
CURRENT_LSB is the lsb size of the current calculation as defined by Equation 2.
For a design example using these equations refer to Section 8.2.2.
8.1.3 ADC Output Data Rate and Noise Performance
The INA237-Q1 noise performance and effective resolution depend on the ADC conversion time. The device
also supports digital averaging which can further help decrease digital noise. The flexibility of the device to
select ADC conversion time and data averaging offers increased signal-to-noise ratio and achieves the highest
dynamic range with lowest offset. The profile of the noise at lower signals levels is dominated by the system
noise that is comprised mainly of 1/f noise or white noise. The INA237-Q1 effective resolution of the ADC can be
increased by increasing the conversion time and increasing the number of averages.
Table 8-2 summarizes the output data rate conversion settings supported by the device. The fastest conversion
setting is 50 µs. Typical noise-free resolution is represented as Effective Number of Bits (ENOB) based on
device measured data. The ENOB is calculated based on noise peak-to-peak values, which assures that full
noise distribution is taken into consideration.
32
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Table 8-2. INA237-Q1 Noise Performance
ADC CONVERSION
TIME PERIOD [µs]
OUTPUT SAMPLE
AVERAGING [SAMPLES]
OUTPUT SAMPLE PERIOD
[ms]
NOISE-FREE ENOB
(±163.84-mV)
(ADCRANGE = 0)
NOISE-FREE ENOB
(±40.96-mV)
(ADCRANGE = 1)
50
0.05
12.5
9.9
84
0.084
12.7
10.5
150
0.15
13.4
11.4
0.28
13.7
12.2
0.54
14.1
12.4
1052
1.052
14.1
12.7
2074
2.074
15.7
13.1
4120
4.12
15.7
13.4
50
0.2
12.7
10.6
84
0.336
13.7
11.4
150
0.6
14.1
12.2
1.12
14.7
12.7
2.16
15.7
13.4
1052
4.208
15.7
14.1
2074
8.296
15.7
14.7
4120
16.48
15.7
14.7
50
0.8
13.7
11.5
84
1.344
15.7
12.7
150
2.4
15.7
13.4
280
4.48
15.7
13.7
280
540
280
540
540
1
4
16
8.64
15.7
14.1
1052
16.832
15.7
14.7
2074
33.184
15.7
15.7
4120
65.92
16.0
15.7
50
3.2
15.7
12.5
84
5.376
15.7
13.7
150
9.6
15.7
14.7
280
17.92
15.7
14.7
540
64
34.56
16.0
14.7
1052
67.328
16.0
15.7
2074
132.736
16.0
15.7
4120
263.68
16.0
15.7
50
6.4
15.7
13.1
84
10.752
15.7
14.1
150
19.2
15.7
14.7
280
35.84
16.0
15.7
540
128
69.12
16.0
15.7
1052
134.656
16.0
15.7
2074
265.472
16.0
15.7
4120
527.36
16.0
16.0
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Table 8-2. INA237-Q1 Noise Performance (continued)
ADC CONVERSION
TIME PERIOD [µs]
OUTPUT SAMPLE
AVERAGING [SAMPLES]
OUTPUT SAMPLE PERIOD
[ms]
NOISE-FREE ENOB
(±163.84-mV)
(ADCRANGE = 0)
NOISE-FREE ENOB
(±40.96-mV)
(ADCRANGE = 1)
50
12.8
15.7
13.7
84
21.504
15.7
14.7
150
38.4
15.7
15.7
280
71.68
16.0
15.7
138.24
16.0
15.7
1052
269.312
16.0
16.0
2074
530.944
16.0
16.0
4120
1054.72
16.0
16.0
50
25.6
15.7
14.1
84
43
16.0
15.7
150
76.8
16.0
15.7
143.36
16.0
15.7
276.48
16.0
15.7
1052
538.624
16.0
16.0
2074
1061.888
16.0
16.0
4120
2109.44
16.0
16.0
50
51.2
15.7
14.7
84
86.016
15.7
15.7
150
153.6
16.0
16.0
280
286.72
16.0
16.0
540
280
540
540
256
512
1024
552.96
16.0
16.0
1052
1077.248
16.0
16.0
2074
2123.776
16.0
16.0
4120
4218.88
16.0
16.0
8.1.4 Input Filtering Considerations
As previously discussed, INA237-Q1 offers several options for noise filtering by allowing the user to select the
conversion times and number of averages independently in the ADC_CONFIG register. The conversion times
can be set independently for the shunt voltage and bus voltage measurements to allow added flexibility in
monitoring of the power-supply bus.
The internal ADC has good inherent noise rejection; however, the transients that occur at or very close to the
sampling rate harmonics can cause problems. Because these signals are at 1 MHz and higher, they can be
managed by incorporating filtering at the input of the device. Filtering high frequency signals enables the use of
low-value series resistors on the filter with negligible effects on measurement accuracy. For best results, filter
using the lowest possible series resistance (typically 100 Ω or less) and a ceramic capacitor. Recommended
values for this capacitor are between 0.1 µF and 1 µF. Figure 8-1 shows the device with a filter added at the
input.
Overload conditions are another consideration for the device inputs. The device inputs are specified to tolerate
±40 V differential across the IN+ and IN– pins. A large differential scenario might be a short to ground on the
load side of the shunt. This type of event can result in full power-supply voltage across the shunt (as long
the power supply or energy storage capacitors support it). Removing a short to ground can result in inductive
kickbacks that could exceed the 40-V differential or 85-V common-mode absolute maximum rating of the device.
Inductive kickback voltages are best controlled by Zener-type transient-absorbing devices (commonly called
transzorbs) combined with sufficient energy storage capacitance. See the Transient Robustness for Current
Shunt Monitors reference design which describes a high-side current shunt monitor used to measure the voltage
developed across a current-sensing resistor when current passes through it.
34
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Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: INA237-Q1
INA237-Q1
www.ti.com
SBOSA27A – JUNE 2020 – REVISED JUNE 2021
In applications that do not have large energy storage, electrolytic capacitors on one or both sides of the shunt,
an input overstress condition may result from an excessive dV/dt of the voltage applied to the input. A hard
physical short is the most likely cause of this event. This problem occurs because an excessive dV/dt can
activate the ESD protection in the device in systems where large currents are available. Testing demonstrates
that the addition of 10-Ω resistors in series with each input of the device sufficiently protects the inputs against
this dV/dt failure up to the 40-V maximum differential voltage rating of the device. Selecting these resistors in the
range noted has minimal effect on accuracy.
Load
Supply
VS = 2.7V± 5.5V
100 nF
VS
RFILTER
VBUS
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