INA300
SBOS613C – FEBRUARY 2014 – REVISED JUNE 2021
INA300 Overcurrent-Protection, Current-Sense Comparator
1 Features
3 Description
•
•
Designed for overcurrent protection applications, the
INA300 is a current-sensing comparator that detects
overcurrent by measuring the voltage developed
across a shunt resistor, and comparing that voltage
to the threshold voltage input level. The device
measures this differential voltage signal on commonmode voltages that can vary from 0 V up to 36
V, independent of the supply voltage. The INA300
device features an adjustable threshold range that
is set using a single external limit-setting resistor.
A selectable hysteresis feature enables adjustable
operation of the comparator to accommodate the wide
input signal range of 0 mV to 250 mV.
•
•
•
•
•
•
Wide Common-Mode Range: 0 V to 36 V
Selectable Response Times:
– 10 µs, 50 µs, 100 µs
Programmable Threshold:
– Adjust Using Single Resistor
– Programmable From 0 mV to 250 mV
Accuracy:
– Offset Voltage: ±500 μV (Maximum)
– Offset Voltage Drift: 0.5 μV/°C (Maximum)
Selectable Hysteresis:
– 2 mV, 4 mV, 8 mV
Active Quiescent Current: 135 μA (Maximum)
Selectable Disable Mode
– Disabled Quiescent Current: 3.5 μA (Maximum)
– Disabled Input Bias Current: 500 nA
(Maximum)
Open-Drain Output With Latch Mode Available
2 Applications
•
•
•
•
•
•
Overcurrent Protection
Computers
Servers
Telecom Equipment
Power Supplies
Battery Chargers
An open-drain alert output on the device can be
configured to operate in either a transparent mode
where the output status follows the input state, or in a
latched mode where the alert output is cleared when
the latch is cleared. The device response time setting
is selectable, which enables overcurrent alerts to be
issued in as fast as 10 µs.
The INA300 device operates from a single 2.7-V to
5.5-V supply, drawing a maximum supply current of
135 µA. The INA300 device is specified over the
extended operating temperature range of –40°C to
+125°C, and is available in WSON-10 and VSSOP-10
packages.
Device Information
PACKAGE(1)
PART NUMBER
INA300
(1)
BODY SIZE (NOM)
WSON (10)
2.00 mm × 2.00 mm
VSSOP (10)
3.00 mm × 3.00 mm
For all available packages, see the package option
addendum at the end of the data sheet.
2.7 V to 5.5 V
CBYPASS
0.1 µF
VS
INA300
RPull-up
10 k
Processor
Power Supply
(0 V to 36 V)
ENABLE
GPIO
LATCH
IN+
GPIO
+
ALERT
GPIO
CMP
IN
LIMIT
±
DAC
DELAY
Load
HYS
GND
RLIMIT
Typical Application Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings(1) .................................... 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Timing Requirements.................................................. 5
6.7 Typical Characteristics................................................ 6
7 Detailed Description......................................................10
7.1 Overview................................................................... 10
7.2 Functional Block Diagram......................................... 10
7.3 Feature Description...................................................10
7.4 Device Functional Modes..........................................18
8 Application and Implementation.................................. 22
8.1 Application Information............................................. 22
8.2 Typical Applications.................................................. 22
9 Power Supply Recommendations................................28
10 Layout...........................................................................29
10.1 Layout Guidelines................................................... 29
10.2 Layout Example...................................................... 29
11 Device and Documentation Support..........................31
11.1 Documentation Support.......................................... 31
11.2 Receiving Notification of Documentation Updates.. 31
11.3 Support Resources................................................. 31
11.4 Trademarks............................................................. 31
11.5 Electrostatic Discharge Caution.............................. 31
11.6 Glossary.................................................................. 31
12 Mechanical, Packaging, and Orderable
Information.................................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2016) to Revision C (June 2021)
Page
• Changed Figure 7-6 caption............................................................................................................................. 16
Changes from Revision A (March 2014) to Revision B (April 2016)
Page
• Changed data sheet title.....................................................................................................................................1
• Added VSSOP (DGS) package to data sheet.................................................................................................... 1
• Changed text in Description section for clarity....................................................................................................1
• Moved storage temperature from Handling Ratings table to Absolute Maximum Ratings table.........................4
• Changed Handling Ratings to ESD Ratings....................................................................................................... 4
• Added DGS data to Thermal Information table ..................................................................................................4
Changes from Revision * (February 2014) to Revision A (March 2014)
Page
• Made changes to product preview data sheet ................................................................................................... 1
2
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5 Pin Configuration and Functions
IN+
1
10 HYS
IN±
2
9
VS
LIMIT
3
8
GND
ENABLE
4
7
DELAY
ALERT
5
6
LATCH
Thermal
Pad
Figure 5-1. DSQ Package 10-Pin WSON Top View
HYS
IN+
1
10
IN±
2
9
VS
LIMIT
3
8
GND
ENABLE
4
7
DELAY
ALERT
5
6
LATCH
Figure 5-2. DGS Package 10-Pin VSSOP Top View
Table 5-1. Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
IN+
Analog input
Connect to supply side of shunt resistor.
2
IN–
Analog input
Connect to load side of shunt resistor.
3
LIMIT
Analog input
Alert threshold limit input.
See Setting The Current-Limit Threshold for details on setting limit threshold.
4
ENABLE
Digital input
Enable or disable selection input
5
ALERT
Digital output
6
LATCH
Digital input
Transparent or latch mode selection input.
7
DELAY
Digital input
Response time selection input.
8
GND
Analog
Ground
9
VS
Analog
Power supply, 2.7 V to 5.5 V.
10
HYS
Digital input
Thermal pad
—
Overlimit alert, active-low, open-drain output.
Hysteresis setting input.
See Selectable Hysteresis for hysteresis settings.
This pad can be connected to ground or left floating.
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6 Specifications
6.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage, VS
)(2)
Differential (VIN+) – (VIN–
MAX
UNIT
6
V
–40
40
Common-mode (3)
GND – 0.3
40
Analog input
LIMIT
GND – 0.3
(VS) + 0.3
V
Digital inputs
LATCH, DELAY, ENABLE, HYS
GND – 0.3
(VS) + 0.3
V
Analog inputs (IN+, IN–)
Alert output
GND – 0.3
6
V
–40
125
°C
150
°C
150
°C
Operating temperature
Junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
(3)
V
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
VIN+ and VIN– are the voltages at the IN+ and IN– terminals, respectively.
Input voltage may exceed the voltage shown if the current at that terminal is limited to 5 mA.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
UNIT
±2500
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VCM
Common-mode input voltage
VS
Operating supply voltage
NOM
2.7
5.5
100
Operating free-air temperature
UNIT
V
3.3
Delay setting
TA
MAX
12
V
µs
–40
125
°C
6.4 Thermal Information
INA300
THERMAL METRIC(1)
DGS (VSSOP)
UNIT
10 PINS
10 PINS
RθJA
Junction-to-ambient thermal resistance
63.5
169.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
79.5
59.1
°C/W
RθJB
Junction-to-board thermal resistance
33.9
89.6
°C/W
ψJT
Junction-to-top characterization parameter
7.8
8.5
°C/W
ψJB
Junction-to-board characterization parameter
34.3
88.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
7.5
n/a
°C/W
(1)
4
DSQ (WSON)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
at TA = 25°C, VSENSE = VIN+ – VIN– = 0 mV, VS = 3.3 V, VIN+ = 12 V, VLIMIT = 10 mV, and DELAY = 100 µs (unless otherwise
noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
VCM
Common-mode input voltage
VIN
Differential input voltage
VIN = VIN+ – VIN–
CMR
Common-mode rejection
VIN+ = 0 V to 36 V,
TA= –40°C to 125°C
VOS
Offset voltage, RTI(1)
0
36
V
0
250
mV
100
120
dB
VS = 3.3 V, DELAY = 100 μs
–75
–500
VS = +3.3 V, DELAY = 50 μs
–125
–500
VS = +3.3 V, DELAY = 10 μs(2)
–350
–650
μV
Offset voltage drift, RTI(1)
TA= –40°C to 125°C
0.1
0.5
μV/°C
PSR
Power-supply rejection ratio
VS = 2.7 V to 5.5 V, VIN+ = 12 V,
TA= –40°C to 125°C
75
150
μV/V
IB
Input bias current
IOS
Input offset current
dVOS/dT
ILIMIT
Limit threshold output current
Disable mode
5
10
0.05
0.5
±0.1
TA= 25°C
19.9
TA= –40°C to 125°C
20
19.85
μA
μA
20.1
20.15
μA
DIGITAL INPUT/OUTPUT
Delay = open, overdrive = 1 mV
tp
Alert propagation delay
10
Delay = GND, overdrive = 1 mV
50
Delay = VS, overdrive = 1 mV
HYS
Hysteresis
μs
100
HYS = open
2
HYS = GND
4
HYS = VS
8
Latch, enable
mV
1.4
6
VS – 0.5
6
Latch, enable
0
0.4
Delay, hysteresis
0
0.5
VIH
High-level input voltage
VIL
Low-level input voltage
VOL
Alert low-level output voltage
IOL = 3 mA
50
400
mV
ALERT terminal leakage input current
VOH = 3.3 V
0.1
1
μA
Digital leakage input current
0 ≤ VIN ≤ VS
1
2
μA
115
135
Delay, hysteresis
V
V
POWER SUPPLY
VSENSE = 0 mV, TA = 25°C
IQ
(1)
(2)
Quiescent current
TA = –40°C to 125°C
150
VSENSE = 0 mV, disable mode,
HYS = 2 mV
2
μA
3.5
RTI = referred-to-input.
Absolute-maximum values are tested with the threshold limit set using the corresponding noise adjustment factor (NAF) value. See
Section 7.3.7 for additional information on applying the NAF value.
6.6 Timing Requirements
MIN
Start-up time
NOM
MAX
UNIT
1
ms
ten
Enable time
300
µs
tdis
Disable time
20
µs
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6.7 Typical Characteristics
Offset Voltage (µV)
50
0
25
-25
-50
-75
-100
-125
-150
-175
-200
-225
-250
-275
-300
200
150
100
0
50
-50
-100
-150
-200
-250
-300
-350
-400
-450
-500
-550
-600
Population
Population
at TA = 25°C, VS = 3.3 V, VIN+ = 12 V, alert pull-up resistor = 10 kΩ, and Delay = 100 µs (unless otherwise noted)
Offset Voltage (µV)
C001
C002
Delay = 10 µs
Delay = 50 µs
Figure 6-1. Input Offset Voltage
Figure 6-2. Input Offset Voltage
0
Population
Offset Voltage (µV)
±100
±200
±300
±400
Delay = 100 µs
Delay = 50 µs
Delay = 10 µs
±600
50
25
0
-25
-50
-75
-100
-125
-150
-175
-200
±500
2.5
3
3.5
4
4.5
5
Supply Voltage (V)
Offset Voltage (µV)
C003
Delay = 100 µs
5.5
C004
Figure 6-4. Input Offset Voltage vs Supply Voltage
Figure 6-3. Input Offset Voltage
0
Common-Mode Rejection Ratio (µV/V)
2.5
±50
Offset Voltage (µV)
±100
±150
±200
±250
±300
±350
±400
100 us
50 us
10 us
±450
±500
±50
±25
0
25
50
75
Temperature (ƒC)
100
125
150
1
0.5
0
±0.5
±1
±1.5
±2
±2.5
±50
±25
0
25
50
75
Temperature (°C)
C005
Figure 6-5. Input Offset Voltage vs Temperature
6
2
1.5
100
125
150
C006
Figure 6-6. Common-Mode Rejection Ratio vs
Temperature
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6
10
8
6
Input Bias Current (nA)
Input Bias Current (µA)
5
4
3
2
1
4
2
0
-2
-4
-6
0
-8
-10
±1
0
5
10
15
20
25
30
35
Common-Mode Voltage (V)
0
40
Figure 6-7. Input Bias Current vs Common-Mode
Voltage (Enabled)
15
20
25
30
35
40
C008
Figure 6-8. Input Bias Current vs Common-Mode
Voltage (Disabled)
250
7
200
Input Bias Current (nA)
Input Bias Current (µA)
10
Common-Mode Voltage (V)
6.5
6
5.5
5
4.5
4
150
100
IB50
0
3.5
3
IB+
±50
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
±50
±25
0
140
50
Quiescent Current (µA)
60
100
80
50
75
100
125
150
C010
Figure 6-10. Input Bias Current vs Temperature
(Disabled)
160
120
25
Temperature (ƒC)
C009
Figure 6-9. Input Bias Current vs Temperature
(Enabled)
Quiescent Current (µA)
5
C007
40
30
20
10
60
0
40
2.3
2.8
3.3
3.8
4.3
Supply Voltage (V)
4.8
5.3
5.8
2.3
Figure 6-11. Quiescent Current vs Supply Voltage
(Enabled)
2.8
3.3
3.8
4.3
Supply Voltage (V)
C011
4.8
5.3
5.8
C012
Figure 6-12. Quiescent Current vs Supply Voltage
(Disabled)
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6
180
160
Quiescent Current (µA)
Quiescent Current (µA)
5
140
120
100
80
60
Vs = 5.5V
40
3
2
Vs = 5.5V
Vs = 3.3V
Vs = 2.7V
1
Vs = 3.3V
20
4
Vs = 2.7V
0
0
±50
0
±25
25
50
75
100
125
150
Temperature (ƒC)
Figure 6-13. Quiescent Current vs Temperature
(Enabled)
200
170
160
25
50
75
100
125
150
Temperature (ƒC)
C014
Figure 6-14. Quiescent Current vs Temperature
(Disabled)
LL
9
ZL, LZ, HL, LH
Quiescent Current (µA)
Quiescent Current (µA)
180
0
±25
10
ZZ
ZL, LZ
ZH, HZ
LL
LH, HL
HH
190
±50
C013
150
140
130
120
8
ZZ, ZH, HZ, HH
7
6
5
4
3
2
110
100
1
2.5
3
3.5
4
4.5
5
5.5
Supply Voltage (V)
Z = Floating
HYS – DELAY
2.5
3
3.5
L = Low
H = High
4
4.5
5
5.5
Supply Voltage (V)
C025
Z = Floating
HYS – DELAY
C026
L = Low
H = High
Figure 6-15. Quiescent Current vs HYS and DELAY Figure 6-16. Quiescent Current vs HYS and DELAY
Settings (Enabled)
Settings (Disabled)
20.5
10
9
Hysteresis (mV)
20.25
Limit Current (µA)
8 mV Hysteresis
8
20
19.75
7
6
4 mV Hysteresis
5
4
3
2 mV Hysteresis
2
1
19.5
0
±50
±25
0
25
50
75
Temperature (ƒC)
100
125
150
Figure 6-17. Limit Current Source vs Temperature
8
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C015
150
C016
Figure 6-18. Hysteresis vs Temperature
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Enable (1 V/div)
Alert (1 V/div)
Alert (1 V/div)
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Time (25 µs/div)
Time (100 µs/div)
C017
C018
Figure 6-19. Alert Step Response
Latch (1 V/div)
Alert (1 V/div)
Figure 6-20. Alert Response (Disable to Enable)
0
5
10
15
20
Time (µs)
25
30
C019
Figure 6-21. Alert Response (Latch Mode to Transparent Mode)
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7 Detailed Description
7.1 Overview
The INA300 INA300 is a 36-V, common-mode comparator designed for overcurrent protection applications. To
reduce the system component count, this device combines the current-sense amplifier and threshold comparison
into a single product for the overcurrent detection function. Programming this comparison threshold is configured
through a single external resistor, which simplifies the current design while allowing for easy adjustments
to the threshold when needed. The threshold setting resistor value is selected based on an internal 20-µA
current source to achieve a corresponding signal to the voltage that develops across the current-sensing or
current-shunt resistor in series with the monitored load current.
The device is designed to accommodate a range of application requirements, including common-mode voltage,
noise thresholds, and signal ranges. A wide signal threshold range reaching up to 250 mV is available to
accommodate both power-sensitive applications requiring small dissipations across a current sense resistor and
larger current-sensing resistors used in lower current applications.
Additional features available with the INA300 INA300 device include a disable mode for reducing the current
consumption of the device to below 10 µA, an output mode selector to enable a latched or transparent alert
output, and a selectable hysteresis value and alert response delay.
The wide signal range of the device is further enhanced with an adjustable hysteresis value to adjust the
characteristics of the comparator, which allows for better accommodation of the full input range. The selectable
alert response delays present in the INA300 INA300 device assist in optimizing device operation to account for
the system noise levels and operating characteristics required from this device. Longer delay settings allow for
added rejection of system noise, thus reducing the potential for false alerts resulting from noise spikes that can
occur in high-speed comparators.
7.2 Functional Block Diagram
VS
VPULL-UP
INA300-Q1
Level
Detection
Power Supply
(0 V to 36 V)
HYS
DELAY
IN+
ALERT
+
Control
Logic
IN±
Load
LATCH
LIMIT
GND
ENABLE
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7.3 Feature Description
7.3.1 Selecting a Current-Sensing Resistor
The device measures the differential voltage developed across a resistor when current flows through it to
determine if the monitored current exceeds a defined limit. This resistor is referred to as a current-sensing
10
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resistor or a current-shunt resistor, with each term used interchangeably. The flexible design of the device allows
for measuring a wide differential input signal range across this current-sensing resistor, which can extend up to
250 mV.
Selecting the value of this current-sensing resistor is based primarily on two factors: the required accuracy of the
current measurement and the allowable power dissipation across the current-sensing resistor. Larger voltages
developed across this resistor allow more accurate measurements. This large signal accuracy improvement
results from the fixed internal amplifier errors that are dominated by the inherent input offset voltage of the
device. When the input signal decreases, these fixed internal amplifier errors become a larger portion of the
measurement and increase the uncertainty in the measurement accuracy. When the input signal increases, the
measurement uncertainty is reduced because the fixed errors are a smaller percentage of measured signal.
A system design trade-off for improving the measurement accuracy using larger input signals is the increase
in power across the current-sensing resistor. Increasing the value of the current-shunt resistor increases the
differential voltage developed across the resistor when current passes through the component. This increase in
voltage across the resistor increases the power that the resistor must be able to dissipate. Decreasing the value
of the current-shunt resistor value reduces the power dissipation requirements of the resistor, but increases the
measurement errors resulting from the decreased input signal. Selecting the optimal value for the shunt resistor
requires factoring both the accuracy requirement for the specific application and the allowable power dissipation
of this component.
An increasing number of low ohmic-value resistors are becoming available with values as low as 200 µΩ, with
power dissipations of up to 5 W that enable large currents to be monitored with sensing resistors.
7.3.1.1 Selecting a Current-Sensing Resistor: Example
In this example, the trade-offs involved in selecting a current-sensing resistor are discussed. This example
requires a 5% measurement accuracy for detecting a 10-A overcurrent event at a 50-µs delay setting where
only 250 mW is allowable for the dissipation across the current-sensing resistor at the full-scale current level.
Although the maximum power dissipation is defined as 250 mW, a lower dissipation is preferred to improve
system efficiency. Some initial assumptions are made that are used in this example: the limit setting resistor,
RLIMIT, is a 1% component and the maximum tolerance specification for the internal threshold setting current
source, 0.5%, is used. Given the total error budget of 5%, up to 3.5% of error is available to be attributed to the
internal offset of the device.
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As shown in Table 7-1, the maximum value calculated for the current-sensing resistor with these requirements
is 2.5 mΩ. Although this value satisfies the maximum power dissipation requirement of 250 mW, headroom is
available from the 5% maximum total error to reduce the value of the current-sensing resistor and reduce the
power dissipation further. Selecting a 1.5-mΩ, current-sensing resistor value offers a tradeoff for reducing the
power dissipation in this scenario by approximately 40%, while still remaining within the defined accuracy region.
Table 7-1. Calculating the Current-Sensing Resistor, RSENSE
PARAMETER
EQUATION
VALUE
UNIT
Maximum measurement error
5%
IMAX
Maximum current
10
A
PRSENSE
Maximum allowable RSENSE power
dissipation
RSENSE × IMAX 2
250
mW
Initial error
RLIMIT + ILIMIT tolerances
RSENSE_MAX
Maximum sensing resistor value
PRSENSE / IMAX 2
1.5%
VSENSE_MAX
Input sense voltage
VOS Error
Offset voltage error
Error_Available
Maximum allowable offset error
Maximum Error – Initial Error
3.5%
VSENSE_MIN
Minimum input sense voltage
VOS / (Error_Available / 100)
14.3
RSENSE_MIN
Minimum sensing resistor value
VSENSE_MIN / IMAX
1.43
mΩ
PRSENSE_MIN
Minimum power dissipation
RSENSE_MIN × IMAX 2
143
mW
2.5
mΩ
RSENSE_MAX × IMAX
25
mV
(VOS / VSENSE_MAX) × 100
2%
mV
7.3.2 Setting The Current-Limit Threshold
The device determines if an overcurrent event is present by comparing the measured differential voltage
developed across the current-sensing resistor to the corresponding signal programmed at the LIMIT terminal.
The threshold voltage for the LIMIT terminal can be set using a resistor or an external voltage source.
7.3.2.1 Resistor-Controlled Current Limit
The typical approach for setting the limit threshold voltage is to connect a resistor from the LIMIT terminal to
ground. The value of this resistor, RLIMIT, is chosen to create a corresponding voltage at the LIMIT terminal
equivalent to the voltage, VTRIP, developed by the load current flowing through the current-sensing resistor. An
internal 20-µA current source is present at the LIMIT terminal that creates the corresponding voltage depending
on the value of RLIMIT. In the equations from Table 7-2, VTRIP represents the overcurrent threshold the device
is programmed to monitor for and VLIMIT is the programmed signal set to detect the VTRIP level. The term noise
adjustment factor (NAF) is included in the VLIMIT equation for the 10-µs delay setting. This value is equal to
500 µV and adjusts the operating point for the internal noise in this delay setting. The 50-µs and 100-µs delay
settings do not use the NAF term in calculating the VLIMIT threshold. See Noise Adjustment Factor (NAF) for
more details on the noise adjustment factor.
In Table 7-2, the process for calculating the required value for RLIMIT to set the appropriate threshold voltage,
VLIMIT, is shown. This calculation is based on the 10-µs delay setting so the NAF term is included in the
calculation. For a delay setting of 50 µs or 100 µs, the NAF term is omitted.
Table 7-2. Calculating the Limit Threshold Setting Resistor, RLIMIT
PARAMETER
EQUATION
VTRIP
Desired current trip value
VLIMIT
Programmed threshold limit voltage
VLIMIT
(1)
RLIMIT (1)
RLIMIT
(1)
(1)
ILOAD × RSENSE
VLIMIT = VTRIP
Threshold voltage
(ILIMIT × RLIMIT) – NAF
Threshold limit setting resistor
(VLIMIT + NAF) / ILIMIT
Limit setting resistor
(VLIMIT + 500 µV) / 20 µA
NAF is used with the 10-µs delay setting. NAF can be omitted in the RLIMIT calculation for the 50-µs and 100-µs delay settings.
TI recommends using NAF in calculating the value for VLIMIT and RLIMIT at the 10-µs delay setting. Removing
NAF from the VLIMIT and RLIMIT calculation at the 10-µs delay setting lowers the trigger point of the alert output.
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Lowering the trigger point results in the device issuing an overcurrent alert prior to reaching the corresponding
VTRIP threshold. The averaging effect included with the 50-µs and 100-µs delay settings inherently eliminates the
effect internal noise has on the threshold voltage.
7.3.2.2 Voltage Source-Controlled Current Limit
The second method for setting the limit voltage is to connect the LIMIT terminal to a programmable DAC
(digital-to-analog converter) or other external voltage source. The benefit of this method is the ability to adjust
the current limit to account for different threshold voltages that are used for different system operating conditions.
For example, this method can be used in a system that has one current-limit threshold level that must be
monitored during the power-up sequence but different thresholds must be monitored during other system
operating modes.
In Table 7-3, VTRIP represents the overcurrent threshold the device is programmed to monitor for and VSOURCE
is the programmed signal set to detect the VTRIP level. NAF is included in the VSOURCE equation for the 10-µs
delay setting. This value equals 500 µV and is adjusts the operating point for the noise in the delay setting. The
50-µs and 100-µs delay settings do not use the NAF term in calculating the VSOURCE threshold. For these delay
settings, the NAF term is omitted. See the Noise Adjustment Factor (NAF) section for more details on the noise
adjustment factor.
Table 7-3. Calculating the Limit Threshold Voltage Source, VSOURCE
PARAMETER
EQUATION
VTRIP
Desired current trip value
VSOURCE (1)
Programmed threshold limit voltage
VSOURCE (1)
Programmed signal set to detect the VTRIP level
(1)
ILOAD × RSENSE
VTRIP + NAF
VTRIP + 500 µV
NAF is used with the 10-µs delay setting. NAF can be omitted in the VSOURCE calculation for the 50-µs and 100-µs delay settings.
TI recommends using NAF in calculating the value for VSOURCE at the 10-µs delay setting. Removing NAF from
the VSOURCE calculation at the 10-µs delay setting lowers the trigger point of the alert output. Lowering the
trigger point results in the device issuing an overcurrent alert prior to reaching the corresponding VTRIP threshold.
The averaging effect included with the 50-µs and 100-µs delay settings inherently eliminates the effect internal
noise has on the threshold voltage.
7.3.3 Delay Setting
The device response time for overcurrent events is adjustable based on the DELAY terminal setting. Three
response time settings are available, ranging from 10 µs to 100 µs. The primary purpose for the three different
delay settings is to offer a trade-off between a faster alert response and a more precise overcurrent threshold
level detection.
The device has a 10-µs internal comparison window. This single comparison window is the fundamental time
unit used for all three delay settings. For the 10-µs delay setting, the device compares the average of the
input signal during the 10-µs comparison window to the threshold limit programmed at the LIMIT terminal. If the
averaged input signal exceeds the threshold at the end of the 10-µs comparison window, the output alert triggers
and pulls the ALERT terminal low. However, if the averaged input does not exceed the threshold at the end of
the 10-µs comparison window, there is no change in the output alert status, which remains high to indicate that
no overcurrent event is detected.
For the 50-µs delay setting, there must be five consecutive 10-µs comparison windows that result in an average
input signal exceeding the threshold limit in order for the output alert to trigger and pull the ALERT terminal low.
If any single 10-µs comparison window fails to detect an overcurrent condition before reaching five consecutive
overcurrent comparisons, the internal counter is reset and no output alert is issued. With the internal counter
reset, a new group of five consecutive 10-µs comparison windows of overcurrent conditions are required in order
to trigger the alert and pull the ALERT terminal low.
The 100-µs delay setting operates in the same manner as the 50-µs method, but instead requires ten
consecutive 10-µs comparison windows with an input signal exceeding the threshold limit to issue an output
alert and pull the ALERT terminal low.
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Requiring multiple consecutive overcurrent detections aides significantly in reducing the likelihood of system
noise causing false alerts, which can be detrimental to critical system operations. However, by enabling an alert
window equal to the comparison window of 10 µs, the device still has the flexibility to be used in fast overcurrent
detection applications that require quick responses to rapidly changing system operating characteristics.
In Figure 7-1, the device alert output response is shown for a 10-µs delay setting and a 50-µs delay setting
based on the same input signal condition. The initial increase of the input signal, VIN, above the VLIMIT level
remains above the limit for approximately 30 µs. With the device set to the 10-µs delay setting, the overcurrent
condition is detected and the alert output terminal is pulled low approximately 10 µs later. With the device set to
the 50-µs delay setting, an alert is not issued because five consecutive 10-µs overcurrent measurements are not
detected. With the input signal only being over the limit for 30 µs rather than the corresponding 50 µs needed
for this delay setting, the device does not issue an alert under this condition. For the second instance where
VIN rises above the VLIMIT threshold, the input remains above the limit for more than five consecutive 10-µs
measurements, indicating an overcurrent condition and the alert output terminal is pulled low.
Transparent Mode
VLIMIT
VIN
(VIN+ - VIN-)
0V
ALERT
(Delay = 10 µs)
10 µs
10 µs
10 µs
10 µs
10 µs
10 µs
ALERT
(Delay = 50 µs)
50 µs
50 µs
50 µs
No Alert
No Alert
10 µs
Figure 7-1. DELAY Terminal Settings
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As discussed previously, there are three different available delay settings that are configured based on the signal
connected to the DELAY terminal, as shown in Figure 7-2 and Table 7-4. The DELAY terminal must be either
connected directly to ground, directly to supply, or left completely floating. Additional external resistors must not
be connected to this terminal. If a resistance is required by the application to be placed in series with either the
supply or ground connection to the DELAY terminal, this resistance must be limited to 1 kΩ so as to not conflict
with the internal level-detection circuitry.
VS
DELAY
GND
Figure 7-2. Delay Response
Table 7-4. Delay Settings
DELAY
ALERT DELAY (µs)
Open or floating
10
GND
50
VS
100
7.3.4 Alert Timing Response
The device has a 10-µs internal comparison window where the input signal is measured to compare to the limit
threshold voltage. This window continuously runs internal to the device without any external indicator or control.
A comparison is made at the completion of each 10-µs comparison window to determine if the averaged input
over the comparison window exceeds the limit threshold, thus indicating if an overcurrent event has occurred.
Limit Threshold
Alert
(1 V/div)
Input Voltage
(5 mV/div)
This comparison window is not synchronized with the input signal so there is an unknown timing component
present. With this free-running internal timing window, an overcurrent event can occur anywhere within the 10-µs
comparison window. This condition causes a variation in the amount of time before the alert appears at the
output because the comparison is always made at the end of the 10-µs comparison window. Figure 7-3 shows
the variation in time between when the input signal rises above the threshold voltage and when a change at the
alert output terminal occurs.
Time (2 µs/div)
C020
Figure 7-3. 10-µs Alert Response Window
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Input Voltage
(5 mV/div)
Input Voltage
(5 mV/div)
The delay shown in Figure 7-3 represents the response time of the device with a 10-µs delay setting. With a
50-µs delay setting, an additional 40 µs is added to the timing response, as shown in Figure 7-4. A 100-µs delay
setting adds 90 µs to the response time, as shown in Figure 7-5.
Limit Threshold
Alert
(1 V/div)
Alert
(1 V/div)
Limit Threshold
Time (10 µs/div)
Time (5 µs/div)
C021
Figure 7-4. 50-µs Alert Response Window
C022
Figure 7-5. 100-µs Alert Response Window
7.3.5 Selectable Hysteresis
Device hysteresis is adjustable based on the setting at the hysteresis (HYS) terminal. The smallest setting for
hysteresis on the device, 2 mV, is enabled by leaving the HYS terminal open and floating. A 4-mV hysteresis is
set by connecting the HYS terminal to ground; connecting this terminal to the supply voltage sets the hysteresis
to 8 mV, as shown in Figure 7-6. The HYS terminal must be either connected directly to ground, directly to
supply, or left completely floating. Additional external resistors must not be connected to this terminal. If a
resistance is required by the application to be placed in series with either the supply or ground connections to
the HYS terminal, this resistance must be limited to 1 kΩ so as to not conflict with the internal level-detection
circuitry.
VS
HYS
GND
Figure 7-6. Hysteresis
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The wide dynamic input range of the INA300 INA300 necessitates an adjustable hysteresis to ensure that the
device can be appropriately configured based on the specific operating conditions and application requirements.
Figure 7-7 illustrates the transition locations for the ALERT terminal based on where the input signal, VIN, is
measured relative the limit threshold, VLIMIT. The corresponding hysteresis levels and physical terminal settings
for the device are shown in Table 7-5.
VOUT
Alert
Output
VIN
VLIMIT - Hysteresis
VLIMIT
Figure 7-7. Typical Comparator Hysteresis
Table 7-5. Hysteresis Settings
HYSTERESIS
HYSTERESIS SETTING
Float
2 mV
GND
4 mV
VS
8 mV
7.3.6 Alert Output
The device ALERT terminal is an active-low, open-drain output. This output is designed to be pulled low when
the input conditions are detected as out-of-range. This open-drain output pin is recommended to include a
10-kΩ, pull-up resistor to the supply voltage. This open-drain terminal can be pulled up to a voltage beyond the
supply voltage, VS, but must not exceed 5.5 V.
7.3.7 Noise Adjustment Factor (NAF)
The device is a high-speed, low-noise comparator that is designed to alert when the measured input signal
exceeds the programmed limit level. Internal noise in the device couples into the measurement and can result
in alerts being issued prior to the input signal exceeding the voltage level present at the LIMIT terminal. This
known internal noise component effects the input signal measurement by causing a consistent shift in the device
internal offset, resulting in a shifted trip threshold. NAF adjusts the VLIMIT setting to account for this internal shift,
thus allowing for a more precise level detection of the measured current.
The NAF value is based on the noise contribution on the measurement at the 10-µs delay setting. This value is
equal to 500 µV and is applied in the calculation to adjust the VLIMIT threshold level to allow for a more accurate
alert trip point. The NAF term is only applied in the VLIMIT calculation at the 10-µs delay setting. The averaging
effect included with the 50-µs and 100-µs delay settings inherently eliminates the effect internal noise has on the
threshold voltage. The NAF term can be omitted from the RLIMIT calculation at the 10-µs delay setting with the
effect of a lower trigger point of the alert output. Lowering the trigger point results in an overcurrent alert prior to
reaching the corresponding VTRIP threshold.
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7.4 Device Functional Modes
7.4.1 Alert Mode
The device has two output operating modes that are selected based on the LATCH terminal setting: transparent
mode and latch mode. These modes change how the ALERT terminal responds to the changing input signal
conditions.
7.4.1.1 Transparent Output Mode
The device is set to transparent mode when the LATCH terminal is pulled low, thus allowing the output alert
state to change and follow the input signal with respect to the programmed alert threshold. For example, when
the differential input signal rises above the alert threshold, the alert output terminal is pulled low. When the
differential input signal drops below the alert threshold for 10 µs, the output returns to the default high output
state. A common implementation using the device in transparent mode is to connect the ALERT terminal to a
hardware interrupt input on a controller. As soon as an overcurrent condition is detected in the device and the
ALERT terminal is pulled low, the controller interrupt terminal detects the output state change and can begin
making changes to the system operation needed to address the overcurrent condition.
7.4.1.2 Latch Output Mode
Some applications do not have the functionality available to continuously monitor the state of the output ALERT
terminal to detect an overcurrent condition. A typical example of this application is a system that is only able to
poll the ALERT terminal state periodically to determine if the system is functioning correctly. If the device is set to
transparent mode in this type of application, missing the change in state of the ALERT terminal is possible when
ALERT is pulled low to indicate an out-of-range event if the out-of-range condition does not appear during one of
these periodic polling events.
Latch mode is specifically intended to accommodate these applications. As shown in Table 7-6, the device
is placed in latch mode by setting the voltage on the LATCH terminal to a logic high level. The difference
between latch mode and transparent mode is how the alert output responds when an overcurrent event ends.
In transparent mode, when the differential input signal drops below the limit threshold level for 10 µs, the output
state returns to the default high setting to indicate that the overcurrent event had ended.
In latch mode, when an overlimit condition is detected and the ALERT terminal is pulled low, the ALERT terminal
does not return to the default high level when the differential input signal drops below the alert threshold level for
10 µs. To clear the alert the LATCH terminal must be pulled low for at least 20 µs. Pulling the LATCH terminal
low allows the ALERT terminal to return to the default high level, provided that the differential input signal has
dropped below the alert threshold. If the input signal is still above the threshold limit when the LATCH terminal
is pulled low, the ALERT terminal remains low. When the alert condition is detected by the system controller (the
LATCH terminal) can be set back to high in order to place the device back in latch mode.
Table 7-6. Output Mode Settings
18
OUTPUT MODE
LATCH TERMINAL SETTING
Transparent mode
LATCH = low
Latch mode
LATCH = high
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The latch and transparent modes are represented in Figure 7-8. In Figure 7-8 when VIN drops back below the
VLIMIT threshold for the first time, the LATCH terminal is pulled high. With the LATCH terminal pulled high, the
device is set to latch mode so that the alert output state does not return high when the input signal drops below
the VLIMIT threshold. Only when the LATCH terminal is pulled low does the ALERT terminal return to the default
high level, indicating that the input signal is below the limit threshold. When the input signal drops below the limit
threshold for the second time, the LATCH terminal is already pulled low. The device is set to transparent mode at
this point and the ALERT terminal is pulled back high when the input signal drops below the alert threshold.
VLIMIT
VIN
(VIN+ - VIN-)
0V
ALERT
LATCH
Figure 7-8. Transparent vs Latch Mode
7.4.2 Disable Mode
The INA300 INA300 device has an ENABLE terminal that allows the device to be placed into an active enabled
state or a low-power disabled state where less than 10 µA is consumed from all terminals. This disable state
allows the device to be used in applications where low current consumption is required to extend battery
life where constant monitoring is not required. The INA300 device requires approximately 20 µs to enter the
low-power state when the ENABLE terminal transitions from high to low, as shown in Table 7-7. To return to the
enabled active state, the INA300 device requires approximately 300 µs to return to normal operation when the
ENABLE terminal transitions from low to high, taking the device out of the low-power state.
Table 7-7. Enable and Disable Mode Settings
ENABLE MODE
ENABLE TERMINAL SETTING
Disable mode
ENABLE = low
Enable mode
ENABLE = high
The internal counter that determines if the necessary consecutive 10-µs window comparison alert conditions are
reached for the 50-µs and 100-µs delay setting is reset when the device is put into a disabled state. When the
device is re-enabled, the counter restarts.
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7.4.3 Input Filtering
External system noise can have a significant effect in the ability of a comparator to accurately measure and
detect whether input signals exceed the reference threshold levels, indicating an overrange condition. The
device is susceptible to external noise, although the 50-µs and 100-µs delay settings are can mitigate the impact
of noise based on the effective averaging achieved in these modes. The obvious effect that external noise can
have on the operation of a comparator is to cause a false alert condition. If a comparator detects a large noise
transient coupled into the signal, the device can interpret this transient as an overrange condition.
External filtering can help reduce the amount of noise that reaches the comparator inputs, and can reduce the
likelihood of a false alert from occurring. The tradeoff to adding this noise filter is increased comparator response
time, because of the input signal being filtered as well as the noise. Figure 7-9 shows the implementation of an
input filter for the device.
+2.7 V to 5.5 V
CBYPASS
0.1 µF
INA300-Q1
VS
Power Supply
(0 V to 36 V)
RPull-up
10 k
ENABLE
LATCH
IN+
+
RFILTER
”100
ALERT
CMP
CFILTER
IN±
LIMIT
±
DELAY
Load
HYS
GND
RLIMIT
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Figure 7-9. Input Filter
Limiting the amount of input resistance used in this filter is important because this resistance can have a
significant effect on the input signal that reaches the device input pins resulting from the device input bias
currents. A typical system implementation involves placing the current-sensing resistor near the device so the
traces are short and the trace impedance is small. This layout helps reduce the ability of coupling additional
noise into the measurement. Under these conditions, the characteristics of the input bias currents have minimal
effect on device performance.
As shown in Figure 7-10, the input bias currents increase in opposite directions when the differential input
voltage increases. This increase results from the design of the device, which allows common-mode input
voltages to far exceed the device supply voltage range. With input filter resistors now placed in series with
these unequal input bias currents, there are unequal voltage drops developed across the input resistors. The
difference between the two drops appears as an added signal that (in this case) subtracts from the voltage
developed across the current-sensing resistor, reducing the signal that reaches the device input terminals.
Smaller value input resistors reduce this effect of signal attenuation to allow for a more accurate measurement.
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30
Input Bias Current (µA)
25
20
IB+
15
10
5
0
IB-
±5
±10
±15
±20
0
50
100
150
200
250
Differential Input Voltage (mV)
C027
Figure 7-10. Input Bias Current vs Differential Input Voltage
For example, with a differential voltage of 10 mV developed across a current-sensing resistor and using 100-Ω
resistors, the differential signal that reaches the device is 9.8 mV. A measurement error of 2% is created as a
result of the external input filter resistors. Using 10-Ω input filter resistors instead of the 100-Ω resistors reduces
this added error from 2% to 0.2%.
7.4.4 Using the INA300 INA300 With Common-Mode Transients Above 36 V
With a small amount of additional circuitry, the device can be used in circuits subject to transients higher than
36 V. Use only zener diodes or zener-type transient absorbers (sometimes referred to as Transzorbs). Any
other type of transient absorber has an unacceptable time delay. Start by adding a pair of resistors, as shown
in Figure 7-11, as a working impedance for the zener diode. Keeping these resistors as small as possible is
best, preferably 100 Ω or less. Larger values can be used with an additional error induced resulting from a
reduced signal that reaches the device input terminals. Because this circuit limits only short-term transients,
many applications are satisfied with a 100-Ω resistor along with conventional zener diodes of the lowest power
rating available. This combination uses the least amount of board space. These diodes can be found in SOT-523
or SOD-523 packages.
+2.7 V to 5.5 V
CBYPASS
0.1 µF
TI Device
VS
Power Supply
(0 V to 36 V)
RPull-up
10 k
ENABLE
LATCH
IN+
+
RPROTECT
≤100 Ω
CMP
ALERT
IN–
LIMIT
–
DELAY
Load
HYS
GND
RLIMIT
Figure 7-11. Transient Protection
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The INA300 INA300 is designed to enable configuration for detecting overcurrent conditions in an application.
This device is individually targeted towards overcurrent detection of a single threshold. However, this device can
be paired with additional devices and circuitry to create more complex monitoring functional blocks.
8.2 Typical Applications
8.2.1 Unidirectional Operation
2.7 V to 5.5 V
CBYPASS
0.1 F
VS
TI Device
Power Supply
(0 V to 36 V)
RPULL-UP
10 k
Processor
ENABLE
GPIO
LATCH
IN+
GPIO
+
CMP
ALERT
GPIO
IN–
LIMIT
–
DAC
DELAY
Load
HYS
GND
RLIMIT
Figure 8-1. Unidirectional Application Schematic
8.2.1.1 Design Requirements
The INA300 device measures current through a resistive shunt with current flowing in one direction, enabling
detection of an overcurrent event only when the differential input voltage exceeds the threshold limit.
8.2.1.2 Detailed Design Procedure
Figure 8-1 shows the basic connections of the INA300 device. The input terminals, IN+ and IN–, must be
connected as closely as possible to the current-sensing resistor to minimize any resistance in series with
the shunt resistance. Additional resistance between the current-sensing resistor and input terminals can result
in errors in the measurement. When input current flows through this external input resistance, the voltage
developed across the shunt resistor can differ from the voltage reaching the input terminals.
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8.2.1.3 Application Curve
Limit Threshold
Alert
(1 V/div)
Input Voltage
(5 mV/div)
Figure 8-2 shows the alert response transitioning from a high to a low state following the input signal exceeding
the limit threshold voltage. The time required for the output to respond varies as a result of when the input signal
crosses the threshold limit voltage relative to where in the continuous running internal 10-µs comparison window
the overrange condition occurs. In Figure 8-2, the output response varies from roughly 2 µs to approximately
12 µs when the input exceeds the threshold level. This variance is a result of where in the 10-µs comparison
window the overrange event occurs. If the overrange event occurs late in the 10-µs comparison window and
is large enough to average the entire window measurement up above the threshold level, the alert appears to
respond very quickly. If the alert occurs late in the 10-µs comparison window and is not large enough to average
the entire window measurement up above the threshold level, the alert does not appear until the next 10-µs
comparison window completes, assuming the input signal remains above the threshold for the entire duration.
Time (2 µs/div)
C020
Figure 8-2. Alert Response
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8.2.2 Bidirectional Operation
CBYPASS
0.1 µF
+2.7 V to 5.5 V
RPull-up
10 k
VS
IN+
Power Supply
(0 V to 36 V)
IN-
+
OCP+
CMP
LIMIT
GND
Output
CBYPASS
0.1 µF
Current
+2.7 V to 5.5 V
RPull-up
10 k
VS
IN+
Load
IN-
+
CMP
OCP-
LIMIT
GND
Figure 8-3. Bidirectional Application
8.2.2.1 Design Requirements
Although the INA300 device is only able to measure current through a current-sensing resistor flowing in one
direction, a second INA300 INA300 device can be used to create a bidirectional monitor.
8.2.2.2 Detailed Design Procedure
With the input terminals of a second INA300 device reversed across the same current-sensing resistor, the
second INA300 device is now able to detect current flowing in the other direction relative to the first device, as
shown in Figure 8-3. The outputs of each INA300 device connect to an AND gate to detect if either of the limit
threshold levels are exceeded. The output of the AND gate is high if neither overcurrent limit thresholds are
exceeded. A low output state of the AND gate indicates that either the positive overcurrent limit or the negative
overcurrent limit are surpassed.
Table 8-1. Bidirectional Overcurrent Output Status
24
OCP STATUS
OUTPUT
OCP+
0
OCP–
0
No OCP
1
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8.2.2.3 Application Curve
Input
(5 mV/div)
Output
(1 V/div)
Figure 8-4 illustrates two INA300 INA300 devices being used in a bidirectional configuration and an output
control circuit to detect if one of the two alerts is exceeded.
Positive Limit
0V
Negtive Limit
Time (5 ms/div)
C024
Figure 8-4. Bidirectional Application Curve
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8.2.3 Window Comparator
CBYPASS
0.1µF
+2.7 V to 5.5 V
RPull-up
10 k
VS
IN+
IN-
Power Supply
(0 V to 36 V)
+
OCP+
CMP
LIMIT
GND
Output
CBYPASS
0.1 µF
+2.7 V to 5.5 V
RPull-up
10 k
VS
IN+
Load
IN-
+
CMP
OCP-
LIMIT
GND
Figure 8-5. Window Comparator Application
8.2.3.1 Design Requirements
The INA300 device can be used to create a window comparator function, detecting whether the current being
monitored is within a programmed range or has fallen outside of the expected operating region.
8.2.3.2 Detailed Design Procedure
Figure 8-5 shows how the window comparator function is setup using two INA300 devices. The input terminals
of each INA300 device are connected to the same current-sensing resistor. The limit threshold for the top device
is set to the upper limit of the window range. The bottom device limit threshold is set to the desired lower limit of
the range. With a logic inverter placed at the output of the device monitoring the lower limit, the OCP– signal is
high when the input signal is above the lower limit threshold. The OCP+ signal is high when the input signal is
below the upper limit threshold. A high value at the output (output of the AND gate) indicates that the monitored
current is operating within the desired window range.
Table 8-2. Window Comparator Output Status
26
INPUT CONDITION
OUTPUT STATUS
Above range
0
Below range
0
In range
1
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8.2.3.3 Application Curve
Output
(5 V/div)
Figure 8-6 shows the output waveform from the device window comparator application. In Figure 8-6, the output
signal is high when OCP– is low (the input signal is above the lower limit) and when OCP+ is high (the input
signal is below the upper limit). If the signal rises above the upper limit or drops below the lower limit, the
corresponding OCP output changes state, causing the state of the output (following the AND gate) to change to
zero to indicate an out-of-range condition.
Output
OCPOCP+
Input
(5 mV/div)
Upper Limit
Lower Limit
Time (2 ms/div)
C023
Figure 8-6. Output Waveform
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9 Power Supply Recommendations
The INA300 device input circuitry can accurately measure signals on common-mode voltages beyond the
power-supply voltage, VS. For example, the voltage applied to the VS power-supply terminal can be 5 V, whereas
the load power-supply voltage being monitored (VCM) can be as high as 36 V. Note that the INA300 device can
withstand the full –0.3 V to +36 V range at the input terminals, regardless of whether the device has power
applied or not.
Power-supply bypass capacitors are required for stability and must be placed as closely as possible to the
supply and ground terminals of the device. A typical value for this supply bypass capacitor is 0.1 µF. Applications
with noisy or high-impedance power supplies may require additional decoupling capacitors to reject powersupply noise.
28
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10 Layout
10.1 Layout Guidelines
•
•
•
•
•
The power-supply bypass capacitor must be placed as closely as possible to the supply and ground
terminals. The recommended value of this bypass capacitor is 0.1 µF. Additional decoupling capacitance
can be added to compensate for noisy or high-impedance power supplies.
The connection of RLIMIT to the ground terminal must be made as direct as possible to limit additional
capacitance on this node. Routing this connection must be limited to the same plane if possible avoiding vias
to internal planes. If the routing cannot be made on the same plane and must pass through vias, ensure that
a path is routed from the RLIMIT back to the ground terminal and that the RLIMIT is not connected directly to a
ground plane.
The DELAY terminal must be either connected directly to ground, directly to supply, or left completely
floating. Additional external resistors must not be connected to this terminal. If a resistance is required by
the application to be placed in series with either the supply or ground connection to the DELAY terminal, this
resistance must be limited to 1 kΩ so as to not conflict with the internal level detection circuitry.
The HYS terminal must be either connected directly to ground, directly to supply, or left completely floating.
Additional external resistors must not be connected to this terminal. If a resistance is required by the
application to be placed in series with either the supply or ground connections to the HYS terminal, this
resistance must be limited to 1 kΩ so as to not conflict with the internal level detection circuitry.
The open-drain output pin is recommended to be pulled up to the supply voltage rail through a 10-kΩ pull-up
resistor.
10.2 Layout Example
VIA to Power or Ground Plane
VIA to Internal Layer
IN+
HYS
IN-
VS
LIMIT
GND
EN
DELAY
ALERT
LATCH
Kelvin Connection
Supply Voltage
Supply Bypass
Capacitor
Pull-Up Resistor
Limit Resistor
Alert Signal Trace
Digital Control Traces
NOTE: Connect the limit resistor directly to the GND terminal.
Figure 10-1. Recommended Layout for WSON Package
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VIA to Power or Ground Plane
VIA to Internal Layer
IN+
HYS
IN-
VS
LIMIT
GND
EN
DELAY
ALERT
LATCH
Kelvin Connection
Supply Voltage
Supply Bypass
Capacitor
Pull-Up Resistor
Limit Resistor
Alert Signal Trace
Digital Control Traces
NOTE: Connect the limit resistor directly to the GND terminal.
Figure 10-2. Recommended Layout for VSSOP Package
30
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
•
INA300EVM User's Guide (SBAU220).
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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3-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
INA300AIDGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAUAG | SN
Level-1-260C-UNLIM
-40 to 125
12T6
Samples
INA300AIDGST
ACTIVE
VSSOP
DGS
10
250
RoHS & Green
NIPDAUAG | SN
Level-1-260C-UNLIM
-40 to 125
12T6
Samples
INA300AIDSQR
ACTIVE
WSON
DSQ
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SKD
Samples
INA300AIDSQT
ACTIVE
WSON
DSQ
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SKD
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
