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INA302, INA303
SBOS775C – SEPTEMBER 2016 – REVISED MARCH 2019
INA30x 36-V, Overcurrent Protection, Precision,
Current-Sense Amplifiers With Dual Integrated Comparators
1 Features
3 Description
•
•
The INA302 and INA303 (INA30x) devices feature a
high common-mode, bidirectional, current-sensing
amplifier and two high-speed comparators to detect
out-of-range current conditions. The INA302
comparators are configured to detect and respond to
overcurrent conditions. The INA303 comparators are
configured to respond to both overcurrent and
undercurrent conditions in a windowed configuration.
These devices feature an adjustable limit threshold
range for each comparator set using an external limitsetting resistor. These current-shunt monitors can
measure differential voltage signals on commonmode voltages that can vary from –0.1 V up to +36 V,
independent of the supply.
1
•
•
Wide common-mode input range: –0.1 V to +36 V
Dual comparator outputs:
– INA302: Two independent overlimit alerts
– INA303: Window comparator
– Threshold levels set individually
– Comparator 1 alert response: 1 µs
– Comparator 2 adjustable delay: 2 µs to 10 s
– Open-drain outputs with independent latch
control modes
High accuracy amplifier:
– Offset voltage: 30 µV (max, A3 version)
– Offset voltage drift: 0.5 µV/°C (max)
– Gain error: 0.15% (max, A3 version)
– Gain error drift: 10 ppm/°C
Available amplifier gains:
– INA302A1, INA303A1: 20 V/V
– INA302A2, INA303A2: 50 V/V
– INA302A3, INA303A3: 100 V/V
The open-drain alert outputs can be configured to
operate in either a transparent mode (output status
follows the input state), or in a latched mode (alert
output is cleared when the latch is reset). The alert
response time for comparator 1 is under 1 µs, and
the alert response for comparator 2 is set through an
external capacitor ranging from 2 µs to 10 s.
These devices operate from a single 2.7-V to 5.5-V
supply, drawing a maximum supply current of 950 μA.
The devices are specified over the extended
operating temperature range of –40°C to +125°C, and
are available in a 14-pin TSSOP package.
2 Applications
•
•
•
•
•
Overcurrent protection
Motor control
Power-supply protection
Computers and servers
Telecom equipment
Device Information
PART NUMBER
INA302
PACKAGE
TSSOP (14)
INA303
BODY SIZE (NOM)
4.40 mm × 5.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Typical Application
2.7 V to 5.5 V
CBYPASS
0.1 …F
VS
INA30x
LIMIT1
RPULL-UP
10 k
RLIMIT1
COMP1
Supply
(0 V to 36 V)
+
Microcontroller
ALERT1
GPIO
LATCH1
IN+
GPIO
+
OUT
ADC
COMP2
INLoad
- (+)
ALERT2
+ (-)
LATCH2
GPIO
GPIO
DELAY
LIMIT2
CDELAY
GND
RLIMIT2
Reference Voltage
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA302, INA303
SBOS775C – SEPTEMBER 2016 – REVISED MARCH 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 14
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
14
14
15
21
8
Application and Implementation ........................ 23
8.1 Application Information .......................................... 23
8.2 Typical Application .................................................. 29
9 Power Supply Recommendations...................... 31
10 Layout................................................................... 31
10.1 Layout Guidelines ................................................. 31
10.2 Layout Example .................................................... 32
11 Device and Documentation Support ................. 33
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Documentation Support .......................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
33
33
33
33
33
33
33
12 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2017) to Revision C
Page
•
Changed locations and text of some sections for clarity; no content was changed............................................................... 1
•
Added MIN and MAX values to VCM and VS rows of Recommended Operating Conditions table......................................... 4
•
Deleted VCM, VS, and temperature range rows from Electrical Characteristics table; same content listed in
Recommended Operating Conditions table............................................................................................................................ 5
Changes from Revision A (February 2017) to Revision B
Page
•
Changed y-axis units from 0.5 V/div to 1 V/div and changed (INA30xA1) to (INA30x) in title of Comparator 1 Total
Propagation Delay figure ...................................................................................................................................................... 12
•
Changed y-axis units from 0.5 V/div to 1 V/div and changed (INA303A1) to (INA303) in title of Comparator 2 Total
Propagation Delay figure ...................................................................................................................................................... 12
•
Deleted Comparator 1 Total Propagation Delay (INA30xA2), Comparator 1 Total Propagation Delay (INA30xA3),
Comparator 2 Total Propagation Delay (INA303A2), and Comparator 2 Total Propagation Delay (INA303A3) figures ..... 12
•
Changed (INA303A1) to (INA303) in title of Comparator 2 Total Propagation Delay figure ................................................ 12
•
Deleted Comparator 2 Total Propagation Delay (INA303A2) and Comparator 2 Total Propagation Delay (INA303A3)
figures ................................................................................................................................................................................... 12
•
Added Comparator 2 Total Propagation Delay (INA302A1) and Comparator 2 Total Propagation Delay (INA302A1)
figures ................................................................................................................................................................................... 12
Changes from Original (September 2016) to Revision A
•
2
Page
Released to production .......................................................................................................................................................... 1
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Product Folder Links: INA302 INA303
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SBOS775C – SEPTEMBER 2016 – REVISED MARCH 2019
5 Pin Configuration and Functions
PW Package
14-Pin TSSOP
Top View
VS
1
14
IN+
OUT
2
13
IN±
LIMIT1
3
12
ALERT1
REF
4
11
ALERT2
GND
5
10
DELAY
LATCH1
6
9
LIMIT2
LATCH2
7
8
NC
Not to scale
Pin Functions
PIN
NO.
NAME
TYPE
DESCRIPTION
1
VS
Analog
2
OUT
Analog output
Power supply, 2.7 V to 5.5 V
3
LIMIT1
Analog input
ALERT1 threshold limit input; see the Setting Alert Thresholds section for details on
setting the limit threshold
4
REF
Analog input
Reference voltage, 0 V to VS
5
GND
Analog
6
LATCH1
Digital input
Transparent or latch mode selection input
7
LATCH2
Digital input
Transparent or latch mode selection input
8
NC
—
9
LIMIT2
Analog input
ALERT2 threshold limit input; see the Setting Alert Thresholds section for details on
setting the limit threshold
10
DELAY
Analog input
Delay timing input; see the Alert Outputs section for details on setting the delayed
alert response for comparator 2
11
ALERT2
Analog output
Open-drain output; active-low. This pin is an overlimit alert for the INA302 and an
underlimit alert for the INA303.
12
ALERT1
Analog output
Open-drain output, active-low overlimit alert
13
IN–
Analog input
Connect to load side of the current-sensing resistor
14
IN+
Analog input
Connect to supply side of the current-sensing resistor
Output voltage
Ground
No internal connection
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VS
6
Differential (VIN+) – (VIN–)
V
–40
40
GND – 0.3
40
Analog input
LIMIT1, LIMIT2, DELAY, REF
GND – 0.3
(VS) + 0.3
V
Analog output
OUT
GND – 0.3
(VS) + 0.3
V
Digital input
LATCH1, LATCH2
GND – 0.3
(VS) + 0.3
V
Digital output
ALERT1, ALERT2
GND – 0.3
6
V
150
°C
150
°C
TJ
Junction temperature
Tstg
Storage temperature
(2)
(3)
(2)
UNIT
Common-mode (3)
Analog inputs (IN+, IN–)
(1)
MAX
Supply voltage
–65
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
VIN+ and VIN– are the voltages at the IN+ and IN– pins, respectively.
Input voltage can exceed the voltage shown without causing damage to the device if the current at that pin is limited to 5 mA.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
–0.1
12
36
V
Operating supply voltage
2.7
5
5.5
V
Operating free-air temperature
–40
125
°C
VCM
Common-mode input voltage
VS
TA
UNIT
6.4 Thermal Information
INA30x
THERMAL METRIC (1)
PW (TSSOP)
UNIT
14 PINS
RθJA
Junction-to-ambient thermal resistance
110.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
35.1
°C/W
RθJB
Junction-to-board thermal resistance
53.2
°C/W
ψJT
Junction-to-top characterization parameter
2.3
°C/W
ψJB
Junction-to-board characterization parameter
52.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS775C – SEPTEMBER 2016 – REVISED MARCH 2019
6.5 Electrical Characteristics
at TA = 25°C, VSENSE = 0 V, VREF = VS / 2, VS = 5 V, VIN+ = 12 V, VLIMIT1 = 3 V, and VLIMIT2 = 3 V (INA302) or 2 V (INA303)
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VIN = VIN+ – VIN–, VREF = VS / 2,
A1 versions
0
±125
VIN = VIN+ – VIN–, VREF = VS / 2,
A2 versions
0
±50
VIN = VIN+ – VIN–, VREF = VS / 2,
A3 versions
0
±25
UNIT
INPUT
VIN
Differential input voltage range
CMRR
Common-mode rejection ratio
Offset voltage, RTI (1)
VOS
VIN+ = 0 V to 36 V,
TA = –40ºC to +125ºC, A1 versions
100
114
VIN+ = 0 V to 36 V, TA = –40ºC to +125ºC,
A2 versions
106
118
VIN+ = 0 V to 36 V,
TA = –40ºC to +125ºC, A3 versions
110
120
mV
dB
A1 versions
±15
±80
A2 versions
±10
±50
A3 versions
±5
±30
µV
Offset voltage drift, RTI (1)
TA= –40ºC to +125ºC
0.02
0.25
µV/°C
PSRR
Power-supply rejection ratio
VS = 2.7 V to 5.5 V, VIN+ = 12 V,
TA = –40ºC to +125ºC
±0.3
±5
µV/V
IB
Input bias current
IB+, IB–
IOS
Input offset current
VSENSE = 0 mV
dVOS/dT
115
µA
±0.01
µA
OUTPUT
A1 versions
G
Gain
Gain error
20
A2 versions
50
A3 versions
100
V/V
VOUT = 0.5 V to VS – 0.5 V, A1 versions
±0.02%
VOUT = 0.5 V to VS – 0.5 V, A2 versions
±0.05%
±0.1%
VOUT = 0.5 V to VS – 0.5 V, A3 versions
±0.1%
±0.15%
3
10
TA= –40ºC to +125ºC
Nonlinearity error
VOUT = 0.5 V to VS – 0.5 V
Maximum capacitive load
No sustained oscillation
±0.075%
ppm/°C
±0.01%
500
pF
VOLTAGE OUTPUT
Swing to VS power-supply rail
RL = 10 kΩ to GND,
TA = –40ºC to +125ºC
VS – 0.05
VS – 0.1
Swing to GND
RL = 10 kΩ to GND,
TA = –40ºC to +125ºC
VGND + 15
VGND + 30
V
mV
FREQUENCY RESPONSE
BW
Bandwidth
SR
A1 versions, COUT = 500 pF
550
A2 versions, COUT = 500 pF
440
A3 versions, COUT = 500 pF
400
Slew rate
kHz
4
V/µs
30
nV/√Hz
NOISE, RTI (1)
Voltage noise density
(1)
RTI = referred-to-input.
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Electrical Characteristics (continued)
at TA = 25°C, VSENSE = 0 V, VREF = VS / 2, VS = 5 V, VIN+ = 12 V, VLIMIT1 = 3 V, and VLIMIT2 = 3 V (INA302) or 2 V (INA303)
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Comparator 1, input overdrive = 1 mV
0.6
1
Comparator 2, input overdrive = 1 mV,
delay = 100 kΩ to VS
1.25
2
1
1.5
Comparator 2 (INA302),
VOUT step = 0.5 V to 4.5 V, VLIMIT = 4 V,
delay = 100 kΩ to VS
1.5
2.5
Comparator 2 (INA303),
VOUT step = 4.5 V to 0.5 V, VLIMIT = 1 V,
delay = 100 kΩ to VS
1.5
2.5
80
80.8
UNIT
COMPARATOR
tp
Total alert propagation delay
Comparator 1, VOUT step = 0.5 V to 4.5 V,
VLIMIT = 4 V
Slew-rate-limited tp
ILIMIT1
Limit threshold output current,
comparator 1
ILIMIT2
Limit threshold output current,
comparator 2
VOS
Offset voltage, both comparators
TA = 25ºC, VLIMIT1 < VS – 0.6 V
79.2
TA = –40ºC to +125ºC,
VLIMIT1 < VS – 0.6 V
78.4
TA = 25ºC, VLIMIT2 < VS – 0.6 V
79.7
TA = –40ºC to +125ºC,
VLIMIT2 < VS – 0.6 V
79.2
81.6
80
µs
µs
µA
80.4
80.8
µA
A1 versions
0.5
3.5
A2 versions
0.5
3.5
A3 versions
0.5
4.0
Hysteresis
comparator 1, comparator 2
100
Internal programmable delay error
TA = –40ºC to +125ºC
VTH
Delay threshold voltage
TA = –40ºC to +125ºC
1.21
1.22
1.23
V
ID
Delay charging current
TA = –40ºC to +125ºC, VDELAY = 0.6 V
4.85
5
5.15
µA
RD
Delay discharge resistance
VIH
LATCH1, LATCH2 high-level input
voltage
TA = –40ºC to +125ºC
1.4
VIL
LATCH1, LATCH2 low-level input voltage
TA = –40ºC to +125ºC
0
0.4
V
VOL
Alert low-level output voltage
IOL = 3 mA, TA = –40ºC to +125ºC
70
400
mV
ALERT1, ALERT2 pin leakage input
current
VOH = 3.3 V
0.1
1
µA
LATCH1, LATCH2 digital leakage input
current
0 V ≤ VLATCH1 , VLATCH2 ≤ VS
HYS
mV
mV
4%
70
Ω
6
1
V
µA
POWER SUPPLY
IQ
6
Quiescent current
TA = 25ºC
TA = –40ºC to +125ºC
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850
950
1150
µA
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6.6 Typical Characteristics
Input Offset Voltage (PV)
100
80
60
40
20
0
-20
-40
-60
-80
-100
100
80
60
40
20
0
-20
-40
-60
-80
-100
Population
Population
at TA = 25°C, VREF = VS / 2, VSENSE = 0 V, VS = 5 V, VIN+ = 12 V, and ALERT1, ALERT2 pullup resistors = 10 kΩ (unless
otherwise noted)
Input Offset Voltage (PV)
Figure 1. Input Offset Voltage Distribution (INA30xA1)
Figure 2. Input Offset Voltage Distribution (INA30xA2)
20
INA30xA1
INA30xA2
INA30xA3
15
Population
Offset Voltage (PV)
10
5
0
-5
-10
-20
-50
100
80
60
40
20
0
-20
-40
-60
-80
-100
-15
-25
0
25
50
75
Temperature (qC)
100
125
150
Input Offset Voltage (PV)
Figure 3. Input Offset Voltage Distribution (INA30xA3)
5
4
3
2
1
0
-1
-2
Common-Mode Rejection Ratio (PV/V)
Common-Mode Rejection Ratio (PV/V)
Figure 5. CMRR Distribution (INA30xA1)
-3
-4
-5
10
8
6
4
2
0
-2
-4
-6
-8
-10
Population
Population
Figure 4. Input Offset Voltage vs Temperature
Figure 6. CMRR Distribution (INA30xA2)
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Typical Characteristics (continued)
at TA = 25°C, VREF = VS / 2, VSENSE = 0 V, VS = 5 V, VIN+ = 12 V, and ALERT1, ALERT2 pullup resistors = 10 kΩ (unless
otherwise noted)
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
INA30xA1
INA30xA2
INA30xA3
-1.8
-2
-50
3
2.5
2
1.5
1
0
0.5
-1
-0.5
-1.5
-2
-2.5
-3
Population
Common-Mode Rejection Ratio (Pv/v)
0
-0.2
-25
0
25
50
75
Temperature (qC)
100
125
150
D008
Common-Mode Rejection Ratio (PV/V)
Figure 7. CMRR Distribution (INA30xA3)
Figure 8. CMRR vs Temperature
140
INA30xA1
INA30xA2
INA30xA3
100
Population
CMRR (dB)
120
80
60
100
1000
10000
Frequency (Hz)
100000
1000000
-0.1
-0.09
-0.08
-0.07
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
40
10
D009
Gain Error (%)
Figure 10. Gain Error Distribution (INA30xA1)
-0.15
-0.135
-0.12
-0.105
-0.09
-0.075
-0.06
-0.045
-0.03
-0.015
0
0.015
0.03
0.045
0.06
0.075
0.09
0.105
0.12
0.135
0.15
-0.2
-0.18
-0.16
-0.14
-0.12
-0.1
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0.2
Population
Population
Figure 9. CMRR vs Frequency
Gain Error (%)
Gain Error (%)
Figure 11. Gain Error Distribution (INA30xA2)
8
Figure 12. Gain Error Distribution (INA30xA3)
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Typical Characteristics (continued)
at TA = 25°C, VREF = VS / 2, VSENSE = 0 V, VS = 5 V, VIN+ = 12 V, and ALERT1, ALERT2 pullup resistors = 10 kΩ (unless
otherwise noted)
50
0.5
INA30xA1
INA30xA2
INA30xA3
0.4
0.3
40
30
0.1
Gain (dB)
Gain Error (%)
0.2
0
-0.1
-0.2
20
10
0
-0.3
INA30xA1
INA30xA2
INA30xA3
-10
-0.4
-0.5
-50
-20
-25
0
25
50
75
Temperature (qC)
100
125
1
150
10
Figure 13. Gain Error vs Temperature
1k
10k
Frequency (Hz)
100k
1M
10M
Figure 14. Gain vs Frequency
VS
140
Output Voltage Swing (V)
120
100
PSRR (dB)
100
80
60
VS - 1
VS - 2
GND + 3
GND + 2
125ºC
25ºC
-40ºC
GND + 1
40
GND
20
1
10
100
1k
10k
Frequency (Hz)
100k
1M
0
10M
2
4
6
8
10
12
14
Output Current (mA)
Figure 16. Output Voltage Swing vs Output Current
Figure 15. PSRR vs Frequency
150
225
200
125
Input Bias Current (PA)
Input Bias Current (PA)
175
150
125
100
75
50
100
75
50
25
25
0
0
-25
-5
0
5
10
15
20
25
30
Common-Mode Voltage (V)
35
40
-25
-5
0
VS = 5 V
5
10
15
20
25
30
Common-Mode Voltage (V)
35
40
VS = 0 V
Figure 17. Input Bias Current vs Common-Mode Voltage
Figure 18. Input Bias Current vs Common-Mode Voltage
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Typical Characteristics (continued)
145
1000
140
950
135
Quiescent Current (PA)
Input Bias Current (PA)
at TA = 25°C, VREF = VS / 2, VSENSE = 0 V, VS = 5 V, VIN+ = 12 V, and ALERT1, ALERT2 pullup resistors = 10 kΩ (unless
otherwise noted)
130
125
120
115
110
900
850
800
750
700
650
105
100
-50
-25
0
25
50
75
Temperature (qC)
100
125
600
2.7
150
Figure 19. Input Bias Current vs Temperature
Input-Referred Voltage Noise (nv/—Hz)
Quiescent Current (PA)
1000
950
900
850
800
750
-25
0
25
50
75
Temperature (qC)
100
125
3.6
3.9 4.2 4.5 4.8
Supply Voltage (V)
5.4
5.7
150
300
200
100
70
50
30
20
10
1000 2000
5000 10000
100000
Frequency (Hz)
1000000
Figure 22. Input-Referred Voltage Noise vs Frequency
Input
Output
Output (1 V/div)
Referred-to-Input Voltage Noise
(200 nV/div)
5.1
1000
700
500
Input (200 mV/div)
Figure 21. Quiescent Current vs Temperature
3.3
Figure 20. Quiescent Current vs Supply Voltage
1050
700
-50
3
Time (1 s/div)
Time (1 Ps/div)
4-VPP output step
Figure 23. 0.1-Hz to 10-Hz Voltage Noise
(Referred to Input)
10
Figure 24. Voltage Output Rising Step Response
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Typical Characteristics (continued)
Output (1 V/div)
Common-Mode Voltage (5 V/div)
Input
Output
VCM
VOUT
Time (1 Ps/div)
VOUT (250 mV/div)
Input (200 mV/div)
at TA = 25°C, VREF = VS / 2, VSENSE = 0 V, VS = 5 V, VIN+ = 12 V, and ALERT1, ALERT2 pullup resistors = 10 kΩ (unless
otherwise noted)
Time (5Ps/div)
4-VPP output step
Figure 25. Voltage Output Falling Step Response
Figure 26. Common-Mode Voltage Transient Response
80.8
Voltage (2 V/div)
LIMIT1 Current Source (PA)
80.6
VSUPPLY
VOUT
80.4
80.2
80
79.8
79.6
79.4
79.2
-50
Time (5 Ps/div)
0
25
50
75
Temperature (qC)
100
125
150
Figure 28. LIMIT1 Current Source vs Temperature
Figure 27. Start-Up Response
5.3
80.8
DELAY Current Source (PA)
80.6
LIMIT2 Current Source (PA)
-25
80.4
80.2
80
79.8
79.6
79.4
79.2
-50
-25
0
25
50
75
Temperature (qC)
100
125
150
Figure 29. LIMIT2 Current Source vs Temperature
5.2
5.1
5
4.9
4.8
4.7
-50
-25
0
25
50
75
Temperature (qC)
100
125
150
Figure 30. DELAY Current vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VREF = VS / 2, VSENSE = 0 V, VS = 5 V, VIN+ = 12 V, and ALERT1, ALERT2 pullup resistors = 10 kΩ (unless
otherwise noted)
0.5
Voltage (1 V/div)
8.5
ALERT1
VSENSE
7.5
0.3
6.5
0.2
5.5
0.1
4.5
0
3.5
-0.1
2.5
-0.2
1.5
-0.3
0.5
-0.4
-0.5
-5E-7
7E-7
1.9E-6
3.1E-6
Time (200 ns/div)
4.3E-6
VOUT
VLIMIT2
0.4
-0.5
5.5E-6
Time (600 ns/div)
D031
DELAY = open
Figure 31. Comparator 1 Total Propagation Delay
(INA30x)
Figure 32. Comparator 2 Total Propagation Delay
(INA303)
VOUT
VLIMIT2
Voltage (1 V/div)
Voltage (1 V/div)
Time (600 ns/div)
Time (600 ns/div)
DELAY = 100 kΩ to VS
DELAY = open
Figure 34. Comparator 2 Total Propagation Delay
(INA302)
Figure 33. Comparator 2 Total Propagation Delay
(INA303)
1000
ALERT2
VSENSE
800
Propagation Delay (ns)
Voltage (1 V/div)
VSENSE Voltage (0.1 V/div)
VOUT
VLIMIT2
ALERT2
VSENSE
VSENSE Voltage (0.1 V/div)
ALERT2
VSENSE
VSENSE Voltage (0.1 V/div)
VOUT
VLIMIT2
ALERT2
VSENSE
VSENSE Voltage (0.1 V/div)
VOUT
VLIMIT1
Voltage (1 V/div)
9.5
600
400
200
0
-50
Time (600 ns/div)
-25
DELAY = 100 kΩ to VS
0
25
50
75
Temperature (qC)
100
125
150
VOD = 1 mV
Figure 35. Comparator 2 Total Propagation Delay
(INA302)
12
Figure 36. Comparator 1 Propagation Delay vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VREF = VS / 2, VSENSE = 0 V, VS = 5 V, VIN+ = 12 V, and ALERT1, ALERT2 pullup resistors = 10 kΩ (unless
otherwise noted)
2200
110
Low-Level Output Voltage (mV)
100
Propagation Delay (ns)
2000
1800
1600
1400
90
80
70
60
50
40
30
20
ALERT1 VOL
ALERT2 VOL
10
1200
-50
0
-25
0
25
50
75
Temperature (qC)
100
125
0
150
0.5
1
1.5
2
2.5
3
3.5
4
Low-Level Output Current (mA)
4.5
5
VOD = 1 mV
Figure 38. Comparator Alert VOL vs IOL
120
120
100
100
80
80
Hysteresis (mV)
Hysteresis (mV)
Figure 37. Comparator 2 Propagation Delay vs Temperature
60
40
INA30xA1
INA30xA2
INA30xA3
20
0
-50
-25
0
25
50
75
Temperature (qC)
100
125
60
40
INA30xA1
INA30xA2
INA30xA3
20
0
-50
150
Figure 39. Comparator 1 Hysteresis vs Temperature
-25
0
25
50
75
Temperature (qC)
100
125
150
Figure 40. Comparator 2 Hysteresis vs Temperature
LATCH1, LATCH2
Voltage (2 V/div)
ALERT1, ALERT2
Time (2 ms/div)
Figure 41. Comparator Latch Response
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7 Detailed Description
7.1 Overview
The INA30x feature a zero-drift, 36-V, common-mode, bidirectional, current-sensing amplifier, and two highspeed comparators that can detect multiple out-of-range current conditions. These specially designed, currentsensing amplifiers can be used in both low-side or high-side applications where common-mode voltages far
exceed the supply voltage of the device. Currents are measured by accurately sensing voltages developed
across current-sensing resistors (also known as current-shunt resistors). Current can be measured on input
voltage rails as high as 36 V, and the device can be powered from supply voltages as low as 2.7 V.
The zero-drift topology enables high-precision measurements with maximum input offset voltages as low as
30 μV (max) with a temperature contribution of only 0.25 μV/°C (max) over the full temperature range of –40°C to
+125°C. The low total offset voltage of the INA302 enables smaller current-sense resistor values to be used,
improving power-efficiency without sacrificing measurement accuracy resulting from the smaller input signal.
Both devices use a single external resistor to set each out-of-range threshold. The INA302 allows for two
overcurrent thresholds, and the INA303 allows for both an undercurrent and overcurrent threshold. The response
time of the ALERT1 threshold is fixed and is less than 1 μs. The response time of the ALERT2 threshold can be
set with an external capacitor. The combination of a precision current-sense amplifier with onboard comparators
creates a highly-accurate solution that is capable of fast detection of multiple out-of-range conditions. The ability
to detect when currents are out-of-range allows the system to take corrective actions to prevent potential
component or system-wide damage.
7.2 Functional Block Diagram
2.7 V to 5.5 V
CBYPASS
0.1 PF
RLIMIT1
LIMIT1
VS
INA30x
ILIMIT1
Power Supply
0 V to 36 V
+
RPULL-UP1
10 k:
RPULL-UP2
10 k:
ALERT1
LATCH1
IN+
+
OUT
Gain = 20,
50, 100
RSENSE
ILIMIT2
IN-
LATCH2
+ (-)
ALERT2
LOAD
- (+)
REF
LIMIT2
Reference Voltage
14
DELAY
GND
CDELAY
RLIMIT2
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7.3 Feature Description
7.3.1 Bidirectional Current Sensing
The INA30x sense current flow through a sense resistor in both directions. The bidirectional current-sensing
capability is achieved by applying a voltage at the REF pin to offset the output voltage. A positive differential
voltage sensed at the inputs results in an output voltage that is greater than the applied reference voltage.
Likewise, a negative differential voltage at the inputs results in output voltage that is less than the applied
reference voltage. The equation for the output voltage of the current-sense amplifier is shown in Equation 1.
VOUT
I LOAD u RSENSE u GAIN
VREF
where
•
•
•
•
ILOAD is the load current to be monitored.
RSENSE is the current-sense resistor.
GAIN is the gain option of the device selected.
VREF is the voltage applied to the REF pin.
(1)
7.3.2 Out-of-Range Detection
The INA303 detects when negative currents are out-of-range by setting a voltage at the LIMIT2 pin that is less
than the applied reference voltage. The limit voltage is set with an external resistor or externally driven by a
voltage source or digital-to-analog converter (DAC); see the Setting Alert Thresholds section for additional
information. A typical application using the INA303 to detect negative overcurrent conditions is illustrated in the
Typical Application section.
7.3.3 Alert Outputs
Both ALERTx pins are active-low, open-drain outputs that pull low when the sensed current is detected to be out
of range. Both open-drain ALERTx pins require an external pullup resistor to an external supply. The external
supply for the pullup voltage can exceed the supply voltage, VS, but is restricted from operating at greater than
5.5 V. The pullup resistance is selected based on the capacitive load and required rise time; however, a 10-kΩ
resistor value is typically sufficient for most applications. The response time of the ALERT1 output to an out-ofrange event is less than 1 μs, and the response time of the ALERT2 output is proportional to the value of the
external CDELAY capacitor. The equation to calculate the delay time for the ALERT2 output is given in Equation 2:
If DELAY is connected to VS with 100 k:
1.5 Ps
tDELAY
CDELAY u VTH
ID
2.5 Ps
If CDELAY > 47 pF
where
•
•
•
CDELAY is the external delay capacitor.
VTH is the delay threshold voltage.
ID is the DELAY pin current for comparator 2.
(2)
For example, if a delay time of 10 µs is desired, the calculated value for CDELAY is 492 pF. The closest standard
capacitor value to the calculated value is 500 pF. If a delay time greater than 2.5 µs on the ALERT2 output is not
needed, the CDELAY capacitor can be omitted. To achieve minimum delay on the ALERT2 output, connect a 100kΩ resistor from the DELAY pin to the VS pin. Both comparators in the INA30x have hysteresis to avoid
oscillations in the ALERTx outputs. The effect hysteresis has on the comparator behavior is described in the
Hysteresis section.
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Feature Description (continued)
Figure 42 shows the alert output response of the internal comparators for the INA302. When the output voltage
of the current-sense amplifier is less than the voltage developed on either limit pin, both ALERTx outputs are in
the default high state. When the current sense amplifier output is greater than the threshold voltage set by the
LIMIT2 pin, the ALERT2 output pulls low after a delay time set by the external delay capacitor. The lower
overcurrent threshold is commonly referred to as the overcurrent warning threshold. If the current continues to
rise until the current-sense amplifier output voltage exceeds the threshold voltage set at the LIMIT1 pin, then the
ALERT1 output becomes active and immediately pulls low. The low voltage on ALERT1 indicates that the
measured signal at the amplifier input has exceeded the programmed threshold level, indicating an overcurrent
condition has occurred. The upper threshold is commonly referred to as the fault or system critical threshold.
Systems often initiate protection procedures (such as a system shutdown) when the current exceeds this
threshold.
Power Supply
0 V to 36 V
2.7 V to 5.5 V
Fault/Critical Threshold
INA302
INPUT (VIN+ - VIN-)
Supply
VS
RPULL-UP1
ALERT1
LIMIT1
RLIMIT1
Warning Threshold
INPUT SIGNAL
LATCH1
IN+
+
VLIMIT1
OUT
RSENSE
Supply
IN-
ALERT2
Load
LIMIT2
RLIMIT2
REF
VOUT
ALERT1
DELAY
LATCH2
OUTPUT
VLIMIT2
RPULL-UP2
ALERT2
CDELAY
GND
GND
tDELAY
Figure 42. Out-of-Range Alert Responses for the INA302
16
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Feature Description (continued)
Figure 43 shows the alert output response of the internal comparators for the INA303. Both ALERTx outputs are
in the default high state when the output voltage of the current-sense amplifier is less than the voltage developed
at the LIMIT1 pin and is greater than the voltage developed at the LIMIT2 pin. The ALERT1 output becomes
active and pulls low when the current-sense amplifier output voltage exceeds the threshold voltage set at the
LIMIT1 pin. The low voltage on ALERT1 indicates that the measured signal at the amplifier input has exceeded
the programmed threshold level, indicating an overcurrent or out-of-range condition has occurred. When the
current-sense amplifier output is less than the threshold voltage set by the LIMIT2 pin, the ALERT2 output pulls
low after the delay time set by the external delay capacitor expires. The delay time for the ALERT2 output is
proportional to the value of the external CDELAY capacitor, and is calculated by Equation 2.
Power Supply
0 V to 36 V
Overcurrent
Threshold
Supply
INA303
VS
RPULL-UP1
ALERT1
LIMIT1
Input (VIN+ - VIN-)
2.7 V to 5.5 V
Input Signal
Undercurrent
Threshold
RLIMIT1
LATCH1
+
VLIMIT1
OUT
VOUT
Supply
IN-
RPULL-UP2
ALERT2
Load
LIMIT2
LATCH2
VLIMIT2
ALERT1
RLIMIT2
ALERT2
DELAY
REF
Output
IN+
RSENSE
CDELAY
GND
tDELAY
Figure 43. Out-of-Range Alert Responses for the INA303
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Feature Description (continued)
Figure 44 shows the alert output response of the INA303 when the two ALERTx pins are connected together.
When configured in this manner, the INA303 can provide a single signal to indicate when the sensed current is
operating either outside the normal operating bands or within a normal operational window. Both ALERT1 and
ALERT2 outputs behave the same in regard to the alert mode. The difference with ALERT2 is that the transition
of the output state is delayed by the time set by the external delay capacitor. If the overcurrent or undercurrent
event is not present when the delay time expires, ALERT2 does not respond.
Power Supply
0 V to 36 V
Supply
VS
INA303
RPULL-UP
ALERT1
LIMIT1
ALERT
RLIMIT1
INPUT (VIN+ - VIN-)
2.7 V to 5.5 V
Normal Operating Region
INPUT SIGNAL
LATCH1
IN+
+
OUT
RSENSE
VLIMIT1
OUTPUT
IN-
ALERT2
Load
LIMIT2
RLIMIT2
VOUT Normal Operating
Region
VLIMIT2
ALERT
DELAY
LATCH2
GND
Figure 44. Current Window Comparator Implementation With the INA303
18
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Feature Description (continued)
7.3.3.1 Setting Alert Thresholds
The INA30x family of devices determines if an out-of-range event is present by comparing the amplifier output
voltage to the voltage at the corresponding LIMITx pin. The threshold voltage for the LIMITx pins can be set
using a single external resistor or by connecting an external voltage source to each pin. The INA302 allows
setting limits for two overcurrent conditions. Generally, the lower overcurrent threshold is referred to as a warning
limit and the higher overcurrent threshold is referred to as the critical or fault limit. The INA303 allows setting
thresholds to detect both undercurrent and overcurrent limit conditions.
7.3.3.1.1 Resistor-Controlled Current Limit
The typical approach to set the limit threshold voltage is to connect resistors from the two LIMITx pins to ground.
The voltage developed across the RLIMIT1, RLIMIT2 resistors represents the desired fault current value at which the
corresponding ALERTx pin becomes active. The values for the RLIMIT1, RLIMIT2 resistors are calculated using
Equation 3:
ITRIP u RSENSE u GAIN
RLIMIT
VREF
I LIMIT
where
•
•
•
•
•
ITRIP is the desired out-of-range current threshold.
RSENSE is the current-sensing resistor.
GAIN is the gain option of the device selected.
VREF is the voltage applied to the REF pin.
ILIMIT is the limit threshold output current for the selected comparator, typically 80 µA.
(3)
NOTE
When solving for the value of RLIMIT, the voltage at the corresponding LIMITx pin as
determined by the product of RLIMIT and ILIMIT must not exceed the compliance voltage of
VS – 0.6 V.
7.3.3.1.1.1 Resistor-Controlled Current Limit: Example
For example, if the current level indicating an out-of-range condition (ITRIP) is 20 A and the current-sense resistor
value (RSENSE) is 10 mΩ, then the input threshold signal is 200 mV. The INA302A1 has a gain of 20, so the
resulting output voltage at the 20-A input condition is 4 V at the output of the current-sense amplifier when the
REF pin is grounded. The value for RLIMIT is selected to allow the device to detect this 20-A threshold, indicating
that an overcurrent event has occurred. When the INA302 detects this out-of-range condition, the ALERTx pin
asserts and pulls low. For this example, the value of RLIMIT to detect a 4-V level is calculated to be 50 kΩ.
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Feature Description (continued)
7.3.3.1.2 Voltage-Source-Controlled Current Limit
The second method for setting the out-of-range threshold is to directly drive the LIMITx pins with a programmable
DAC or other external voltage source. The benefit of this method is the ability to adjust the current-limit threshold
to account for different threshold voltages used for different system operating conditions. For example, this
method can be used in a system with one current-limit threshold level that must be monitored during a power-up
sequence, but different threshold levels must be monitored during other system operating modes.
The voltage applied at the LIMITx pins sets the threshold voltage for out-of-range detection. The value of the
voltage for a given desired current trip point is calculated using Equation 4:
VSOURCE
ITRIP u RSENSE u GAIN
VREF
where
•
•
•
•
ITRIP is the desired out-of-range current threshold.
RSENSE is the current-sensing resistor.
GAIN is the gain option of the device selected.
VREF is the voltage applied to the REF pin.
(4)
NOTE
The maximum voltage that can be applied to the LIMIT2 pin is VS – 0.6 V and the
maximum voltage that can be applied to the LIMIT1 pin must not exceed VS.
7.3.3.2 Hysteresis
The hysteresis included in the comparators of the INA30x reduces the possibility of oscillations in the alert
outputs when the measured signal level is near the overlimit threshold level. For overrange events, the
corresponding ALERTx pin is asserted when the output voltage (VOUT) exceeds the threshold set at either LIMITx
pin. The output voltage must drop to less than the LIMITx pin threshold voltage by the hysteresis value in order
for the ALERTx pin to deassert and return to the nominal high state. Likewise for underrange events, the
corresponding ALERTx pin is also pulled low when the output voltage drops to less than the threshold set by
either LIMITx pin. The ALERTx pin is released when the output voltage of the current-sense amplifier rises to
greater than the set threshold plus hysteresis. Hysteresis functionality for both overrange and underrange events
is shown in Figure 45 and Figure 46 for the INA302 and INA303, respectively.
VLIMIT1
VLIMIT1 - VHYS
VLIMIT2
VLIMIT2 - VHYS
Critical Threshold
VLIMIT1
VLIMIT1 - VHYS
Overcurrent Threshold
Warning Threshold
VOUT
VOUT
VLIMIT2 + VHYS
VLIMIT2
Undercurrent
Threshold
ALERT1
ALERT1
ALERT2
ALERT2
Figure 45. Comparator Hysteresis Behavior (INA302)
20
Figure 46. Comparator Hysteresis Behavior (INA303)
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7.4 Device Functional Modes
7.4.1 Alert Operating Modes
Each comparator has two output operating modes: transparent and latched. These modes determine how the
ALERTx pins respond when an out-of-range condition is removed. The device is placed into either transparent or
latched state based on the voltage applied to the corresponding LATCHx pin, as shown in Table 1.
Table 1. Output Mode Settings
OUTPUT MODE
LATCHx PINS SETTINGS
ALERTx transparent mode
LATCHx = low
ALERTx latch mode
LATCHx = high
7.4.1.1 Transparent Output Mode
The comparators are set to transparent output mode when the corresponding LATCHx pin is pulled low. When
set to transparent mode, the output of the comparators changes and follows the input signal with respect to the
programmed alert threshold. For example, when the amplifier output violates the set limit value, the ALERTx
output pin is pulled low. As soon as the differential input signal drops to less than the alert threshold, the output
returns to the default high output state. A common implementation using the device in transparent mode is to
connect the ALERTx pins to a hardware interrupt input on a microcontroller. The ALERTx pin is pulled low as
soon as an out-of-range condition is detected, thus notifying the microcontroller. The microcontroller immediately
reacts to the alert and takes action to address the overcurrent condition. In transparent output mode, there is no
need to latch the state of the alert output because the microcontroller responds as soon as the out-of-range
condition occurs.
7.4.1.2 Latch Output Mode
The comparators are set to latch output mode when the corresponding LATCHx pin is pulled high. Some
applications do not continuously monitor the state of the ALERTx pins as described in the Transparent Output
Mode section. For example, if the device is set to transparent output mode in an application that only polls the
state of the ALERTx pins periodically, then the transition of the ALERTx pins can be missed when the out-ofrange condition is not present during one of these periodic polling events. Latch output mode allows the output of
the comparators to latch the output of the range condition so that the transition of the ALERTx pins is not missed
when the status of the comparator ALERTx pins is polled.
The difference between latch mode and transparent mode is how the alert output responds when an overcurrent
condition is removed. In transparent mode (LATCH1, LATCH2 = low), when the differential input signal drops to
within normal operating range, the ALERTx pin returns to the default high setting to indicate that the overcurrent
event has ended.
In latch mode (LATCHx = high), when an out-of-range condition is detected and the corresponding ALERTx pin
is pulled low; the ALERTx pin does not return to the default high state when the out-of-range condition is
removed. In order to clear the alert, the corresponding LATCHx pin must be pulled low for at least 100 ns. Pulling
the LATCHx pins low allows the corresponding ALERTx pin to return to the default high level, provided the outof-range condition is no longer present. If the out-of-range condition is still present when the LATCHx pins are
pulled low, then the corresponding ALERTx pin remains low. The ALERTx pins can be cleared (reset to high) by
toggling the corresponding LATCHx pin when the alert condition is detected by the system controller.
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The latch and transparent modes are illustrated in Figure 47. As illustrated in this figure, at time t1, the currentsense amplifier exceeds the limit threshold. During this time the LATCH1 pin is toggled with no affect to the
ALERT1 output. The state of the LATCH1 pin only matters when the output of the current-sense amplifier returns
to the normal operating region, as shown at t2. At this time the LATCH1 pin is high and the overcurrent condition
is latched on the ALERT1 output. As shown in the time interval between t2 and t3, the latch condition is cleared
when the LATCHx pin is pulled low. At time t4, the LATCH1 pin is already pulled low when the amplifier output
drops below the limit threshold for the second time. The device is set to transparent mode at this point and the
ALERT1 pin is pulled back high as soon as the output of the current-sense amplifier drops below the alert
threshold.
VLIMIT1
VOUT
(VIN+ - VIN-) x GAIN
0V
t1
LATCH1
t2
t3
t4
t5
Latch Mode
Transparent Mode
Alert Clears
ALERT1
Alert Does Not Clear
Figure 47. Transparent versus Latch Mode
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Selecting a Current-Sensing Resistor (RSENSE)
Selecting the value of this current-sensing resistor is based primarily on two factors: the required accuracy of the
current measurement and the allowable power dissipation across the current-sensing resistor. Larger voltages
developed across this resistor allow for more accurate measurements to be made. Amplifiers have fixed internal
errors that are largely dominated by the inherent input offset voltage. When the input signal decreases, these
fixed internal amplifier errors become a larger portion of the measurement and increase the uncertainty in the
measurement accuracy. When the input signal increases, the measurement uncertainty is reduced because the
fixed errors are a smaller percentage of the signal being measured. Therefore, the use of larger-value, currentsensing resistors inherently improves measurement accuracy.
However, a system design trade-off must be evaluated through the use of larger input signals for improving
measurement accuracy. Increasing the current-sense resistor value results in an increase in power dissipation
across the current-sensing resistor. Increasing the value of the current-shunt resistor increases the differential
voltage developed across the resistor when current passes through the component. This increase in voltage
across the resistor increases the power that the resistor must be able to dissipate. Decreasing the value of the
current-shunt resistor value reduces the power dissipation requirements of the resistor, but increases the
measurement errors resulting from the decreased input signal. Selecting the optimal value for the shunt resistor
requires factoring both the accuracy requirement for the specific application and the allowable power dissipation
of this component.
An increasing number of very low ohmic-value resistors are becoming more widely available with values reaching
down to 200 µΩ or lower, with power dissipations of up to 5 W that enable large currents to be accurately
monitored with sensing resistors.
8.1.1.1 Selecting a Current-Sensing Resistor: Example
In this example, the trade-offs involved in selecting a current-sensing resistor are discussed. This example
requires 2.5% accuracy for detecting a 10-A overcurrent event where only 250 mW is allowed for the dissipation
across the current-sensing resistor at the full-scale current level. Although the maximum power dissipation is
defined as 250 mW, a lower dissipation is preferred to improve system efficiency. Some initial assumptions are
made that are used in this example: the limit-setting resistor (RLIMIT) is a 1% component, and the maximum
tolerance specification for the internal threshold setting current source (1%) is used. Given the total error budget
of 2.5%, up to 0.5% of error can be attributed to the measurement error of the device under these conditions.
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Application Information (continued)
As shown in Table 2, the maximum value calculated for the current-sensing resistor with these requirements is
2.5 mΩ. Although this value satisfies the maximum power dissipation requirement of 250 mW, headroom is
available from the 2.5% maximum total overcurrent detection error to reduce the value of the current-sensing
resistor and to further reduce power dissipation. Selecting a 1.5-mΩ, current-sensing resistor value offers a good
tradeoff for reducing the power dissipation in this scenario by approximately 40% and stays within the accuracy
region.
Table 2. Calculating the Current-Sensing Resistor, RSENSE
PARAMETER
EQUATION
VALUE
UNIT
DESIGN TARGETS
IMAX
Maximum current
10
A
PD_MAX
Maximum allowable power dissipation
250
mW
Allowable current threshold accuracy
2.5%
DEVICE PARAMETERS
VOS
Offset voltage
EG
Gain error
30
µV
0.15%
CALCULATIONS
RSENSE_MAX
Maximum allowable RSENSE
PD_MAX / IMAX2
VOS_ERROR
Initial offset voltage error
(VOS / (RSENSE_MAX × IMAX ) × 100
0.12%
ERRORTOTAL
Total measurement error
√(VOS_ERROR2 + EG2)
0.19%
ERRORINITIAL
Initial threshold error
ILIMIT tolerance + RLIMIT tolerance
2%
ERRORAVAILABLE
Maximum allowable measurement error
Maximum error – ERRORINITIAL
1%
VOS_ERROR_MAX
Maximum allowable offset error
√(ERRORAVAILABLE2
VDIFF_MIN
Minimum differential voltage
VOS / VOS_ERROR_MAX (1%)
6.3
mV
RSENSE_MIN
Minimum sense resistor value
VDIFF_MIN / IMAX
0.63
mΩ
PD_MIN
Lowest-possible power dissipation
RSENSE_MIN × IMAX2
63
mW
24
2.5
2
– EG )
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mΩ
0.48%
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8.1.2 Input Filtering
The integrated comparators in the INA30x are very accurate at detecting out-of-range events because of the low
offset voltage; however, noise present at the input of the current-sense amplifier and noise internal to the device
can make the offset appear larger than specified. The most obvious effect that external noise can have on the
operation of a comparator is to cause a false alert condition. If a comparator detects a large noise transient
coupled into the signal, the device can easily falsely interpret this transient as an overrange condition.
External filtering helps reduce the amount of noise that reaches the comparator and reduce the likelihood of a
false alert from occurring because of external noise. The trade-off to adding this noise filter is that the alert
response time is increased because the input signal and the noise are filtered. Figure 48 shows the
implementation of an input filter for the device.
2.7 V to 5.5 V
CBYPASS
0.1 PF
RLIMIT1
LIMIT1
VS
RPULL-UP1
10 k:
ILIMIT1
Power Supply
0 V to 36 V
+
RPULL-UP2
10 k:
ALERT1
LATCH1
IN+
RSENSE
RFILTER
< 10 :
CFILTER
+
OUT
Gain = 20,
50, 100
ILIMIT2
IN-
LATCH2
+
ALERT2
LOAD
DELAY
REF
Reference Voltage
LIMIT2
GND
CDELAY
RLIMIT2
Figure 48. Input Filter Implementation
Limiting the amount of input resistance used in this filter is important because this resistance can have a
significant effect on the input signal that reaches the device input pins by adversely affecting the gain error of the
device. A typical system implementation involves placing the current-sensing resistor very near the device so the
traces are very short and the trace impedance is very small. This layout helps reduce coupling of additional noise
into the measurement. Under these conditions, the characteristics of the input bias currents have minimal effect
on device performance.
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As shown in Figure 49, the input bias currents increase in opposite directions when the differential input voltage
increases. This increase results from the design of the device that allows common-mode input voltages to far
exceed the device supply voltage range. When input filter resistors are placed in series with the unequal input
bias currents, unequal voltage drops are developed across the input resistors. The difference between these two
drops appears as an added signal that (in this case) subtracts from the voltage developed across the currentsensing resistor, thus reducing the signal that reaches the device input pins. Smaller-value input resistors reduce
this effect of signal attenuation to allow for a more accurate measurement.
160
Input Bias Current (PA)
140
120
100
80
IB+
IB60
-125 -100 -75
-50 -25
0
25
50
75
Differential Input Voltage (mV)
100
125
Figure 49. Input Bias Current vs Differential Input Voltage
The internal bias network present at the input pins shown in Figure 50 is responsible for the mismatch in input
bias currents that is shown in Figure 49. If additional external series filter resistors are added to the circuit, the
mismatch in bias currents results in a mismatch of voltage drops across the filter resistors. This mismatch
creates a differential error voltage that subtracts from the voltage developed at the shunt resistor. This error
results in a voltage at the device input pins that is different than the voltage developed across the shunt resistor.
Without the additional series resistance, the mismatch in input bias currents has little effect on device operation.
The amount of error these external filter resistors add to the measurement is calculated using Equation 6, where
the gain error factor is calculated using Equation 5.
V+
VCM
RS < 10 W
RINT
VOUT
RSHUNT
CF
Bias
RS < 10 W
VREF
RINT
Load
NOTE: Comparators omitted for simplicity.
Figure 50. Filter at Input Pins
26
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The amount of variance in the differential voltage present at the device input relative to the voltage developed at
the shunt resistor is based both on the external series resistance value as well as the internal input resistors, R3
and R4 (or RINT as illustrated in Figure 50). The reduction of the shunt voltage reaching the device input pins
appears as a gain error when comparing the output voltage relative to the voltage across the shunt resistor. A
factor can be calculated to determine the amount of gain error that is introduced by the addition of external series
resistance. The equation used to calculate the expected deviation from the shunt voltage to what is measured at
the device input pins is given in Equation 5:
(1250 ´ RINT)
Gain Error Factor =
(1250 ´ RS) + (1250 ´ RINT) + (RS ´ RINT)
where
•
•
RINT is the internal input resistor (R3 and R4).
RS is the external series resistance.
(5)
With the adjustment factor from Equation 5, including the device internal input resistance, this factor varies with
each gain version, as shown in Table 3. Each individual device gain error factor is shown in Table 4.
Table 3. Input Resistance
PRODUCT
GAIN
RINT (kΩ)
INA30xA1
20
12.5
INA30xA2
50
5
INA30xA3
100
2.5
Table 4. Device Gain Error Factor
PRODUCT
SIMPLIFIED GAIN ERROR FACTOR
INA30xA1
12,500
11u RS 12,500
INA30xA2
1000
RS 1000
INA30xA3
2500
3 u RS 2500
The gain error that is expected from the addition of the external series resistors is then calculated based on
Equation 6:
Gain Error (%) = 100 - (100 ´ Gain Error Factor)
(6)
For example, using an INA302A2 and the corresponding gain error equation from Table 4, a series resistance of
10 Ω results in a gain error factor of 0.99. The corresponding gain error is then calculated using Equation 6,
resulting in a gain error of approximately 1% solely because of the external 10-Ω series resistors.
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8.1.3 Using the INA30x With Common-Mode Transients Greater Than 36 V
With a small amount of additional circuitry, these devices can be used in circuits subject to transients higher than
36 V. Use only zener diodes or zener-type transient absorbers (sometimes referred to as transzorbs). Any other
type of transient absorber has an unacceptable time delay. Start by adding a pair of resistors as a working
impedance for the zener diode, as shown in Figure 51. Keep these resistors as small as possible, preferably 10
Ω or less. Larger values can be used with an additional induced error resulting from a reduced signal that
actually reaches the device input pins. Many applications are satisfied with a 10-Ω resistor along with
conventional zener diodes of the lowest power rating available because this circuit limits only short-term
transients. This combination uses the least amount of board space. These diodes can be found in packages as
small as SOT-523 or SOD-523.
2.7 V to 5.5 V
CBYPASS
0.1 PF
RLIMIT1
LIMIT1
VS
ILIMIT1
Power Supply
0 V to 36 V
+
RPULL-UP1
RPULL-UP2
10 k:
10 k:
ALERT1
LATCH1
IN+
RSENSE
RPROTECT
< 10 :
+
Gain = 20,
50, 100
OUT
ILIMIT2
IN-
LATCH2
+
ALERT2
LOAD
DELAY
REF
Reference
Voltage
LIMIT2
CDELAY
GND
RLIMIT2
Figure 51. Transient Protection
28
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8.2 Typical Application
The INA30x are designed to be easily configured for detecting multiple out-of-range current conditions in an
application. These devices are capable of monitoring and providing overcurrent detection of bidirectional
currents. By using the REF pin of the INA303, both positive and negative overcurrent events can be detected.
(+)
Bidirectional
Current Monitoring
(-)
RSENSE
2.7 V to 5.5 V
RLIMIT1
CBYPASS
0.1 µF
LIMIT1
INA303
VS
10 k:
ILIMIT1
+
RD
100 k:
ALERT1
-
IN+
RPULL-UP
LATCH1
+
OUT
VS
CBYP
0.1 µF
System
Alert
ILIMIT2
IN-
Current
Sense
LATCH2
-
ALERT2
GND
+
R1
100 k:
REF
LIMIT2
DELAY
GND
+
OPA313
R2
100 k:
RLIMIT2
CFLT
0.1 PF
Figure 52. Bidirectional Application
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Typical Application (continued)
8.2.1 Design Requirements
To allow for bidirectional monitoring, the INA303 requires a voltage applied to the REF pin. A voltage that is half
of the supply voltage is usually preferred to allow for maximum output swing in both the positive and negative
current direction. To reduce the errors in the reference voltage, drive the REF pin with a low-impedance source
(such as an op amp or external reference). A low-value resistor divider can be used at the expense of quiescent
current and accuracy. For this design, a single alert output is preferred, so both ALERT1 and ALERT2 are
connected together and use a single pullup resistor.
8.2.2 Detailed Design Procedure
To achieve bidirectional monitoring, drive the reference pin halfway between the supply with a resistor divider
buffered by an op amp, as shown in Table 5. To reduce the current draw from the supply, use 100-kΩ resistors
to create the divide-by-two voltage divider. The TLV313-Q1 is selected to buffer the voltage divider because this
device can operate from a single-supply rail with low IQ and offset voltage. To minimize the response time of the
ALERT2 output, a 100-kΩ pullup resistor was added from the DELAY pin to the VS pin. Select values for RSENSE,
RLIMIT2, and RLIMIT1 based on the desired current-sense levels and trip thresholds using the information in the
Resistor-Controlled Current Limit and Selecting a Current-Sensing Resistor (RSENSE) sections. For this example,
the values of RLIMIT1 and RLIMIT2 were selected so that the positive and negative overcurrent thresholds are the
same. Table 5 shows the alert output of the INA303 application circuit with the capability to detect both positive
and negative overcurrent conditions.
Table 5. Bidirectional Overcurrent Output Status
OVERCURRENT PROTECTION (OCP) STATUS
OUTPUT
Positive overcurrent detection (OCP+)
0
Negative overcurrent detection (OCP–)
0
Normal operation (no OCP)
1
8.2.3 Application Curve
Input
(5 mV/div)
Alert Output
(1 V/div)
Figure 53 shows the INA303 device being used in a bidirectional configuration to detect both negative and
positive overcurrent events.
Positive Limit
0V
Negative Limit
Time (5 ms/div)
Figure 53. Bidirectional Application Curve
30
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9 Power Supply Recommendations
The device input circuitry accurately measures signals on common-mode voltages beyond the power-supply
voltage, VS. For example, the voltage applied to the VS power-supply pin can be 5 V, whereas the load powersupply voltage being monitored (VCM) can be as high as 36 V. At power-up, for applications where the commonmode voltage (VCM) slew rate is greater than 6 V/μs with a final common-mode voltage greater than 20 V, the VS
supply is recommended to be present before VCM. If the use case requires VCM to be present before VS with VCM
under these same slewing conditions, then a 331-Ω resistor must be added between the VS supply and the VS
pin bypass capacitor.
Power-supply bypass capacitors are required for stability, and must be placed as close as possible to the supply
and ground pins of the device. A typical value for this supply bypass capacitor is 0.1 µF. Applications with noisy
or high-impedance power supplies may require additional decoupling capacitors to reject power-supply noise.
During slow power-up events, current flow through the sense resistor or voltage applied to the REF pin can result
in the output voltage momentarily exceeding the voltage at the LIMITx pins, resulting in an erroneous indication
of an out-of-range event on the ALERTx output. When powering the device with a slow ramping power rail where
an input signal is already present, all alert indications should be disregarded until the supply voltage has reached
the final value.
10 Layout
10.1 Layout Guidelines
•
•
•
•
•
Apply connections to the current-sense resistor, RSENSE, on the inside of the resistor pads to avoid additional
voltage losses incurred by the high current traces to the resistor. Route the traces from the current-sense
resistor symmetrically and side-by-side back to the input of the INA to minimize common-mode errors and
noise pickup.
Place the power-supply bypass capacitor as closely as possible to the supply and ground pins. The
recommended value of this bypass capacitor is 0.1 µF. Additional decoupling capacitance can be added to
compensate for noisy or high-impedance power supplies.
Make the connection of RLIMIT to the ground pin as direct as possible to limit additional capacitance on this
node. Routing this connection must be limited to the same plane if possible to avoid vias to internal planes. If
the routing can not be made on the same plane and must pass through vias, make sure that a path is routed
from RLIMIT back to the ground pin, and that RLIMIT is not simply connected directly to a ground plane.
Routing to the delay capacitor must be short and direct. Keep the routing trace from the DELAY pin to the
delay capacitor away from the ALERT2 trace (or any other noisy signals) to minimize any coupling effects. If
no delay capacitor is used do not have any connection to the DELAY pin. Long trace lengths on the DELAY
pin can cause noise to couple to the device, resulting in false trips.
Pull up the open-drain output pins to the supply voltage rail; a 10-kΩ pullup resistor is recommended.
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10.2 Layout Example
SYSALERT2
SYSALERT1
Supply Voltage
Power
Supply
RPULL-UP1
Bottom or
mid-layer
trace
CBYPASS
RPULL-UP2
VIA to Power
Ground Plane
VS
1
14
IN+
OUT
2
13
IN-
LIMIT1
3
12
ALERT1
REF
4
11
ALERT2
GND
5
10
DELAY
LATCH1
6
9
LIMIT2
LATCH2
7
8
NC
RSENSE
Current Sense
Output
RLIMIT1
VIA to Analog
Ground Plane
INA30x
CDELAY
RLIMIT2
Load
NOTE: Connect the limit resistors and delay capacitors directly to the GND pin; leave the DELAY pin unconnected or
connected to VS through a pullup resistor if no delay is needed.
Figure 54. Recommended Layout
32
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, TLVx313-Q1 Low Power Rail-to-Rail In/Out 750-µV Typical Offset Op Amps data sheet
• Texas Instruments, Monitoring Current for Multiple Out-of-Range Conditions application report
11.2 Related Links
Table 6 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to order now.
Table 6. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
INA302
Click here
Click here
Click here
Click here
Click here
INA303
Click here
Click here
Click here
Click here
Click here
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
INA302A1IPW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
I302A1
INA302A1IPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
I302A1
INA302A2IPW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
I302A2
INA302A2IPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
I302A2
INA302A3IPW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
I302A3
INA302A3IPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
I302A3
INA303A1IPW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
I303A1
INA303A1IPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
I303A1
INA303A2IPW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
I303A2
INA303A2IPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
I303A2
INA303A3IPW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
I303A3
INA303A3IPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
I303A3
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
