INA597
INA597
SBOS385B – AUGUST 2019 – REVISED APRIL
2021
SBOS385B – AUGUST 2019 – REVISED APRIL 2021
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INA597 High-Precision, Wide-Bandwidth e-trim™ Difference Amplifier
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
The INA597 is a low-power, wide-bandwidth,
difference amplifier for cost-sensitive applications.
The INA597 consists of a precision operational
amplifier (op amp) and a precision resistor network.
Excellent tracking of resistors maintains gain accuracy
and common-mode rejection over temperature.
Unique features such as low offset (200 μV,
maximum), low offset drift (5 μV/°C maximum) high
slew rate (18 V/μs), and high capacitive load drive
of up to 500 pF make the INA597 a robust,
high-performance difference amplifier for high-voltage
industrial applications.
•
•
Low offset voltage: 200 μV (maximum)
Low offset voltage drift: ±5 μV/°C (maximum)
Low noise: 18 nV/√Hz at 1 kHz
Low gain error: ±0.03% (maximum)
High common-mode rejection: 88 dB (minimum)
Wide bandwidth: 2-MHz GBW
Low quiescent current: 1.1 mA per amplifier
High slew rate: 18 V/μs
High capacitive load drive capability: 500 pF
Wide supply range:
– Single-supply: 4.5 V to 36 V
– Dual-supply: ±2.25 V to ±18 V
Specified temperature range:
–40°C to +125°C
Packages: 8-pin SOIC and VSSOP, 10-pin VSON
2 Applications
•
•
•
•
•
•
•
•
Data acquisition (DAQ)
Sensor modules and tags for asset tracking
Flow transmitter
Optical module
Power supply module
AC drive position feedback
Servo drive position feedback
Voltage conditioning module
The common-mode range of the
extends to the negative supply,
device to operate in single-supply
device operates on single (4.5 V
supplies (±2.25 V to ±18 V).
The difference amplifier is the foundation of many
commonly used circuits. The INA597 provides this
circuit function without using an expensive precision
resistor network.
Device Information
(1)
VCC
SOIC (8)
4.90 mm × 3.91 mm
VSON (10)
3.00 mm × 3.00 mm
VSSOP (8)
3.00 mm × 3.00 mm
For all available packages, see the package option
addendum at the end of the data sheet.
6k
12 k
±
OUT
+
ADC
AIN
16 Bits Out
6k
REF
Total Amplifiers (%)
15
SENSE
12 k
BODY SIZE (NOM)
20
V+
±IN
+IN
PACKAGE(1)
PART NUMBER
INA597
INA597
internal op amp
and enables the
applications. The
to 36 V) or dual
10
5
V±
VOUT
1
˜ V
2
,1
V±,1
Differential Input Data Acquisition
0
-80
-60
-40
-20
0
20
Offset Voltage (PV)
40
60
80
D004
Typical Distribution of Offset Voltage (RTO)
G = 1/2, VS = ±18 V
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings ....................................... 4
7.2 ESD Ratings .............................................................. 4
7.3 Recommended Operating Conditions ........................4
7.4 Thermal Information ...................................................4
7.5 Electrical Characteristics: G = 1/2 ..............................5
7.6 Electrical Characteristics: G = 2 .................................6
7.7 Typical Characteristics................................................ 7
8 Detailed Description......................................................22
8.1 Overview................................................................... 22
8.2 Functional Block Diagram......................................... 22
8.3 Feature Description...................................................22
8.4 Device Functional Modes..........................................22
9 Application and Implementation.................................. 23
9.1 Application Information............................................. 23
9.2 Typical Applications.................................................. 23
10 Power Supply Recommendations..............................30
11 Layout........................................................................... 30
11.1 Layout Guidelines................................................... 30
11.2 Layout Example...................................................... 31
12 Device and Documentation Support..........................33
12.1 Documentation Support.......................................... 33
12.2 Receiving Notification of Documentation Updates..33
12.3 Support Resources................................................. 33
12.4 Trademarks............................................................. 33
12.5 Electrostatic Discharge Caution..............................33
12.6 Glossary..................................................................33
13 Mechanical, Packaging, and Orderable
Information.................................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (February 2021) to Revision B (April 2021)
Page
• Added DRC package and associated content.................................................................................................... 1
Changes from Revision * (August 2019) to Revision A (February 2021)
Page
• Added D package and associated content......................................................................................................... 1
• Added input current (max) to Absolute Maximum Ratings ................................................................................ 4
• Deleted input voltage (max) from Absolute Maximum Ratings ..........................................................................4
• Changed common-mode voltage (min and max) in Electrical Characteristics .................................................. 4
• Added input impedance specifications to Electrical Characteristics .................................................................. 4
• Changed Fig. 6-39, Positive Output Voltage vs Output Current (sourcing) G = ½, Y-axis unit from µV to V......7
2
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5 Device Comparison Table
DEVICE
DESCRIPTION
GAIN EQUATION
INA597
Cost-effective, wide-bandwidth e-trim™ difference amplifier
G = 0.5 V/V or 2 V/V
INA592
High-precision, wide-bandwidth e-trim™ difference amplifier
G = 0.5 V/V or 2 V/V
INA159
High-speed, precision, gain of 0.2 level translation difference amplifier
G = 0.2 V/V
INA137
Audio differential line receiver ±6 dB (G = 1/2 or 2)
G = 0.5 V/V or 2 V/V
INA132
Low-power, single-supply difference amplifier
G = 1 V/V
INA819
35-µV offset, 0.4 µV/°C VOS drift, 8-nV/√Hz noise, low-power, precision instrumentation amplifier
G = 1 + 50 kΩ / RG
INA821
35-µV offset, 0.4 µV/°C VOS drift, 7-nV/√Hz noise, high-bandwidth, precision instrumentation amplifier
G = 1 + 49.4 kΩ / RG
INA333
25-µV VOS, 0.1 µV/°C VOS drift, 1.8-V to 5-V, RRO, 50-µA IQ, chopper-stabilized INA
G = 1 + 100 kΩ / RG
PGA280
20-mV to ±10-V Programmable Gain IA With 3-V or 5-V Differential Output; Analog Supply up to ±18 V
Digital programmable
PGA112
Precision Programmable Gain Op Amp With SPI
Digital programmable
6 Pin Configuration and Functions
REF
1
±IN
2
8
NC
–INOP
1
7
V+
REF
2
10
+INOP
9
NC
8
V+
±
Thermal
+
–IN
+IN
3
6
OUT
V±
4
5
SENSE
3
Pad
+IN
4
7
OUT
V–
5
6
SENSE
NC = No Connection
Figure 6-1. D (8-Pin SOIC) and DGK (8-Pin VSSOP)
Packages, Top View
Not to scale
Figure 6-2. DRC (10-Pin VSON With Thermal Pad)
Package, Top View
Table 6-1. Pin Functions
PIN
I/O
DESCRIPTION
D (SOIC),
DGK (VSSOP)
DRC (VSON)
+IN
3
4
I
12-kΩ resistor to noninverting terminal of op amp.
Used as positive input in G = ½ configuration.
Used as reference pin in G = 2 configuration.
–IN
2
3
I
12-kΩ resistor to inverting terminal of op amp.
Used as negative input in G = ½ configuration.
Connect to output in G = 2 configuration.
+INOP
—
10
I
Direct connection to noninverting terminal of op amp
–INOP
—
1
I
Direct connection to inverting terminal of op amp
NC
8
9
—
No internal connection (can be left floating)
OUT
6
7
O
Output
REF
1
2
I
6-kΩ resistor to noninverting terminal of op amp.
Used as reference pin in G = ½ configuration.
Used as positive input in G = 2 configuration.
SENSE
5
6
I
6-kΩ resistor to inverting terminal of op amp.
Connect to output in G = ½ configuration.
Used as negative input in G = 2 configuration.
V+
7
8
—
Positive (highest) power supply
V–
4
5
—
Negative (lowest) power supply
NAME
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
Single supply, (V+) to (V–)
V±
Input current
IS
Output short circuit (to ground)
TA
Operating temperature
TJ
Junction temperature
Tstg
Storage temperature
(1)
UNIT
36
Dual supply, (V+) – (V–)
IIN
MAX
V
±18
V
10
mA
–55
125
°C
–55
125
°C
150
°C
Continuous
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Section 7.3.
Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±500
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Single supply, VS = (V+) to (V–)
V±
Supply voltage
TA
Specified temperature
Dual supply, VS = (V+) – (V–)
NOM
MAX
UNIT
4.5
36
V
±2.25
±18
V
–40
125
°C
7.4 Thermal Information
INA597
THERMAL METRIC(1)
DGK
DRC
8 PINS
8 PINS
10 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
158
115
47.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
48.6
52.4
49.6
°C/W
RθJB
Junction-to-board thermal resistance
78.7
59.2
21.0
°C/W
ψJT
Junction-to-top characterization parameter
3.9
9.5
0.8
°C/W
ψJB
Junction-to-board characterization parameter
77.3
58.3
20.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
5.3
°C/W
(1)
4
D
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics: G = 1/2
at VS = ±2.25 V to ±18 V, TA = 25°C, VCM = VOUT = VS / 2, RL = 10 kΩ connected to ground, and REF pin connected to
ground (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
G = 1/2, RTO, TA = 25°C, VS = ±2.25 V to ±3
V,
VCM = –3V
±14
±200
µV
G = 1/2, RTO, TA = 25°C, VS = ±3 V to ±18
V, VCM = VS / 2
±14
±200
µV
±0.7
±5.0
µV/°C
±0.5
±5
µV/V
OFFSET VOLTAGE (RTO)
VOS
Input offset voltage
dVOS/dT
Input offset voltage
drift
PSRR
Power-supply
rejection ratio
VS = ±3 V to ±18 V
INPUT VOLTAGE
VCM
CMRR
Common-mode
voltage
Common-mode
rejection ratio
3[(V–)–0.1]
–2VREF
VOUT = 0 V
3(V+)–2VREF
100
V
RTO, 3 [(V−) – 0.1 V)] ≤
VCM ≤ 3 [(V+) – 3 V]
TA = 25°C
88
dB
TA = –40°C to +125°C
82
90
dB
RTO, 3 [(V+) - 1.5 V)] ≤
VCM ≤ 3 [(V+))]
TA = 25°C
88
100
dB
TA = –40°C to +125°C
72
90
dB
24
kΩ
9
kΩ
1/2
V/V
INPUT IMPEDANCE
zid
Differential
zic
Common-mode
VO = 0 V
GAIN
G
GE
Initial
Gain error
VOUT = –10 V to +10 V, VS = ±15 V
Gain error drift(1)
±0.01
±0.03
%
±0.2
±0.5
ppm/°C
Gain nonlinearity
VOUT = –10 V to +10 V, VS = ±15 V
1
ppm
VO
Output voltage
swing
Positive rail
170
220
mV
Negative rail
190
220
mV
ISC
Short-circuit
current
OUTPUT
±65
mA
NOISE
Vn
Output voltage
noise
f = 0.1 Hz to 10 Hz, RTO
Output voltage
noise density
3
μVpp
f = 1 kHz, RTO
18
nV/√Hz
Amplitude = –3 dB
2.0
MHz
18
V/µs
FREQUENCY RESPONSE
GBW
Small signal
bandwidth
SR
Slew rate
tS
Settling time
THD+N
Total harmonic
distortion + noise
f = 1 kHz, VOUT = 2.8 VRMS
Noise floor, RTO
80-kHz bandwidth, VOUT = 3.5 VRMS
tDR
To 0.1%
VOUT = 10-V step
1
µs
To 0.01%
VOUT = 10-V step
1.3
µs
0.00038
%
–116
dB
200
ns
Overload recovery
time
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7.5 Electrical Characteristics: G = 1/2 (continued)
at VS = ±2.25 V to ±18 V, TA = 25°C, VCM = VOUT = VS / 2, RL = 10 kΩ connected to ground, and REF pin connected to
ground (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.1
1.2
mA
1.5
mA
POWER SUPPLY
IQ
(1)
Quiescent current
TA = 25°C
IOUT = 0 mA
TA = –40°C to +125°C
Specified by wafer test to 95% confidence level.
7.6 Electrical Characteristics: G = 2
at VS = ±2.25 V to ±18 V, TA = 25°C, VCM = VOUT = VS / 2, RL = 10 kΩ connected to ground, and REF pin connected to
ground (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
G = 2, RTO, TA = 25°C, VS = ±2.25 V to ±3
V , VCM = –1.5V
±28
±400
µV
G = 2, RTO, TA = 25°C, VS = ±3 V to ±18
V,
VCM = VS / 2
±28
±400
µV
±1.4
±10
µV/°C
±1
±5
µV/V
OFFSET VOLTAGE (RTO)
VOS
Input offset voltage
dVOS/dT Input offset voltage drift
PSRR
Power-supply rejection
ratio
VS = ±2.25 V to ±18 V
INPUT VOLTAGE
VCM
Common-mode voltage
CMRR
Common-mode rejection
ratio
3/2[(V–)–
0.1]–0.5VREF
VOUT = 0 V
RTO, 1.5 [(V−) – 0.1 V)] TA = 25°C
≤ VCM ≤ 1.5 [(V+) – 3 V)] TA = –40°C to +125°C
RTO, 1.5 [(V+) - 1.5 V)]
≤ VCM ≤ 1.5 [(V+))]
3/2(V+)–
0.5VREF
V
82
94
dB
80
84
dB
TA = 25°C
82
94
dB
TA = –40°C to +125°C
65
84
dB
12
kΩ
9
kΩ
INPUT IMPEDANCE
zid
Differential
VO = 0 V
zic
Common-mode
GAIN
G
Initial
GE
Gain error
Gain error drift
2
VOUT = –10 V to +10 V, VS = ±15 V
(1)
Gain nonlinearity
VOUT = –10 V to +10 V, VS = ±15 V
V/V
±0.01
±0.03
%
±0.25
±0.5
ppm/°C
1
ppm
OUTPUT
VO
Output voltage swing
ISC
Short-circuit current
Positive rai
130
180
mV
Negative rail
140
180
mV
±65
mA
NOISE
Vn
Output voltage noise
f = 0.1 Hz to 10 Hz, RTO
6
μVpp
Output voltage noise
density
f = 1 kHz, RTO
36
nV/√Hz
Amplitude = –3 dB
0.8
MHz
FREQUENCY RESPONSE
GBW
Small signal bandwidth
SR
Slew rate
tS
6
Settling time
18
V/µs
To 0.1%
VOUT = 10-V step
1.0
µs
To 0.01%
VOUT = 10-V step
1.7
µs
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7.6 Electrical Characteristics: G = 2 (continued)
at VS = ±2.25 V to ±18 V, TA = 25°C, VCM = VOUT = VS / 2, RL = 10 kΩ connected to ground, and REF pin connected to
ground (unless otherwise noted)
PARAMETER
TEST CONDITIONS
THD+N
Total harmonic distortion +
f = 1 kHz, VOUT = 2.8 VRMS
noise
tDR
Overload recovery time
Noise floor, RTO
80-kHz bandwidth, VOUT = 3.5 VRMS
MIN
TYP
MAX
UNIT
0.00066
%
–110
dB
200
ns
POWER SUPPLY
IQ
(1)
Quiescent current
TA = 25°C
IOUT = 0 mA
1.1
TA = –40°C to +125°C
1.2
mA
1.5
mA
Specified by wafer test to 95% confidence level.
7.7 Typical Characteristics
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
Table 7-1. Table of Graphs
DESCRIPTION
FIGURE
Typical Distribution of Offset Voltage (RTO) G= 1/2, VS = ±2.25 V
Figure 7-1
Typical Distribution of Offset Voltage (RTO) G= 2, , VS = ±2.25 V
Figure 7-2
Typical Distribution of Offset Voltage (RTO) G= 1/2, , VS = ±18 V
Figure 7-3
Typical Distribution of Offset Voltage (RTO) G= 2, VS = ±18 V
Figure 7-4
Typical Distribution of Offset Voltage Drift (RTO) G = 1/2
Figure 7-5
Typical Distribution of Offset Voltage Drift (RTO) G = 2
Figure 7-6
Output Offset Voltage vs Temperature G = 1/2
Figure 7-7
Output Offset Voltage vs Temperature G = 2
Figure 7-8
Offset Voltage vs Common-Mode Voltage G = 1/2
Figure 7-9
Offset Voltage vs Common-Mode Voltage G = 2
Figure 7-10
Input Bias Current vs Temperature G = 1/2 and G = 2
Figure 7-11
Input Offset Current vs Temperature
Figure 7-12
Input Bias Current vs Common Mode Voltage G = 1/2
Figure 7-13
Input Bias Current vs Common Mode Voltage G = 2
Figure 7-14
Typical CMRR Distribution G= 1/2, Vs = ±2.25 V
Figure 7-15
Typical CMRR Distribution G = 2, Vs = ±2.25 V
Figure 7-16
Typical CMRR Distribution G= 1/2, Vs = ±18 V
Figure 7-17
Typical CMRR Distribution G = 2, Vs = ±18 V
Figure 7-18
CMRR vs Temperature G= 1/2
Figure 7-19
CMRR vs Temperature G= 2
Figure 7-20
Common-Mode Rejection Ratio vs Frequency (RTI) G = 1/2 and 2
Figure 7-21
Maximum Output Voltage vs Frequency
Figure 7-22
PSRR vs Temperature G = 1/2
Figure 7-23
PSRR vs Temperature G = 2
Figure 7-24
PSRR vs Frequency (RTI) G = 1/2
Figure 7-25
PSRR vs Frequency (RTI) G = 2
Figure 7-26
Typical Distribution of Gain Error G = 1/2, VS = ±2.25 V
Figure 7-27
Typical Distribution of Gain Error G = 2, VS = ±2.25 V
Figure 7-28
Gain Error vs Temperature G = 1 /2
Figure 7-29
Gain Error vs Temperature G = 2
Figure 7-30
Closed-Loop Gain vs Frequency G = 1/2
Figure 7-31
Closed-Loop Gain vs Frequency G = 2
Figure 7-32
Voltage Noise Spectral Density vs Frequency (RTI) G = 1/2
Figure 7-33
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7.7 Typical Characteristics
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
Table 7-1. Table of Graphs (continued)
DESCRIPTION
8
FIGURE
Voltage Noise Spectral Density vs Frequency (RTI) G = 2
Figure 7-34
0.1-Hz to 10-Hz RTI Voltage Noise G = 1/2
Figure 7-35
0.1-Hz to 10-Hz RTI Voltage Noise G = 2
Figure 7-36
Integrated Output Voltage Noise vs Noise Bandwidth G = 1/2
Figure 7-37
Integrated Output Voltage Noise vs Noise Bandwidth G = 2
Figure 7-38
Positive Output Voltage vs Output Current (sourcing) G = 1/2
Figure 7-39
Positive Output Voltage vs Output Current (sourcing) G = 2
Figure 7-40
Negative Output Voltage vs Output Current (sinking) G = 1/2
Figure 7-41
Negative Output Voltage vs Output Current (sinking) G = 2
Figure 7-42
Settling Time G = 1/2
Figure 7-43
Settling Time G = 2
Figure 7-44
Large Signal Step Response G = 1/2
Figure 7-45
Large Signal Step Response G =2
Figure 7-46
Slew Rate over Temperature
Figure 7-47
Overload Recovery (Normalized to 0V)
Figure 7-48
Small-Signal Overshoot vs Capacitive Load G = 1/2
Figure 7-49
Small-Signal Overshoot vs Capacitive Load G = 2
Figure 7-50
Small-Signal Step Response G = 1/2
Figure 7-51
Small-Signal Step Response G = 2
Figure 7-52
THD+N vs Frequency G = 1/2
Figure 7-53
THD+N vs Frequency G = 2
Figure 7-54
THD+N Ratio vs Output Amplitude G = 1/2
Figure 7-55
THD+N Ratio vs Output Amplitude G = 2
Figure 7-56
Supply Current vs Temperature G = 1/2
Figure 7-57
Supply Current vs Temperature G = 2
Figure 7-58
Supply Current vs Supply Voltage G = 1/2
Figure 7-59
Supply Current vs Supply Voltage G = 2
Figure 7-60
Short Circuit Current vs Temperature G = 1/2
Figure 7-61
Short Circuit Current vs Temperature G = 2
Figure 7-62
Differential-Mode EMI Rejection Ratio G = 1/2
Figure 7-63
Differential-Mode EMI Rejection Ratio G = 2
Figure 7-64
Common-Mode EMI Rejection Ratio G = 1/2
Figure 7-65
Common-Mode EMI Rejection Ratio G = 2
Figure 7-66
Input Common-Mode Voltage vs Output Voltage G = 1/2, Bipolar Supply
Figure 7-67
Input Common-Mode Voltage vs Output Voltage G= 2, Bipolar Supply
Figure 7-68
Input Common-Mode Voltage vs Output Voltage G = 1/2, 5-V Supply
Figure 7-69
Input Common-Mode Voltage vs Output Voltage G = 2, 5-V Supply
Figure 7-70
Input Common-Mode Voltage vs Output Voltage G = 1/2, 36-V Supply
Figure 7-71
Input Common-Mode Voltage vs Output Voltage G = 2, 36-V Supply
Figure 7-72
Closed-Loop Output Impedance vs Frequency
Figure 7-73
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7.7 Typical Characteristics (continued)
50
50
40
40
Total Amplifiers (%)
Total Amplifiers (%)
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
30
20
30
20
10
10
0
-40
-32
-24
-16
-8
0
8
16
24
32
Offset Voltage (PV)
0
-80
40
-60
-40
-20
0
20
40
60
Offset Voltage (PV)
D001
80
D002
N = 470
Mean = 0.82 μV
Std. Dev. = 2.91 μV
N = 470
Mean = 1.64 μV
Std. Dev. = 5.82 μV
G = 1/2
VS = ±2.25 V
VCM = –3 V
G=2
VS = ±2.25 V
VCM = –3 V
20
20
15
15
10
5
0
-40
-32
-24
-16
-8
0
8
16
24
32
Offset Voltage (PV)
N = 470
Mean = –5.22 μV
5
-40
Std. Dev. = 8.38 μV
-20
0
20
40
60
Offset Voltage (PV)
N = 470
80
D004
Mean = –10.43 μV Std. Dev. = 16.77 μV
G=2
Figure 7-4. Typical Distribution of Offset Voltage (RTO)
35
25
30
Total Amplifiers (%)
30
20
15
10
5
0
-2
-60
D003
Figure 7-3. Typical Distribution of Offset Voltage (RTO)
25
20
15
10
5
-1.6
-1.2
-0.8
-0.4
0
0.4
0.8
Offset Voltage Drift (PV/qC)
N = 30
10
0
-80
40
G = 1/2
Total Amplifiers (%)
Figure 7-2. Typical Distribution of Offset Voltage (RTO)
Total Amplifiers (%)
Total Amplifiers (%)
Figure 7-1. Typical Distribution of Offset Voltage (RTO)
Mean = –0.075 μV/°C
1.2
1.6
0
-4
2
Std. Dev. = 0.502 μV/°C
G = 1/2
-3.2
-2.4
-1.6
-0.8
0
0.8
1.6
Offset Voltage Drift (PV/qC)
D005
N = 30
Mean = –0.325 μV/°C
2.4
3.2
4
D006
Std. Dev. = 0.887 μV/°C
G=2
Figure 7-5. Typical Distribution of Offset Voltage Drift (RTO)
Figure 7-6. Typical Distribution of Offset Voltage Drift (RTO)
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7.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
150
100
100
50
Offset Voltage (PV)
Offset Voltage (PV)
50
0
-50
0
-50
-100
-150
-200
-100
-250
-150
-40
-20
0
G = 1/2
20
40
60
80
Temperature (qC)
100
120
-300
-40
140
-20
0
20
D007
30 units
G=2
Figure 7-7. Output Offset Voltage vs Temperature
40
60
80
Temperature (qC)
100
120
140
D008
D051
30 units
Figure 7-8. Output Offset Voltage vs Temperature
1000
1500
750
1000
Offset Voltage (PV)
Offset Voltage (PV)
500
500
0
-500
250
0
-250
-500
-1000
-750
-1500
-60
-40
-20
0
20
Common-Mode Voltage (V)
G = 1/2
40
-1000
-30 -25 -20 -15 -10 -5
0
5 10 15
Common-Mode Voltage (V)
60
D009
12 units
G=2
100
1000
0
800
600
400
200
0
-200
-40
30
D010
12 units
-100
-200
-300
-400
-500
-20
0
20
40
60
80
Temperature (qC)
100
120
140
-600
-40
D011
Figure 7-11. Input Bias Current vs Temperature
10
25
Figure 7-10. Offset Voltage vs Common-Mode Voltage
1200
Input Bias Current (pA)
Input Bias Current (pA)
Figure 7-9. Offset Voltage vs Common-Mode Voltage
20
-20
0
20
40
60
80
Temperature (qC)
100
120
140
D012
Figure 7-12. Input Offset Current vs Temperature
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SBOS385B – AUGUST 2019 – REVISED APRIL 2021
7.7 Typical Characteristics (continued)
3500
3500
3000
3000
2500
2500
Input Bias Current (pA)
Input Bias Current (pA)
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
2000
1500
1000
500
0
-500
-1500
-60
-40
-20
0
20
Common-Mode Voltage (V)
40
1500
1000
500
0
-500
40qC
25qC
125 qC
-1000
2000
60
D013
-1500
-30 -25 -20 -15 -10 -5
0
5 10 15
Common-Mode Voltage (V)
20
25
30
D014
G=2
G = 1/2
Figure 7-13. Input Bias Current vs Common-Mode Voltage
Figure 7-14. Input Bias Current vs Common-Mode Voltage
30
30
25
25
Total Amplifiers (%)
Total Amplifiers (%)
40qC
25qC
125qC
-1000
20
15
10
20
15
10
5
5
0
-40
-32
-24
-16
-8
0
8
16
24
32
Common-Mode Rejection Ratio (PV/V)
N = 470
Mean = 6.01 μV/V
G = 1/2
VS = ±2.25 V
0
-80
40
-60
Std. Dev. = 4.85 μV/V
-40
-20
0
20
40
60
Common-Mode Rejection Ratio (PV/V)
D015
N = 470
Mean = –6.22 μV/V
G= 2
VS = ±2.25 V
Figure 7-15. Typical CMRR Distribution
80
D016
Std. Dev. = 10.74 μV/V
Figure 7-16. Typical CMRR Distribution
40
30
25
Total Amplifiers (%)
Total Amplifiers (%)
30
20
10
20
15
10
5
0
-40
-32
-24
-16
-8
0
8
16
24
32
Common-Mode Rejection Ratio (PV/V)
N = 470
Mean = 4.86 μV/V
0
-80
40
Std. Dev. = 4.75 μV/V
G = 1/2
-60
-40
-20
0
20
40
60
Common-Mode Rejection Ratio (PV/V)
D017
N = 470
Mean = –8.64 μV/V
80
D018
Std. Dev. = 9.70 μV/V
G=2
Figure 7-17. Typical CMRR Distribution
Figure 7-18. Typical CMRR Distribution
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7.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
35
Common-Mode Rejection Ratio (PV/V)
Common-Mode Rejection Ratio (PV/V)
-5
-10
-15
-20
-25
-30
-40
-20
0
G = 1/2
20
40
60
80
Temperature (qC)
100
120
30
25
20
15
10
5
0
-5
-10
-15
-40
140
24 units
0
20
G=2
Figure 7-19. CMRR vs Temperature
40
60
80
Temperature (qC)
100
120
140
D020
24 units
Figure 7-20. CMRR vs Temperature
40
120
G = 1/2
G=2
VS = ±18 V
VS = ±4 V
35
Output Voltage (VPP )
100
Rejection Ratio (dB)
-20
D019
80
60
30
25
20
15
10
40
5
20
100m
0
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
1
10
100
1k
10k
Frequency (Hz)
D056
100k
1M
10M
G = 1/2 and G = 2
Figure 7-22. Maximum Output Voltage vs Frequency
Figure 7-21. Common-Mode Rejection Ratio vs Frequency,
Referred-to-Input
1.8
Power Supply Rejection Ratio (PV/V)
Power Supply Rejection Ratio (PV/V)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-40
-20
G = 1/2
0
20
40
60
80
Temperature (qC)
100
24 units
120
140
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-40
D023
G=2
0
20
40
60
80
Temperature (qC)
100
120
140
D024
24 units
Figure 7-24. PSRR vs Temperature
Figure 7-23. PSRR vs Temperature
12
-20
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SBOS385B – AUGUST 2019 – REVISED APRIL 2021
7.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
140
PSRR+
PSRR ̶
120
PSRR+
PSRR ̶
120
100
Rejection Ratio (dB)
Power Supply Rejection Ratio (dB)
140
80
60
40
100
80
60
40
20
20
0
0
1
10
100
1k
10k
Frequency (Hz)
100k
1M
1
10M
G = 1/2
10
100k
1M
10M
Figure 7-26. PSRR vs Frequency (RTI)
50
50
40
40
Total Amplifiers (%)
Total Amplifiers (%)
1k
10k
Frequency (Hz)
G=2
Figure 7-25. PSRR vs Frequency (RTI)
30
20
10
30
20
10
0
0
0.005
0.01
0.015
0.02
0.025
N = 470
Mean = 0.0085%
0
-0.03
0.03
Gain Error (%)
-0.025
-0.02
Std. Dev. = 0.0014%
-0.015
-0.01
-0.005
Gain Error (%)
D027
N = 470
G = 1/2
Mean = –0.0076%
0
D028
Std. Dev. = 0.0015%
G=2
Figure 7-27. Typical Distribution of Gain Error
Figure 7-28. Typical Distribution of Gain Error
0.01
1
Gain Error (%)
0.008
.8
Gain Error (%)
100
0.006
.6
0.004
.4
0.002
.2
-40
-20
G = 1 /2
0
20
40
60
80
Temperature (qC)
100
120
140
-0.002
-0.0025
-0.003
-0.0035
-0.004
-0.0045
-0.005
-0.0055
-0.006
-0.0065
-0.007
-0.0075
-0.008
-0.0085
-0.009
-0.0095
-0.01
-40
D029
G=2
30 units
Figure 7-29. Gain Error vs Temperature
-20
0
20
40
60
80
Temperature (qC)
100
120
140
D030
30 units
Figure 7-30. Gain Error vs Temperature
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7.7 Typical Characteristics (continued)
10
20
0
10
Gain (dB)
Gain (dB)
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
-10
0
-10
-20
CLOAD = 20 pF
CLOAD = 100 pF
CLOAD = 20 pF
CLOAD = 100 pF
-30
100
1k
10k
100k
Frequency (Hz)
1M
-20
100
10M
1000
10M
D032
1000
Voltage Noise Density (nV/—Hz)
Voltage Noise Density (nV/—Hz)
1M
Figure 7-32. Closed-Loop Gain vs Frequency
Figure 7-31. Closed-Loop Gain vs Frequency
100
10
1
10
100
1k
Frequency (Hz)
10k
100
10
1
100m
100k
D033
1
10
100
1k
Frequency (Hz)
10k
100k
D034
G=2
G = 1/2
Figure 7-34. Voltage Noise Spectral Density vs Frequency (RTI)
Input Referred Voltage Noise (1 nV/div)
Input Referred Voltage Noise (500 nV/div)
Figure 7-33. Voltage Noise Spectral Density vs Frequency (RTI)
Time (1 s/div)
Time (1 s/div)
G=2
G = 1/2
Figure 7-35. 0.1-Hz to 10-Hz RTI Voltage Noise
14
10k
100k
Frequency (Hz)
G=2
G = 1/2
1
100m
1k
D031
Figure 7-36. 0.1-Hz to 10-Hz RTI Voltage Noise
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SBOS385B – AUGUST 2019 – REVISED APRIL 2021
7.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
100
Noise Voltage (PVrms)
Noise Voltage (PVrms)
100
10
1
1
10
100
1k
Frequency (Hz)
10k
1
100k
18
17.5
17
16.5
16
15.5
15
14.5
14
13.5
13
12.5
12
11.5
10k
100k
D038
Figure 7-38. Integrated Output Voltage Noise vs Noise
Bandwidth
Vout ( V )
-40qC
25qC
85qC
125qC
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75
ILoad (mA)
18
17.5
17
16.5
16
15.5
15
14.5
14
13.5
13
12.5
12
11.5
-40qC
25qC
85qC
125qC
0
G = 1/2
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75
ILoad ( mA )
G=2
Figure 7-39. Positive Output Voltage vs Output Current
(Sourcing)
Figure 7-40. Positive Output Voltage vs Output Current
(Sourcing)
-40qC
25qC
85qC
125qC
Vout ( V )
-14
-14.25
-14.5
-14.75
-15
-15.25
-15.5
-15.75
-16
-16.25
-16.5
-16.75
-17
-17.25
-17.5
-17.75
-18
-5
100
1k
Frequency (Hz)
G=2
Figure 7-37. Integrated Output Voltage Noise vs Noise
Bandwidth
0
10
D037
G = 1/2
VOUT (V)
1
0.1
0.1
Vout ( V )
10
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75
ILoad ( mA )
G = 1/2
-14
-14.25
-14.5
-14.75
-15
-15.25
-15.5
-15.75
-16
-16.25
-16.5
-16.75
-17
-17.25
-17.5
-17.75
-18
-40qC
25qC
85qC
125qC
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75
ILoad ( mA )
G=2
Figure 7-41. Negative Output Voltage vs Output Current
(Sinking)
Figure 7-42. Negative Output Voltage vs Output Current
(Sinking)
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7.7 Typical Characteristics (continued)
Output Delta from Final Value (1 mV/div)
Output Delta from Final Value (1 mV/div)
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
Falling
Rising
Falling
Rising
Time (1 Ps/div)
Time (1 Ps/div)
D044
D043
G = 1/2
G=2
Figure 7-43. Settling Time
Figure 7-44. Settling Time
VIN
VIN +
VOUT
Output Voltage (4 V/div)
Output Voltage (2 V/div)
VIN–
VIN+
VOUT
Time (1 μs/div)
Time (1 Ps/div)
D046
G=2
G = 1/2
Figure 7-46. Large-Signal Step Response
Figure 7-45. Large-Signal Step Response
30
Negative
Positive
24
Voltage (5 V/div)
Slewrate (V/Ps)
Rising
Falling
18
12
-60
-35
-10
15
40
65
Temperature (qC)
90
115
Time (200 μs/div)
D047
Figure 7-47. Slew Rate Over Temperature
16
140
Figure 7-48. Overload Recovery (Normalized to 0 V)
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7.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
80
80
RISO = 0 Ω
RISO = 25 Ω
RISO = 50 Ω
70
60
Overshoot ( %)
60
50
40
30
50
40
30
20
20
10
10
0
10
100
Capacitance (pF)
0
10
1000
G = 1/2
100
Capacitance (pF)
G=2
Figure 7-49. Small-Signal Overshoot vs Capacitive Load
Figure 7-50. Small-Signal Overshoot vs Capacitive Load
VIN–
VIN+
VOUT
Output Voltage (2 mV/div)
Output Voltage (4 mV/div)
VIN
VIN +
VOUT
Time (1 Ps/div)
Time (1 μs/div)
D051
G=2
G = 1/2
Figure 7-52. Small-Signal Step Response
-40
-60
0.01
-80
0.001
-100
-120
0.0001
100
G = 1/2
1k
Frequency (Hz)
VOUT = 3.5 VRMS
Noise (dB)
0.1
-40
1
Total Harmonic Distortion
RL = 10 k:
RL = 2 k:
RL = 600 :
Total Harmonic Distortion + Noise (%)
1
RL = 10 k:
RL = 2 k:
RL = 600 :
0.1
-60
0.01
-80
0.001
-100
-120
0.0001
10k
100
D053
G=2
Figure 7-53. THD+N vs Frequency
Noise (dB)
Figure 7-51. Small-Signal Step Response
Total Harmonic Distortion + Noise ( )
1000
Total Harmonic Distortion
Overshoot ( %)
RISO = 0 Ω
RISO = 25 Ω
RISO = 50 Ω
70
1k
Frequency (Hz)
10k
D054
VOUT = 3.5 VRMS
Figure 7-54. THD+N vs Frequency
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7.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
-60
0.01
-80
0.001
-100
-120
0.0001
10m
100m
1
Output Amplitude (VRMS)
10
-40
RL = 10 k:
RL = 2 k:
RL = 600 :
0.1
-60
0.01
-80
0.001
-100
-120
0.0001
10m
100m
1
Output Amplitude (VRMS)
D055
G = 1/2
Total Harmonic Distortion + Noise (dB)
0.1
1
Total Harmonic Distortion + Noise (%)
-40
RL = 10 k:
RL = 2 k:
RL = 600 :
Total Harmonic Distortion + Noise (dB)
Total Harmonic Distortion + Noise (%)
1
10
D056
G=2
Figure 7-55. THD+N Ratio vs Output Amplitude
Figure 7-56. THD+N Ratio vs Output Amplitude
1.07
1.1
1.06
1.05
Quiescent Current (mA)
Quiescent Current (mA)
1.08
1.06
1.04
1.02
1.04
1.03
1.02
1.01
1
0.99
0.98
1
0.97
0.98
-40
-20
0
G = 1/2
20
40
60
80
Temperature (qC)
100
120
0.96
-40
140
30 units
20
40
60
80
Temperature (qC)
100
120
140
D058
30 units
Figure 7-58. Supply Current vs Temperature
5
5
4.5
4.5
4
4
Quiescent Current (mA)
Quiescent Current (mA)
0
G=2
Figure 7-57. Supply Current vs Temperature
3.5
3
2.5
2
1.5
1
3.5
3
2.5
2
1.5
1
0.5
0.5
0
0
-0.5
0
G = 1/2
5
10
15
20
25
Total Supply (V)
30
35
40
0
D059
G=2
30 units
Figure 7-59. Supply Current vs Supply Voltage
18
-20
D057
5
10
15
20
25
Total Supply (V)
30
35
40
D060
30 units
Figure 7-60. Supply Current vs Supply Voltage
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7.7 Typical Characteristics (continued)
90
90
60
60
Short Circuit Current (mA)
Short Circuit Current (mA)
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
30
0
-30
G = 1/2
-20
0
20
40
60
80
Temperature (qC)
100
120
D061
G=2
30 units
EMI Rejection Ratio (dB)
EMI Rejection Ratio (dB)
0
20
40
60
80
Temperature (qC)
100
120
140
D062
30 units
160
140
130
120
110
100
100M
1G
Frequency (Hz)
140
120
100
80
60
10M
10G
100M
1G
10G
Frequency (Hz)
G = 1/2
G=2
Figure 7-63. Differential-Mode EMI Rejection Ratio
Figure 7-64. Differential-Mode EMI Rejection Ratio
140
160
130
EMI Rejection Ratio (dB)
180
140
120
100
80
60
10M
-20
Figure 7-62. Short Circuit Current vs Temperature
150
EMI Rejection Ratio (dB)
-30
-90
-40
140
Figure 7-61. Short Circuit Current vs Temperature
90
10M
0
-60
-60
-90
-40
30
120
110
100
90
80
100M
1G
Frequency (Hz)
10G
70
10M
G = 1/2
100M
1G
10G
Frequency (Hz)
D065
G=2
Figure 7-65. Common-Mode EMI Rejection Ratio
Figure 7-66. Common-Mode EMI Rejection Ratio
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7.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
80
40
VS = r2.25 V
VS = r18 V
40
20
0
-20
-40
-60
-16
-12
G = 1/2
-8
-4
0
4
Output Voltage (V)
8
Bipolar supply
12
16
0
-10
-20
VREF = 0 V
15
7.5
10
5
0
-5
1.25
2.5
3.75
Output Voltage (V)
G = 1/2
5-V supply
-5
0
5
Output Voltage (V)
5
Bipolar supply
VREF = 0 V
0
1.25
2.5
3.75
Output Voltage (V)
50
Common-Mode Voltage (V)
60
0
-20
5-V supply
5
6.25
D070
VREF = 0 V
Figure 7-70. Input Common-Mode Voltage vs Output Voltage
100
20
VREF = 0 V
-2.5
120
40
D068
0
G=2
60
20
2.5
D069
80
15
5
-5
-1.25
6.25
Figure 7-69. Input Common-Mode Voltage vs Output Voltage
10
Figure 7-68. Input Common-Mode Voltage vs Output Voltage
10
0
-10
G=2
20
-10
-1.25
-15
D067
Common-Mode Voltage (V)
Common-Mode Voltage (V)
10
-40
-20
20
Figure 7-67. Input Common-Mode Voltage vs Output Voltage
Common-Mode Voltage (V)
20
-30
-80
-20
40
30
20
10
0
-10
-40
-60
-20
0
G = 1/2
4
8
12
16
20
24
28
Output Voltage (V)
36-V supply
32
36
40
0
D071
VREF = 0 V
Figure 7-71. Input Common-Mode Voltage vs Output Voltage
20
VS = r2.25 V
VS = r18 V
30
Common-Mode Voltage (V)
Common-Mode Voltage (V)
60
G=2
4
8
12
16
20
24
28
Output Voltage (V)
36-V supply
32
36
40
D072
VREF = 0 V
Figure 7-72. Input Common-Mode Voltage vs Output Voltage
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7.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
1000
Output Impedance (:)
100
10
1
0.1
0.01
0.001
G=2
G = 0.5
0.0001
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
D073
Figure 7-73. Closed-Loop Output Impedance vs Frequency
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8 Detailed Description
8.1 Overview
The INA597 consists of a high-precision, e-trim™ operational amplifier and four trimmed resistors. These
resistors can be connected to make a wide variety of amplifier configurations, including difference, noninverting,
and inverting configurations. Using the on-chip resistors of the INA597 provides the designer with several
advantages over a discrete design. The INA597 also includes internal compensation capacitors, as shown in
Section 8.2.
8.2 Functional Block Diagram
V+
INA597
12 k
6k
SENSE
±IN
16 pF
±
OUT
+
16 pF
12 k
6k
V±
+IN
REF
V±
8.3 Feature Description
Much of the dc performance of op-amp circuits depends on the accuracy of the surrounding resistors. The
resistors on the INA597 are laid out to be tightly matched. The resistors of each part are matched on-chip and
tested for their matching accuracy. As a result of this trimming and testing, the INA597 provides high accuracy
for specifications such as gain drift, common-mode rejection, and gain error.
8.4 Device Functional Modes
The INA597 measures voltages beyond the rails. For the G = ½ and G = 2 difference amplifier configurations,
see the input voltage range in Section 7 for details. The INA597 can be configured in several ways; see
Figure 9-5 to Figure 9-9. These configurations rely on the internal, matched resistors; therefore, all of these
configurations have excellent gain accuracy and gain drift.
22
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
Figure 9-1 shows the basic connections required for operation of the INA597. Connect power supply bypass
capacitors close to the device pins.
The differential input signal is connected to pins 2 and 3, as shown. The source impedances connected to the
inputs must be nearly equal to provide good common-mode rejection. An 8-Ω mismatch in source impedance
degrades the common-mode rejection of a typical device to approximately 80 dB. Gain accuracy is also slightly
affected. If the source has a known impedance mismatch, use an additional resistor in series with one input to
preserve good common-mode rejection.
9.2 Typical Applications
9.2.1 Basic Power-Supply and Signal Connections
V+
V–
1 µF
1 µF
7
4
INA597
V2
V3
2
3
R1
R2
12 kW
6 kW
5
6
R3
RL
12 kW
R4
6 kW
VOUT = V3 – V2
1
REF
Figure 9-1. Basic Power-Supply and Signal Connections
9.2.1.1 Design Requirements
For the application shown in Figure 9-1, the design requirements are:
•
•
Gain of G = ½
VREF = 0 V
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9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Operating Voltage
The INA597 operates from single (4.5 V to 36 V) or dual (±2.25 V to ±18 V) supplies with excellent
performance. Specifications are production tested with +5-V and ±15-V supplies. Most behavior remains
unchanged throughout the full operating voltage range. Parameters that vary significantly with operating voltage
are shown in Section 7.7. The internal op amp in the INA597 is a single-supply design. This design allows linear
operation with the op amp common-mode voltage equal to, or slightly less than V– (or single-supply ground).
Although input voltages on pins 2 and 3 that are less than the negative supply voltage do not damage the
device, operation in this region is not recommended. Transient conditions at the inverting input terminal less than
the negative supply can cause a positive feedback condition that could lock the device output to the negative rail.
The INA597 accurately measures differential signals that are greater than the positive power supply. For
example with G = ½, the linear common-mode range extends to nearly three times the positive power supply
voltage; see Section 7.7, as well as Section 9.2.1.2.3.
9.2.1.2.2 Offset Voltage Trim
The INA597 is production trimmed for low offset voltage and drift. Most applications require no external offset
adjustment. Figure 9-2 shows an optional circuit for trimming the output offset voltage. The output is referred to
the output reference terminal (pin 1), which is normally grounded. A voltage applied to the REF pin is summed
with the output signal. This configuration can be used to null offset voltage. To maintain good common-mode
rejection, make sure the source impedance of a signal applied to the REF pin is less than 8 Ω. For low
impedance at the REF pin, the trim voltage can be buffered with an op amp, such as the OPA177.
INA597
2
V2
R1
R2
5
6
8W
V3
3
VO
R3
R4
+15 V
VO = V3 – V2
Offset Adjustment
Range = ±500 µV
REF
1
R = 237 kW
100 kW
8W
–15 V
NOTE: For ±750-µV range, R = 158 kW.
Figure 9-2. Offset Adjustment
24
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9.2.1.2.3 Input Voltage Range
The INA597 measures input voltages beyond the supply rails. The internal resistors divide down the voltage
before the voltage reaches the internal op amp and provide protection to the op amp inputs. Figure 9-3 shows
an example of how the voltage division works in a difference-amplifier configuration. For the INA597 to measure
correctly, the input voltages at the input nodes of the internal op amp must stay less than 0.1 V of the positive
supply rail, and can exceed the negative supply rail by 0.1 V. See Section 10 for more details.
INOP
R4
˜V
R3 R4
R3
IN
R4
V±IN
SENSE
±IN
±
OUT
+
R1
R2
V+IN
+IN
REF
INOP
R2
˜V
R1 R2
IN
Figure 9-3. Voltage Division in the Difference Amplifier Configuration
The INA597 has integrated ESD diodes at the inputs that provide overvoltage protection. This feature simplifies
system design by eliminating the need for additional external protection circuitry, and enables a more robust
system. The voltages at any of the inputs of the parts in G = ½ configuration with ±18 V supplies can safely
range from +VS − 54 V up to −VS + 54 V. For example, on ±10-V supplies, the input voltages can go as high as
±30 V.
9.2.1.2.4 Capacitive Load Drive Capability
The INA597 can drive large capacitive loads, even at low supplies. The device is stable with a 500-pF load; see
Section 7.7.
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9.2.1.3 Application Curve
The interaction between the output stage of an operational amplifier (op amp) and capacitive loads can impact
the stability of the circuit. Throughout the industry, op-amp output-stage requirements have changed greatly
since their original creation. Classic output stages with the class-AB common-emitter bipolar junction transistor
(BJT) have now been replaced with common-collector BJT and common-drain complementary metal-oxide
semiconductor (CMOS) devices. Both of these technologies enable rail-to-rail output voltages for single-supply
and battery-powered applications. A result of changing these output-stage structures is that the op-amp
open-loop output impedance (Zo) changed from the largely resistive behavior of early BJT op amps to a
frequency-dependent ZO that features capacitive, resistive, and inductive portions. Proper understanding of
ZO over frequency—and also the resulting closed-loop output impedance over frequency—is crucial for the
understanding of loop gain, bandwidth, and stability analysis. Figure 9-4 shows how the INA597 closed-loop
output impedance varies over frequency.
1000
Output Impedance (:)
100
10
1
0.1
0.01
0.001
G=2
G = 0.5
0.0001
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
D073
VS = ±18 V
Figure 9-4. Closed-Loop Output Impedance vs Frequency
26
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9.2.2 Precision Instrumentation Amplifier
The INA597 can be combined with op amps to form a complete instrumentation amplifier (IA) with specialized
performance characteristics, as shown in Figure 9-5.
V1
INA597
–IN
A1
5
2
R2
6
R1
VO
R2
1
3
A2
V2
+IN
VO = (1 + 2R2 / R 1) (V2 – V1)
Figure 9-5. Precision Instrumentation Amplifier
9.2.3 Low Power, High-Output Current, Precision, Difference Amplifier
BUF634 inside feedback
loop contributes no error.
INA597
–IN
2
5
6
+IN
1
3
VO
BUF634
(Low IQ mode)
RL
Figure 9-6. Low Power, High-Output Current, Precision, Difference Amplifier
9.2.4 Pseudoground Generator
V+
V+
3
INA597
2
5
7
6
Ground
1
4
(V+) / 2
Ground
Figure 9-7. Pseudoground Generator
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9.2.5 Differential Input Data Acquisition
5V
7
INA597
–IN
2
5
6
+IN
1
3
4
12 Bits
Out
ADS7806
0-V to 4-V
Input
VCM = 0 V to 8 V
tS = 45 µs (4-V Step to 0.01%)
Figure 9-8. Differential Input Data Acquisition
9.2.6 Precision Voltage-to-Current Conversion
V+
12.5 k
1k
0-V to 10-V in
7
50 k
±
5
6k
12 k
+
V±IN
R1
R2
Set R1 = R2
2
15 V
±
6
+
OPA192
2
VOUT
INA597
REF10
6
10 V
R3
1
V+IN
R4
6k
12 k
4
3
R1
50.1
VREF
R2
50.1
IOUT = 4 mA to 20 mA
RL
4
For 4-mA to 20-mA applications,
the REF10 sets the 4-mA,
low-scale output for the 0-V input.
IOUT
2N3904
2˜ V
IN
V
IN
§ 1
¨
© 40 k:
1 ·
¸
R2 ¹
Figure 9-9. Precision Voltage-to-Current Conversion
28
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9.2.7 Additional Applications
Texas Instruments offers many complete high-performance instrumentation amplifiers. See Table 9-1 for some of
the products with related performance.
Table 9-1. Recommended Op Amp Products to Use With the INA597
A1, A2
FEATURE
SIMILAR TI IA
OPA27
Low noise
INA103
OPA129
Ultra-low bias current (fA)
INA116
OPA177
Low offset drift, low noise
INA114, INA128
OPA2130
Low power, FET-input (pA)
INA111
OPA2234
Single supply, precision, low power
INA122. INA118
OPA2237
SIngle supply, low power, 8-pin MSOP
INA122, INA126
The difference amplifier is a highly versatile building block that is useful in a wide variety of applications. See the
INA105 data sheet for additional applications ideas, including:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Current receiver with compliance to rails
Precision unity-gain inverting amplifier
±10-V precision voltage reference
±5-V precision voltage reference
Precision unity-gain buffer
Precision average value amplifier
Precision G = 2 amplifier
Precision summing amplifier
Precision G = 1/2 amplifier
Precision bipolar offsetting
Precision summing amplifier with gain
Instrumentation amplifier guard drive generator
Precision summing instrumentation amplifier
Precision absolute value buffer
Precision voltage-to-current converter with differential inputs
Differential input voltage-to-current converter for low IOUT
Isolating current source
Differential output difference amplifier
Isolating current source with buffering amplifier for greater accuracy
Window comparator with window span and window center inputs
Precision voltage-controlled current source with buffered differential inputs and gain
Digitally controlled gain of ±1 amplifier
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10 Power Supply Recommendations
The nominal performance of the INA597 is specified with a supply voltage of ±15 V and midsupply reference
voltage. The device operates using power supplies from ±2.25 V (4.5 V) to ±18 V (36 V) and non-midsupply
reference voltages with excellent performance. Parameters that can vary significantly with operating voltage and
reference voltage are shown in Section 7.7.
11 Layout
11.1 Layout Guidelines
Attention to good layout practices is always recommended. For best operational performance of the device, use
good PCB layout practices, including:
•
•
•
•
•
30
Take care to make sure that both input paths are well-matched for source impedance and capacitance to
avoid converting common-mode signals into differential signals.
Noise propagates into analog circuitry through the power pins of the circuit as a whole and of the device.
Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the analog
circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible.
If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in
parallel with the noisy trace.
Place the external components as close to the device as possible.
Keep the traces as short as possible.
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11.2 Layout Example
V±
V+
1 F
1 F
C1
3
+IN
VOUT
12 k
6k
R1
R2
SENSE
6
OUT
R3
R4
12 k
6k
1
˜ V
2
5
+
V+IN
2
±IN
C2
7
±
V±IN
4
RL
1
VREF = GND
REF
V
IN
VOUT
IN
+V
Use ground pours for
shielding the input signal
pairs
Low-impedance
connection for reference
terminal
GND
C2
INA597
2
+IN
3
±IN
NC
8
V+
7
+
±IN
REF
±
1
+IN
OUT
6
VOUT
4
V±
SENSE
5
C1
GND
RL
Place bypass capacitors
as close to IC as
possible
GND
±V
Figure 11-1. Example Schematic and Associated PCB Layout for SOIC and VSSOP Packages
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V±
V+
1 F
1 F
C1
12 k
6k
R1
R2
1
-INOP
10
+INOP
4
V+IN
+IN
VOUT
OUT
R4
12 k
6k
IN
SENSE
7
R3
1
˜ V
2
6
+
3
±IN
C2
8
±
V±IN
5
VOUT
RL
2
VREF = GND
REF
V
IN
Low-impedance
connection for
reference terminal
INA597
í INOP
1
REF
REF
2
±IN
±IN
3
+IN
+IN
4
10 NC
±
GND
+INOP
9
NC
8
V+
+
V±
5
7
+INOP
6
OUT
C2
SENSE
GND
C1
Use ground pours
for shielding
the input
signal pairs
±V
NC= No Connection
RL
Place bypass capacitors
as close to IC as
possible
Figure 11-2. Example Schematic and Associated PCB Layout with VSON Package
32
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Universal Difference Amplifier Evaluation Module user's guide
• Texas Instruments, Precision Signal-Conditioning Solutions for Motor-Control Position Feedback technical
brief
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
e-trim™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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20-Jun-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
INA597IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1WT6
INA597IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1WT6
INA597IDR
ACTIVE
SOIC
D
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
INA597IDRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
IN597
INA597IDRCT
ACTIVE
VSON
DRC
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
IN597
INA597IDT
ACTIVE
SOIC
D
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
INA597
INA597
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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