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INA828
SBOS792A – AUGUST 2017 – REVISED JANUARY 2018
INA828 50-µV Offset, 7-nV/√Hz Noise, Low-Power, Precision Instrumentation Amplifier
1 Features
3 Description
•
The INA828 is a high-precision instrumentation
amplifier that offers low power consumption and
operates over a very wide single- or dual-supply
range. A single external resistor sets any gain from 1
to 1000. The device offers excellent precision due to
the use of new super-beta input transistors which
provide exceptionally low input offset voltage, offset
voltage drift, input bias current, and input voltage and
current noise. Additional circuitry protects the inputs
against overvoltage up to ±40 V.
1
•
•
•
•
•
•
•
•
•
•
•
•
Precision Instrumentation Amplifier Evolution:
– Second Generation: INA828
– First Generation: INA128
Low Offset Voltage: 50 µV, MAX
Gain Drift: 5 ppm/°C (G = 1), 50 ppm/°C (G > 1)
Noise: 7 nV/√Hz
Bandwidth: 2 MHz (G = 1), 260 kHz (G = 100)
Stable with 1-nF Capacitive Loads
Inputs Protected Up to ±40 V
Common-Mode Rejection:
– 110 dB, MIN (G = 10)
Power-Supply Rejection: 100 dB, MIN (G = 1)
Supply Current: 650 µA, MAX
Supply Range:
– Single Supply: 4.5 V to 36 V
– Dual Supply: ±2.25 V to ±18 V
Specified Temperature Range:
–40°C to +125°C
Package: 8-Pin SOIC
The INA828 is optimized to provide excellent
common-mode rejection ratio. At G = 1, the commonmode rejection ratio exceeds 90 dB across the full
input common-mode range. The device is well-suited
for low-voltage operation from a 5-V single supply as
well as dual supplies up to ±18 V. Finally, INA828 is
available in an 8-pin SOIC package and specified
over the –40°C to +125°C temperature range.
Device Information(1)
PART NUMBER
INA828
PACKAGE
SOIC (8)
BODY SIZE (NOM)
4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
Industrial Process Controls
Circuit Breakers
Battery Testers
ECG Amplifiers
Power Automation
Medical Instrumentation
Portable Instrumentation
INA828 Simplified Internal Schematic
Typical Distribution of Input Offset Voltage Drift
+VS
Overvoltage
Protection
RG
40 k
3500
±
3000
25 k
±
25 k
+
OUT
Overvoltage
Protection
2500
2000
1500
±
RG
+IN
4000
40 k
+
Count
-IN
4500
REF
+
40 k
1000
40 k
500
-VS
Copyright © 2017, Texas Instruments Incorporated
0
-0.5
-0.45
-0.4
-0.35
-0.3
-0.25
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
•
•
•
•
•
•
•
Input Offset Voltage Drift ( V/ƒC)
C001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA828
SBOS792A – AUGUST 2017 – REVISED JANUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Detailed Description ............................................ 16
7.1
7.2
7.3
7.4
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
16
16
17
21
Application and Implementation ........................ 22
8.1
8.2
8.3
8.4
8.5
Reference Terminal.................................................
Input Bias Current Return Path...............................
PCB Assembly Effects on Precision .......................
Typical Application ..................................................
Other Application Examples....................................
22
24
25
26
28
9 Power Supply Recommendations...................... 29
10 Layout................................................................... 29
10.1 Layout Guidelines ................................................. 29
10.2 Layout Example .................................................... 30
11 Device and Documentation Support ................. 31
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
31
31
12 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
Changes from Original (August 2017) to Revision A
•
2
Page
Changed MAX value for G = 1 in "GE" row from "±0.020%" to "±0.025%"............................................................................ 5
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SBOS792A – AUGUST 2017 – REVISED JANUARY 2018
5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
1
RG
RG
8
2
±IN
+VS
7
3
+IN
OUT
6
4
-VS
REF
5
Pin Functions
PIN
NAME
RG
NO.
1
8
–IN
2
+IN
–VS
I/O
—
DESCRIPTION
Gain setting pin. Place a gain resistor between pin 1 and pin 8.
I
Negative (inverting) input
3
I
Positive (noninverting) input
4
—
REF
5
I
Reference input. This pin must be driven by a low impedance source.
OUT
6
O
Output
+VS
7
—
Positive supply
Negative supply
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SBOS792A – AUGUST 2017 – REVISED JANUARY 2018
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
–18
18
V
Voltage
–40
40
REF pin
–18
18
Supply voltage
Signal input pins
Output short-circuit (2)
Continuous
Operating, TA
Temperature
–50
(2)
150
Junction, TJ
175
Storage, Tstg
(1)
V
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Short-circuit to VS / 2.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±1500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±750
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
4.5
36
±2.25
±18
Specified temperature
–40
125
°C
Operating temperature
–50
150
°C
Single supply
Supply voltage
Dual supply
UNIT
V
6.4 Thermal Information
INA828
THERMAL METRIC (1)
D (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
119.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
66.3
°C/W
RθJB
Junction-to-board thermal resistance
61.9
°C/W
ψJT
Junction-to-top characterization parameter
20.5
°C/W
ψJB
Junction-to-board characterization parameter
61.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS792A – AUGUST 2017 – REVISED JANUARY 2018
6.5 Electrical Characteristics
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
20
50
UNIT
INPUT
G = 100, RTI
Input stage offset
voltage (1) (2)
VOSI
90
µV
vs temperature, TA = –40°C to +125°C
0.5
µV/°C
250
µV
G = 1, RTI
VOSO
Output stage offset
voltage (1) (2)
50
TA = –40°C to +125°C (3)
500
vs temperature, TA = –40°C to +125°C
PSRR
Power-supply rejection
ratio
zid
Differential impedance
zic
Common-mode impedance
5
G = 1, RTI
110
120
G = 10, RTI
114
130
G = 100, RTI
130
135
G = 1000, RTI
136
RFI filter, –3-dB frequency
Operating input range (4)
VCM
Input overvoltage range
CMRR
Common-mode rejection
ratio
µV
TA = –40°C to +125°C (3)
µV
µV/°C
dB
140
100 || 1
GΩ || pF
100 || 10
GΩ || pF
53
(V–) + 2
VS = ±2.25 V to ±18 V, TA = –40°C to +125°C
MHz
(V+) – 2
V
See Figure 48 to Figure 51
TA = –40°C to +125°C
±40
At dc to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) – 2 V,
G=1
90
100
At dc to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) – 2 V,
G = 10
110
120
At dc to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) – 2 V,
G = 100
130
140
At dc to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) – 2 V,
G = 1000
140
145
V
dB
BIAS CURRENT
IB
Input bias current
IOS
Input offset current
VCM = VS / 2
0.15
TA = –40°C to +125°C
0.6
nA
2
VCM = VS / 2
0.15
TA = –40°C to +125°C
0.6
nA
2
NOISE VOLTAGE
eNI
eNO
In
Input stage voltage
noise (5)
f = 1 kHz, G = 100, RS = 0 Ω
Output stage voltage
noise (5)
f = 1 kHz, RS = 0 Ω
Noise current
7
fB = 0.1 Hz to 10 Hz, G = 100, RS = 0 Ω
nV/√Hz
0.14
µVPP
90
nV/√Hz
fB = 0.1 Hz to 10 Hz, RS = 0 Ω
7.7
µVPP
f = 1 kHz
170
fA/√Hz
fB = 0.1 Hz to 10 Hz, G = 100
4.7
pAPP
GAIN
G
Gain equation
1 + (50 kΩ / RG)
Range of gain
GE
Gain error
Gain vs temperature (6)
(1)
(2)
(3)
(4)
(5)
(6)
1
V/V
1000
G = 1, VO = ±10 V
±0.005%
±0.025%
G = 10, VO = ±10 V
±0.025%
±0.15%
G = 100, VO = ±10 V
±0.025%
±0.15%
G = 1000, VO = ±10 V
±0.05%
G = 1, TA = –40°C to +125°C
±5
G > 1, TA = –40°C to +125°C
±50
V/V
ppm/°C
Total offset, referred-to-input (RTI): VOS = (VOSI) + (VOSO / G).
Offset drifts are uncorrelated. Input-referred offset drift is calculated using: ΔVOS(RTI) = √[ΔVOSI2 + (ΔVOSO / G)2]
Specified by characterization.
Input voltage range of the INA828 input stage. The input range depends on the common-mode voltage, differential voltage, gain, and
reference voltage. See Typical Characteristic curves Figure 48 through Figure 51 for more information.
Total RTI voltage noise is equal to: eN(RTI) = √[eNI2 + (eNO / G)2]
The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
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Electrical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
G = 1 to 10, VO = –10 V to +10 V, RL = 10 kΩ
Gain nonlinearity
TYP
MAX
1
10
G = 100, VO = –10 V to +10 V, RL = 10 kΩ
15
G = 1000, VO = –10 V to +10 V, RL = 10 kΩ
20
G = 1 to 100, VO = –10 V to +10 V, RL = 2 kΩ
UNIT
ppm
30
OUTPUT
Voltage swing
(V–) + 0.15
Load capacitance stability
(V+) – 0.15
V
1000
pF
ZO
Closed-loop output
impedance
f = 10 kHz
1.3
Ω
ISC
Short-circuit current
Continuous to VS / 2
±18
mA
G=1
2.0
MHz
G = 10
640
G = 100
260
G = 1000
33
G = 1, VO = ±10 V
1.2
0.01%, G = 1 to 100, VSTEP = 10 V
12
0.01%, G = 1000, VSTEP = 10 V
40
0.001%, G = 1 to 100, VSTEP = 10 V
16
0.001%, G = 1000, VSTEP = 10 V
50
FREQUENCY RESPONSE
BW
SR
tS
Bandwidth, –3 dB
Slew rate
Settling time
kHz
V/µs
µs
REFERENCE INPUT
RIN
Input impedance
40
Voltage range
(V–)
Gain to output
kΩ
(V+)
1
Reference gain error
V
V/V
0.01%
POWER SUPPLY
VS
Power-supply voltage
IQ
Quiescent current
6
Single supply
Dual supply
VIN = 0 V
4.5
36
±2.25
±18
600
vs temperature, TA = –40°C to +125°C
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650
850
V
µA
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SBOS792A – AUGUST 2017 – REVISED JANUARY 2018
6.6 Typical Characteristics
4500
400
4000
350
3500
300
3000
250
2500
200
2000
150
1500
100
1000
50
500
0
0
Input Offset Voltage ( V)
-0.5
-0.45
-0.4
-0.35
-0.3
-0.25
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Count
450
-80
-72
-64
-56
-48
-40
-32
-24
-16
-8
0
8
16
24
32
40
48
56
64
72
80
Count
At TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
Input Offset Voltage Drift ( V/ƒC)
C001
Mean = 4.73 µV
C001
N = 19081
Std. Dev. = 0.09 µV/°C
Figure 2. Typical Distribution of Input Offset Voltage Drift
6000
500
5000
400
4000
Count
600
300
3000
200
2000
100
1000
0
0
-300
-270
-240
-210
-180
-150
-120
-90
-60
-30
0
30
60
90
120
150
180
210
240
270
300
Count
Figure 1. Typical Distribution of Input Offset Voltage
Mean = 0.16 nV/°C
-5
-4.5
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
N = 1886
Std. Dev. = 13.98 µV
Output Offset Voltage Drift ( V/ƒC)
Output Offset Voltage ( V)
C001
N = 1886
Std. Dev. = 48.57 µV
Mean = –8.71 µV
Figure 3. Typical Distribution of Output Offset Voltage
500
Mean
1
- 1
80
60
Mean = –0.73 µV/°C
Figure 4. Typical Distribution of Output Offset Voltage Drift
Input-Referred Offset Voltage ( V)
Input-Referred Offset Voltage ( V)
100
C001
N = 19081
Std. Dev. = 0.74 µV/°C
40
20
0
±20
±40
±60
±80
Mean
1
- 1
400
300
200
100
0
±100
±200
±300
±400
±500
±100
±50
0
50
Temperature (ƒC)
100
150
±50
C001
G = 100
88 units, 3 wafer lots
0
50
Temperature (ƒC)
100
150
C001
G=1
88 units, 3 wafer lots
Figure 5. Input-Referred Offset Voltage vs Temperature
Figure 6. Input-Referred Offset Voltage vs Temperature
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
450
5000
400
4500
350
4000
3500
250
Count
200
3000
2500
2000
150
1500
1000
50
500
0
0
-350
-315
-280
-245
-210
-175
-140
-105
-70
-35
0
35
70
105
140
175
210
245
280
315
350
100
-350
-315
-280
-245
-210
-175
-140
-105
-70
-35
0
35
70
105
140
175
210
245
280
315
350
Count
300
Input Bias Current (pA)
Input Bias Current (pA)
C001
N = 1886
Std. Dev. = 65.31 pA
Mean = 36.25 pA
C001
N = 19081
Std. Dev. = 57.46 pA
Figure 7. Typical Distribution of Input Bias Current (25°C)
Figure 8. Typical Distribution of Input Bias Current (90°C)
450
Input Bias Current (nA)
400
350
Count
300
250
200
150
100
50
-350
-315
-280
-245
-210
-175
-140
-105
-70
-35
0
35
70
105
140
175
210
245
280
315
350
0
Mean = –5.32 pA
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
Mean
1
- 1
0
±50
Input Offset Current (pA)
N = 1886
Std. Dev. = 63.86 pA
100
150
C117
Mean = –52.64 pA
Figure 10. Input Bias Current vs Temperature
Figure 9. Typical Distribution of Input Offset Current
0.8
300
Mean
1
- 1
0.6
250
0.4
200
0.2
Count
Input Offset Current (nA)
50
Temperature (ƒC)
C001
0
-0.2
150
100
-0.4
50
0
-0.8
-50
0
50
100
-40
-36
-32
-28
-24
-20
-16
-12
-8
-4
0
4
8
12
16
20
24
28
32
36
40
-0.6
150
Temperature (ƒC)
Common-Mode Rejection Ratio ( V/V)
C116
C001
N = 1886
Std. Dev. = 10.04 µV/V
Figure 11. Input Offset Current vs Temperature
8
Mean = 1.18 µV/V
Figure 12. Typical CMRR Distribution (G = 1)
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
125
Common-Mode Rejection Ratio (dB)
300
250
Count
200
150
100
0
115
110
105
100
95
90
-0.4
-0.36
-0.32
-0.28
-0.24
-0.2
-0.16
-0.12
-0.08
-0.04
0
0.04
0.08
0.12
0.16
0.2
0.24
0.28
0.32
0.36
0.4
50
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
120
85
-50
0
50
Common-Mode Rejection Ratio ( V/V)
N = 1886
Std. Dev. = 0.1 µV/V
100
150
Temperature (ƒC)
C001
C121
5 Typical Units
Mean = 0.01 µV/V
Figure 14. CMRR vs Temperature (G = 1)
10
20
150
8
15
145
6
Input Current (mA)
Common-Mode Rejection Ratio (dB)
155
140
135
130
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
125
120
115
-50
10
4
2
5
0
0
±2
-5
±4
-10
±6
Input Current
±8
0
50
100
150
Temperature (ƒC)
80
60
G=1
G = 10
G = 100
G = 1000
100
10k
100k
Frequency (Hz)
0
10
20
30
40
C015
140
120
100
80
60
G=1
40
G = 10
20
G = 100
G = 1000
0
1k
±10
Input Voltage (V)
Common-Mode Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB)
100
10
±20
Figure 16. Input Current vs Input Overvoltage
120
0
±30
C122
140
20
-20
±10
Figure 15. CMRR vs Temperature (G = 100)
40
-15
Output Voltage
±40
Output Voltage (V)
Figure 13. Typical CMRR Distribution (G = 100)
10
C005
Figure 17. CMRR vs Frequency (RTI)
100
1k
10k
Frequency (Hz)
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C006
Figure 18. CMRR vs Frequency
(RTI, 1-kΩ Source Imbalance)
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Typical Characteristics (continued)
140
140
120
120
Negative Power Supply
Rejection Ratio (dB)
Positive Power Supply
Rejection Ratio (dB)
At TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
100
80
60
G=1
G = 10
G = 100
G = 1000
40
20
0
1
10
100
80
60
20
0
100
1k
10k
100k
Frequency (Hz)
1
80
Gain (dB)
20
0
-20
-40
1M
Frequency (Hz)
C004
100
10
1
10M
1
10
100
1k
10k
100k
Frequency (Hz)
C001
C002
Figure 22. Voltage Noise Spectral Density
vs Frequency (RTI)
3
1000
2
1
Noise ( V/div)
Current Noise Spectral Density (fA/¥Hz)
100k
G=1
G = 10
G = 100
G = 1000
Figure 21. Gain vs Frequency
100
0
-1
-2
-3
10
-4
1
10
100
1k
10k
Frequency (Hz)
0
1
2
3
4
5
6
Time (1 s/div)
C007
Figure 23. Current Noise Spectral Density
vs Frequency (RTI)
10
10k
1000
40
100k
1k
Frequency (Hz)
Voltage Noise Spectral Density (nv/¥Hz)
60
10k
100
Figure 20. Negative PSRR vs Frequency (RTI)
G=1
G = 10
G = 100
G = 1000
1k
10
C003
Figure 19. Positive PSRR vs Frequency (RTI)
100
G=1
G = 10
G = 100
G = 1000
40
7
8
9
10
C008
Figure 24. 0.1-Hz to 10-Hz RTI Voltage Noise (G = 1)
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Typical Characteristics (continued)
80
2
60
1.5
40
1
Noise (pA/div)
Noise (nV/div)
At TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
20
0
-20
0.5
0
-0.5
-40
-1
-60
-1.5
-2
-80
0
1
2
3
4
5
6
7
8
9
Time (1 s/div)
10
0
1.5
0.5
Gain Error (ppm)
Input Bias Current (nA)
1
1
0.5
0
-40°C
25°C
125°C
-0.5
-1
-8
3
-4
0
4
8
Common Mode Voltage(V)
12
4
5
6
7
8
9
10
C008
Figure 26. 0.1-Hz to 10-Hz RTI Current Noise
2
-12
2
Time (1 s/div)
Figure 25. 0.1-Hz to 10-Hz RTI Voltage Noise (G = 1000)
-16
1
C008
0
-0.5
-1
-1.5
-2
-50
16
0
50
100
Temperature (ƒC)
C116
150
C119
VS = ±15 V
Figure 28. Gain Error vs Temperature (G = 1)
Figure 27. Input Bias Current vs Common-Mode Voltage
30
0.9
0.8
10
0.7
0
IQ (mA)
Gain Error (ppm)
20
-10
-20
0.6
0.5
-30
0.4
-40
-50
VS = ± 15 V
VS = ± 2.25 V
0.3
-50
0
50
100
150
Temperature (ƒC)
±50
C120
Figure 29. Gain Error vs Temperature (G = 100)
0
50
Temperature (ƒC)
100
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C123
Figure 30. Supply Current vs Temperature
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
10
20
8
15
10
4
Nonlinearity (ppm)
Nonlinearity (ppm)
6
2
0
-2
-4
-6
5
0
-5
-10
-15
-8
-10
-20
±10
±8
±6
±4
0
±2
2
4
6
8
10
Output Voltage (V)
±10
±8
±6
±4
Figure 31. Gain Nonlinearity (G = 1)
300
0
±2
2
4
6
C125
-40°C
-160
25°C
25°C
-180
85°C
Offset Voltage ( V)
Offset Voltage ( V)
10
Figure 32. Gain Nonlinearity (G = 100)
-40°C
250
8
Output Voltage (V)
C124
125°C
200
150
85°C
125°C
-200
-220
-240
-260
100
-280
50
-14
-13.8
-13.6
-13.4
-13.2
-13
-12.8
-300
12.5
-12.6
Input Common-Mode Voltage (V)
-14
-14.1
14.8
-14.2
Output Voltage (V)
Output Voltage (V)
15
14.6
14.5
14.4
-40°C
25°C
85°C
125°C
14.2
14.1
14
0
2
4
13.3
13.5
13.7
C127
-40°C
25°C
85°C
125°C
-14.3
-14.4
-14.5
-14.6
-14.7
-14.8
-14.9
-15
6
8
10
Output Current (mA)
12
14
16
0
2
4
6
8
10
Output Current (mA)
C128
Figure 35. Positive Output Voltage Swing vs Output Current
12
13.1
Figure 34. Offset Voltage vs Positive Common-Mode
Voltage
14.9
14.7
12.9
Input Common-Mode Voltage (V)
Figure 33. Offset Voltage vs Negative Common-Mode
Voltage
14.3
12.7
C126
12
14
16
C129
Figure 36. Negative Output Voltage Swing vs Output Current
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Typical Characteristics (continued)
20
Total Harmonic Distortion + Noise (%)
VS = ±15 V
18
VS = ±5 V
Output Amplitude (Vp)
16
14
12
10
8
6
4
2
0
1
-40
0.1
-60
0.01
-80
G=1
G = 10
G = 100
0.001
100
1k
10k
100k
1M
10M
Frequency (Hz)
10
100
1k
-100
100k
10k
Frequency (Hz)
C001
C002
500-kHz Measurement bandwidth
100-kΩ Load
Figure 37. Large-Signal Frequency Response
1-VRMS Output voltage
Figure 38. THD+N vs Frequency
100
60
Positive Overshoot
80
Negative Overshoot
60
Output Amplitude (mV)
70
50
Overshoot (%)
Total Harmonic Distortion + Noise (dB)
At TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
40
30
20
40
20
0
-20
-40
-60
-80
10
-100
-10
0
1
10
100
-5
0
5
1000
Capacitive Load (pF)
10
15
20
25
30
Time ( s)
C012
C011
G = 1, RL = 10 kΩ, CL = 100 pF
Figure 40. Small-Signal Response
100
80
80
60
60
Output Amplitude (mV)
Output Amplitude (mV)
Figure 39. Overshoot vs Capacitive Loads
100
40
20
0
-20
-40
-60
40
20
0
-20
-40
-60
-80
-80
-100
-100
-10
-5
0
5
10
15
20
25
30
-50
Time ( s)
-30
-10
10
30
50
70
90
110 130 150
Time ( s)
C013
G = 10, RL = 10 kΩ, CL = 100 pF
C014
G = 100, RL = 10 kΩ, CL = 100 pF
Figure 41. Small-Signal Response
Figure 42. Small-Signal Response
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
100
Output
Input
60
40
Amplitude (2 V/div)
Output Amplitude (mV)
80
20
0
-20
-40
-60
-80
-100
-200 -100
0
100 200 300 400 500 600 700 800
Time (10 µs/div)
Time ( s)
C015
C0xx
G = 1000, RL = 10 kΩ, CL = 100 pF
Figure 43. Small-Signal Response
Figure 44. Large Signal Step Response
1000
90
EMIRR (dB)
Output Impedance (O)
110
100
10
1
0.1
70
50
30
0.01
10
1
10
100
1k
10k
100k
1M
Frequency (Hz)
10M
10M
100M
1G
Figure 45. Closed-Loop Output Impedance
C001
Figure 46. Differential-Mode EMI Rejection Ratio
5
VREF = 0 V
Common-Mode Voltage (V)
110
90
EMIRR (dB)
10G
Frequency (Hz)
C001
70
50
30
VREF = 2.5 V
4
3
2
1
0
10
10M
100M
1G
10G
Frequency (Hz)
0
1
2
3
Output Voltage (V)
C001
4
5
6
C006
VS = 5 V, G = 1
Figure 47. Common-Mode EMI Rejection Ratio
14
Figure 48. Input Common-Mode Voltage vs Output Voltage
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
5
VREF = 0 V
4
VREF = 2.5 V
Common-Mode Voltage (V)
Common-Mode Voltage (V)
5
4
3
2
1
3
2
1
0
-1
-2
-3
G=1
-4
0
G = 100
-5
0
1
2
3
4
5
6
Output Voltage (V)
±6
±4
±2
0
2
4
Output Voltage (V)
C006
VS = 5 V, G = 100
6
C006
VS = ±5 V, VREF = 0 V
Figure 49. Input Common-Mode Voltage vs Output Voltage
Figure 50. Input Common-Mode Voltage vs Output Voltage
Common-Mode Voltage (V)
15
10
5
0
-5
-10
-15
G=1
G = 100
-20
±20
±10
0
Output Voltage (V)
10
20
C006
VS = ±15 V, VREF = 0 V
Figure 51. Input Common-Mode Voltage vs Output Voltage
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7 Detailed Description
7.1 Overview
The INA828 is a monolithic precision instrumentation amplifier incorporating a current-feedback input stage and a
4-resistor difference amplifier output stage. The differential input voltage is buffered by Q1 and Q2 and is forced
across RG, which causes a signal current to flow through RG, R1, and R2. The output difference amplifier, A3,
removes the common-mode component of the input signal and refers the output signal to the REF terminal. The
VBE and voltage drop across R1 and R2 produce output voltages on A1 and A2 that are approximately 0.8 V lower
than the input voltages.
Each input is protected by two field-effect transistors (FETs) that provide a low series resistance under normal
signal conditions, and preserve excellent noise performance. When excessive voltage is applied, these
transistors limit input current to approximately 8 mA.
7.2 Functional Block Diagram
+VS
VB
RB
IB Cancellation
RB
IB Cancellation
-VS +VS
40 k
±
±
+
±
+
40 k
A1
A2
A3
OUT
+
40 k
REF
40 k
+VS
+VS
-VS +VS
Q1
-IN
Overvoltage
Protection
SuperNPN
+VS
R1
25 k
+VS
RG
-VS
16
Q2
+IN
Overvoltage
Protection
R2
25 k
RG
(External)
-VS
SuperNPN
-VS
RG
-VS
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7.3 Feature Description
7.3.1 Setting the Gain
Figure 52 shows that the gain of the INA828 is set by a single external resistor, RG, connected between the RG
pins (pins 1 and 8).
V+
+VS
Overvoltage
Protection
-IN
1
50 k:
RG
40 k
±
RG
G
40 k
+
RG
25 k
±
25 k
+
OUT
VO
RG
G V
IN
V
IN
VREF
±
Overvoltage
Protection
+IN
+
40 k
40 k
REF
-VS
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V-
Figure 52. Simplified Diagram of the INA828 With Gain and Output Equations
The value of RG is selected according to:
50 k:
G 1
RG
(1)
Table 1 lists several commonly-used gains and resistor values. The 50-kΩ term in Equation 1 comes from the
sum of the two internal 25-kΩ feedback resistors. These on-chip resistors are laser-trimmed to accurate absolute
values. The accuracy and temperature coefficients of these resistors are included in the gain accuracy and drift
specifications of the INA828.
Table 1. Commonly-Used Gains and Resistor Values
DESIRED GAIN
RG (Ω)
NEAREST 1% RG (Ω)
1
NC
NC
2
50 k
49.9 k
5
12.5 k
12.4 k
10
5.556 k
5.49 k
20
2.632 k
2.61 k
50
1.02 k
1.02 k
100
505.1
511
200
251.3
249
500
100.2
100
1000
50.05
49.9
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7.3.1.1 Gain Drift
The stability and temperature drift of the external gain setting resistor, RG, also affects gain. The contribution of
RG to gain accuracy and drift can be determined from Equation 1.
The best gain drift of 5 ppm/℃ (maximum) can be achieved when the INA828 uses G = 1 without RG connected.
In this case, gain drift is limited only by the slight mismatch of the temperature coefficient of the integrated 40-kΩ
resistors in the differential amplifier (A3). At gains greater than 1, gain drift increases as a result of the individual
drift of the 25-kΩ resistors in the feedback of A1 and A2, relative to the drift of the external gain resistor RG. The
low temperature coefficient of the internal feedback resistors significantly improves the overall temperature
stability of applications using gains greater than 1 V/V over alternate solutions.
Low resistor values required for high gain can make wiring resistance important. Sockets add to the wiring
resistance and contribute additional gain error (such as a possible unstable gain error) at gains of approximately
100 or greater. To assure stability, avoid parasitic capacitance of more than a few picofarads at RG connections.
Careful matching of any parasitics on both RG pins maintains optimal CMRR over frequency; see Typical
Characteristics, Figure 17.
7.3.2 EMI Rejection
Texas Instruments developed a method to accurately measure the immunity of an amplifier over a broad
frequency spectrum, extending from 10 MHz to 6 GHz. This method uses an EMI rejection ratio (EMIRR) to
quantify the ability of the INA828 to reject EMI. The offset resulting from an input EMI signal can be calculated
using Equation 2:
'VOS
§ VRF _ PEAK 2
¨
¨ 100 mVP
©
·
¸ ˜ 10
¸
¹
§ EMIRR (dB) ·
¨
¸
20
©
¹
where
•
VRF_PEAK is the peak amplitude of the input EMI signal.
(2)
110
110
90
90
EMIRR (dB)
EMIRR (dB)
Figure 53 and Figure 54 show the INA828 EMIRR graph for both differential and common-mode EMI rejection
across this frequency range. Table 2 shows the EMIRR values for the INA828 at frequencies commonly
encountered in real-world applications. Applications listed in Table 2 can be centered on or operated near the
particular frequency shown. Depending on the end-system requirements, additional EMI filters may be required
near the signal inputs of the system, as well as incorporating known good practices such as using short traces,
low-pass filters, and damping resistors combined with parallel and shielded signal routing.
70
50
30
70
50
30
10
10
10M
100M
1G
10G
Frequency (Hz)
10M
C001
Figure 53. Common-Mode EMIRR Testing
18
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100M
1G
Frequency (Hz)
10G
C001
Figure 54. Differential Mode EMIRR Testing
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Table 2. INA828 EMIRR for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
DIFFERENTIAL
EMIRR
COMMON-MODE
EMIRR
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultrahighfrequency (UHF) applications
48 dB
87 dB
900 MHz
Global system for mobile communications (GSM) applications, radio
communication, navigation, GPS (up to 1.6 GHz), GSM, aeronautical mobile,
UHF applications
52 dB
98 dB
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite,
L-band (1 GHz to 2 GHz)
94 dB
51 dB
2.4 GHz
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications,
industrial, scientific and medical (ISM) radio band, amateur radio and satellite,
S-band (2 GHz to 4 GHz)
66 dB
57 dB
3.6 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
79 dB
87 dB
802.11a, 802.11n, aero communication and navigation, mobile communication,
space and satellite operation, C-band (4 GHz to 8 GHz)
90 dB
92 dB
5 GHz
7.3.3 Input Common-Mode Range
The linear input voltage range of the INA828 input circuitry extends within 2 Volts of both power supplies and
maintains excellent common-mode rejection throughout this range. The common-mode range for the most
common operating conditions are shown in Figure 55, Figure 50, and Figure 51. The common-mode range for
other operating conditions is best calculated using the INA common-mode range calculating tool. The INA828
device can operate over a wide range of power supplies and VREF configurations, thus providing a
comprehensive guide to common-mode range limits for all possible conditions is impractical.
5
VREF = 0 V
VREF = 2.5 V
Common-Mode Voltage (V)
Common-Mode Voltage (V)
5
4
3
2
1
0
VREF = 0 V
VREF = 2.5 V
4
3
2
1
0
0
1
2
3
4
5
Output Voltage (V)
6
0
2
3
4
5
Output Voltage (V)
VS = 5 V, G = 1
6
C006
VS = 5 V, G = 100
Figure 55. Input Common-Mode Voltage vs Output Voltage
Figure 56. Input Common-Mode Voltage vs Output Voltage
5
15
Common-Mode Voltage (V)
4
Common-Mode Voltage (V)
1
C006
3
2
1
0
-1
-2
-3
G=1
-4
G = 100
-5
±6
±4
10
5
0
-5
-10
-15
G=1
G = 100
-20
±2
0
2
Output Voltage (V)
4
6
±20
±10
0
Output Voltage (V)
C006
VS = ±5 V, VREF = 0 V
10
20
C006
VS = ±15 V, VREF = 0 V
Figure 57. Input Common-Mode Voltage vs Output Voltage
Figure 58. Input Common-Mode Voltage vs Output Voltage
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7.3.4 Input Protection
The inputs of the INA828 device are individually protected for voltages up to ±40 V. For example, a condition of
–40 V on one input and 40 V on the other input does not cause damage. Internal circuitry on each input provides
low series impedance under normal signal conditions. If the input is overloaded, the protection circuitry limits the
input current to a value of approximately 8 mA.
+V
ZD1
+VS
IN
+
Input Voltage
Source
Overvoltage
Protection
Input Transistor
±
-VS
ZD2
-V
Figure 59. Input Current Path During an Overvoltage Condition
10
20
8
15
Input Current (mA)
6
10
4
2
5
0
0
±2
-5
±4
-10
±6
Input Current
±8
-15
Output Voltage
-20
±10
±40
±30
±20
±10
0
10
20
Input Voltage (V)
30
Output Voltage (V)
During an input overvoltage condition, current flows through the input protection diodes into the power supplies,
see Figure 59. If the power supplies are unable to sink current, then Zener diode clamps (ZD1 and ZD2 in
Figure 59) must be placed on the power supplies to provide a current pathway to ground. Figure 60 illustrates the
input current for input voltages from –40 V to +40 V when the INA828 is powered by ±15-V supplies.
40
C015
Figure 60. Input Current vs Input Overvoltage
20
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7.3.5 Operating Voltage
The INA828 operates over a power-supply range of 4.5 V to 36 V (±2.25 V to ±18 V).
CAUTION
Supply voltages higher than 40 V (±20 V) can permanently damage the device.
Parameters that vary over supply voltage or temperature are shown in the Typical
Characteristics section of this data sheet.
7.4 Device Functional Modes
The INA828 has a single functional mode and is operational when the power-supply voltage is greater than 4.5 V
(±2.25 V). The maximum power-supply voltage for the INA828 is 36 V (±18 V).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Reference Terminal
The output voltage of the INA828 is developed with respect to the voltage on the reference terminal, REF. Often,
in dual-supply operation, the reference pin (pin 6) is connected to the low-impedance system ground. In singlesupply operation, offsetting the output signal to a precise mid-supply level is useful (for example, 2.5 V in a 5-V
supply environment). To accomplish this level shift, a voltage source must be connected to the REF pin to levelshift the output so that the INA828 can drive a single-supply ADC.
The voltage source applied to the reference terminal must have a low output impedance. As illustrated in
Figure 61, any resistance at the reference terminal (shown as RREF in Figure 61) is in series with one of the
internal 40-kΩ resistors.
V+
+VS
-IN
Overvoltage
Protection
40 k
±
RG
RG
RG
+IN
40 k
+
25 k
±
25 k
+
OUT
±
Overvoltage
Protection
REF
+
40 k
40 k
RREF
-VS
V-
Figure 61. Parasitic Resistance Shown at the Reference Terminal
The parasitic resistance at the reference terminal, RREF, creates an imbalance in the 4 resistors of the internal
difference amplifier, resulting in degraded common-mode rejection ratio (CMRR). Figure 62 shows the
degradation in CMRR of the INA828 for increasing resistance at the reference terminal. For the best
performance, keep the source impedance to the REF terminal, RREF, below 5 Ω.
22
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Reference Terminal (continued)
Common-Mode Rejection Ratio
120
100
80
60
40
20
0
10
100
1k
10k
Frequency (Hz)
C001
Figure 62. The Effect of Increasing Resistance at the Reference Terminal
Voltage reference ICs are an excellent option for providing a low-impedance voltage source for the reference
terminal. However, if a resistor voltage divider is used to generate a reference voltage, it must be buffered by an
op amp as shown in Figure 63 to avoid CMRR degradation.
±IN
OUT
±VS
INA828
RG
REF
RG
RG
5V
OPA191
5V
100 k
+
+IN
+VS
5V
1 F
100 k
±
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Figure 63. Using an Op Amp to Buffer Reference Voltages
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8.2 Input Bias Current Return Path
The input impedance of the INA828 is extremely high—approximately 100 GΩ. However, a path must be
provided for the input bias current of both inputs. This input bias current is typically 150 pA. High input
impedance means that this input bias current changes very little with varying input voltage.
Input circuitry must provide a path for this input bias current for proper operation. Figure 64 shows various
provisions for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds
the common-mode range of the INA828, and the input amplifiers saturate. If the differential source resistance is
low, the bias current return path can be connected to one input (as shown in the thermocouple example in
Figure 64). With a higher source impedance, using two equal resistors provides a balanced input with possible
advantages of a lower input offset voltage as a result of bias current and better high-frequency common-mode
rejection.
Microphone,
Hydrophone,
and So Forth
TI Device
47 kW
47 kW
Thermocouple
TI Device
10 kW
TI Device
Center tap provides
bias current return.
Copyright © 2017, Texas Instruments Incorporated
Figure 64. Providing an Input Common-Mode Current Path
24
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8.3 PCB Assembly Effects on Precision
The printed-circuit board (PCB) assembly process, including reflow soldering, imparts thermal stresses on the
INA828 which can degrade the precision of the device and must be considered in the development of very-highprecision systems. Baking the PCBs after the assembly process can restore the precision of the device to preassembly values. Figure 65, Figure 66, and Figure 67 illustrate the effect of reflow soldering on the typical
distribution of input offset voltage of the INA828. Figure 65 shows the distribution of input offset voltage for a set
of INA828 devices prior to the PCB assembly process. Exposing the INA828 to a JEDEC-standard thermal
profile for reflow soldering produces the histogram shown in Figure 66 on another set of INA828 devices. The
standard deviation of input offset voltage has almost doubled due to the thermal stress imparted to the INA828
from the reflow process. However, baking INA828 units for 30 minutes at 125°C after the reflow soldering
process produced the distribution given in Figure 67. The post-reflow bake restored the standard deviation of the
input offset voltage to pre-assembly levels.
80
300
70
250
60
50
Count
Count
200
150
40
30
100
20
50
0
-80
-72
-64
-56
-48
-40
-32
-24
-16
-8
0
8
16
24
32
40
48
56
64
72
80
-80
-72
-64
-56
-48
-40
-32
-24
-16
-8
0
8
16
24
32
40
48
56
64
72
80
0
10
Input Offset Voltage ( V)
Input Offset Voltage ( V)
C001
Figure 65. Typical Distribution of INA828 Input Offset
Voltage Prior to Reflow Soldering
C001
Figure 66. Typical Distribution of INA828 Input Offset
Voltage After Reflow Soldering
250
Count
200
150
100
0
-80
-72
-64
-56
-48
-40
-32
-24
-16
-8
0
8
16
24
32
40
48
56
64
72
80
50
Input Offset Voltage ( V)
C001
Figure 67. Typical Distribution of Post-Reflow INA828 Units Baked at 125°C for 30 Minutes
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8.4 Typical Application
Figure 68 shows a three-terminal programmable-logic controller (PLC) design for the INA828. This PLC
reference design accepts inputs of ±10 V or ±20 mA. The output is a single-ended voltage of 2.5 V ±2.3 V (or
200 mV to 4.8 V). Many PLCs typically have these input and output ranges.
±10 V
REF5025
R1 = 100 NŸ
1 F
VOUT
VIN
GND
NR
15 V
1 F 1 F
15 V
R2 = 4.17 NŸ
±20 mA
-IN +VS
RG
REF
R3 =
RG = 10.5 NŸ
20 Ÿ
INA828
RG
+IN
VOUT 2.5 V ± 2.3 V
OUT
-VS
-15 V
Copyright © 2017, Texas Instruments Incorporated
Figure 68. PLC Input (±10 V, 4 mA to 20 mA)
8.4.1 Design Requirements
For this application, the design requirements are:
• 4-mA to 20-mA input with less than 20-Ω burden
• ±20-mA input with less than 20-Ω burden
• ±10-V input with impedance of approximately 100 kΩ
• Maximum 4-mA to 20-mA or ±20-mA burden voltage equal to ±0.4 V
• Output range within 0 V to 5 V
8.4.2 Detailed Design Procedure
There are two modes of operation for the circuit shown in Figure 68: current input and voltage input. This design
requires R1 >> R2 >> R3. Given this relationship, Equation 3 calculates the current input mode transfer function.
VOUT-I = VD ´ G + VREF = -(IIN ´ R3) ´ G + VREF
where
•
•
•
•
G represents the gain of the instrumentation amplifier
VD represents the differential voltage at the INA828 inputs
VREF is the voltage at the INA828 REF pin
IIN is the input current
(3)
Equation 4 shows the transfer function for the voltage input mode.
R2
VOUT-V = VD ´ G + VREF = - VIN ´
´ G + VREF
R 1 + R2
where
•
VIN is the input voltage
(4)
R1 sets the input impedance of the voltage input mode. The minimum typical input impedance is 100 kΩ. 100 kΩ
is selected for R1 because increasing the R1 value also increases noise. The value of R3 must be extremely
small compared to R1 and R2. 20 Ω for R3 is selected because that resistance value is much smaller than R1 and
yields an input voltage of ±400 mV when operated in current mode (±20 mA).
26
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Typical Application (continued)
Use Equation 5 to calculate R2 given VD = ±400 mV, VIN = ±10 V, and R1 = 100 kΩ.
R2
R ´ VD
VD = VIN ´
® R2 = 1
= 4.167 kW
R 1 + R2
VIN - VD
(5)
The value obtained from Equation 5 is not a standard 0.1% value, so 4.17 kΩ is selected. R1 and R2 also use
0.1% tolerance resistors to minimize error.
Use Equation 6 to calculate the ideal gain of the instrumentation amplifier.
V
- VREF 4.8 V - 2.5 V
V
= 5.75 V
G = OUT
=
VD
400 mV
(6)
Equation 7 calculates the gain-setting resistor value using the INA828 gain equation, Equation 1.
50 k:
50 k:
RG
10.5 k:
G 1 5.75 1
(7)
10.5 kΩ is a standard 0.1% resistor value that can be used in this design.
8.4.3 Application Curves
5
5
4
4
Output Voltage (V)
Output Voltage (V)
Figure 69 and Figure 70 show typical characteristic curves for the circuit in Figure 68.
3
2
1
3
2
1
0
0
-10
-5
0
5
10
Input Voltage (V)
-20
-10
Figure 69. PLC Output Voltage vs Input Voltage
0
10
Input Current (mA)
C001
20
C001
Figure 70. PLC Output Voltage vs Input Current
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8.5 Other Application Examples
8.5.1 Resistance Temperature Detector Interface
Figure 71 illustrates a 3-wire interface circuit for resistance temperature detectors (RTDs). The circuit
incorporates analog linearization and has an output voltage range from 0 to 5 V. The linearization technique
employed is described in Analog linearization of resistance temperature detectors. Series and parallel
combinations of standard 1% resistor values are used to achieve less than 0.02°C of error over a 200°C
temperature span.
15 V
NR
1 F
VIN
GND
1.13
k
100
k
100
2.87
k
INA828
RG
+IN
Pt100 RTD
100
REF
-IN
RG
+VS
4.99
k
VOUT
0 V at 0°C
5 V at 200°C
25 mV/°C
OUT
-VS
4.99
k
VOUT
1 F
1 F
REF5050
-15 V
105 k
1.18 k
Copyright © 2017, Texas Instruments Incorporated
Figure 71. A 3-Wire Interface for RTDs With Analog Linearization
5
0.018
4.5
0.016
0.014
3.5
0.012
3
Error (ƒC)
Output Voltage (V)
4
2.5
2
1.5
0.006
1
0.004
0.5
0.002
0
0
0
50
100
Temperature (ƒC)
150
200
0
50
100
Temperature (ƒC)
C001
Figure 72. Transfer Function of 3-Wire RTD Interface
28
0.01
0.008
150
200
C001
Figure 73. Temperature Error Over Full Temperature
Range
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9 Power Supply Recommendations
The nominal performance of the INA828 is specified with a supply voltage of ±15 V and mid-supply reference
voltage. The device can also be operated using power supplies from ±1.5 V (3 V) to ±18 V (36 V) and non midsupply reference voltages with excellent performance. Parameters that can vary significantly with operating
voltage and reference voltage are illustrated in the Typical Characteristics section.
10 Layout
10.1 Layout Guidelines
Attention to good layout practices is always recommended. For best operational performance of the device, use
good PCB layout practices, including:
• Care must be taken to assure that both input paths are well-matched for source impedance and capacitance
to avoid converting common-mode signals into differential signals. In addition, parasitic capacitance at the
gain-setting pins can also affect CMRR over frequency. For example, in applications that implement gain
switching using switches or PhotoMOS® relays to change the value of RG, select the component so that the
switch capacitance is as small as possible.
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of the device
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in
parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in Figure 74, keeping RG
close to the pins minimizes parasitic capacitance.
• Keep the traces as short as possible.
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10.2 Layout Example
+V
C2
RG
RG
-IN
OUT
±VS
INA828
R3
REF
+IN
+VS
R2
R1
C1
Ground plane
removed at gain
resistor to minimize
parasitic capacitance
-V
Use ground pours for
shielding the input
signal pairs
R3
+V
GND
R1
Input traces routed
adjacent to each other
1
RG
RG
8
±IN
2
±IN
+VS
7
+IN
3
+IN
OUT
6
4
-VS
REF
5
R2
C2
GND
OUT
Low-impedance
connection for
reference terminal
C1
-V
Place bypass
capacitors as close to
IC as possible
Copyright © 2017, Texas Instruments Incorporated
Figure 74. Example Schematic and Associated PCB Layout
30
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• REF50xx Low-Noise, Very Low Drift, Precision Voltage Reference
• OPA191 Low-Power, Precision, 36-V, e-trim CMOS Amplifier
• TINA-TI software folder
• INA Common-Mode Range Calculator
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
PhotoMOS is a registered trademark of Panasonic Electric Works Europe AG.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
INA828ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA828
INA828IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA828
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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